Semiconductor Devices and Models - NCKU

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog IC Design, 20162-1

Semiconductor Devices and Models

Resistor

Capacitor

Diode

Bipolar Transistor

MOSFET

SPICE Model

Appendix


Material

Diffusion layers: e.g. n+, p+, well

Conductors : e.g. polysilicon, …

Resistance calculation

R=ρL/A=ρL/tW= R□L/W

R□=ρ/t is sheet resistance

Resistivity

Sheet resistance

Resistors

A

LR

Cross-section

area, AW

L

tResistivity=ρ

W

W

LRR 口

L

Sheet resistance

= R□

metal metal

SiO2SiO2

n+

p-substrate

V1V2


Resistors (Cont.)

Graphical calculations from sheet resistance

VC (voltage coefficient) and TC (temperature coefficient) of R (or C)

⇨ nonlinearity ⇨ THD

W

1 11 1 11 1 ½

R

R5.7

W W WW

W W W W/2

.55

1

1

.5

1 1 .55

1

1

R

R1.8

.5


Metal-or polysilicon-over-diffusion

C is voltage dependent

Metal-Insulator-metal

High linearity

Inter-metal and intra-metal

Inter: different layer

Intra: same layer

Capacitors

metal metal

SiO2SiO2

n+

p-

l

V1

V2

metal n

metal n-1

Via

Via

V1

V2

metal n

metal n-1

V1 V2


Resister ratio-matching considerations

MetalResistor Contact

w

L

w

3L

w

L

w

R1

R2

R3

R4


Capacitor ratio-matching considerations

C1

X

LL

2X

C2

X

3L

3L

C3

2X

L2

177

L

LL

2

175

C4

X

L

2X

L


Diode

VT

IS

IO

VO

p-type n-typeXn-Xp

Depletion Region

0

Holes Electrons

Donor ions

x

Acceptor ions

q

kT Vwhere T

)1exp( II TV

V

S

current saturationIS

2/1

DAA

DR00S ])NN(N

N

q

)V(K2[Xp

2/1

DAD

AR00S ])NN(N

N

q

)V(K2[Xn

silicon of ypermitivit relativeKS

voltage biasreverseVR

potential inbulit0


Junction Capacitance

For abrupt junction:

For graded junction

2/1

DA

DAR00S ]

NN

NN)V(qK2[QQ

0

R

0j2/1

DA

DA

R0

0S

R

jV

1

C]

NN

NN

)V(2

qK[

dV

dQC

] ]NN

NN

2

qK[C [ 2/1

DA

DA

0

0S0j

m1

DA

DAR00S ]

)NN(

NN)V(qK2[QQ

m

0

R

0j

m

R0

m1

DA

DA0S

R

j

)V

1(

C

)V(

1]

NN

NNqK2)[m1(

dV

dQC

] 1

]NN

NNqK2)[m1(C [

m

0

m1

DA

DA0S0j

m depend on the doping profile

m ≈ 1/3 for a linearly graded junction


Diode Model

DC Model

For V < Vr (off)

For V > Vr (on)

Small Signal Model

For forward-biased diode

A

-

+

V

Rf

Vr

ID

Vr

IS

ID

VO

D

T

V/V

S

T1

fI

V

eI

V)

dV

dI(R

TD

Cdrd

0jj C2C

Cjd

Td

rC

D

Td

I

Vr

Normally, Cd>>Cj (Cd≈100Cj)

Diffusion capacitance:

Junction capacitance:

is the transit time of diodeT


Bipolar Process

Vertical and lateral transistor in a bipolar process

Vertical PNP or NPN

high β

Lateral PNP or NPN

low β

verticalnpn

transistor

lateralpnp

transistor

p

n

n+ n+ pp

n

n+n+n

p

n+

n

p+

collectorbase

emitter

basecollector

emitter

n+p+


BJT Model: Ebers-Moll model (DC Model)

1e -I1eα

-I I

1eα

I - 1e I I

T

BC

T

BB

T

BC

T

BB

VV

S

VV

R

SE

VV

R

SVV

SC

-VBE

+

+

-+

-

VCE

VBC

IB

IE

IC

C

E

B

NPN

-VBE

+

+

-+

-

VCE

VBC

IB

IE

IC

C

E

B

PNP

B

E C

αRIR

IE

IB

ICIRIF

- -VEB VCB

αFIF


Small Signal BJT Model

p substrate

Aluminum contacts

Collector

Emitter

Base

Isolation island

n+ n+

PP

P+

n


Small Signal BJT Model (Cont.)

+

-

gmvbe

CBC

rμ

rn CBE vbe

RE

ro CCS

RC

Sub

CBS

rb

Sub

B

E

C


MOS Transistors

MOS structure

SEMICONDUCTOR SUBSTRATE

DRAIN SOURCE

GATE

SUBSTRATE

symbol

DRAIN SOURCE

GATE

SUBSTRATE

PMOS symbol

P - DOPED

n n

DRAIN

GATE

CONDUCTOR

INSULATOR

SOURCE

SEMICONDUCTOR SUBSTRATE

n - DOPED

p p

DRAIN

GATE

CONDUCTOR

INSULATOR

SOURCE

NMOS


MOS Transistors (Cont.)

Vgs

Source Gate Drain

VD

Vs

P

-Enhancement NMOS

Source Gate Drain

P

Source Gate Drain

n

-Depletion NMOS

-Enhancement PMOS

Metal

Polysilicon

Oxide

n-diffusion

p-diffusion

p-substrate

n-depletion

substrate

-Depletion PMOSSource Gate Drain

n

Implant

Implant


MOS Transistor Symbol (Cont.)

nMOS

enhancement

nMOS

depletionpMOS

enhancement


MOS Transistor Operation

Example : nMOS

Vgs > Vt, Vds = 0 (linear region)

Vgs > Vt, Vds = Vgs-Vt

GND (0 V)Vgs

0V Channel

( inversion layer)

( inversion layer)

gate

+ + +dv

GND (0 V)Vgs

0V


MOS Transistor Operation (Cont.)

Example : nMOS

Vgs > Vt, Vds > Vgs-Vt (saturation region)

I-V characteristic of nMOS

GND (0 V)

0V

Pinch off, Xd

Ids

Vgs- Vt = Vds

Vgs4

Vgs2

Vgs3

Vgs1

Vds

LINEARREGION SATURATION

REGION


Large Signal Behavior of MOSFETs

Threshold voltage

Large-Signal I-V

If depletion-layer width Xd is considered Leff = L-Xd

Channel length modulation

2tGS

2

tGSox

DS VVL2

kWVV

L2

WCI

2tGS

eff

DS VVL2

kWI

DS

eff2

tGS2

effDS

DS

dV

dLVV

L2

kW

V

I

DSeff

dDS

dVL

dxI

Let

ox

ox

ox

0oxOX

ox

ASiO

fSBf0t

fSBf

ox

ASiO

0tt

t

ε

t

εk C and

C

Nqε2 γ where

2- V 2V

2 - V 2 C

Nqε2V V

2

2

DS

d

effA dV

dx

L

1

V

1 DS

2

tGSDS V1VVL2

kWI

DS

A

DS

o

1

DS

DS

I

V

I

1 r

V

I


Small Signal Model of MOSFETs in Saturation

Equivalent circuit model

+

-

+

-

bsv

gsv

G D

B

S sbC

gbCdbC

gdC

gsCbsmbvg

dsrgsmvg


Derivation of

Total charge stored in the channel

Small Signal Model of MOSFETs in Saturation (Cont.)

m

BS

ttGS

BS

DSmb g

V

VVV

L

Wk

V

Ig

BSfBS

fSBfto

BS

t

V22V

2V2V

V

V

21

0

SB

0sbsb

V1

CC

21

0

DS

0dbdb

V1

CC

OX

GS

Tgs WLC

3

2

V

QC

gsC

TQ

tGSox VVWLC3

2

ox

GS

Tgs WLC

3

2

V

QC

IL

Wk2 V V

L

Wk

V

I g DStGS

'

GS

DSm

1VDS

DS

A

DS

1-

DS

d

DS

eff

1-

DS

DSo

I

V

λI

1 )

dV

dX (

I

L

V

I r

dVV - V- VI

μCW dy]V - V(y) - V[WC Q

2

tGS

D

2

ox

2L

0tGSoxT

WLC3

2

) - VV(L

WK

2

1

πC2

g f

ox

tGS

gs

mt

tGS2tt VV2L

3 f2


Example—Small Signal Model

Derive the complete small-signal model for an NMOS transistor with

IDS=100μA, VSB=0.15V, VDS=0.6V. Device parameters are 2 = 0.65,

W=10 μm, L=0.18 μm, γ= 0.4V1/2, μnCox = 200μA/V2 , λ = 0.4V-1, tox =

40Å = 4nm, Ψ0 = 0.69 V, Csb0 = Cdb0 = 9.3fF. Overlap capacitance from

gate to source and gate to drain is 1fF. Assume Cgb =5fF.

VmA5.1

VA10100

18.0

10102002I

L

WC2g 66

Doxnm

VA333

VA

15.065.02

1010018.0

1010200

4.0V22

IL

WC

g

66

SBf

Doxn

mb

k25101004.0

1

I

1r

6

D

o

f


Example—Small Signal Model (Cont.)

With VSB=0.15V,we find

The voltage from drain to body is

Hence ,

The oxide capacitance per unit area is

The intrinsic portion of the gate source capacitance is

fF4.8fF

69.0

15.01

3.9

V1

CC

2/12/1

0

SB

0sbsb

210

14

ox

SiOr

oxm

fF6.8m1040

cmF10854.89.3

tC 2

fF10fF6.818.0103

2Cgs

V75.0VVV SBDSDB

fF4.6fF

69.0

75.01

3.9

V1

CC

2/12/1

0

DB

0dbdb


Example—Small Signal Model (Cont.)

The addition of overlap capacitance gives Cgs = 11 fF

Gate-drain capacitance is overlap capacitance Cgd = 1 fF

The complete small-signal equivalent circuit is shown below

The fT of the device can be calculated with Cgb = 5fF giving

1fF

5fF 6.4fF

25k

8.4fF

11fF

+

-

+

-

bsv 610333

bsv

gsvgsv 3105.1

G D

B

S

GHz04.14Hz

105111

105.1

2

1

CCC

g

2

1f

15

3

gbgdgs

mT


Subthreshold Conduction in MOSFETs

1.5n

parameters processon depends k ere wh

exp - 1expL

Wk I

x

nVt

V

nVt

V

xDS

DSGS

)( AIDS

)(VVGS0.1 0.2 0.3 0.4 0.5

0.1

0.2

0.3

0.4

VDS = 5V

W = 20 μ m

L = 20μm

0.5


Subthreshold Conduction in MOSFET (cont.)

Plotted on linear scales as versus VGS ,showing the square-law

characteristic.

2/1

DS )A(I

)(VVGS

Extrapolated Vt = 0.7V

1 2 3 4 5

5

10

15

20

VDS = 5V

W = 20 μm

L = 20μm

DSI


Subthreshold Conduction in MOSFET (cont.)

Plotted on log-linear scales showing the exponential characteristic in the

subthreshold region.

)A(IDS

)(VVGS

0.1 0.2 0.3 0.4

VDS = 5V

W = 20 μ m

L = 20μm

10-4

10-7

10-10

Subthreshold exponential region

Square-law region


Mobility Degradation

Large lateral electric fields accelerate carriers up to a maximum velocity

Larger vertical electric fields effective channel depth ↓ collisions ↑

These effects can be modeled by an effective carrier mobility

n+

p-substrate

n+

Source DrainGate

Lateral Electric Field

m/1m

eff

neff,n

])V (1[

s parameterare devicemandwhere θ

)])V (1[

1(V

L

WC

2

1I

m/1m

eff

2

effoxnD

VDS (V)

ID (A) Without mobility degradation

With mobility degradation

effoxnD VL

WC

2

1I

This effect can also expressed as

α-law model from curve-fitting

2 ,


Substrate Current Flow in MOSFETs

where and are process-dependent parameters and VDSsat is the

value of VDS where the drain characteristics enter the saturation region2k

) - VV(

k-exp)I - V(Vk I

sat

sat

DSDS

2DSDSDS1DB

2DSDS

DB2

DB

DBdb

sat - VV

Ik

V

I g

1k


Example (1/2)

Calculate for 2 V and 4 V, and compare with the

device .

Assume IDS = 100μA, λ = 0.05 V-1, VDS(sat) = 0.3 V, K1 = 5 V-1, and

K2 = 30 V.

For VDS = 2 V, we have

and thus

dbdb 1/g r

or VDS

A 108.17.1

30exp101007.1 5 I 116

DB

V

A 109.1

7.1

108.130 g 10

2

11

db

G 3.5 103.5g

1 r 9

db

db


Example (2/2)

This result is negligibly large compared with

However, for 4 V

The substrate leakage current is now about 0.5% of the drain current.

We find

and thus

This parasitic resistor is now comparable to and can have a

dominant effect on high-output-impedance MOS current mirrors.

DSV

k 200 1010005.0

1

λI

1 r

6

D

o

A 106.5 7.3

30-exp101007.35 I 76

DB

V

A 102.1

7.3

106.530 g 6

2

7

db

kΩ 833 Ω1033.8g

1 r 5

db

db

or


Summary of MOSFET Parameters

Large-Signal Operation

Quantity Formula

Drain current (saturation region)

Drain current (triode region)

Threshold voltage

Threshold voltage parameter

Oxide capacitance

2

tgsox

ds ) - VV(L

W

2

μC I

] - VV) - VV(2[L

W

2

μC I

2

dsdstgsox

ds

]φ2 - - Vφ2[γ V V fsbf0tt

A

ox

Nq2C

1 γ

ο

ox

2

ox

oxox A 100 tfor mfF 45.3

t

ε C



Large-Signal Operation

Quantity Formula

Top-gate transconductance

Transconductance-to-current ratio

Body-effect transconductance

Channel-length modulation parameter

Output resistance

L

WCI2 ) - VV(

L

WμC g oxDStGSoxm

tGSDS

m

- VV

2

I

g

mm

SBf

mb χg g V φ22

γ g

DS

d

effA dV

dX

V

1

V

1 λ

1

DS

d

DS

eff

DS

odV

dX

I

L

λI

1 r


Quantity Formula


Effective channel length

Maximum gain

Source-body depletion capacitance

Drain-body depletion capacitance

Gate-source capacitance

Transition frequency

dddrwneff X - 2L - L L

tGS

A

tGS

omV - V

2V

V - V

2

λ

1 rg

0.5

0

SB

sb0sb

ψ

V 1

C C

0.5

0

DB

db0db

ψ

V 1

C C

oxgs WLC3

2 C

gbgdgs

mT

C C C2π

g f


Parameter

(Level 2 model) Enhancement Depletion Units

VTO 1.14 -3.79 V

KP 37.3 32.8

GAMMA 0.629 0.372

PHI 0.6 0.6

LAMBDA 3.1E-2 1.00E-6

CGSO 1.60E-4 1.60E-4 width

CGDO 1.60E-4 1.60E-4 width

CGBO 1.70E-4 1.70E-4 width

RSH 25.4 25.4

CJ 1.1E-4 1.1E-4

MJ 0.5 0.5

CJSW 5.0E-4 5.0E-4 perimeter

MJSW 0.33 0.33

TOX 544 544

2μA/V

21

V

1V

fF/

fF/

fF/

Ω/

2pF/μ

2pF/μ

SPICE MOSFET Model Parameters of A Typical

NMOS Process (MOSIS)

V


(Level 2 model) Enhancement Depletion Units

NSUB 2.09E15 1.0E16

NSS 0 0

NFS 1.90E12 4.3E12

TPG 1 1

XJ 1.31 0.6

LD 0.826 1.016

UO 300 900

UCRIT 1.0E6 0.805E6

UEXP 1.001E-3 1.001E-3

VMAX 1.0E5 6.75E5 m/s

NEFF 1.001E-2 1.001E-2

DELTA 1.16 2.80

The SPICE parameters: Empirical parameters

Fitting measured device characteristics to the mathematical equations

Using a numerical optimization algorithm

This approach gives good fit to the model but causes a deviation from the typical parameters.

Parameter relationships may not be self-consistent with some of the fundamental relationships.

31/cm

21/cm

21/cm

s)/(vcm2 V/cm

SPICE MOSFET Model Parameters of A Typical

NMOS Process (MOSIS) (Cont.)

*Please refer to the chapters about SPICE model in the HSPICE document suggested in assignment 1


Appendix

Resistance Estimation

Capacitance Estimation

Inductance Estimation

APP2-1


Resistance Estimation

Sheet Resistance

R=ρL/A=ρL/tW= R□L/W

R□=ρ/t

/ ,ohm/squareresistancesheet :

widthconductor :W

lengthconductor :L

s thicknes:t

yresistivit :

t

W

L

Current

R□ □

APP2-2


Resistance Estimation (cont.)

Typical sheet resistance for conductors

Material Min. Typical Max.

Intermatal

(metal1-metal2)0.05 0.07 0.1

Top-metal(metal3) 0.03 0.04 0.05

Polysilicon 15 20 30

Silicide 2 3 6

Diffusion(n+, p+) 10 25 100

Silicided diffusion 2 4 10

N-well 1K 2K 5K

APP2-3


Resistance Estimation of Nonrectangular Shapes

Direct estimation

Table-assisted estimation

R = L/WL

W

L

R = L/WW

Current

Current

W2

W1

L4L

R = L + 4W1

W1

W2

L2L

R = L + 2W2

C

W2W2

W1W1

W1RATIO =

W2W1

W1W2

W2

B

W1RATIO =

W2

W1

W1

W2

E

W2RATIO =

W1

L

W

A

LRATIO =

W

W1

W2

D

W1

W2RATIO =

W1

W2

Shape Ratio Resistance

A 1 1

A 5 5

B 5 5

B 1 2.5

B 2 2.55

B 3 2.66

C 1.5 2.1

C 2 2.25

C 3 2.5

C 4 2.65

D 1 2.2

D 1.5 2.3

D 2 2.3

D 3 2.6

E 1.5 1.45

E 2 1.8

E 3 2.3

E 4 2.65

APP2-4


Contact and Via Resistance

Proportional to the area of the contact

e.g. feature size↓ =>Rcontact↑

0.25Ω ~ a few tens of Ωs

Multiple contacts to obtain low-resistance interlayer connections

APP2-5


MOS-Capacitor Characteristics

C-V plot

Accumulation region

1.0

accumulation depletion inversion

low frequency

high frequencyCmin

0 VtVgs

Three regions in the plot

(i)Accumulation region

(ii)Depletion region

(iii)Inversion region

- - - - - - - - - - - - - - -Co

gategate Vg< 0

tox

p-substrate

+ + + + + ++ +

++

+

+

+

+

+

areaunit per ecapacitanc gate :t

εεC

area gate :A

space free ofty permittivi :ε

)9.3(SiO ofconstant dielectric :ε

ecapacitanc :C

ACAt

εεC

ox

oSiO

ox

o

2SiO

o

ox

ox

oSiO

o

2

2

2

gate

APP2-6


MOS-Capacitor Characteristics (cont.)

Depletion region

Inversion region

surface and gatebetween

ecapacitancfrequency low is C Where

areaunit per ecapacitanc gate :CC

CCC

)12(Si ofconstant dielectric :ε

depthlayer depletion :d

CAd

εεC

o

depo

depo

gb

Si

oxoSi

dep

gate

Cdep

Vth > Vg > 0

tox

p-substrate

+

+

+

+

depletion layerCo

gate

+ +

+

d

gbC 100Hz)frequency, low (i.e. static :Co

frequency)high (i.e. dynamic :CCC

CCmin

depo

depo

3-15-3-14-

omin

O

ox

dep

min

cm105 tocm101 from riesdensity va doping substratefor

0.3~0.02 from varies/CC,A200~100For t

density. doping substrateon depends i.e.

region,depletoin theofdepth on the depends C

C

gate Vg > Vth

tox

p-substrate++

depletion layer

+

d

+ + + + + + + + + + + + + +

channel

+

--- -

--- -

--

Co

gate

Cdep

APP2-7


MOS Device Capacitance

Cross section of MOS device

Equivalent circuit

GATE

tox

Cgs Cgb

CdbCsb

Cgd

SOURCE CHANNEL

DEPLETION LAYER

SUBSTRATE

DRAIN

Cgs

Cgd

Csb

Cdb

Cgb

GATEDRAIN

SOURCE

SUBSTRAT

E

d

g

s

b

APP2-8


Approximation of gate capacitance

MOS Device Capacitance (cont.)

Self-aligned process is assumed (i.e. overlap caps. are negligible)

Parameter off Non-saturated Saturated

Cgb

Cgs

Cgd

Cg=Cgb+Cgs+Cgd A

A

A

tox

2tox

2tox

0 0

0(finite for short channel devices)

A

A

0

tox

0

tox

A A 2 0.9

tox3tox

(short channel)

A 2

3tox

APP2-9


Cgs,Cgd and Cox

Example 1: W=49.2 m, L=4.5 m (long channel)

Cgs and Cgd

1.0

0.8

0.6

0.4

0.2

0.0

1 2 3 4 5

Cgs , Cgd

CoxWL

Vgs - Vt

Vds (volts)

Cgs

Vgs - Vt

Cgd

＊large Cg & small

Cgd (in saturation

region)

Cgd

Cg

(Cgd is due to

channel side

fringing fields

between

gate and drain.)

0

large L

1

23 4 5

1

2

34

5

APP2-10


Cgs,Cgd and Cox (cont.)

Example 2: L=0.75 m (short channel)

Cgs and Cgd

0.8

0.6

0.4

0.2

0.0

1 2 3 4 5

Cgs , Cgd

CoxWL

Vgs - Vt

Vds (volts)

Cgs

Vgs - Vt

Cgd

＊small Cg & small

Cgd (in saturation

region)

Cgd

Cg

(Cgd is due to

channel side

fringing fields

between

gate and drain.)

0.2

small L

1 2 3 4 5

1

2

34

5

APP2-11


Cox, gate capacitance per unit area

Cox =

Unit transistor

It is the same width

as a metal-diffusion

contact

Minimum-size transistor

223-

ox

o

ox

14

oSiO

ox

oSiO

1fF/μfpF/μF101 C A 350 te.g.

108.854ε and 3.9ε where;A t

εε

2

2

2

5

4W

L

2

5

W

L

4

APP2-12


Diffusion Capacitance

Area and periphery

Cd=Cja*(ab)+Cjp*(2a+2b)

Cja: junction capacitance per μm2

Cjp: periphery capacitance per μm

a: width of diffusion region

b: length of diffusion region

Typical value (1μm n-well process)

Cja: 2*10-4pf/μm2 (n+ diffusion)

5*10-4pf/μm2 (p+ diffusion)

Cjp: 4*10-4pf/μm2 (n+ diffusion)

4*10-4pf/μm2 (p+ diffusion)

Voltage dependent

m

b

j

j0jjV

V1CVC

C jaC jp

poly

Diffusion

Areaa

b

junction abrupt0.5

junction graded0.3m

ecapacitanc bias zero is C

0.6V~potential junction in-built is V

voltage junction is V

j0

b

j

~

APP2-13


SPICE Modeling of MOS Capacitances

SPICE example

.

.

.....

0.7PB 0.3MJSW 0.5MJ 400PCJSW 200UCJ

600PCGDO 600PCGSO 200PCGBO

8-100E TOX

NMOS NFET .MODEL

.

.

11.5UPD 11.5UPS 15P AD15P AS1UL 4U WNFET 0 5 3 4 M1

.

m1length channel

m11.5PDperiphery drain m4 widthchannel

m11.5PSperiphery source substrate-node0

m15 ADarea drain source-node5

m15 ASarea source gate-node3

A100TOX drain-node4o

2

2

F/M10600.transistor the of structure

physical the in overlap to due ecapacitanc

insource/dra-to-gate the representC andC

F/M10200channel. the beyond

extesion npolysilico the to due occoursC

12-

gdo gso

12-

gbo

APP2-14


SPICE Modeling of MOS Capacitances (cont.)

Capacitance

MJSWMJ

jj

c)g(extrinsic)g(intrinsig(total)

444

gb0gd0gs0c)g(extrinsi

4

OXc)g(intrinsi

PB

VJ1CJSWperiphery

PB

VJ1CAreaC

ecapacitanc drain and source

0.02PFCCC

0.0052PF

PF1021210641064

C2LCWCWC

0.014PFPF103514CLW C

ecapacitanc gate

assumed is2.5V VJ0.0043PFC

assumed is2.5V VJ0.0043PFC

drain or source the ofperiphery the PD, or PS Periphery

drain or souce the of area the AD,or ASArea

0.8volts-0.4~ voltage in-built the PB

potential junction the VJ

sidewall junction the of tcoefficien grading the MJSW

bottom junction the of tcoefficien grading the MJ

periphery junction per ecapacitanc bias-zero the CJSW

area junction per ecapacitanc bias-zero the C

where

j(source)

j(drain)

j

APP2-15


Routing Capacitance

Single wire capacitance

Parallel-plate effect and fringing effect

Accurate capacitance evaluation : use computer

Hand calculation : use simple model (less than 10% error)

W L

HT

Insulator(Oxide)

Fringing field

Substrate

Half cylinders

t

hw

Parallel plate

0.50.25

h

t1.06

h

w1.060.77

h

wεC

APP2-16


Routing Capacitance (cont.)

Multiple conductor capacitances

Three-layer example

Capacitance calculation is very complex—refer to textbook

Typical dielectric and conductor thicknesses

c23

c21

c22

layer3

layer2

layer1

oo

1

oo

o

21

o

oo

A20000 nPassivatio A6000 oxidepolyM

A12000 Metal2 A3000 nPolysilico

A6000 oxide MM A6000 oxideField

A6000 Metal1 A200 oxideThin

APP2-17


Distributed RC Effects

Transmission line

Delay time from one end to the other end

Substrate

conductor layer

isolation

layer

l

wire theoflength :l

lengthunit per ecapacitanc:c

lengthunit per resistance:r

l2

rct 2

APP2-18


Distributed RC Effects (cont.)

Disadvantages of long wire:

Long delay

Reduction in sensitivity to noise

t0 t0t1

t0t1

t2

t2

APP2-19



Method to improve disadvantages mentioned previously

g

rc

2 τ

2

rcl

possible, if design, actualIn

used be should buffers more ,2

rcl If

reduced is delay time ,4

rcl If

4

rcl

2

l

2

rc

2

l

2

rcdelay

g

g

2

g

2

g

2

g

2

2

g

2

l

APP2-20



Transmission line effect is particularly severe in poly wire because of

the relatively high resistance of this layer. Gate poly layer is the worst

one because of its high capacitance to substrate.

Strategies

Use metal line : small r

Use wider metal for signal distribution line

(e.g. clock distribution line) : small r, a tiny bit large C

APP2-21


Inductance

On-chip inductance are normally small.

Bond-wire inductance is larger.

Inductance of bonding wires and the pins on packages

Inductance of on-chip wires

wirethe of diameter the:d

plane ground the above height the :h

H/cm)101.257 (typically

wirethe ofty permeabilimagnetic the

H/cm d

4hln

2L

8-

:

substrate the above height the :h

widthconductor w

H/cm 4h

w

w

8hln

2L

:

APP2-22

Documents

Semiconductor Devices and Models - NCKU