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8WayneWolf

3

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4

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8WayneWolf dev1 dev2

enq

ack

data

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8WayneWolf

time

enq

ack

data

1

2

3

4

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8WayneWolf time

A

B

C

zero

one

rising falling

stable

changing

10 ns

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2008WayneWolf

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

(Used by Timer_B) TxSSELx IDx MCx - TxCLR TxIE TxIFG

Bit Description

9-8 TxSSELx Timer_x clock source: 0 0 TxCLK0 1 ACLK1 0 SMCLK1 1 INCLK

7-6 IDx Clock signal divider: 0 0 / 10 1 / 21 0 / 41 1 / 8

5-4 MCx Clock timer operating mode: 0 0 Stop mode0 1 Up mode1 0 Continuous mode1 1 Up/down mode

2 TxCLR Timer_x clear when TxCLR = 1

1 TxIE Timer_x interrupt enable when TxIE = 1

0 TxIFG Timer_x interrupt pending when TxIFG = 1

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MCx Mode Description

0 0 Stop The timer is halted.

0 1 Up The timer repeatedly counts from 0x0000 to

the value in the TxCCR0 register.

1 0 Continuous The timer repeatedly counts from 0x0000 to

0xFFFF.1 1 Up/down The timer repeatedly counts from 0x0000 to

the value in the TxCCR0 register and

back down to zero.

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SMCLK .set 1200000 ; 1200000 clocks / secondTIME_1MS .set 1000 ; 1 ms = 1/1000 s

TA_CTL .set TASSEL_2+ID_0+MC_1+TAIE ; SMCLK, /1, UP, IETA_FREQ .set SMCLK/TIME_1MS ; clocks / 1 ms

clr.w &TAR ; reset timerA mov.w #TA_CTL,&TACTL ; set timerA control reg mov.w #TA_FREQ,&TACCR0 ; set interval (frequency) bis.w #LPM0+GIE,SR ; enter LPM0 w/interrupts jmp $ ; will never get here!

TA_isr: ; timer A ISR bic.w #TAIFG,&TACTL ; acknowledge interrupt; reti

.sect ".int08" ; timer A section

.word TA_isr ; timer A isr

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2008WayneWolf

host CPU watchdogtimer

interrupt

reset

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RESET:

mov.w #0x0300,SP ; Initialize stack pointer

mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT

bis.b #0x0f,&P1DIR ; Set P1.0-3 output

mov.w #0,r14

...

passwd = 0x5A

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2008WayneWolf

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2008WayneWolf

row

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2008WayneWolf

R

2R

4R

8R

bn

bn-1

bn-2

bn-3

Vout

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2008WayneWolf

encoder

Vin

...

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2008WayneWolf

Vin timer

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08WayneWolf

converterVin