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Selection and Design of High performance Frequency Synthesisers

Project submitted in partial fulfilment of the requirements for the degree of

Bachelor of Engineering

02 June 2014

Revision 2 (Final)

Faculty of Sciences, Engineering and HealthCentral Queensland University

RockhamptonAustralia

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Table of ContentsExecutive Summary..............................................................................................................................4Background...........................................................................................................................................5Project Goals........................................................................................................................................ 6Scope of Work...................................................................................................................................... 7Conditions for Success......................................................................................................................... 7Literature Review................................................................................................................................. 8Investigation of Existing Transceiver architectures........................................................................... 10

Yaesu FRG-7..................................................................................................................................10Yaesu FT-101................................................................................................................................. 12Kenwood TS-450........................................................................................................................... 13Digital Bluetooth Transceiver........................................................................................................15WLAN Direct-Conversion Transceiver......................................................................................... 17

Block-level design of project..............................................................................................................192nd IF Bandpass Filter...................................................................................................................192nd LO........................................................................................................................................... 201st IF Bandpass Filter.................................................................................................................... 201st LO............................................................................................................................................ 20

Detailed Local Oscillator Design....................................................................................................... 222nd LO........................................................................................................................................... 22

Crystal Oscillator...................................................................................................................... 22Temperature Compensation...................................................................................................... 24Frequency Doubler....................................................................................................................24

1st Local Oscillator........................................................................................................................28Integer N PLL........................................................................................................................... 28Fractional N PLL...................................................................................................................... 29DDS...........................................................................................................................................29Proposed Architecture............................................................................................................... 31Detailed Design.........................................................................................................................34

DDS & Postfilter.................................................................................................................. 34DDS Clock Oscillator...........................................................................................................37

VCO Design..............................................................................................................................38PLL Section...............................................................................................................................42

Phase Detector Frequency.................................................................................................... 42Settling Time........................................................................................................................ 43Loop Bandwidth................................................................................................................... 43

Conclusion..........................................................................................................................................47Resources & Schedule of Work..........................................................................................................48Implementation Work Schedule......................................................................................................... 51Budget and Resources........................................................................................................................ 54References.......................................................................................................................................... 55Reflective Paper..................................................................................................................................57Risk Assessment..................................................................................................................................60

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List of FiguresFigure 1: FRG-7 Block Diagram (Yaesu, 1974).................................................................................11Figure 2: Yaesu FT-101 Block Diagram (Yaesu corporation 1976)................................................... 12Figure 3: Kenwood TS450S Block Diagram (Kenwood corporation, 1992)..................................... 15Figure 4: All-Digital Bluetooth Transceiver Block diagram (Staszewski et al, 2004).......................16Figure 5: Direct-Sampling Bluetooth Receiver (Staszewski et al, 2004)...........................................16Figure 6: Direct-Conversion WLAN Transceiver (Zhang et al).........................................................18Figure 7: Proposed Transceiver Architecture..................................................................................... 19Figure 8: Frequency Allocations for System...................................................................................... 20Figure 9: Pierce oscillator topology (Carr, 2002)...............................................................................23Figure 10: Temperature Compensated Pierce Oscillator.................................................................... 24Figure 11: LO2 Full Schematic.......................................................................................................... 26Figure 12: LO2 Simulated Output Waveform.................................................................................... 27Figure 13: LO2 Simulated Output Spectrum......................................................................................27Figure 14: Integer N PLL Block Diagram (Texas Instruments 1999)................................................ 28Figure 15: Basic DDS Architecture (Analog Devices Inc 1999).......................................................30Figure 16: Proposed LO1 Synthesiser Configuration........................................................................ 32Figure 17: 0.01dB ripple Chebychev Filter Attenuation Curves for different values of n (Bowick, 1997)...................................................................................................................................................36Figure 18: DDS Post-Filter Circuit.....................................................................................................37Figure 19: DDS Post-Filter Frequency Response.............................................................................. 37Figure 20: Colpitts Oscillator Circuit................................................................................................. 38Figure 21: Colpitts Oscillator Output Waveform............................................................................... 39Figure 22: VCO Tuning Curve........................................................................................................... 40Figure 23: VCO Circuit with Amplifier............................................................................................. 40Figure 24: Amplified VCO Output Waveform................................................................................... 40Figure 25: Predicted VCO Phase Noise............................................................................................. 42Figure 26: PLL Section Schematic..................................................................................................... 45Figure 27: Simulated Phase Noise of Synthesiser..............................................................................45Figure 28: Simulated PLL PFD Spur Level....................................................................................... 46

List of TablesTable 1: Comparison of Oscillator Characteristics (Mancini 2004)...................................................22Table 2: Normalised component values for 5th order Chebychev filter.............................................36Table 3: Actual component values for 5th order Chebychev filter.....................................................36Table 4: VCO Phase Noise Parameters.............................................................................................. 41Table 5: PLL Parameters.................................................................................................................... 44

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Executive Summary

This report will document the design process undertaken to design a high performance local oscillator frequency synthesiser system for use in a HF radio transceiver. The selection of the overall synthesiser architecture will be provided along with an in-depth discussion on the low level design aspects of the system.

In this report a number of commercially produced transceivers will be analysed to determine the relative advantages and disadvantages presented by their different architectures. Additionally a number of transceiver designs developed by the academic sector will be investigated to gain an insight into the types of radio signal processing techniques used in today's leading-edge transceiver technology. A brief outline of the operating principle behind each of these designs will be provided and the characteristics of each will be discussed.

The concepts presented by past and present transceiver designs will then be used to develop a new architecture that seeks to deliver high performance while minimising cost. Specifications for a system-level design will be generated that gives the performance requirements and operational characteristics needed for each sub-component in the system. Various potential solutions for the design of each sub-component will be investigated, followed by a detailed design for each.Complete electrical schematics will then be developed that are to be used during the prototyping stage of the project. Finally the system presented in the report will be simulated to ensure that it is able to meet the defined performance goals for the project.

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BackgroundMost modern radio transceivers are based on the superheterodyne principle and therefore require some form of local oscillator (LO) signal. In more recent years the trend has been to move away from traditional single-conversion superheterodyne architectures toward double and even triple conversion designs that require two and three LO signal sources respectively. The performance of these local oscillators is one of the most critical aspects of transceiver design because it is the LO that defines the frequency stability and spectral cleanliness characteristics of a transmitter's output signal. Additionally the LO performance has a substantial effect on the stability and weak signal sensitivity of a receiver. Therefore when setting out to design a transmitter or receiver one must pay particular attention to the design of these LO signal sources if a high quality end-product is desired.

Commercially produced HF radio transceivers have historically used a number of different local oscillator systems ranging in complexity from free-running LC oscillators to advanced synthesiser designs involving multiple PLLs. However local oscillators using the more complex and higher performing synthesiser types have typically been used only in the more high-end transceiver designs due to their higher cost and greater power consumption. This means that in general the radios produced for the low-end and portable-radio markets have had to use the cheaper or low power options for their LO systems, resulting in a compromise in the performance of the device.

This means that low-cost transceivers or those designed for portable applications have generally had somewhat worse performance when compared to the more expensive devices on the market. Radios that use the lower performance “budget” LO systems typically suffer from afflictions like poor phase noise performance, excessive spurious signal content in the transmitter output, high numbers of “phantom signals” (better known as “birdies”) across the receiver's tuning range, poor frequency stability or slow channel hopping speed. Over the years many low-cost synthesiser topologies have been designed in an attempt to alleviate these problems, but most solutions have been based on trade-offs where solving one of the above conditions only exacerbates another. Therefore there is a significant performance gap between the high-end transceivers and the low-cost alternatives that still exists even in today's products.

What the market needs is a LO synthesiser system that delivers the performance typically seen in the high-end transceivers, but at a cost that makes it suitable for use in even the most low-end radios.

This project has therefore been instigated to address the problem of designing such a LO system. The synthesiser produced in this project will see use in a high frequency (HF) radio transceiver construction project that is currently being undertaken. In general the project seeks to design two local oscillator signal sources to be used as building blocks for the transceiver that will meet a pre-defined set of performance goals at a minimal cost.

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Project GoalsAs mentioned previously, the frequency synthesisers that will be developed in this project are intended to be used as the core building blocks of a HF radio transceiver. As such there are a number of constraints that will be applicable to the design. The proposed synthesiser will have to comply both with the standards set by the Australian Communications and Media Authority (ACMA) and with the additional performance requirements described later in the report.

The primary regulation set by the ACMA that will be applicable to this project is the spectral cleanliness and spurious emissions requirement. The ACMA has adopted the International Telecommunications Union recommendations for spurious emission requirements which state that a amateur radio transmitter operating under 30MHz must attenuate spurious emissions by 43+10Log(PEP)dB or 50dB, whichever is less stringent (ITU 2003, p.107). However due to the fact that this transceiver may eventually serve as an exciter for a microwave frequency transmitter it must adhere to the regulations for these higher frequencies. The ITU recommendations state that for this application a spur attenuation of 43+10Log(PEP)dB or 70dB will be required, whichever is less stringent (ITU 2003, p107). For this reason a design goal of 70dB attenuation will be used to ensure the project complies with the regulations regardless of what frequency or power level it will be used at. To achieve this goal the frequency synthesisers designed in this report will need to have exceptionally low levels of spurious signal content.

Aside from the above regulatory requirements a number of additional key performance requirements are desired. These include:

• Transceiver frequency coverage from 0Hz to 35MHz• Continuous frequency coverage with no gaps• Minimum tuning resolution of 1Hz• Absolute frequency accuracy of +/- 100Hz• Short term frequency drift of less than 10Hz per hour (after warmup)• Minimal power consumption

While these technical constraints apply to the project, a number of other constraints will also be applicable. The major non-technical constraint is that this project is part of an Engineering Project Planning course and is therefore subject to limitations on the resources that will be available through CQ University. Additionally there will be a limit on the level of detail that can be put into this report. During the second project implementation phase of the project the manufacturing facilities available at CQ University will place limitations on what prototypes can and cannot be built. The laboratory facilities at CQUniversity are not well equipped with the specialised test equipment needed to develop radio frequency electronic circuits. This will make it difficult to prototype the project design during the implementation phase and will be an incentive to keep the operating frequencies used in the design as low as possible.

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Scope of WorkThe deliverables of this phase of the project will be limited to the detailed design of the synthesiser system. Complete schematic diagrams for each part of the proposed design will also be provided in this report as well as simulation data to verify the design. During the second phase of the project the system will be prototyped and the actual performance achieved by the design will be measured.

Conditions for SuccessThis project will be successful if and only if a frequency synthesiser system can be developed that meets the design goals and constraints listed above. The overall success of the project as a whole will depend on whether or not the physical prototype synthesiser constructed in phase 2 of the project meets the design goals, however for the purposes of this phase of the project success will be achieved if the proposed design meets the goals based on theoretical performance figures and on the results of simulations.

The process undertaken during this project can be summarised as follows: First a global architecture for the transceiver will chosen to allow the relative arrangement of frequencies for each of the local oscillator sources to be determined. Next a specific frequency or tuning range and general performance requirements will be allocated to each system sub-section to provide well defined design goals for each. Finally, a number of possible solutions for each block in the system's architecture will be assessed and a final design will be generated that will meet the aforementioned design goals.

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Literature ReviewWhat is a frequency synthesiser?Frequency synthesisers, as their name suggests, are used to generate some form of signal of a specific frequency and/or phase. Generally speaking, the task of a synthesiser is to take a known, fixed frequency signal and transform it by various means to create a new signal with more desirable properties.

In times gone by radio transmitters and receivers were controlled by simple free-running oscillators. These oscillators were often plagued by frequency drift which made narrow-band communications extremely difficult during that era. What was needed was some form of tuneable yet stable signal source. The concept of the frequency synthesiser was developed to fill this role.

Initially synthesisers were based on the concept of direct analog synthesis where signals from multiple highly accurate crystal oscillators were multiplied, divided, added and subtracted from one-another in a number of ingenious ways to obtain the desired output frequency. In theory this allowed a wide number of frequencies to be generated from only a few master oscillators. However due to the reliance on analog signal processing circuitry it is generally quite difficult to change the output frequency of synthesisers based on this principle after they have been built. Therefore the concept does not lend itself well to situations where the user needs to be able to freely choose from a large number of output frequencies. Additionally, due to the large number of processing steps sometimes required in the signal chain this direct analog synthesis technique will often require substantial amounts of power to operate. Therefore in the modern world where flexible, low power synthesisers are desired this archaic analog synthesis technique is practically extinct, except in a small number of niche applications.

As technology progressed newer synthesiser architectures were developed. One of the earliest “modern” synthesiser types to be used was the phase-locked-loop. This invention allowed the previously unstable, free-running, oscillators to be locked to an arbitrary frequency multiple of a precision master oscillator. The breakthrough with this design was that the particular multiple the oscillator was locked to could be easily changed by re-programming a small amount of digital logic. This opened up the possibility of using a single master oscillator to generate a virtually unlimited number of freely-selectable output frequencies.

However, in the early days of it's development the technology required for a practical implementation of the PLL was still in it's infancy. The integrated circuits available during this era were limited in their functionality and operating speed, resulting in PLLs produced during this period suffering from excessive levels of phase noise, spurious signal content and loop instability. In modern times the science of integrated circuit design has made remarkable progress with faster, higher performance devices being produced each year. This allows the creation of modern PLL based synthesisers with excellent performance characteristics.

In the years since it's inception much has been written on the subject of PLL design. In fact during the research phase of this project it was discovered that almost all of the major semiconductor manufacturers have at one stage provided some form of application note or tutorial on the design of phase locked loop synthesisers. Throughout this report these application notes and tutorials have been invaluable in guiding the design of the project's synthesiser and in educating the author on the finer points of PLL design.

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Additionally, during research for this project a large amount of information was found that relate to other essential aspects of synthesiser design, such as the occurrence and effects of phase noise on a PLL, the design and simulation of voltage controlled oscillators as well as documentation on the control theory applicable to synthesiser design.

Texas Instruments is one of the semiconductor manufacturers who have provided a number of in-depth application notes on PLLs covering topics such as loop filter design, stability assessment and the prediction of spurious signal levels in the output. Furthermore the approach used when designing PLLs have been published in many texts. Examples include “RF Circuit Design” by C. Bowick, and “RF Components and Circuits” by J. Carr which were both referred to during this project.

More modern synthesiser architectures such as the Direct Digital Synthesis approach have been well documented in many publications ranging from application notes and tutorials to books such as “Microwave and Wireless Synthesisers: Theory and Design” by U. Rhode.

As technology has improved over the years more advanced synthesiser designs have been developed. Many research papers have been published which detail transceiver designs using synthesisers much more innovative and complex than the traditional types. One such paper published by Staszewski (et al) describes a transceiver that incorporates modern digital-signal-processing techniques into the design. This transceiver takes the concept of the traditional PLL synthesiser and adds a modern angle to it by utilising a digitally controlled VCO, phase detector and loop filter. This results in a fully self contained, all-digital synthesiser solution that represents a new direction in synthesiser design. The paper gives just one small insight into the range of advanced synthesiser and radio transceiver architectures that can be produced with modern semiconductor technology.

However, despite there being an ocean of information available on the design of individual segments of a frequency synthesiser, it was apparent that very little has been written on the larger systems-level design process. Information on the process of designing the entire synthesiser system to meet a finite set of performance goals has been relatively sparse, which makes the task of choosing what particular synthesiser architecture to use for a given application rather difficult. This project will investigate the design of a synthesiser from the ground up, focusing on not only the design of each component of the system, but also on the effect each will have on the system as a whole. A number of different topologies of synthesisers will be assessed on their suitability for the project and the relative strengths and weaknesses of each will be discussed.

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Investigation of Existing Transceiver architecturesThe global level architecture of the transceiver project has not been defined and as such it will be possible to freely choose a design that best allows the goals of this project to be met. Existing radio transceivers are constructed with a variety of different global architectures, each having their own advantages and disadvantages. The goal of this section will be to develop an architecture that combines the best aspects of existing designs while minimising any disadvantageous characteristics.

To gain an understanding of the types of synthesisers historically utilised for receivers and transmitters it will be advantageous to analyse the design of a few of the more popular commercially produced radios. Among the more popular devices that will be analysed are the Yaesu FRG-7, Yaesu FT-101 and the Kenwood TS-450. Each of these radios are based on a different configuration of local oscillators but each design encounters a differing set of challenges and constraints. After reviewing the characteristics of these traditional architectures an appropriate starting point will be chosen for the architecture used in this project.

Yaesu FRG-7

The classic FRG-7 is a all-band communications receiver that was commercially manufactured from the mid 1970s to the late 1980s. It is a triple-conversion superheterodyne type receiver that uses a highly unusual LO design. The LO system used in the FRG-7 is formally known as the Wadley loop and was the solution to the problem of frequency drift that was common in the days before phase-locked-loop technology was established. The block diagram of the FRG-7 is shown below.

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Figure 1: FRG-7 Block Diagram (Yaesu, 1974)

The underlying principle of the Wadley loop is very similar to the concept of vernier-tuning where rough, megahertz-scale tuning is done using one oscillator, and finer tuning is accomplished using a secondary oscillator (Yaesu corporation 1974). The Wadley architecture has the advantage that any frequency drift present in the primary LO (MHz set oscillator in the diagram) is cancelled out, resulting in a receiver that covers the very wide frequency range from 500KHz to 30MHz with reasonably low levels of frequency drift, while retaining the ability to do so in a semi-continuous manner with no gaps in the frequency coverage. However, the frequency stability of this system is still dependant on that of the low frequency, secondary VFO (kHz set oscillator in the above diagram)(Yaesu corporation 1974). The system will have a frequency stability and accuracy no better than this free-running oscillator, which means that

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despite being a novel concept the Wadley loop will not meet the project's frequency stability requirements and therefore makes the concept unsuitable as the basis of the synthesiser design for this project.

Yaesu FT-101

The Yaesu FT-101 is another classic transceiver that was manufactured in the 1970s and 1980s which featured coverage of most of the amateur radio bands and the ability to use SSB, AM and CW modes. The FT-101 utilises a more straight-forward architecture based on the double conversion superheterodyne principle. A simplified block diagram of the signal chain used in this transceiver is shown below.

Figure 2: Yaesu FT-101 Block Diagram (Yaesu corporation 1976)

A summary of the operation of this transceiver is as follows: First, the incoming signals are mixed with a fixed frequency crystal oscillator to select a single band and convert it to an intermediate frequency of 5.77MHz. The resulting IF signal is passed through a 500KHz wide IF filter, then mixed with a second local oscillator signal that can be varied from 8.7-9.2MHz. This converts the signal to a second IF frequency of 3.18MHz. A selectable bank of second-IF filters at this frequency provides the receiver's selectivity characteristics, and by selecting the appropriate filter the bandwidths required for the SSB, CW and AM modes can be provided.

The primary feature of this architecture is that is based on the concept of down-converting each discreet frequency band to a fixed IF frequency. This allows the use of relatively low frequency oscillators throughout the system, which inherently have better stability than those operating at higher frequencies (Da Silva 2001). This enables the design to achieve a quite respectable frequency stability of less than 100Hz drift in any 30 minute period (Yaesu corporation 1976). However this concept of down-converting each band to a common IF frequency can quickly become impractical when coverage of the entire HF spectrum is desired due to the potential overlap of RF and IF frequencies. It is therefore not well suited as the basis of this project's design.

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Kenwood TS-450

The TS-450 is a more modern transceiver that uses a different signal processing architecture to the previous two products. This radio's defining feature is that it uses a triple-conversion, up-converting superheterodyne architecture. Whereas the previous radios have their first IF at a relatively low frequency, the up-converting design of the TS-450 uses an IF frequency that is much higher than the range of received frequencies (Kenwood corporation 1992). This architecture has the benefit of permitting continuous coverage of the entire spectrum below the first IF frequency without the need for multiple switched local oscillators, while improving the IF feedthrough and LO leakage characteristics of previous designs. A simplified block diagram of the TS-450 signal chain is shown below.

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Figure 3: Kenwood TS450S Block Diagram (Kenwood corporation, 1992)

A summary of the operation of this radio is as follows: Fist the incoming signal is pre-selected by a bank of band pass filters, then mixed with the first variable high-frequency local oscillator signal. The resulting IF signal is then passed through a 73.05MHz roofing filter then mixed with the second local oscillator signal of 64.22MHz to create the second IF at 8.83MHz. After being further bandpass filtered the signal is mixed with a third local oscillator to translate it to an IF of 455KHz, and is then passed to the transceiver's demodulation circuitry. The most critical sections of this architecture are the first and second local oscillators. These two oscillators can be PLL disciplined to achieve a wide tuning range whilst maintaining excellent frequency stability. In fact the TS450 is specified to have a frequency error of no more than +-10PPM on all bands (Kenwood corporation, 1992).As mentioned earlier the ability of this up-converting design to tune the entire HF spectrum in one continuous sweep without having to use multiple switched oscillators makes it a very attractive option for applications where wideband tuning ranges and continuous coverage are desired.

Aside from the progress made in the commercial sector of transceiver design, the subject has also been further developed in academic studies. In recent year many innovative new architectures have been developed for radio-frequency devices. To gain further insight into the architectures that can be used in a radio transceiver design a number of academic research papers will be investigated.

Digital Bluetooth Transceiver

One such paper developed by Staszewski (et al) describes the design of an All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio. This device is intended to be used as a single-chip solution to provide a fully compliant bluetooth radio modem. The operating principle behind this device is vastly different to what has been traditionally used in radio transceivers because in this device most of the signal processing work is done in the digital discreet-time domain. The device operates by directly sampling the radio frequency waveforms using high-speed digital signal processing techniques then performing further processing in the digital domain. A block diagram of this transceiver chip is shown below.

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Figure 4: All-Digital Bluetooth Transceiver Block diagram (Staszewski et al, 2004)

The operation of the transmitter section of the device is relatively simple. A Digitally Controlled Oscillator (DCO) is used to generate a clock signal at the desired transmit frequency which is then coupled to a programmable amplifier and finally to the antenna. The frequency and phase of this oscillator is controlled via a digital phase locked loop. To modulate the transmitted signal with data the frequency of the DCO is rapidly changed, resulting in the desired bluetooth compatible FM signal.

However the most interesting aspect of this device is the receiver section. A block diagram of this is shown below.

Figure 5: Direct-Sampling Bluetooth Receiver (Staszewski et al, 2004)

The operation of this section is as follows; First the incoming signal is converted to a time-varying current, then after being split into two quadrature components it is sampled at a rate of 2400MS/s.

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The signal is low pass filtered then decimated by a factor of 8 to yield a signal at 300MS/s. Further filtering and decimation by 4 reduces the data rate to 75MS/s. Automatic gain control is then applied to the signal to amplify it to a consistent level, followed by more filtering and an additional stage of decimation to bring the final sample rate to 37.5MS/s. The resulting baseband signal is then passed to an analog to digital converter and finally to the bluetooth modem interface logic. The key feature of this receiver is that all of the high speed signal processing is done using discreet-time sampling circuitry. This design has the advantage of not requiring continuous time analog signal processing circuitry and can therefore eliminate some of the drawbacks associated with it. An additional advantage this new transceiver architecture brings is a substantial reduction in power consumption and because of the fully-integrated nature of the design great reductions in physical size can be achieved as well.

While the design is no doubt innovative, it does have it's drawbacks. The most significant of which is that it is capable of transmitting only frequency modulated signals and is therefore incapable of utilising more complex modulation schemes such as single-sideband or quadrature-amplitude-modulation. A further complication with the concept is that the direct-sampling receiver it uses is not well suited to application requiring many octaves of tuning range.

WLAN Direct-Conversion Transceiver

Another transceiver design has recently been developed by Zhang et al in a research paper published in the IEEE journal of solid state circuits. Their transceiver is based on a direct-conversion architecture and operates in the 5HGz ISM band. This device aims to provide a low-cost, low-power solution for wireless local area networking of computers and mobile devices. The direct-conversion architecture described in this paper operates on a similar principle to a standard single conversion superheterodyne radio, but with the main difference that an intermediate frequency of 0Hz is used. In receive mode this device operates by simply mixing the incoming RF signals with a local oscillator signal at the same frequency. This will create the usual sum and difference frequencies, of which the difference frequency is selected by the use of a low pass filter. Since the difference between the LO and RF signal frequencies is zero the IF signal will be comprised of baseband data centred at 0Hz which can be passed directly to the digital decoding logic. The operation of the device in transmit mode is equally simple. Two data streams, representing the in-phase and quadrature components of the transmitted signal, are mixed with the local oscillator signal to generate the final 5GHz modulated output. A block diagram of this architecture is shown below.

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Figure 6: Direct-Conversion WLAN Transceiver (Zhang et al)

There are many advantageous characteristics presented by this architecture. Due to the minimal number of high frequency signal processing stages the power consumption of the transceiver can be quite low – the device presented in the paper is specified as drawing only 171mW during receive and135mW on transmit. Additionally due to the simplicity of the circuit the device can be made extremely small.

However, this architecture also has it's drawbacks. The main characteristic that makes the direct conversion topology unsuitable for transceivers operating in the HF spectrum is it's inability to use high-Q filters with it's IF signal, thus limiting the design's ability to reject out-of-band interference. Additionally practical implementations of the design will often suffer from RF to IF leakage due to imperfections in the frequency mixer circuitry used. This can cause RF signals to leak into the IF sections of the receiver, causing spurious interference and in some cases causing overload of the downstream signal chain.

When the requirements of this project are compared against the characteristics provided by these different transceiver architectures it can be seen that the most sensible choice for this project will be to use a topology similar to the up-converting system used in the Kenwood TS-450. Therefore this project will be based on a double conversion superheterodyne type system with a first IF much higher than the frequency band of interest, followed by a second IF at a somewhat lower frequency.

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Block-level design of projectThe specific details of the design (such as IF and LO frequencies, VCO power levels etc) will be dictated by both the project's requirements and by the availability of parts. For this reason a block-level design of the system must first be proposed to allow the specifications of each sub-section to be developed. As discussed previously the system will be using the up-converting architecture with the block diagram therefore taking the following form.

Figure 7: Proposed Transceiver Architecture

Each of the blocks in this digram must meet it's own set of requirements regarding frequency range, power levels, dynamic range etc. To determine the required specifications for each block it will be worthwhile to start with blocks that have known constraints and work forward from there.

2nd IF Bandpass Filter

The first step in the process of allocating frequencies for the transceiver's architecture will be to select a suitable centre frequency for the 2nd IF filter. This will in turn dictate the frequencies chosen for the 2nd LO, 1st IF filter and finally the 1st LO. Since the completed transceiver must be able to be used for single sideband communications it will require that at least one of the IF filters have a bandwidth of 2-3KHz with sharp attenuation skirts outside the passband. These characteristics are most commonly achieved through the use of a multi-pole crystal ladder filter. Reviewing the literature relevant to the subject of crystal filter design it was determined that if typical ladder filter topologies were going to be used these characteristics would be obtainable if the filter is designed with a centre frequency of between approximately 4 and 11MHz (Steder & Hardcastle 2009). This is due to the fact that the bandwidth of the filter is proportional to the centre frequency and Q-factor of it's resonators. Since the Q of typical AT-cut crystals generally decreases with increasing resonant frequency, there is a certain range of frequencies where the crystal will have sufficient Q factors to allow a filter with the required characteristics to be constructed.Because the first IF frequency of this particular up-converting design must be higher than the frequency band of interest – ie above 35MHz – the narrowband SSB filtering cannot be done at the first IF and must therefore be done at the lower 2nd IF frequency. The choice of 2nd IF frequency must therefore fall in the 4-11MHz region as discussed above.

Due to availability of inexpensive 11.059MHz crystals it was decided that the 2nd IF filter will be constructed using these. The 2nd IF frequency will therefore be 11.059MHz.

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2nd LO

Working backwards toward the RF input port the next relevant block is the 2nd local oscillator. This device will be a fixed frequency oscillator that will drive the 2nd mixer. A few constraints will apply to the choice of this oscillator's frequency. The most significant constraint is that this frequency must be as low as possible for ease of construction, but must also be sufficiently far outside the frequency bands of interest to minimise the potential for unwanted signal leakage into other sections of the radio (which will cause spurious signals and interference). With transceiver coverage extending up to 35MHz the lowest possible LO2 frequency will thus be 35MHz, while the highest practical frequency will be limited by the ability to design effective oscillators and filters using the available parts. Additionally this oscillator must have excellent frequency stability and phase noise characteristics as these will directly affect the quality of signal passing through this section of the transceiver.

One of the constraints of the project is to minimise the power consumption of the design. Therefore in the interests of minimising the amount of power this section of the radio uses it was decided not to use a PLL based synthesiser and instead use a free-running oscillator instead. The simplest way to create a stable, low-VHF signal source without using a PLL is to use a crystal oscillator (Da Silva 2002, p.378). A plentiful supply of 27MHz crystals are available so these will be used to generate a 27MHz signal, which can then be doubled to generate an appropriate 2nd LO frequency of 54MHz.

1st IF Bandpass Filter

The choice of centre frequency for the first IF filter will be determined by the second local oscillator and second IF frequencies. The first IF must be at either LO2+IF2, or at LO2-IF2. This gives the choice of either 65.059MHz or 42.941MHz. As mentioned earlier lower frequency circuitry is easier to build and troubleshoot so the option of 42.941MHz will be chosen.

1st LO

The final block to consider is the first local oscillator. This is a variable frequency oscillator that will be tuned to select the desired receive/transmit frequency of the completed transceiver. Since the transceiver requires a frequency tuning range of DC-35MHz, this oscillator will have to tune from 0Hz+IF1 to 35MHz+IF1. More specifically this means that given an IF1 frequency of 42.941MHz this first LO must tune from 42.941MHz to 77.941MHz.

Now that the specifications of each of the blocks is known, the block diagram for the system can be updated as shown.

Figure 8: Frequency Allocations for System

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The operating principle of this architecture is as follows: When operating in the receive mode signals from the band of interest, with frequencies ranging from 0Hz to 35MHz, will enter the first mixer. Here they will be mixed with the first LO synthesiser signal to generate two signal components, one at the sum of the RF and LO frequencies and at the other at the difference of the two frequencies. If, for example, the transceiver is tuned to an RF signal at 0.1MHz the first local oscillator will be programmed to 43.041MHz. After being mixed by the 1st LO signal the RF signal will be split into two components, one at 43.141MHz (LO1+RF) and the other at 42.941MHz (LO1-RF). Similarly if the transceiver is tuned elsewhere, such as 35MHz, the 1st LO will be programmed to 77.941MHz. The result of the first stage of mixing will again be comprised of two signal components, this time at 112.941MHz and 42.941MHz. Regardless of what frequency the transceiver is tuned to one component will always be at 42.941MHz, while the other will be at LO1+RF.

In any scenario the 42.941MHz component will be selected by the 1st IF filter then mixed with the 2nd LO signal. This will again split the signal into two components, one will be at 96.941MHz (LO2+IF1) while the other will be at 11.059MHz (LO2-IF1). The 11.059MHz component is selected by the second IF filter and is then passed on to the demodulating circuitry elsewhere in the radio.

When the transceiver is switched into transmit mode the signal flow will be reversed. Signals will begin at the 2nd IF frequency of 11.059MHz, then be mixed with the 2nd LO to generate the usual sum and difference frequencies at 96.941MHz and 42.941MHz respectively. The 42.941MHz component is selected then mixed with the 1st LO synthesiser signal. The result of this last step will depend on what frequency the LO1 synthesiser is programmed to. If it is running at a frequency of 42.941MHz the sum frequency will be at 85.882MHz (LO1+IF1) while the difference frequency component will be at 0Hz. Conversely, if it is running at 77.941MHz the sum component will be at 112.941MHz an the difference will be at 35MHz. In transmit mode the difference frequency is able to be varied from 0Hz to 35MHz, allowing the transmitter to generate any frequency in this range. A 35MHz low pass filter (not shown) then removes the sum frequency while leaving the difference frequency intact. The 0-35MHz difference frequency is then passed to the transmitter's power amplifier, filter banks and finally to the antenna.

This shows that in both transmit and receive modes the architecture presented here is capable of taking any signal in the 0-35MHz range and converting it to the required 2nd IF frequency, and is capable of operating in the reverse direction by generating any frequency in the 0-35MHz range from the given IF2 frequency. Therefore the architecture will be able to meet the project goals for both tuning range and continuous coverage characteristics.

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Detailed Local Oscillator Design

2nd LO

Crystal Oscillator

The oscillator design that has been selected for the second LO is that of a fixed frequency crystal oscillator at 54MHz. The crystal-oscillator approach has been chosen for this signal source because oscillators based upon quartz resonators are able to provide very stable frequency characteristics, which is essential in this application. Since this oscillator will be a simple free-running crystal oscillator it will not be using any complex frequency synthesiser circuitry. As such the design of this oscillator is somewhat off-topic and the level of detail included in this section of the report will be kept brief.

Referring to the project specifications, the maximum frequency error allowable for the entire system is +/- 100Hz. From the explanation of how the transceiver architecture operates it can be seen that the output frequency of the transceiver depends on the linear addition and subtraction of the two local oscillator signals to or from the signal as it passes through the system. Therefore any frequency errors in either oscillator will add linearly to the overall system error. If both the first and second LOs are permitted to contribute equally to the total frequency error then the worst-case error of a single LO source must not be more than half of the 100Hz allowance - i.e. no more than 50Hz. For the second local oscillator with a nominal frequency of 54MHz this equates to an error of +/- 0.926ppm. The specific sub-type of crystal oscillator chosen must be able to meet this stability criterion. Many different sub-categories of crystal oscillator exist, the characteristics of each are summarised in the table below.

Table 1: Comparison of Oscillator Characteristics (Mancini 2004)

From this table it can bee seen that while a microcomputer-controlled crystal oscillator may easily be able to provide the required level of frequency stability, a temperature-compensated crystal oscillator also comes very close to being an acceptable solution while using fewer components and

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significantly less power.

Therefore the topology chosen for this oscillator will be of the TCXO type. Additionally, it can be seen in the block-level diagram that this oscillator must drive one of the frequency mixers in the system, and will therefore have certain power output requirements. The mixers have been specified as "class 2" passive diode ring types, which have a drive requirement of +13dBm. This LO will therefore have to provide at least +13dBm (20mW) of output power.

As mentioned in previous sections a large number of 27MHz crystal resonators are available which can be frequency doubled to yield the required 54MHz. The first step in designing this block will thus be to design a TCXO using these 27MHz crystals. For simplicity the design will be based around a pierce oscillator with active temperature compensation. Temperature compensation will be achieved by measuring ambient temperature with a NTC thermistor, generating an error signal based on this information and applying the result to a set of varactor diodes in the oscillator tank circuit to correct the error.

The first step in developing this oscillator will thus be to design a pierce oscillator using the available 27MHz crystals. The general topology of this type of oscillator is shown below.

Figure 9: Pierce oscillator topology (Carr, 2002)

The circuit used for this oscillator is based on the general pierce topology, however it has been modified in several ways. The crystal load capacitances (C2&C3 above) have both been set to 33pF to present a load of approximately 16.5pF (33pF/2) to the crystal, as recommended by the crystal manufacturer. The DC bias stability of the transistor has been improved by using a voltage divider arrangement to set the collector voltage to approximately 7.5v, removing the bias' dependence on transistor beta that is present in the above circuit. A collector voltage of 7.5V results in a 4.5V drop across the collector load resistance (R1), and therefore a transistor bias current of (4.5V/1Kohm) 4.5mA.

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Additionally a pair of back-to-back varactor diodes have been added to the circuit to enable the oscillation frequency to be controlled by a DC voltage. These capacitors are coupled to the left-hand crystal load capacitance (C2) via a 10pF capacitor. Changing the DC voltage on these varactors will change their capacitance, and therefore the load capacitance seen by the crystal. This will cause the crystal's oscillation frequency to be pulled away from it's nominal value and will thus allow the circuit to be tuned.

Temperature Compensation

To compensate for any frequency drift caused by temperature changes a correction signal needs to be generated in order to tune the oscillator in the opposite direction and cancel the drift. To achieve this the temperature of the oscillator circuit is monitored by a NTC thermistor connected in a voltage divider arrangement with R21. The voltage at the mid-point of this divider is buffered by Opamp U1.Resistors R22&R23 were chosen generate a reference signal at ½ VCC to which the signal from the NTC voltage divider can be compared. Opamp U2 compares the difference between these two signals and provides an output to drive the varactor diodes. Resistors R24 and R25 set the gain of the temperature measurement loop and will determine how much correction signal is applied to the oscillator. Since the temperature coefficient of the overall oscillator module will be affected by the characteristics of both Q1, the tuning varactors and the crystal itself, the exact amount of correction required is difficult to calculate and is best determined by measuring the behaviour of the completed prototype. Therefore R24 and R25 will need be adjusted during the prototyping phase of the project, but for simulation purposes an initial value of 1K was used for each.

The circuit that will be used for the TCXO section is illustrated in the figure below.

Figure 10: Temperature Compensated Pierce Oscillator

Frequency Doubler

The 27MHz output signal is extracted from the collector of Q1 and passed to a buffer amplifier to

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boost the signal level. This buffer amplifier is comprised of Q2, R4,R5, R6 and L2. The transistor was biased with enough headroom to allow for an approximately 2V peak-to-peak input signal, and with a quiescent current of 6mA. The bias components were determined as follows:

Desired emitter DC current= 6mADesired emitter DC voltage= 1 to 2V

Required Emitter resistance= 1

0.006=167Ω to

20.006

=333Ω≫220Ω selected

Required base voltage=0.7+I e Re=0.7+0.006∗220=2.02VBase Bias resistors :R5=1KΩ

R6=R5V cc−V b

V b

=1000∗12−2.022.02

=4941Ω

Rounded to nearest E12 value R6=4.7KΩ

The signal is then passed through a full-wave rectifier comprised of L2, L3 L4 and D1 & D2. This will generate a comb of even order harmonics at 54MHz, 108MHz, 162MHz, etc. The second harmonic at 54MHz is selectively amplified by two stages of tuned amplifiers (Q3 & Q4). The DC biasing conditions for both of these amplifiers is identical to that used for Q2. However due to the higher frequency that these amplifiers will be operating at a grounded base topology was chosen instead. In this configuration the base is decoupled by a 100nF capacitor and the signal is fed into the emitter of the transistor. This arrangement has the advantage of avoiding the miller effect, which can be detrimental to the gain of high frequency amplifiers (Bowick, 1997). The collector load of both stages of amplification is a tuned LC tank circuit that will filter out all signals except the desired 54MHz component. An inductance of 100nH was chosen as a sensible starting point for this tank circuit. The capacitance required to resonate this is calculated as follows:

L=100nHF=54MHz

C= 1(2π F )2∗L

= 1(2π ∗54MHz)2∗100nH

=86.9pF

This 86.9pF will need to be the combined total of the tank capacitance (C8), the inter-stage coupling capacitor (C10) and the output capacitance of the transistor. The datasheet for the BC547C transistors lists the output capacitance at a Vcb of 10V to be 1.7pF. The inter-stage coupling capacitor was chosen to be 10pF, which leaves a remainder of 75.2pF for the main tank capacitance. In order to compensate for any component variations when constructing the prototype, a 60-160pF trimmer capacitor will be used for C8, which will be adjusted to the correct capacitance during prototyping.

The second stage of filtering/amplification is identical to the first, with the exception that a larger output coupling capacitor (C12) is used to allow for a higher output power level. Again a 60-160pF trimmer capacitor is used in the tank circuit to allow for component variations etc.

The full circuit diagram for the TCXO, frequency doubler and amplifiers used for this LO signal

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source is shown below.

Figure 11: LO2 Full Schematic

The design was simulated using LTSpice to verify the operation of each stage of the circuit. To ensure that the simulation is accurate the motional parameters of the crystal resonator were obtained from the manufacturer's datasheet and used to customise the crystal equivalent circuit used. After running the simulation the result can be seen below.

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Figure 12: LO2 Simulated Output Waveform

Figure 13: LO2 Simulated Output Spectrum

The V(n013) waveform (Green) represents the 27MHz signal as it appears at the collector of Q1, while the V(out) trace (Blue) is the final frequency-doubled output signal. From this figure it can be seen that the design will meet the output power requirements as it is delivering 5.6 volts p-p (78.4mW, +18.9dBm) into the 50 ohm load. Additionally the spectral purity of the design's output is quite acceptable, with the 27MHz precursor signal attenuated by 73dB below the fundamental as shown in the figure above. The higher order harmonics at 108MHz and 162MHz are attenuated by only 29dB, however these will have minimal effect on the performance of the mixer that this oscillator will drive.

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1st Local Oscillator

The heart of this project is the design of this particular synthesiser module. The first local oscillator has similar requirements to the previous 54MHz LO in that it will also need to supply a stable 13dBm signal to a diode ring mixer, but the defining difference is that it's oscillation frequency must be tuneable from 42.941MHz to 77.941MHz. The design of this particular module will therefore focus on the task of creating a stable, yet frequency agile oscillator with almost a full octave of tuning range.

As per the requirements set out previously in this report the synthesiser architecture chosen for this module must have excellent frequency stability, must achieve single hertz tuning precision, and have a tuning range of 42.941-77.942MHz as stated above. There are many ways of creating a synthesiser capable of meeting these requirements but for the purpose of this report only two of the most common methods, PLL and DDS, will be investigated. These are the two broad categories that most frequency synthesisers will tend to fall into. To begin the process of designing a synthesiser it will be worthwhile to investigate typical designs from both categories to determine the strengths and weaknesses of each, and to choose the most appropriate path for the design. The topologies to be investigated are the Integer N PLL, Fraction N PLL and Direct Digital Synthesis.

Integer N PLL

The integer-ratio PLL was one of the first PLL architectures to be developed and is among the simplest type of frequency synthesiser. The overall concept of this type of synthesiser is akin to that of a mechanical gearbox, in which a fixed frequency reference signal is effectively multiplied by an integer ratio to yield the desired output frequency, as shown in the equation below (Texas Instruments, 1999):

Fout=N/R*Fref

In brief this is achieved by sampling the output frequency of a voltage-controlled oscillator, dividing it by a factor N and comparing the result to a reference frequency using a phase-frequency detector (PFD). The phase difference information obtained from this process is used to correct the frequency of the VCO until it's phase exactly matches that of the reference signal. A block diagram of this type of synthesiser is shown below.

Figure 14: Integer N PLL Block Diagram (Texas Instruments 1999)

This approach has many advantages and disadvantages that govern it's suitability for different

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applications. Some of the advantages of this system is that it can deliver an output signal that has low levels of spurious products that occur at easily predictable offsets from the carrier. The biggest disadvantage of this PLL architecture is that the system is only able to generate output frequencies that are integer multiples of the phase detector operating frequency (Texas instruments 1999). This makes the design unsuitable for applications that require closely spaced tuning steps, as the required PFD frequency would be impractically low.

Fractional N PLL

The fractional N PLL is an improvement on the integer PLL type that solves the issue of minimum frequency step size. The core concept behind this architecture is the notion that smaller step sizes can be achieved if the division ratio is rapidly switched between N and N+1 such that the average value of N lies somewhere in between the two values. This allows the PLL to operate according to the equation:

Fout=Fref*(N+K)

In this equation K is a fractional value between 0.0 and 1.0 that represents the percentage of time the division ratio is set to N vs N+1.

The primary advantage of this PLL type is obviously that it can achieve much finer frequency step sizes without having to resort to impractically low reference frequencies. The disadvantage, however, is that the spurious signals generated by this system are more difficult to predict and can thus pose a greater problem when a clean output signal is required.

DDS

The Direct Digital Synthesis technique is vastly different from the PLL based methods discussed above. In the DDS method the output signal is directly generated by a digital-to-analog converter that is being fed with waveform samples from a lookup table. At the heart of the DDS method is a device called a numerically controlled oscillator. This is essentially an accumulator who's numerical value represents the instantaneous phase of the output signal. A fixed value designated the tuning word is added to this phase accumulator on each clock cycle, causing it to repetitively count up and subsequently overflow back to zero. The value of the phase accumulator is used as a pointer to a lookup table which converts the sawtooth-like waveform to the desired shape - usually a sine wave (Analog Devices inc, 1999). The frequency generated via this method depends directly on how often the phase accumulator overflows, which is in proportional to the tuning word. A block diagram of this architecture is shown below.

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Figure 15: Basic DDS Architecture (Analog Devices Inc 1999)

The greatest advantage of this synthesiser type is that it is capable of achieving extremely fine frequency resolutions, often on the order of millihertz with modern devices. A further advantage of the DDS architecture is that due to it's principle of operation it is extremely frequency agile and is capable of making instantaneous, phase-continuous frequency jumps (Analog Devices 1999). This characteristic makes the design very desirable for applications requiring rapid frequency hops, such as direct-sequence spread spectrum.

However, the DDS approach has many disadvantages, the largest being the problem of spurious product content in the the output signal. Since the DDS system operates in a discreet-time, sample based manner it is subject to the usual caveats surrounding a sampling system. The output frequency of this type of synthesiser is therefore theoretically limited to 50% of the sample clock frequency, and in most practical applications is limited to 40% lest the Nyquist-images begin to interfere with the desired output signal.

Additionally the spurious-signal free dynamic range (SFDR) a DDS synthesiser is capable of producing directly depends on the number of bits available in the system's DAC. The DAC bit depth of devices currently on the market typically ranges from 10 to 14 bits, giving theoretical spur-free dynamic ranges of between 62 and 86dB (Analog Devices Inc 1999). While these aren't terrible figures they do make bare DDS synthesisers unsuitable for all but the least demanding applications.

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Proposed Architecture

While each of the three synthesiser architectures have their respective advantages and disadvantages, neither of them alone will be able to meet the requirements for the first LO of this project. For this project the LO must have the fine frequency resolution capabilities that can be found in a DDS, but at the same time have the spectral purity characteristic of the integer N PLL. The solution will thus be to combine both technologies to develop a synthesiser that exhibits the best attributes of both but with none of the disadvantages. A number of different methods for combining the technologies can be chosen depending on what characteristics are desired for the completed synthesiser.

One such method involves simply replacing the N divider of the integer-N PLL with a DDS IC. The VCO output would be used as the core clock source for the DDS while the output of the DDS would fed tot he phase comparator. In this configuration the DDS acts as a high-resolution fractional frequency divider. The output frequency of a synthesiser using this topology is given by the equation:

F out=F ref

R× 2A

TWWhere A=DDS Phase accumulator bit depth TW=DDS Tuning Word

However this particular arrangement has the disadvantage that the minimum frequency step size achievable will vary depending on the output frequency. In some applications this is a non-issue, but for this project it was deemed undesirable.

Another method is to replace the R divider of the integer-N PLL with a DDS core. In this arrangement the reference signal for the PLL phase detector is derived from the output of the DDS, while the DDS is clocked from the master reference oscillator. The DDS will again act as a high resolution fractional frequency divider that will allow the master reference frequency to be divided with excellent resolution. The output frequency of this type of synthesiser is given by:

F out=F ref ×TW

2A×N

Where : A=DDS Phase accumulator bit depth TW=DDS Tuning Word

This topology has the advantage that the minimum step size is directly proportional to N, and thus will be constant if N is set to a fixed value.

A third topology for the hybrid synthesiser is to use the DDS to add a small frequency offset to the signal flowing into the N divider of the integer-N PLL. This causes the PLL control loop to compensate by raising or lowering the VCO frequency by an amount equal to the offset. By using this particular design extremely fine frequency resolution can be achieved, as shown in the equation below:

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F out=F ref ×NR

+F DDS×TW2A

Where :F DDS=DDS Clock Frequency A=DDS Phase accumulator bit depth TW=DDS Tuning Word

This design has the advantage of having a constant minimum frequency step size across the whole tuning range, but is significantly more complex. The design requires more circuitry than the other options and will therefore require more physical space and consume more power.

The hybrid architecture proposed for this project will be based on the second option. It will use a DDS core to generate a reference signal for the PLL, which will then multiply it by a fixed ratio to give the required range of output frequencies. The PLL will also act as a narrowband tracking filter that will clean up the spurs from the DDS's output spectrum and increase the spur-free dynamic range of the synthesiser. A block diagram of the proposed design is shown below.

Figure 16: Proposed LO1 Synthesiser Configuration

When designing a synthesiser with this particular architecture there are two general options for choosing the DDS tuning frequencies and value of the R divider that will be used. At one extreme the DDS can be used to generate the same frequency as the output, with the R and N dividers set to identical ratios and the PLL to acting simply as a tracking filter. At the other extreme the R divider can be set to 1 (or omitted) with the DDS operating directly at the phase detector frequency. The PLL would then act as a both a frequency multiplier and tracking filter. In other words the overall ratio by which the PLL multiplies the DDS output must be chosen.

A high division ratio will allow the DDS to operate at a lower clock speed, resulting in reduced power consumption, however multiplying the DDS output signal will have the effect of increasing the phase noise and the level of the spurious signals by 20Log(N), where N is the multiplication factor (Texas Instruments 1999). Therefore to minimise the spur levels in the synthesiser output the overall multiplication ratio must be kept small.

Referring back to the project goals it was seen that spurious signal content in the transceiver's output must be attenuated by at least 70dB relative to the carrier. Therefore this local oscillator must also attenuate spurs to at least -70dBc. However upon researching the characteristics of low cost DDS ICs it was discovered that devices with 10-bit DACs and a spur-free-dynamic-range of 78-85dB would typically be the only options affordable for this project. In fact the DDS chosen for the project (AD9851, see detailed design

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section) has a SFDR of 80dB, which means an increase in spur levels of only 10dB can be permitted. This places an upper limit on the overall PLL multiplication ratio of:

20Log(N )=10dBthus

N =10(10dB

20)=3.15

A ratio of 3 gives a 9.5dB increase in spur levels, leaving only a 0.5dB safety margin. This was deemed unacceptable so the only practical ratios will be between 2 and 1, giving 6dB to 0dB increases respectively. A ratio of 1 will be initially chosen to give the best possible spur performance.

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Detailed Design

DDS & Postfilter

The first step in designing this synthesiser will be to select a DDS core that will meet the requirements. To be suitable the DDS core must be able to generate the desired range of frequencies, and must have reasonably low spur levels. Reviewing the Analog Devices DDS product range it was determined that the AD9851 will be a suitable device to use, as it can meet all requirements for the lowest cost. This device is designed to run form a 180MHz clock and will generate any sinusoidal waveform from DC to approximately 80MHz with a frequency resolution of 0.042Hz. More importantly this device is specified to have a narrowband spurious-free-dynamic-range of 80dB, which for this application is acceptable. The device is also equipped with a x6 clock frequency multiplier that will allow a 30MHz oscillator to be used as the external clock input while maintaining the required internal 180MHz core clock. To tune the DDS output to the desired frequency a 40 bit tuning word must be programmed into the device. The task of calculating this tuning word and loading it into the AD9851 will be handled by transceiver's core microcontroller. Communication to the DDS IC will be performed over an 8 bit parallel bus. To calculate the tuning word for a desired output frequency the equation below is used.

TW=F out×232

F clk

Where : TW=Tuning Word F out=Desired Output Frequency F clk=Core Clock Frequency

As mentioned previously DDS synthesisers typically have high levels of spurious signals in their output. Some of the most prevalent spurs are the Nyquist images formed by the digital sampling process. To prevent the possibility of these spurs interfering with the PLL section of this synthesiser a low pass filter must be included to remove the image frequencies. An attenuation of 50dB was chosen to be sufficient to ensure the Nyquist images do not cause problems in the PLL section and typically an LC lowpass filter would be used to perform the filtering.

However, with a DDS output of ~78MHz the Nyquist image will occur at (180-78=) 102MHz which represents a frequency ratio of 1.3 between the wanted and unwanted signals. For this ratio the rolloff curve of the filter required will be:

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α '=αlog(2)

log ( ff c

)=50

log(2)log(1.3)

=132dB/Octave

Where : f =Frequency of Interest f c=Filter Cutoff Frequency α=Attenuation(dB)α '=Filter Rolloff (dB /Octave)

A filter with a rolloff curve this steep would require an absurd number of poles and would therefore be very impractical to build. The problem can however be solved if the DDS is permitted to operate at a lower output frequency. If for instance the DDS core is configured to generate exactly half of the required output frequency (ie have a tuning range of 21.5-39MHz) the Nyquist images will occur from 141-158.5MHz. The worst case relative frequency ratio between wanted and unwanted signal components then becomes 3.6:1, which will require a rolloff curve of:

α '=αlog(2)

log( ff c

)=50

log(2)log(3.6)

=27dB/Octave

Where : f =Frequency of Interest f c=Filter Cutoff Frequency α=Attenuation (dB)α '=Filter Rolloff (dB /Octave)

This is a much more realistic figure that can be achieved with practical LC filters. Therefore the design will be modified to use a half-frequency DDS coupled with a PLL section that acts as both a tracking filter and as a frequency doubler. This choice to change the overall PLL multiplication ratio to 1:2 will degrade the phase noise and spur-free-dynamic-range performance of the synthesiser by 6dB, but will still result in an acceptable spur attenuation of -74dBc.

A practical DDS post filter can now be designed using the process described in chapter 3 of “RF Circuit Design” by C. Bowick. To begin the required order of the filter can be selected by examining the rolloff curves of various orders of Chebychev filters as shown below.

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Figure 17: 0.01dB ripple Chebychev Filter Attenuation Curves for different values of n (Bowick, 1997)

For an attenuation slope of 27dB/octave figure 16 shows that a 5th order filter will be required. The normalised inductances and capacitances required for such a filter were then obtained from Table 3-4B in “RF Circuit Design” and have been reproduced below.

Table 2: Normalised component values for 5th order Chebychev filter

Rs/Rl C1 L2 C3 L4 C5

1.000 0.977 1.685 2.037 1.685 0.977

These values were scaled to the required cutoff frequency of 39MHz and impedance of 50 ohms with the following equations:

C=C n

2π f c R

and

L=(R×Ln )(2π f c)

Giving the following values

Table 3: Actual component values for 5th order Chebychev filter

Rs/Rl C1 L2 C3 L4 C5

1.000 79.7pF 344nH 166pF 344nH 79.7pF

The filter was simulated using LTSpice to verify it's response, the result is shown in figure 18 and 19 below.

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Figure 18: DDS Post-Filter Circuit

Figure 19: DDS Post-Filter Frequency Response

DDS Clock Oscillator

As mentioned earlier the AD9851 requires a 30MHz clock source which it then multiplies internally to yield the 180MHz core clock frequency. This clock source is the primary timing reference for the DDS synthesiser an will therefore have direct control over the stability and phase noise of the DDS output signal (Analog Devices Inc 1999, p.39). For this reason a clock source with excellent stability and minimum phase noise is required. To meet this requirement a temperature compensated crystal oscillator was chosen. Due to the budget constraints applicable to the project a commercially manufactured TCXO cannot be used and one will have to be hand-built instead. The design process followed for this 30MHz clock oscillator is identical to that used for the LO2 oscillator, but with the difference that a 30MHz fundamental crystal was used directly without the additional frequency doubler. For simplicity the details of this oscillator's design process will be omitted.

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VCO Design

The next task will be to select a VCO for the PLL section of the synthesiser. As mentioned earlier the chosen device must be capable of tuning from approximately 43-78MHz while delivering a minimum of 13dBm of signal to the load. Additionally this VCO should have minimal levels of phase noise and have reasonably low power consumption. There are two paths to chose from when choosing a VCO for this project - either a commercially manufactured VCO module can be purchased from one of the many companies that supply such things, or a custom VCO can be designed from scratch. The latter method will be chosen for this project as it will allow greater customisation of the device's performance characteristics. The procedure will thus be to select an oscillator topology, calculate the component values required, optimise the design's phase noise performance and finally design a buffer amplifier to boost the signal output to the required level.

The parallel-tuned Colpitts oscillator topology with a BJT active device was selected as the basis of the design. The oscillation frequency is controlled by a set of varactor diodes which will be connected to the tuning voltage source. To minimise the phase noise of the oscillator a few important guidelines were kept in mind while designing the circuit - the first being the use of multiple varactor pairs in parallel to reduce the noise contribution of their dynamic resistance, the second being to use light coupling to the resonant tank circuit to maximise it's loaded Q, and the third is to operate the active device at the lowest current that will allow stable oscillation in order to lower it's flicker noise corner frequency as far as possible (Rhode 1994). The basic oscillator circuit that was developed is shown below.

Figure 20: Colpitts Oscillator Circuit A brief outline of how this circuit was designed is as follows: First the type and number of varactors was chosen. A back-to back array of 8x BB809 type varactors was chosen as a sensible starting point, which the datasheet lists as having a capacitance of 35pF each at 2V reverse bias, or an overall capacitance of 70pF for the full array. The tank circuit inductance (L1) required for a resonant frequency of 40MHz was then calculated using the equation:

L=( 1

2π f)

2

C=

( 12π 40MHz

)2

70pF=226nH

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To maximise the loaded Q of the tank circuit the value of the coupling capacitor (C3) must be small in comparison to the tank circuit capacitance. With this in mind a value of 10pF was chosen. Next, feedback capacitors C1&C2 were chosen to be 68pF which is roughly similar to the tank capacitance. A BC547C transistor was selected as the active device and biased for a quiescent current of approximately 1.75mA. The circuit was then simulated using LTspice, giving the waveforms below.

Figure 21: Colpitts Oscillator Output Waveform

From the simulation results it can be seen that the oscillator will provide roughly 0.9V peak into a 470 ohm load which is approximately -0.6dBm. Additionally the tuning sensitivity of the oscillator can be found by plotting the tuning voltage vs frequency curve using the simulation data, as shown below. The maximum sensitivity region of the oscillator's response is approximately 5.5MHz/V while at the opposite end of the tuning curve this falls to 0.715MHz/V before reaching compression at 26V. This information will be used later in the PLL loop filter calculations.

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Figure 22: VCO Tuning Curve

To boost the power output to the required level an amplifier was added to the circuit. A cascode arrangement was chosen as the amplifier topology as it has appropriate characteristics for this application (high gain, wide bandwidth, good reverse isolation). BF199 devices were chosen for the amplifier as they have significantly higher gain than the BC547C's at the high frequencies used here. The amplified oscillator circuit is shown below.

Figure 23: VCO Circuit with Amplifier

The amplifier was biased to a quiescent current of 14mA and the emitter degeneration resistance (R13) was set to 10 ohms to give a theoretical voltage gain of ~31. Inductors L4 & L3 and L2 & L5 form impedance matching transformers which couple the input and output signals to the amplifier respectively. The VCO circuit was again simulated and the result is shown below:

Figure 24: Amplified VCO Output Waveform

The simulation shown that the VCO is now capable of driving approximately 2.1V peak into a 50 ohm load (at 39MHz) which equates to a power output of 16dBm, which is more than sufficient for the requirements of this project. When the oscillation frequency is tuned to the maximum of 80MHz the power output falls to 1.75V peak into 50 ohms, or 14.9dBm, which is still adequate for this project's needs.

Of particular note in the above diagram is the partial distortion that is present on the VCO output

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signal. The cause of this distortion is due to the oscillator delivering too much power to the input of the buffer amplifier, causing it to clip. As the amplitude of the oscillations in the tank circuit grows, the output of the colpitts oscillator becomes large enough to drive the buffer amplifier into compression, resulting in the generation of the second-harmonic distortion seen in the VCO output. This effect could be remedied by simply reducing the amount of signal coupled into the amplifier by increasing R6. However, due to the nature of the oscillator the output power it develops declines as the operating frequency is increased. This means that reduced signal coupling to the buffer amplifier could result in the VCO delivering insufficient signal power when tuned to high frequencies. However the presence of harmonic distortion in the VCO output is of little consequence because the diode-ring mixer it will be driving will distort the LO signal into a quasi-square wave anyway. Additionally, the diode-ring mixer is part of the commutating family of mixers who's LO drive requirements are only mildly effected by harmonic distortion.

In order to calculate the optimum bandwidth for the PLL control loop the phase noise characteristics of the VCO must be known. To gain a basic idea of how the VCO will perform in this respect, Leeson's equation can be used to calculate the theoretical phase noise performance (Phase Noise Basics 2006).

L( f m)=10 log( FkT2Pavs

(1+f c

f m

+(f o

2f mQ l

)2

(1+f c

f m

)))

Where : Q l= Resonator loaded Q f m= carrier offset frequency (Hz) f o= carrier centre frequency (Hz) f c= transistor flicker corner frequency (Hz) T = Temperature (K) Pavs= oscillator output power (W) F= noise factor of transistor k= Boltzman constant

Which gives the phase noise in dBm/Hz for carrier offsets between the flicker noise and flat white noise segments of the total phase noise curve. The parameters for the VCO designed here are as follows:

Table 4: VCO Phase Noise Parameters

Loaded Q 25

Carrier centre frequency 78MHz

Transistor flicker corner frequency 6KHz

Temperature 300K

Noise factor of transistor 10

Oscillator output power 250uW

When the equation is calculated using the parameters of the designed VCO, the resulting phase noise prediction can be plotted as shown below.

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Figure 25: Predicted VCO Phase Noise

This information will be used when choosing a loop bandwidth for the synthesiser's PLL section.

PLL Section

The PLL section of the synthesiser will consist of two frequency dividers, a phase-frequency detector, a charge pump and a loop filter. The signals generated by both the DDS section and the VCO will be divided down to a frequency that is more practical for the phase-frequency detector to operate at. The phase-frequency detector will generate an error signal proportional to the phase difference between the DDS and VCO signals, which will in turn be filtered by the loop filter and sent to the VCO tuning control to correct the error.

Due to budget constraints and the requirement for minimal current consumption, a commercially manufactured IC the incorporates both the frequency dividers and PFD and charge pump will be utilised, rather than a custom design based on discreet logic devices. There are a large number of potentially suitable ICs to choose from, but for this project the Analog Devices ADF4002 was chosen because of it's excellent phase noise floor and charge pump leakage characteristics. An active loop filter will be paired with this device to boost it's charge pump output to the required voltage range.

Additionally there are a number of other characteristics of the PLL that need to be chosen carefully.

Phase Detector Frequency

The frequency at which the phase detector operated has a direct impact on the minimum frequency step size of an integer type PLL, and on the position and size of the reference frequency spurs in the synthesiser output signal. The output of the PFD is a series of current pulses which have the effect

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of modulating the tuning voltage - and therefore the VCO - at the PFD frequency. This creates spurious signals in the sidebands of the synthesiser output which can only be suppressed by the correct choice of loop filter bandwidth (Azarian 2013). Therefore the choice of PFD operating frequency becomes a tradeoff between desired minimum step size, loop stability and the ability of the loop filter to suppress the PFD-frequency spurs in the synthesiser output. Since the PLL used in this project's synthesiser will be operating at a fixed multiplication ratio with the tuning steps defined instead by the DDS section, the PFD operating frequency is largely irrelevant as long as it is compatible with the chosen loop filter bandwidth. As stated earlier in this report the overall multiplication ratio of the PLL section needs to be 1:2, which implies that the N divider will need to have a division ratio that is twice as high as the R divider. If ratios of 128 and 64 are chosen for the N and R dividers respectively, the resulting PFD operating frequency will vary from 336KHz to 609KHz (43MHz/128 to 78MHz/128). This will be high enough to allow the loop filter to suppress the PFD spurs if a relatively modest bandwidth is chosen.

Settling Time

The settling time is of a PLL is the time taken for the loop stabilise after hopping to a new frequency. It is closely related to the loop bandwidth and damping factor of the loop, and a PLL can be designed for either the loop bandwidth or for a specific settling time.

Loop Bandwidth

The loop filter is the component that defines the majority of the PLL's characteristics. The speed at which the loop can hop between frequencies and the time taken for the loop to stabilise at a new frequency will depend on the chosen loop filter bandwidth and damping characteristics. Furthermore the loop filter will dictate the stability of the PLL frequency control loop, as it's response will dominate the overall loop's transfer function. Another important factor is that the loop filter is responsible for attenuating spurious signals in the synthesiser output that originate from both the reference signal (the DDS) and the PFD charge pump. Therefore the level of spectral cleanliness achievable with a particular PLL design depends greatly on the choice of loop filter.

Ideally the loop filter cutoff frequency should be chosen to equal the frequency where the VCO phase noise and PFD phase noise floor plots intersect (Banerjee 1998). In doing so this will minimise the amount of noise peaking that will occur at offset frequencies near the cutoff of the loop filter. The ADF4002 is specified to have a noise floor of -166dBc/Hz at a PFD frequency of 600KHz, however due to the multiplication action of the PLL circuit the noise floor of the PFD will be raised by 20Log(N)=42dB which brings the overall device noise floor to -144dBc/Hz. From the VCO phase noise plot in the previous section it can be seen that this would imply the loop filter should be at least 300KHz wide, however the this would result in insufficient attenuation of the PFD spurs so a lower cutoff frequency must be used. A value of 30KHz was chosen as a reasonable trade off between these conflicting requirements.

The only remaining design task for this section of the synthesiser is to calculate the component values required for the loop filter. It is worth noting that due to the amplifying action of the active loop filter the effective tuning sensitivity of the VCO will be greatly increased. A gain of 5.7 was chosen to scale the ADF4002's 5V charge pump output up to the 28.5V required by the VCO. This also multiplies the tuning sensitivity by 5.7 giving an effective value of 31.35MHz/V. With this in mind the loop filter can be calculated using the method shown below (see: Fujitsu 2008).

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Table 5: PLL Parameters

Loop Bandwidth 30KHz

Kvco 31.35MHz/V

Damping factor 0.7

Icp 1mA (from ADF4002 datasheet)

N divider value 128

PFD Frequency 336KHz-609KHz

First, the natural frequency of the loop was calculated:

BW =π∗ f n∗(δ + 14δ

)

thus

f n=BW

(π∗(δ + 14δ

))= 30KHz

(π∗(0.7+ 14∗0.7

))=9.03KHz

Then capacitor C2 was calculated using the equation:

C2=( I CP∗KVCO )

(N∗(2π∗ f n)2)

=(1mA∗31.35MHz /V )(128∗(2π∗9.03KHz)2)

=76nF

Rounded to nearest E12 value of 82nF.

Then R1 was calculated:

R1=2∗δ ∗√ NI CP∗K VCO∗C 2

=2∗0.7∗√ 1281mA∗31.35MHz /V∗82nF

=324Ω

Rounded to nearest E12 value of 330 Ohms.

C1:

C1=C2/10=7.6nF

Rounded to nearest E12 value of 8n2.

R2:R2=R1=330 Ohms

C3=C1=8n2

The resulting circuit for the PLL section is shown below.

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Figure 26: PLL Section Schematic

The performance of the completed PLL was then simulated using ADIsimPLL to assess the stability and locking characteristics of the system. The simulation reveals that the PLL is capable of successfully obtaining phase lock to within 10 degrees in 180us. Additionally the phase noise characteristics of the completed synthesiser can be predicted by the simulation and is plotted below.

Figure 27: Simulated Phase Noise of Synthesiser

The spurious signals resulting from the PFD charge pump have also been attenuated quite substantially by the action of the loop filter. The simulation reveals that the spurs are slightly over 100dB below the carrier, which is orders of magnitude better than what is required for the project.

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Figure 28: Simulated PLL PFD Spur Level

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ConclusionReviewing the work done in this report it can be seen that the design goals for the project have been met. Specifically, it is evident from figure 22 that the tuning range requirement will easily be met by the designed VCO, while figure 25 shows that the phase noise characteristics are of the VCO also quite acceptable. The frequency accuracy and stability requirement will also be met since the combined error of both LO1 and LO2 will be roughly +/- 90-100Hz which is just within the set tolerance. Additionally the continuous tuning coverage and 1Hz resolution requirements have also been met with the proposed design. Therefore the design for the transceiver local oscillator system developed during this report will be suitable for prototyping during phase 2 of the project.

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Resources & Schedule of WorkA breakdown of the time used during the project planning stage of this thesis project is as follows.

Activity Resources Required Estimated Time Taken (Hours)

Research problem Web access, library access 10

Research commercial transceiver architectures

Web access, library access 25

Research synthesiser technology

Web access, library access 25

Develop system level design Web access, library access 5

Develop LO2 design Web access, library access, LTspiceIV

15

Simulate LO2 design LtspiceIV 2

Develop LO1 design Web access, library access, LTspiceIV

25

Simulate LO1 design LtspiceIV 4

Evaluate success of project planning stage

2

Prepare planning report draft 36

Prepare planning report final draft

12

Total 161

A gantt chart of the work undertaken in this stage of the project is included below.

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Implementation Work ScheduleThe work that will be carried out in the implementation phase of the project is planned according to the gantt chart below.

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Budget and Resources

A summary of the resources that will be required for the planning stage of the project is as follows.

Resource Supplied by Cost

Research papers, CQU Library, Internet -

Academic journals CQU Library, Internet -

Literature on circuit design, synthesisers, etc

CQU Library, Internet, Own Library

-

Simulation software (Ltspice) Self -

The resources that will be required during the implementation phase of the project will include:

Resource Supplied by Cost

Electronic parts, ICs, etc Self $250 budgeted

Access to prototyping tools, test equipment

Self -

Access to spectrum analyser/oscilloscope with FFT

CQU laboratory facilities -

Assistance from supervisor and lab technicians

CQU laboratory facilities -

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References

• Analog Devices Inc, 1999, "A Technical Tutorial on Digital Digital Synthesis" viewed 10 May 2014 <http://www.ieee.li/pdf/essay/dds.pdf>

• Azarian M, Ezell W 2013, "A simple method to Accurately predict PLL Reference Spur levels due to leakage current" viewed 10 May 2014 <http://cds.linear.com/docs/en/application-note/AN143f.pdf>

• Banerjee, D, 1998 "PLL Performance, Simulation, and Design" viewed 10 May 2014 <http://www.rfdh.com/ez/system/db/pds_tn/upload/57/PLL_performance,_simulation_and_design.pdf>

• BOWICK, C. 1997, "RF Circuit Design" 1st edition, Newnes, Indianapolis

• CARR, J. J. 2002, "RF Components and Circuits", First edition, Newnes, Massachusetts

• DA SILVA, E. 2001, "High Frequency and Microwave Engineering" First Edition, Butterworth-Heinemann, Massachusetts

• Fujitsu Microelectronics Inc. 2008 "PLL Basics-Loop Filter Design" viewed 10 May 2013 <http://www.sm0vpo.com/_pdf/miscellaneous_tech_info/pll_basics-fujitsu.pdf>

• ITU, 2003, "Final Acts of the World Radiocommunications Conference (WRC-2003)" viewed 10 May 2014 <http://www.itu.int/dms_pub/itu-s/oth/02/01/S020100002D4005PDFE.pdf>

• Kenwood corporation, 1992, "Kenwood TS-450 Instruction Manual", viewed 10 May 2014 <http://qrzcq.com/pub/RADIO_MANUALS/KENWOOD/KENWOOD--TS-450-690-User-Manual.pdf>

• Lee, T "Oscillator Phase Noise: A Tutorial" IEEE Journal of Solid State Circuits, VOL. 35, NO. 3, March 2000, viewed 10 May 2014 <http://ee.sharif.edu/~comcir/readings/oscillators/osc-phase-noise.pdf>

• Mancini, O 2004, "Preciscion frequency generation utilising OCXO and Rubidium Atomic Atandards" viewed 10 May 2014 <http://www.ieee.li/pdf/viewgraphs/precision_frequency_generation.pdf>

• Phase Noise Basics 2006, viewed 10 May 2014, <http://www.ieee.li/pdf/essay/phase_noise_basics.pdf>

• Rhode, U, "Designing Low-Phase-Noise Oscillators" QEX October 1994. Print.

• Steder H, Hardcastle J, "Crystal Ladder Filters for All" QEX November/December 2009. Web. viewed 10 May 2014 <http://www.arrl.org/files/file/QEX_Next_Issue/Nov-Dec_2009/QEX_Nov-Dec_09_Feature.pdf>

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• Texas Instruments corporation, 1999, "Fractional/Integer-N PLL Basics" viewed 10 May 2014 <http://www.ti.com/lit/an/swra029/swra029.pdf>

• Yaesu corporation, 1974 "FRG-7 Instruction Manual", viewed 10 May 2014 <http://www.repeater-builder.com/yvs/pdfs/yaesu-frg-7-receiver-inst-manual.pdf>

• Yaesu corporation, 1976, "FT-101 Instruction Manual", viewed 10 May 2014 <http://www.radiomanual.info/schemi/FT101_user.pdf>

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Reflective Paper

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