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Seed layer enhancement by electrochemical deposition: The copper seed solution for beyond 45 nm A. Roule a, * , M. Amuntencei b , E. Deronzier a , P.H. Haumesser a , S. Da Silva c , X. Avale c , O. Pollet c , R. Baskaran c , G. Passemard b a CEA-DRT-LETI-MINATEC – 17, rue des Martyrs, 38054 Grenoble Cedex 9, France b STMicroelectronics, 850 rue Jean Monnet, F38926 Grenoble, France c Semitool INC. 655 West Reserve Drive, Kalispell, MT 59901, USA Received 22 June 2007; accepted 24 June 2007 Available online 3 July 2007 Abstract With the downscaling of feature dimensions, each layer of the metallization stack has to become thinner and thinner to comply with the geometrical constraints. In particular, seed layer thickness will have to be drastically reduced for the 45 nm node and beyond. As PVD is a non-conformal technique, discontinuous seeding of the sidewalls of narrow features can be expected. In this study, a seed layer enhancement (SLE) process is evaluated for 300 mm processing, as a possible solution for copper seeding for the 45 nm node and below. We demonstrate the extendibility of this process to the fabrication of 300 mm wafers. We confirm the excellent morphological properties of the deposit, which is extremely conformal, thus continuous inside the features. This process is successfully integrated in the existing metallization sequence, without any modification of the subsequent steps, including electroplating. This demonstration is supported by electrical results, showing that a 10 nm thick PVD liner, which leads to severe degradation of line and via resistance, is efficiently repaired with only 20 nm SLE. All electrical performances (line and via resistance, dispersion and yield) are fully recovered with implementation of the SLE step. Ó 2007 Elsevier B.V. All rights reserved. Keywords: Seed repair; Copper; Interconnects 1. Introduction The transition from aluminium to copper for the inter- connect technologies was a fundamental technological revolution. Due to its advantages, i.e. lower resistivity (1.7 lX cm) and better electromigration resistance, copper was adopted in deep submicron ULSI metallization [1]. Its integration has required new processes and materials in the damascene architecture. In this metallization scheme, patterns are created in the dielectric and then filled with the conducting metal. In the conventional approach, barrier layers are first deposited to prevent copper diffusion into the dielectric [2]. For this application, some refractory met- als and their nitrides including Ta, TaN have been studied. The literature reveals that TaN present a higher resistivity than Ta but a better thermal stability due to the amor- phous/nanocrystalline structures of the barrier layer [3–7]. As a result, a TaN/Ta bi-layer barrier is usually preferred because of its good adhesion to both dielectric material and Cu wire and its better barrier properties [8,9]. Currently, electrochemical deposition (ECD) is used to fill structures with copper in the damascene approach [10,11]. In this process, the wafer acts as the cathode, where copper deposition (reduction reaction) occurs. However, due to its high resistivity (the less resistive phase of Ta, a-Ta, exhibits a resistivity of about 30 lX cm), the barrier layer is not efficient as a cathode material. Therefore, a thin copper layer is deposited onto this barrier, usually referred to as seed layer. This step is essential to uniformly initiate 0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.06.014 * Corresponding author. Tel.: +33 4 38 78 91 55; fax: +33 4 38 78 53 88. E-mail address: [email protected] (A. Roule). www.elsevier.com/locate/mee Microelectronic Engineering 84 (2007) 2610–2614

Seed layer enhancement by electrochemical deposition: The copper seed solution for beyond 45 nm

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Page 1: Seed layer enhancement by electrochemical deposition: The copper seed solution for beyond 45 nm

www.elsevier.com/locate/mee

Microelectronic Engineering 84 (2007) 2610–2614

Seed layer enhancement by electrochemical deposition: The copperseed solution for beyond 45 nm

A. Roule a,*, M. Amuntencei b, E. Deronzier a, P.H. Haumesser a, S. Da Silva c,X. Avale c, O. Pollet c, R. Baskaran c, G. Passemard b

a CEA-DRT-LETI-MINATEC – 17, rue des Martyrs, 38054 Grenoble Cedex 9, Franceb STMicroelectronics, 850 rue Jean Monnet, F38926 Grenoble, Francec Semitool INC. 655 West Reserve Drive, Kalispell, MT 59901, USA

Received 22 June 2007; accepted 24 June 2007Available online 3 July 2007

Abstract

With the downscaling of feature dimensions, each layer of the metallization stack has to become thinner and thinner to comply withthe geometrical constraints. In particular, seed layer thickness will have to be drastically reduced for the 45 nm node and beyond. AsPVD is a non-conformal technique, discontinuous seeding of the sidewalls of narrow features can be expected. In this study, a seed layerenhancement (SLE) process is evaluated for 300 mm processing, as a possible solution for copper seeding for the 45 nm node and below.We demonstrate the extendibility of this process to the fabrication of 300 mm wafers. We confirm the excellent morphological propertiesof the deposit, which is extremely conformal, thus continuous inside the features. This process is successfully integrated in the existingmetallization sequence, without any modification of the subsequent steps, including electroplating. This demonstration is supported byelectrical results, showing that a 10 nm thick PVD liner, which leads to severe degradation of line and via resistance, is efficiently repairedwith only 20 nm SLE. All electrical performances (line and via resistance, dispersion and yield) are fully recovered with implementationof the SLE step.� 2007 Elsevier B.V. All rights reserved.

Keywords: Seed repair; Copper; Interconnects

1. Introduction

The transition from aluminium to copper for the inter-connect technologies was a fundamental technologicalrevolution. Due to its advantages, i.e. lower resistivity(1.7 lX cm) and better electromigration resistance, copperwas adopted in deep submicron ULSI metallization [1].Its integration has required new processes and materialsin the damascene architecture. In this metallization scheme,patterns are created in the dielectric and then filled with theconducting metal. In the conventional approach, barrierlayers are first deposited to prevent copper diffusion intothe dielectric [2]. For this application, some refractory met-

0167-9317/$ - see front matter � 2007 Elsevier B.V. All rights reserved.doi:10.1016/j.mee.2007.06.014

* Corresponding author. Tel.: +33 4 38 78 91 55; fax: +33 4 38 78 53 88.E-mail address: [email protected] (A. Roule).

als and their nitrides including Ta, TaN have been studied.The literature reveals that TaN present a higher resistivitythan Ta but a better thermal stability due to the amor-phous/nanocrystalline structures of the barrier layer [3–7].As a result, a TaN/Ta bi-layer barrier is usually preferredbecause of its good adhesion to both dielectric materialand Cu wire and its better barrier properties [8,9].

Currently, electrochemical deposition (ECD) is used tofill structures with copper in the damascene approach[10,11]. In this process, the wafer acts as the cathode, wherecopper deposition (reduction reaction) occurs. However,due to its high resistivity (the less resistive phase of Ta,a-Ta, exhibits a resistivity of about 30 lX cm), the barrierlayer is not efficient as a cathode material. Therefore, a thincopper layer is deposited onto this barrier, usually referredto as seed layer. This step is essential to uniformly initiate

Page 2: Seed layer enhancement by electrochemical deposition: The copper seed solution for beyond 45 nm

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0Electrical charge (A.min)

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Fig. 1. Copper SLE thickness vs. electrical charge on 40 nm and 20 nmPVD liners.

A. Roule et al. / Microelectronic Engineering 84 (2007) 2610–2614 2611

the electrochemical deposition and ensure perfect featurefilling with copper.

The most widespread technique for seed layer depositionis physical vapour deposition (PVD). However, this tech-nique intrinsically suffers from limited coverage of the side-walls of trenches and contact holes (vias) [12,13]. Withcontinuous shrinking of feature size (45 nm node andbeyond), this may compromise the continuity of the seedlayer on the sidewalls, and in turn degrade the continuityof the final structures.

Therefore, seed layer deposition becomes a critical stepfor the copper metallization in the future technologicalnodes. In this work, a possible solution to address this issueis explored for 300 mm processing, referred to as ‘‘seedrepair’’. For this purpose, a specific process called seedlayer enhancement (SLE) is used [14]. In Section 1, theprinciples of this particular process are described. Experi-mental conditions of this study will then be described. InSection 4, the morphology of the films will be discussed,with impact on filling performances. The benefit of theSLE process is quantified through electrical testing of linesand vias in Section 6.

2. The seed layer enhancement (SLE) process

With the downscaling of feature dimensions, each layerof the metallization stack has to become thinner and thin-ner to comply with the geometrical constraints [15]. In par-ticular, seed layer thickness will have to be drasticallyreduced for the 45 nm node and beyond. As PVD is anon-conformal technique, with limited coverage of the ver-tical portions of the wafer surface, discontinuous seeding ofthe sidewalls of narrow features can be expected. These dis-continuities are amplified during the electrochemical fillinginto large voids which compromise the electrical continuityof the structures.

A straightforward solution to extend the viability of thePVD process is to bridge the discontinuities with copper,using a conformal deposition technique. In this work, anoriginal electroplating solution was adopted, which is com-parable to conventional copper ECD. This process, calledseed layer enhancement (SLE) was designed to yield con-formal and continuous deposition, even on resistive por-tions of exposed barrier. To achieve this, a specificelectrolyte was formulated [16]. The benefits of thisapproach were already discussed in a previous article[14]. In this work, this solution is demonstrated to be com-patible for 300 mm processing, confirming its potential forsuccessful integration of copper at the 45 nm node andbeyond.

3. Experimental

In this study, 300 mm structured and fullsheet waferswere used. The fullsheet substrates were fabricated usingSiO2 as a dielectric. For electrical evaluations, structureswere built at the metal 2 level using the 65 nm node tech-

nology in a porous ultra-low K dielectric material. A con-ventional barrier stack of TaN/Ta was deposited by ionisedPVD. The nominal barrier thickness was 10 nm. A copperliner was also deposited with ionised PVD in the same tool,without air break. A 40 nm thick PVD seed was consideredas a reference for the following studies. This thickness wasdecreased to 10 nm to test the capabilities of the SLEprocess.

The SLE process was performed in a 300 mm Raiderplatform from Semitool. Copper was electrolytically depos-ited in a CFD2 reactor equipped with four independentinert anodes for uniformity control [17]. ECD and hotplateanneal were performed in the same equipment, using stan-dard process conditions. Excess copper was removed bychemical mechanical polishing (CMP) prior to electricaltests. First tests aimed at controlling continuity of110 lm long, 100 nm wide resistors at the metal 2 level.Then, integrity of linear via chains between metal 1 andmetal 2 levels was checked, with via diameter of 100 nm,and via number up to 25 500000.

4. Thickness control and morphological characterization

An intrinsic advantage of electrolytic deposition is thatfilm thickness is proportional to the electrical chargeaccording to Faraday’s law. This was verified in our pro-cess, by depositing SLE films on 40 nm thick PVD linerswith increasing electrical charge (Fig. 1). Deposited thick-ness (measured by profilometry) is proportional to theapplied charge in a wide range. Moreover, it was verifiedthat there is no difference when a 20 nm thick PVD lineris used. This linear behaviour allows an accurate controlof the deposited thickness in the range of interest, and inthe following, a nominal thickness of 20 nm was targeted,corresponding to a charge of 0.5 A min.

These conditions (20 nm SLE deposition) were appliedto patterned wafers covered with 20 nm PVD copper. A

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typical TEM cross-section of the resulting seed in narrowtrenches is printed in Fig. 2. As expected, the SLE depositis extremely conformal, providing a final copper film thatis perfectly continuous on the sidewalls of the lines. Withmore careful observation, it is found that final seed thick-ness is about 25 nm on top and at the bottom of the lines,whereas it does not exceed 14 nm on the sidewalls. Thisreflects the non-conformality of the initial PVD liner. Fur-thermore, this shows that SLE thickness is about 14 nm(assuming a conformal deposit, and a negligible PVDthickness on the sidewalls), which is significantly less thanthe 20 nm expected. In fact, this is due to the excess sur-face of the patterned wafers as compared to the fullsheetsubstrates used for thickness calibration. For the sameamount of charge (i.e. of copper), a larger surface is cov-ered when patterns are present (corresponding to theamount of sidewalls). In this case and in the following,this excess surface is not taken into account. For the sakeof clarity, indicated SLE thickness will refer to the nomi-nal value expected form the calibration on fullsheetwafers.

This seed layer composed of 20 nm PVD and 20 nm SLEcopper is efficient to initiate copper filling of the trenches,as illustrated in Fig. 3. Void free gap fill is obtained, with-out any modification of the ECD process.

Fig. 2. TEM cross-section of a 20 nm thick SLE deposit (nominal value)on a 20 nm thick PVD liner in a 90/90 nm width/space trench array.

Fig. 3. FIB/SEM cross-section of a 90/90 nm width/space trench arrayseeded with 20 nm SLE 20 nm PVD after ECD filling.

5. Electrical performances

To quantify the benefit of the SLE process, this morpho-logical study was completed by an evaluation of the electri-cal performances of test structures. Considering theexcellent morphological results obtained with initial20 nm PVD liner, more aggressive conditions were used.The PVD thickness was decreased to 10 nm. Test waferswere fabricated using this liner as a stand-alone seed layer,or with 20 nm thick SLE reparation. Both situations werecompared to a reference using a 40 nm PVD seed layer.Conventional ECD, anneal and CMP were used to finishthe structures.

In a first approach, electrical resistance of line resistorswas measured. The corresponding distributions are plottedin Fig. 4. For the reference 40 nm PVD seed layer, alldevices are functional, and narrow distribution of lineresistance is found around 130 mX/sq. When using a10 nm PVD seed layer, this median value increases to150 mX/sq, with larger dispersion. More important, severeloss of yield is observed, as <70% of the devices are func-tional. This is clearly related to a poor filling of the struc-tures, as shown in Fig. 5. The voids are mainly situatedat the barrier/copper interface, which is expected from dis-continuous seeding of the sidewalls. With 20 nm SLE rep-aration, electrical performances are spectacularly recovered(Fig. 4): full yield is restored, and resistance value and dis-tribution are comparable to the reference. This clearly con-firms the benefit of this process for subsequent ECD filling.

To go further in this evaluation, the same study was car-ried out in via chains. The corresponding results areprinted in Fig. 6 for long via chains. For the referencesequence (with 40 nm thick PVD seed layer), a via resis-tance of about 1.6 X is measured, with narrow distribution.In this case, yield is close to 95%. When decreasing PVDthickness to 10 nm, performances are dramaticallyimpacted, as yield drops below 10%. In this case, the

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Fig. 4. Cumulative plots of line resistance of 110 lm long, 100 nm wideresistors with reference 40 nm thick PVD seed and 10 nm PVD Cu liner asa stand-alone seed or after 20 nm SLE.

Page 4: Seed layer enhancement by electrochemical deposition: The copper seed solution for beyond 45 nm

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Fig. 6. Cumulative plots of via resistance of 100 nm wide vias in long viachains (25500000 vias) with reference 40 nm thick PVD seed and 10 nmPVD Cu liner as a stand-alone seed or after 20 nm SLE.

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Fig. 7. Yield of via chains with increasing length for the various seedsolutions. Resistance threshold used for yield determination was set to7 X.

Fig. 5. SEM top view of 100 nm lines fabricated with (a) a reference 40 nm thick PVD seed and (b, c) a 10 nm thick PVD liner.

A. Roule et al. / Microelectronic Engineering 84 (2007) 2610–2614 2613

benefit of the SLE process is even more spectacular. Viaresistance value and dispersion are fully restored and com-parable to the reference. Yield is even improved up to 97%.This result can be extended to shorter via chains (Fig. 7).As compared to the reference, a 10 nm PVD seed layerleads to severe yield loss, whatever chain length. Interest-ingly, yield increases as via chain length decreases: this isexpected with poor filling of the vias, which is confirmed

Fig. 8. FIB/SEM cross-section of via chain structure after copper filling with (alayers.

by FIB/SEM cross-section (Fig. 8). When using SLE, fill-ing performances are recovered, and electrical perfor-mances restored to the level of the reference for all viachains. This important result demonstrates the capabilityof the SLE process to offer an efficient solution for copperseeding for the 45 nm node and beyond, with the majoradvantage to be fully compatible with the existing metalli-zation scheme.

) 10 nm Cu PVD and (b) 10 nm Cu PVD repaired with 20 nm Cu SLE seed

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2614 A. Roule et al. / Microelectronic Engineering 84 (2007) 2610–2614

6. Conclusion

In this study, a seed layer enhancement (SLE) processwas evaluated for 300 mm processing, as a possible solu-tion for copper seeding for the 45 nm node and below. Thiselectrolytic process had been shown to be an efficient solu-tion to ‘‘repair’’ discontinuous ultra-thin PVD copper lin-ers, enabling efficient filling of narrow features. In thisstudy, we have demonstrated the extendibility of this pro-cess to the fabrication of 300 mm wafers. We have con-firmed the excellent morphological properties of thedeposit, which is extremely conformal, thus continuousinside the features. This process was successfully integratedin the existing metallization sequence, without any modifi-cation of the subsequent steps, including electroplating.This demonstration was supported by electrical results,showing that a 10 nm thick PVD liner, which leads tosevere degradation of line and via resistance, is efficientlyrepaired with only 20 nm SLE. All electrical performances(line and via resistance, dispersion and yield) were fullyrecovered with implementation of the SLE step.

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