Section 6 Digital Combinational Circuits

VLSI Design-EEE453A © D.Al-KhaliliCombinational-6Combinational-6

Section 6

Digital Combinational Circuits

VLSI Design-EEE453A © D. Al-KhaliliCombinational-6Combinational-62

CMOS Circuits

Combinational» Static » Dynamic

Sequential» Static » Dynamic


Static Combinational Network

PMOSNetwork

NMOSNetwork

Inputs Output

VDDCMOS Circuits

• Pull-up network-PMOS• Pull-down network- NMOS• Networks are complementary to each other• When the circuit is dormant, no current flows between supply lines.• Number of the NMOS transistors (PMOS transistors) equals to the number of the inputs.• Output load is capacitive


NAND Gates

Transistors in Parallel

(W/L)1 (W/L)2 (W/L)eff

1/Rcheff = (1/Rch1) + (1/Rch2)

WL-----

eff

WL-----

1

WL-----

2+=

Transistors in Series

WL-----

eff

WL-----

1

1– WL-----

2

1–+

1–=

Rcheff = Rch1 + Rch2

(W/L)1

(W/L)2

(W/L)eff


NAND Gates: Analysis

VDD

MP1MP2

MN1

MN2

A

B

X

CL

DC Analysis

Two possible scenarios:1. Both inputs are toggling2. One input is toggling, the other one set high

Assumptions: MP2=MP1=MP MN1=MN2=MNW/L for MP = (W/L)pW/L for MN = (W/L)n

Compare with a CMOS inverter: MP/MN

Determine KR, hence the shift in VTC



Scenario #1-Both inputs are togglingL-H > (W/L)eff = 2(W/L)pH-L > (W/L)eff = 1/2(W/L)nKR|NAND = 1/4 KR|INV

Scenario #2- One input is togglingL-H > (W/L)eff = (W/L)pH-L > (W/L)eff = 1/2(W/L)nKR|NAND = 1/2 KR|INV

Vout

Vin

VOH

VOLVx2 Vx1

Vin=Vout

InverterOne input toggling

Two inputs toggling



VDD

MP1MP2

MN1

MN2

A

B

X

CL

Switching AnalysisScenario #1-Both inputs are togglingtPLH |NAND = 1/2tPLH |INVERTER

tPHL |NAND = 2tPHL |INVERTER

Scenario #2- One input is togglingtPLH |NAND = tPLH |INVERTER

tPHL |NAND = 2tPHL |INVERTER


NAND Gates: Layout

Layout Transistors in Series

Transistors in Parallel


NAND Gates: Layout

A BX

Metal IIVia

VDD

GND


NAND Gate: Power Dissipation

VDD

MP1MP2

MN1

MN2

A

B

X

CL

Pac= .f . C VDD2

A B X 0 0 1 1 0 1 0 1 1 1 1 0

= P (X=1). P (X=0) assuming A and B have equal probabilities for 1 and 0 = (1/4). (3/4)= 3/16C = CL + C parasitic


AND Gate: Layout

1. Draw the schematic

2. Do the stick diagram

3. Optimize stick diagram

4. Generate Layout


NOR Gate: Analysis

VDD

A

BCL

X

MN2 MN1

MP1

MP2

DC Analysis/ AC Analysis

Two possible scenarios:1. Both inputs are toggling (one is set low)2. One input is toggling, the other one set high

Assumptions: MP2=MP1=MP MN1=MN2=MNW/L for MP = (W/L)pW/L for MN = (W/L)n

Compare with a CMOS inverter: MP/MN

KR, and the shift in VTC

Propagation delay tPLH and tPHL


NOR Gate: Layout

ABX

VDD

GND


4 INPUT NOR Gate

VDD

A

B

C

D

A B C D CL

X

Very slow rise time and rise delays

Could be compensated by increasing of PMOS transistor size.

Implications: Silicon Area Input capacitance


Practical Considerations

1. Minimize the use of NOR gates2. Minimize the fan-in of NOR gates3. Limit the fan-in to 4 for NAND gates4. Use De morgan’s theorem to reduce the number of fan-in per gate

Example:

F = ABCDEFGH = (ABCD) + (EFGH)


Analysis and Design of Complex Gate

A B C D E F

A B C D E F

VDD

GND

OUT

active(diffusion)

n+ layermetalpolysilicon

contact

p+ layer

N-well

Analysis

1. Construct the schematic2. Determine the logic function.3. Determine transistor sizes.4. Determine the input pattern to cause slowest and fastest operations.5. Determine the worst case rise delay (tPLH)and fall delay (tPHL)6. Determine the best case rise and fall delays.


Transmission Gate

Bi-directional switch, passes digital signalsLess complex and more versatile than AND gate Passes analog signals

Problems: Large ON resistance during transitions of input signals Large input and output capacitance (useful for data storage applications) Capacitive coupling

Applications:Multiplexers, encoders, latches, registersvarious combinational logic circuits

C

C

A B

BA

C

C

C

C

A B TGA B

C

INV included


NMOS/PMOS as Pass Transistors

Vi Vo

C

CL

NMOS Transistor Passes weak “1” signal Vo = VDD -VTN

Passes “0” signal undegraded

Vo

Vi

VDD -VTN

Vi Vo

C

CL

VDD -VTN

Vo

Vi

-VTP

-VTP

PMOS Transistor

Passes “1” signal undegraded

Passes weak “0” signal Vo= -VTP


TX Gate: Characteristics

C

Vin Vo

Vo

Vin

0V |VTP| VDD-VTN VDD

nmos:sat nmos:sat nmos:offpmos:sat pmos:lin pmos:lin

Req,pReq,n

Req,TX

Vo

R

VDD-VTN VDD0


TX Gate: Layout

VDD

VSS

VOVi

C

C C CFor data path structure

P+P+

N+N+


TX Gate: Applications

Exclusive OR 12 Transistors 8 Transistors

Multiplexers

Realization of Combinational Logic Functions

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Section 6 Digital Combinational Circuits