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Section 1.3 Section 1.3 Asynchronous Circuits Asynchronous Circuits Exercises Exercises Alfredo Benso Alfredo Benso Politecnico di Torino, Italy Politecnico di Torino, Italy [email protected] [email protected]

Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy [email protected]

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Page 1: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

Section 1.3Section 1.3Asynchronous CircuitsAsynchronous Circuits

ExercisesExercises

Alfredo BensoAlfredo Benso

Politecnico di Torino, ItalyPolitecnico di Torino, Italy

[email protected]@polito.it

Page 2: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#1#1

• Find a minimal race free state coding for the Find a minimal race free state coding for the following transition table.following transition table.

• Also, find the boolean functions representing the Also, find the boolean functions representing the future state.future state.

00 01 11 10 00 01 11 10

A A A B C D A A B

B A - C B A D C B

C C C C C B B D C

D A C - A D D A D

abc=0 c=1

Page 3: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#1: stable states#1: stable states

00 01 11 10 00 01 11 10

A A A B C D A A B

B A - C B A D C B

C C C C C B B D C

D A C - A D D A D

c=0 c=1

Page 4: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#1: Vicinity graph#1: Vicinity graph

00 01 11 10 00 01 11 10

A A A B C D A A B

B A - C B A D C B

C C C C C B B D C

D A C - A D D A D

A B

DC

c=0 c=1

Page 5: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

C

#1: Minimize the vicinity graph#1: Minimize the vicinity graph

0000 0101 1111 1010 0000 0101 1111 1010

AA AA AA BB CC DD AA AA BB

BB AA -- CC BB AA DD CC BB

CC CC CC CC CC BB BB DD CC

DD AA CC -- AA DD DD AA DD

A B

D

c=0 c=1

Page 6: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

C

#1: Minimize the vicinity graph#1: Minimize the vicinity graph

0000 0101 1111 1010 0000 0101 1111 1010

AA AA AA BB CC BB AA AA BB

BB AA -- CC BB DD DD AA BB

CC CC CC CC CC DD BB AA CC

DD BB CC -- CC DD DD BB DD

A B

D 10

00 01

11

c=0 c=1

Page 7: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#2#2

• Design the reduced transition table of an Design the reduced transition table of an asynchronous circuit functioning in fundamental asynchronous circuit functioning in fundamental mode. The circuit has three inputs a, b, and c, and mode. The circuit has three inputs a, b, and c, and one output U, which is 1 only if all inputs are equal one output U, which is 1 only if all inputs are equal to ‘1’, and they went to ‘1’ in the order a, b, and c. to ‘1’, and they went to ‘1’ in the order a, b, and c. U returns to 0 when all inputs returned to ‘0’. U returns to 0 when all inputs returned to ‘0’.

• Also, find the minimum number of state variables Also, find the minimum number of state variables required to have a race free state assignment, and required to have a race free state assignment, and find a possible state assignment.find a possible state assignment.

Page 8: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#2: Transition table#2: Transition table

• We have to recognize the following sequence:We have to recognize the following sequence:

000 000 100 100 110 110 111 111

A 0A 0 - -- - - -- - - -- - B 0B 0 - -- - - -- - - -- -

A 0A 0 - -- - - -- - - -- - B 0B 0 - -- - - -- - C 0C 0

- -- - - -- - - -- - - -- - - -- - - -- - D -D - C 0C 0

A -A - D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1

A 0A 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0

0000 0101 1111 1010 0000 0101 1111 1010c=0c=0 c=1c=1

Waiting for 100Waiting for 100

Wrong sequence.Wrong sequence.

Waiting for 110Waiting for 110

Waiting for 111Waiting for 111

OK! Now waiting for all 0OK! Now waiting for all 0

AA

BB

CC

DD

EE

Page 9: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#2: Transition table#2: Transition table

• We have to recognize the following sequence:We have to recognize the following sequence:

000 000 100 100 110 110 111 111

A 0A 0 E 0E 0 - -- - E 0E 0 B 0B 0 - -- - - -- - - -- -

A 0A 0 - -- - - -- - - -- - B 0B 0 E 0E 0 - -- - C 0C 0

- -- - - -- - - -- - E 0E 0 E 0E 0 - -- - D -D - C 0C 0

A -A - D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1

A 0A 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0

0000 0101 1111 1010 0000 0101 1111 1010c=0c=0 c=1c=1

Waiting for 100Waiting for 100

Wrong sequence.Wrong sequence.

Waiting for 110Waiting for 110

Waiting for 111Waiting for 111

OK! Now waiting for all 0OK! Now waiting for all 0

AA

BB

CC

DD

EE

Page 10: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#2: Minimize the transition table#2: Minimize the transition table

A 0A 0 E 0E 0 - -- - E 0E 0 B 0B 0 - -- - - -- - - -- -

A 0A 0 - -- - - -- - - -- - B 0B 0 E 0E 0 - -- - C 0C 0

- -- - - -- - - -- - E 0E 0 E 0E 0 - -- - D -D - C 0C 0

A -A - D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1

A 0A 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0

0000 0101 1111 1010 0000 0101 1111 1010c=0c=0 c=1c=1

Waiting for 100Waiting for 100

Wrong sequence.Wrong sequence.

Waiting for 110Waiting for 110

Waiting for 111Waiting for 111

OK! Now waiting for all 0OK! Now waiting for all 0

AA

BB

CC

DD

EE

States A and B are compatible, so I can collapse them in one States A and B are compatible, so I can collapse them in one

statestate

Page 11: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#2: Minimize the transition table#2: Minimize the transition table

A 0A 0 E 0E 0 - -- - E 0E 0 A 0A 0 E 0E 0 - -- - C 0C 0

- -- - - -- - - -- - E 0E 0 E 0E 0 - -- - D -D - C 0C 0

A -A - D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1

A 0A 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0

0000 0101 1111 1010 0000 0101 1111 1010c=0c=0 c=1c=1

Wrong sequence.Wrong sequence.

Waiting for 100 & 110Waiting for 100 & 110

Waiting for 111Waiting for 111

OK! Now waiting for all 0OK! Now waiting for all 0

AA

CC

DD

EE

States A and B are compatible, so I can collapse them in one States A and B are compatible, so I can collapse them in one

statestate

Page 12: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#2: Vicinity graph#2: Vicinity graph

A 0A 0 E 0E 0 - -- - E 0E 0 A 0A 0 E 0E 0 - -- - C 0C 0

- -- - - -- - - -- - E 0E 0 E 0E 0 - -- - D -D - C 0C 0

A -A - D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1

A 0A 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0

0000 0101 1111 1010 0000 0101 1111 1010c=0c=0 c=1c=1

AA

CC

DD

EE

E

A C

D

A-C and C-E are essential, so we can try to eliminate A-E A-C and C-E are essential, so we can try to eliminate A-E

and C-Dand C-D

Page 13: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#2: Vicinity graph#2: Vicinity graph

A 0A 0 C 0C 0 - -- - C 0C 0 A 0A 0 C 0C 0 D 0D 0 C 0C 0

A 0A 0 E 0E 0 - -- - E 0E 0 E 0E 0 E -E - A -A - C 0C 0

A -A - D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1 D 1D 1

C 0C 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0 E 0E 0

0000 0101 1111 1010 0000 0101 1111 1010c=0c=0 c=1c=1

AA

CC

DD

EE

E

A C

D

00

11 01

10

Page 14: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3#3

• Find the Future State and Output functions of an Find the Future State and Output functions of an asynchronous circuit functioning in fundamental asynchronous circuit functioning in fundamental mode. The circuit has three inputs X, Y, and Z and mode. The circuit has three inputs X, Y, and Z and one output U, which goes to ‘1’ only when:one output U, which goes to ‘1’ only when:– There is a rising edge of X ANDThere is a rising edge of X AND– While the value of X was ‘0’, Y and Z followed the While the value of X was ‘0’, Y and Z followed the

sequence 00 - 10 – 11 (even if BEFORE or AFTER sequence 00 - 10 – 11 (even if BEFORE or AFTER this sequence Y and Z changed to different this sequence Y and Z changed to different values).values).

• U returns to ‘0’ as soon as X returns to ‘0’.U returns to ‘0’ as soon as X returns to ‘0’.• The circuit must have a race free state assignment.The circuit must have a race free state assignment.

Page 15: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Transition Table#3: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 A 0A 0 - -- - C 0C 0 A 0A 0 - -- - - -- - - -- -

B 0B 0 - -- - D 0D 0 C 0C 0 - -- - - -- - - -- - A 0A 0

D 0D 0 D 0D 0 D 0D 0 D 0D 0 E -E - E -E - E -E - E -E -

B -B - A -A - A -A - A -A - E 1E 1 E 1E 1 E 1E 1 E 1E 1

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

Wait for 00Wait for 00

Wait for X to return to 0Wait for X to return to 0

Wait for 10Wait for 10

Wait for 11Wait for 11

Now wait for rising edge XNow wait for rising edge X

AA

BB

CC

DD

EE

• We have to recognize the following sequence on Y We have to recognize the following sequence on Y and Z with X=0:and Z with X=0:

00 00 10 10 11 11

Page 16: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Transition Table Minimization#3: Transition Table Minimization

B 0B 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 A 0A 0 D 0D 0 B 0B 0 A 0A 0 - -- - - -- - A 0A 0

D 0D 0 D 0D 0 D 0D 0 D 0D 0 E -E - E -E - E -E - E -E -

B -B - A -A - A -A - A -A - E 1E 1 E 1E 1 E 1E 1 E 1E 1

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

Wait for 00Wait for 00

Wait for X to return to 0Wait for X to return to 0

Wait for 10 & 11Wait for 10 & 11

Now wait for rising edge XNow wait for rising edge X

AA

BB

DD

EE

• B and C are compatible so they can be collapsed in B and C are compatible so they can be collapsed in one stateone state

Page 17: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Transition Table Minimization#3: Transition Table Minimization

B 0B 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 A 0A 0 D 0D 0 B 0B 0 A 0A 0 - -- - - -- - A 0A 0

D 0D 0 D 0D 0 D 0D 0 D 0D 0 E -E - E -E - E -E - E -E -

B -B - A -A - A -A - A -A - E 1E 1 E 1E 1 E 1E 1 E 1E 1

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

AA

BB

DD

EE

I can remove E-B going trough E - A - BI can remove E-B going trough E - A - B

D

A B

E

Page 18: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Transition Table Minimization#3: Transition Table Minimization

B 0B 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 A 0A 0 D 0D 0 B 0B 0 A 0A 0 - -- - - -- - A 0A 0

D 0D 0 D 0D 0 D 0D 0 D 0D 0 E -E - E -E - E -E - E -E -

A -A - A -A - A -A - A -A - E 1E 1 E 1E 1 E 1E 1 E 1E 1

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

AA

BB

DD

EE

D

A B

E 11

00 01

10

Page 19: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Output function#3: Output function

00 00 00 00 00 00 00 00

00 00 00 00 00 -- -- --

00 00 00 00 -- -- -- --

-- -- -- -- 11 11 11 11

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

0000

0101

1111

1010

Page 20: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Output function#3: Output function

00 00 00 00 00 00 00 00

00 00 00 00 00 00 00 00

00 00 00 00 11 11 11 11

00 00 00 00 11 11 11 11

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

0000

0101

1111

1010

U = X SU = X S00

Page 21: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Future state function#3: Future state function

0101 0000 0000 0000 0000 0000 0000 0000

0101 0000 1010 0101 0000 0000 0000 0000

1111 1111 1111 1111 1010 1010 1010 1010

0000 0000 0000 0000 1010 1010 1010 1010

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

0000

0101

1111

1010

Page 22: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Future state function#3: Future state function

00 00 00 00 00 00 00 00

00 00 11 00 00 00 11 00

11 11 11 11 11 11 11 11

00 00 00 00 11 11 11 11

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

0000

0101

1111

1010

SS00 = S = S00SS11 + XS + XS0 0 + YZS+ YZS11

Page 23: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#3: Future state function#3: Future state function

11 00 00 00 00 00 00 00

11 00 00 11 00 00 00 00

11 11 11 11 00 00 00 00

00 00 00 00 00 00 00 00

0000 0101 1111 1010 0000 0101 1111 1010X=0X=0 X=1X=1

0000

0101

1111

1010

SS11 = S = S00SS11X + XYZSX + XYZS1 1 + XYZS+ XYZS0 0 + XYZS+ XYZS11

Page 24: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#5#5

• Design the reduced transition table of an Design the reduced transition table of an asynchronous circuit functioning in fundamental asynchronous circuit functioning in fundamental mode. The circuit has two inputs X and Y, and one mode. The circuit has two inputs X and Y, and one output U, which is 1 only if X=1 and, during the last output U, which is 1 only if X=1 and, during the last two rising-edges of X, Y maintained the same value.two rising-edges of X, Y maintained the same value.

• Also, find out the minimum number of state Also, find out the minimum number of state variables required to have a race free state variables required to have a race free state assignment.assignment.

Page 25: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#5: Primitive Transition table#5: Primitive Transition table

XY

00 01 11 10

A A,0 A,0 E,0 B,0 wait for the first transition of X

B C,0 C, 0 B,0 B,0 1st trans. & Y=0 – wait for X to go low

C C,0 C,0 E,0 D,- wait for another transition of X

D H,- H,- D,1 D,1 2nd trans. & Y=0 – wait for X to go low

E F,0 F,0 E,0 E,0 1st trans. & Y=1 – wait for X to go low

F F,0 F,0 G,- B,0 wait for another transition

G I,- I,- G,1 G,1 2nd trans. & Y=1 – wait for X to go low

H H,0 H,0 E,0 D,- last 2 trans Y=0 – wait for a new transition

I I,0 I,0 G,- B,0 last 2 trans Y=1 – wait for a new transition

Page 26: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#5: Reduced Transition table#5: Reduced Transition table

XW

00 01 11 10

A A,0 A,0 E,0 B,0 Equivalent states: C & H C

B C,0 C, 0 B,0 B,0 F & I F

C C,0 C,0 E,0 D,- No compatible states

D H,- H,- D,1 D,1

E F,0 F,0 E,0 E,0

F F,0 F,0 G,- B,0

G I,- I,- G,1 G,1

H H,0 H,0 E,0 D,-

I I,0 I,0 G,- B,0

Page 27: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#5: Reduced Transition table#5: Reduced Transition table

XW

00 01 11 10

A A,0 A,0 E,0 B,0 Equivalent states: C & H C

B C,0 C, 0 B,0 B,0 F & I F

C C,0 C,0 E,0 D,- No compatible states

D H,- H,- D,1 D,1

E F,0 F,0 E,0 E,0

F F,0 F,0 G,- B,0

G I,- I,- G,1 G,1

H H,0 H,0 E,0 D,-

I I,0 I,0 G,- B,0

Page 28: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#5: Reduced Transition table#5: Reduced Transition table

XW

00 01 11 10

A A,0 A,0 E,0 B,0 Equivalent states: C & H C

B C,0 C, 0 B,0 B,0 F & I F

C C,0 C,0 E,0 D,- No compatible states

D H,- H,- D,1 D,1

E F,0 F,0 E,0 E,0

F F,0 F,0 G,- B,0

G I,- I,- G,1 G,1

H H,0 H,0 E,0 D,-

I I,0 I,0 G,- B,0

Page 29: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#5: Reduced Transition table#5: Reduced Transition table

XW

00 01 11 10

A A,0 A,0 E,0 B,0 Equivalent states: C & H C

B C,0 C, 0 B,0 B,0 F & I F

C C,0 C,0 E,0 D,- No compatible states

D C,- C,- D,1 D,1

E F,0 F,0 E,0 E,0

F F,0 F,0 G,- B,0

G F,- F,- G,1 G,1

Page 30: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#5: Vicinity Graph#5: Vicinity Graph

• Max outdegree is 3. I need at least three state Max outdegree is 3. I need at least three state variablesvariables

A B C D E F G

Page 31: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#5: Vicinity Graph#5: Vicinity Graph

• It seems that there is no It seems that there is no solution with three solution with three variables.variables.

• Either we need 4 state Either we need 4 state variablesvariables

A B C D E F G

000

111

100

101001

010 110

011

?? ??

??

??

?? ??

??

??

Page 32: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#6#6

• Design the gate level model of an asynchronous Design the gate level model of an asynchronous circuit functioning in fundamental mode. The circuit circuit functioning in fundamental mode. The circuit has two inputs P (pulse) and R (reset) and one has two inputs P (pulse) and R (reset) and one output Z, which is normally at ‘0’. Z follows the output Z, which is normally at ‘0’. Z follows the following rules:following rules:– It goes to ‘1’ when a rising edge is detected on P It goes to ‘1’ when a rising edge is detected on P

and R=0.and R=0.– It goes to ‘0’ when R=1.It goes to ‘0’ when R=1.

Page 33: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

AA

BB

#6: Transition table#6: Transition table

P RP R

A 0A 0 B -B -

B 1B 1 C -C - B 1B 1C -C -

Let’s start with the correct sequence. Let’s start with the correct sequence. R=0 and P=0 and we wait for a R=0 and P=0 and we wait for a transition on P.transition on P.

CC

- -- -

We can stay in B until R changes back We can stay in B until R changes back to 1. to 1.

If R goes to 1, Z goes to 0 but we have If R goes to 1, Z goes to 0 but we have to wait for R to go to 0 again before to wait for R to go to 0 again before checking for another rising edge on Pchecking for another rising edge on P

Page 34: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

AA

BB

#6: Transition table#6: Transition table

P RP R

A 0A 0 B -B -

B 1B 1 C -C - B 1B 1C -C -

We can exit C only when both R and We can exit C only when both R and P are ‘0’.P are ‘0’.

CC

- -- -

If R goes to 1 while we are waiting for If R goes to 1 while we are waiting for a rising edge on P, we go out-of-a rising edge on P, we go out-of-sequence.sequence.

C 0C 0 C 0C 0 C 0C 0A 0A 0

C 0C 0

Page 35: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

AA

BB

#6: Vicinity graph#6: Vicinity graph

P RP R

A 0A 0 B -B -

B 1B 1 C -C - B 1B 1C -C -

CC

- -- -

C 0C 0 C 0C 0 C 0C 0A 0A 0

C 0C 0

B

A C2

21

00 01

Page 36: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

AA

BB

#6: Vicinity graph#6: Vicinity graph

P RP R

A 0A 0 B -B -

B 1B 1 A 0A 0 B 1B 1A 0A 0

CC

C 0C 0

C 0C 0 C 0C 0 C 0C 0A 0A 0

C 0C 0

B

A C2

21

Page 37: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

AA

BB

#6: Race free state assignment#6: Race free state assignment

P RP R

A 0A 0 B -B -

B 1B 1 A 0A 0 B 1B 1A 0A 0

CC

C 0C 0

C 0C 0 C 0C 0 C 0C 0A 0A 0

C 0C 0

B

A C0000 1010

0101

Page 38: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

0000

0101

#6: Output function#6: Output function

P RP R

A 0A 0 B -B -

B 1B 1 A 0A 0 B 1B 1A 0A 0

1010

C 0C 0

C 0C 0 C 0C 0 C 0C 0A 0A 0

C 0C 0 00 00 00 --

11 00 00 11

-- -- -- --

00 00 00 00

0000

0101

P RP R

1111

1010

Z = SZ = S00SS11RR

SS00 S S110000 0101 1111 1010

Page 39: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

0000

0101

#6: State function#6: State function

P RP R

A 0A 0 B -B -

B 1B 1 A 0A 0 B 1B 1A 0A 0

1010

C 0C 0

C 0C 0 C 0C 0 C 0C 0A 0A 0

C 0C 0 0000 1010 1010 0101

0101 0000 0000 0101

---- ---- ---- ----

0000 1010 1010 1010

0000

0101

P RP R

1111

1010

SS00 S S110000 0101 1111 1010

Page 40: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

0000

0101

#6: S#6: S00 variable variable

P RP R

A 0A 0 B -B -

B 1B 1 A 0A 0 B 1B 1A 0A 0

1010

C 0C 0

C 0C 0 C 0C 0 C 0C 0A 0A 0

C 0C 0 00 11 11 00

00 00 00 00

-- -- -- --

00 11 11 11

0000

0101

P RP R

1111

1010

SS00 S S110000 0101 1111 1010

SS00 = S = S0 0 P + SP + S1 1 RR

Page 41: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

0000 0101 1111 1010

0000

0101

#6: S#6: S11 variable variable

P RP R

A 0A 0 B -B -

B 1B 1 A 0A 0 B 1B 1A 0A 0

1010

C 0C 0

C 0C 0 C 0C 0 C 0C 0A 0A 0

C 0C 0 00 00 00 11

11 00 00 11

-- -- -- --

00 00 00 00

0000

0101

P RP R

1111

1010

SS00 S S110000 0101 1111 1010

SS11 = S = S1 1 R + SR + S0 0 P RP R

Page 42: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#6: Final circuit#6: Final circuit

PP

RR

SS00

ZZ

SS11

Page 43: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10#10

• Design an asynchronous circuit functioning in Design an asynchronous circuit functioning in fundamental mode. The circuit has two inputs A and fundamental mode. The circuit has two inputs A and B, and one output Z, which is normally at ‘0’. Z B, and one output Z, which is normally at ‘0’. Z changes value when it recognize the sequence 00 – changes value when it recognize the sequence 00 – 01 – 00 on the inputs. 00 can be considered 01 – 00 on the inputs. 00 can be considered concurrently the end of a sequence and the concurrently the end of a sequence and the beginning of a new one.beginning of a new one.

• Show:Show:– A Minimized Transition tableA Minimized Transition table– A race free state assignmentA race free state assignment– The Boolean function for ZThe Boolean function for Z

Page 44: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10: Transition Table#10: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 C 0C 0 - -- -

D -D - C 0C 0 - -- -

D 1D 1 E 1E 1 - -- -

B -B - E 1E 1 - -- -

0000 0101 1111 1010

Wait for 00Wait for 00

Wait for 00Wait for 00

Wait for 01;Wait for 01;

Wait for 00Wait for 00

Sequence OK; wait for 01Sequence OK; wait for 01

AA

BB

CC

DD

EE

FF

Sequence OKSequence OK

Out of sequenceOut of sequence

Page 45: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10: Transition Table#10: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 C 0C 0 - -- - A 0A 0

D -D - C 0C 0 A 0A 0 - -- -

D 1D 1 E 1E 1 - -- - F 1F 1

B -B - E 1E 1 F 1F 1 - -- -

D 1D 1 F 1F 1 F 1F 1 F 1F 1

0000 0101 1111 1010

Out of sequence; Wait for 00Out of sequence; Wait for 00

Wait for 00Wait for 00

Wait for 01Wait for 01

Wait for 00Wait for 00

Sequence OK; wait for 01Sequence OK; wait for 01

AA

BB

CC

DD

EE

FF

Sequence OKSequence OK

Out of sequence; wait for 00Out of sequence; wait for 00

U=0U=0

U=1U=1

Page 46: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10: Vicinity Graph#10: Vicinity Graph

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 C 0C 0 - -- - A 0A 0

D -D - C 0C 0 A 0A 0 - -- -

D 1D 1 E 1E 1 - -- - F 1F 1

B -B - E 1E 1 F 1F 1 - -- -

D 1D 1 F 1F 1 F 1F 1 F 1F 1

0000 0101 1111 1010

AA

BB

CC

DD

EE

FF

• There are no equivalent or There are no equivalent or compatible states.compatible states.

B

A C

E

F D

Page 47: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10: Vicinity Graph#10: Vicinity Graph

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 C 0C 0 - -- - A 0A 0

D -D - C 0C 0 A 0A 0 - -- -

D 1D 1 E 1E 1 - -- - F 1F 1

B -B - E 1E 1 F 1F 1 - -- -

D 1D 1 F 1F 1 F 1F 1 F 1F 1

0000 0101 1111 1010

AA

BB

CC

DD

EE

FF

• We can eliminate A – C and F - EWe can eliminate A – C and F - E

B

A C

E

F D

Page 48: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10: Vicinity Graph#10: Vicinity Graph

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 C 0C 0 A 0A 0 A 0A 0

D -D - C 0C 0 B 0B 0 - -- -

D 1D 1 E 1E 1 F 1F 1 F 1F 1

B -B - E 1E 1 D 1D 1 - -- -

D 1D 1 F 1F 1 F 1F 1 F 1F 1

0000 0101 1111 1010

AA

BB

CC

DD

EE

FF

• We can eliminate A – C and F - EWe can eliminate A – C and F - E

B

A C

E

F D

Page 49: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10: Vicinity Graph#10: Vicinity Graph

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 C 0C 0 A 0A 0 A 0A 0

D -D - C 0C 0 B 0B 0 - -- -

D 1D 1 E 1E 1 F 1F 1 F 1F 1

B -B - E 1E 1 D 1D 1 - -- -

D 1D 1 F 1F 1 F 1F 1 F 1F 1

0000 0101 1111 1010

AA

BB

CC

DD

EE

FF

• A race free state assignment is:A race free state assignment is:

110

111 010

100

001 000

Page 50: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10: Output Function#10: Output Function

00 00 00 00

00 00 00 00

-- 00 00 --

11 11 11 11

-- 11 11 --

11 11 11 11

0000 0101 1111 1010

111111

110110

010010

000000

100100

001001

• Be careful! To cover the table, Be careful! To cover the table, you have to order the rows you have to order the rows correctly: it has to be a K-map!correctly: it has to be a K-map!

Page 51: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#10: Output Function#10: Output Function

00 00 00 00

00 00 00 00

-- 00 00 --

11 11 11 11

-- 11 11 --

11 11 11 11

111111

110110

010010

000000

100100

001001

11 11 11 11

11 11 11 11

-- -- -- --

-- 00 00 --

-- 11 11 --

-- -- -- --

00 00 00 00

00 00 00 00

Z = SZ = S11

0000 0101 1111 1010

000000

001001

011011

010010

100100

101101

111111

110110

0000 0101 1111 1010SS00 S S11 SS22

Page 52: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16#16

• Design an asynchronous circuit with two inputs (A Design an asynchronous circuit with two inputs (A and B) and one output, functioning in fundamental and B) and one output, functioning in fundamental mode. The output U of the circuit is equal to 1 iff:mode. The output U of the circuit is equal to 1 iff:– A=0 ANDA=0 AND– During the last interval in which A=1 there has During the last interval in which A=1 there has

been a SINGLE transition (1-0-1) on B.been a SINGLE transition (1-0-1) on B.• U changes back to ‘0’ as soon as A goes back to ‘1’.U changes back to ‘0’ as soon as A goes back to ‘1’.• Show:Show:

– A Minimized Transition tableA Minimized Transition table– A race free state assignmentA race free state assignment– The Output and State Boolean functionsThe Output and State Boolean functions

Page 53: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Comment#16: Comment

• The problem asks to design a sequence recognizer The problem asks to design a sequence recognizer for the following sequence:for the following sequence:

11 11 10 10 11 11 0- 0-

A

B

U

Page 54: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: transition table#16: transition table

AA

BB

CC

DD

EE

FF

A 0

• Let’s start to draw the transition table from a Let’s start to draw the transition table from a state where we wait for the correct beginning of state where we wait for the correct beginning of the sequence. the sequence.

0000 0101 1111 1010

A 0 B 0 • A correct sequence starts A correct sequence starts when A goes to 1 while B is when A goes to 1 while B is already 1already 1B 0

Page 55: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: transition table#16: transition table

AA

BB

CC

DD

EE

FF

A 0

• Let’s start to draw the transition table from a Let’s start to draw the transition table from a state where we wait for the correct beginning of state where we wait for the correct beginning of the sequence. the sequence.

0000 0101 1111 1010

A 0 B 0

B 0

A

B

Page 56: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: transition table#16: transition table

AA

BB

CC

DD

EE

FF

A 0

• Now we can fill the transition table with the Now we can fill the transition table with the CORRECT sequenceCORRECT sequence

0000 0101 1111 1010

A 0 B 0

B 0 C 0

D 0 C 0

E -

E 1 E 1 B 0

D 0

A

B

Page 57: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: transition table#16: transition table

AA

BB

CC

DD

EE

FF

A 0

• Now we have to complete the table with the out-Now we have to complete the table with the out-of-sequence conditionsof-sequence conditions

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

• If A goes to 1 with B=0, I am If A goes to 1 with B=0, I am already out of sequence, already out of sequence, because I will have too many because I will have too many transitions of B while A=1.transitions of B while A=1.

Too many transitions!

• I can now wait in F until A goes I can now wait in F until A goes back to 0, and then go to state A back to 0, and then go to state A to wait for the right condition.to wait for the right condition.

Page 58: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: transition table#16: transition table

AA

BB

CC

DD

EE

FF

A 0

• Now we have to complete the table with the out-Now we have to complete the table with the out-of-sequence conditionsof-sequence conditions

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

• If A goes to 0 to early, I go back If A goes to 0 to early, I go back to state A waiting for the to state A waiting for the beginning of a new sequence.beginning of a new sequence.

Too many transitions!

• If B goes to 0 again, I have too many If B goes to 0 again, I have too many transitions on B, and therefore I will transitions on B, and therefore I will have to go to the F statehave to go to the F state

- - A 0

A 0 - -

- - F 0

F 0

Page 59: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Minimize the Transition table#16: Minimize the Transition table

AA

BB

CC

DD

EE

FF

A 0

• There are no equivalent statesThere are no equivalent states• There are no compatible statesThere are no compatible states

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

- - A 0

A 0 - -

- - F 0

F 0

Page 60: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

- - A 0

A 0 - -

- - F 0

F 0

B

A C

E

F D

3

3

1

1

1

1

1

1

1

Page 61: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

- - A 0

A 0 - -

- - F 0

F 0

B

A C

E

F D

3

3

1

1

1

1

1

1

1

Page 62: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 - -

- - F 0

F 0

B

A C

E

F D

3

3

1

1

1

1

1

1

1

Page 63: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 - -

- - F 0

F 0

B

A C

E

F D

3

3

1

1

1

1

1

1

1

Page 64: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0

- -

- - F 0

D 0

B

A C

E

F D

3

3

1

1

1

1

1

1

1

A 0

B 0

Page 65: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0

- -

- - F 0

D 0

B

A C

E

F D

A 0

B 0

Page 66: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Race free state assignment#16: Race free state assignment

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0

- -

- - F 0

D 0

000

100 001

010

??? 011

A 0

B 0

Page 67: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Race free state assignment#16: Race free state assignment

• It seems there is no solution with three state It seems there is no solution with three state variables. variables.

• Before deciding to add a new variable, let’s try to Before deciding to add a new variable, let’s try to modify the graph in another waymodify the graph in another way

Page 68: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

- - A 0

A 0 - -

- - F 0

F 0

B

A C

E

F D

3

3

1

1

1

1

1

1

1

Page 69: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

- - A 0

A 0 - -

- - F 0

F 0

B

A C

E

F D

A-C

Page 70: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 - -

- - F 0

F 0

B

A C

E

F D

A-C

Page 71: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 - -

- - F 0

F 0

B

A C

E

F D

D-F

Page 72: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 - -

- - E 0

F 0

B

A C

E

F D

D-F

Page 73: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 - -

- - E 0

F 0

B

A C

E

F D

D-E

• In this case we can try to move the arcIn this case we can try to move the arc

Page 74: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

F 0

B

A C

E

F D

D-E

• In this case we can try to move the arcIn this case we can try to move the arc

Page 75: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

F 0

B

A C

E

F D

E-F

• Again, we can try to remove the arcAgain, we can try to remove the arc

Page 76: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

B

A C

E

F D

E-F

• Again, we can try to remove the arcAgain, we can try to remove the arc

Page 77: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

B

A C

E

F D

B-E

• Again, we can try to remove the arcAgain, we can try to remove the arc

Page 78: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 A 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

B

A C

E

F D

B-E

• The last edge we can remove is B-EThe last edge we can remove is B-E

Page 79: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Vicinity Graph#16: Vicinity Graph

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

001

000 011

010

100 111

• Now a race free assignment is possibleNow a race free assignment is possible

B

A C

E

F D

Page 80: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Output table#16: Output table

000000

001001

011011

111111

010010

100100

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

• Let’s start with the output tableLet’s start with the output table

00 00 00 00

00 00 00 00

00 00 00 00

11 11 00 00

00 00 00 00

-- -- -- --

-- 00 00 00

-- -- -- --

000000

001001

011011

010010

100100

101101

111111

110110

0000 0101 1111 1010SS00 S S11 SS22

Page 81: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Output table#16: Output table

000000

001001

011011

111111

010010

100100

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

• Let’s start with the output tableLet’s start with the output table

00 00 00 00

00 00 00 00

00 00 00 00

11 11 00 00

00 00 00 00

00 00 00 00

00 00 00 00

11 11 00 00

000000

001001

011011

010010

100100

101101

111111

110110

0000 0101 1111 1010SS00 S S11 SS22

U=S1 S2 A

Page 82: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: State variables#16: State variables

000000

001001

011011

111111

010010

100100

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

000000 000000 001001 100100

000000 000000 001001 011011

001001 010010 111111 011011

010010 010010 001001 000000

000000 000000 100100 100100

-- -- -- --

-- 011011 111111 010010

-- -- -- --

000000

001001

011011

010010

100100

101101

111111

110110

0000 0101 1111 1010SS00 S S11 SS22

Page 83: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: S#16: S00 state variable state variable

000000

001001

011011

111111

010010

100100

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

00 00 00 11

00 00 00 00

00 00 11 00

00 00 00 00

00 00 11 11

-- -- -- --

-- 00 11 00

-- -- -- --

000000

001001

011011

010010

100100

101101

111111

110110

0000 0101 1111 1010SS00 S S11 SS22

Page 84: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: S#16: S11 state variable state variable

000000

001001

011011

111111

010010

100100

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

00 00 00 00

00 00 00 11

00 11 11 11

11 11 00 00

00 00 00 00

-- -- -- --

-- 11 11 11

-- -- -- --

000000

001001

011011

010010

100100

101101

111111

110110

0000 0101 1111 1010SS00 S S11 SS22

Page 85: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: S#16: S22 state variable state variable

000000

001001

011011

111111

010010

100100

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

C 0 D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

A 0 A 0

B 0 E 0

- - E 0

A 0

00 00 11 00

00 00 11 11

11 00 11 11

00 00 11 00

00 00 00 00

-- -- -- --

-- 11 11 00

-- -- -- --

000000

001001

011011

010010

100100

101101

111111

110110

0000 0101 1111 1010SS00 S S11 SS22

Page 86: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Another solution for State coding#16: Another solution for State coding

• There is another possible solution for the vicinity There is another possible solution for the vicinity graph.graph.

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

- - A 0

A 0 - -

- - F 0

F 0

B

A C

E

F D

Page 87: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Another solution for State coding#16: Another solution for State coding

• By removing only A-C and F-D, a solution is By removing only A-C and F-D, a solution is possible:possible:

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

- - A 0

B 0 - -

- - E 0

F 0

B

A C

E

F D

Page 88: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#16: Another solution for State coding#16: Another solution for State coding

• By removing only A-C and F-D, a solution is By removing only A-C and F-D, a solution is possible:possible:

AA

BB

CC

DD

EE

FF

A 0

0000 0101 1111 1010

A 0 B 0 F 0

B 0 C 0

D 0 C 0

E - D 0

E 1 E 1 B 0

A 0 A 0 F 0 F 0

D 0

- - A 0

B 0 - -

- - E 0

F 0

001

000 101

011

010 111

Page 89: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#9#9

• Design an asynchronous circuit with two inputs (A Design an asynchronous circuit with two inputs (A and B) and one output, functioning in fundamental and B) and one output, functioning in fundamental mode. The output U of the circuit is equal to 1 iff it mode. The output U of the circuit is equal to 1 iff it recognize the following input sequence:recognize the following input sequence:– AB = 00 – 01 – 11 – 10 - 00AB = 00 – 01 – 11 – 10 - 00

• U changes back to ‘0’ as soon as A or B change to 1.U changes back to ‘0’ as soon as A or B change to 1.• Show:Show:

– A Minimized Transition tableA Minimized Transition table– A race free state assignmentA race free state assignment

Page 90: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#9: Transition Table#9: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 C 0C 0 - -- - A 0A 0

B 0B 0 C 0C 0 D 0D 0 - -- -

- -- - A 0A 0 D 0D 0 E 0E 0

F -F - - -- - A 0A 0 E 0E 0

F 1F 1 C -C - - -- - A -A -

AA

BB

CC

DD

EE

0000 0101 1111 1010

FF

Page 91: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#9: Transition Table#9: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 C 0C 0 - -- - A 0A 0

B 0B 0 C 0C 0 D 0D 0 - -- -

- -- - A 0A 0 D 0D 0 E 0E 0

F -F - - -- - A 0A 0 E 0E 0

F 1F 1 C -C - - -- - A -A -

AA

BB

CC

DD

EE

0000 0101 1111 1010

FF

Compatible States

Page 92: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#9: Transition Table#9: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 B 0B 0 D 0D 0 A 0A 0

- -- - A 0A 0 D 0D 0 E 0E 0

F -F - - -- - A 0A 0 E 0E 0

F 1F 1 B -B - - -- - A -A -

AA

BB

DD

EE

0000 0101 1111 1010

FF

D

A B

E F

Page 93: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#9: Transition Table#9: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 B 0B 0 D 0D 0 A 0A 0

- -- - A 0A 0 D 0D 0 E 0E 0

F -F - - -- - A 0A 0 E 0E 0

F 1F 1 B -B - - -- - A -A -

AA

BB

DD

EE

0000 0101 1111 1010

FF

D

A B

E F

Page 94: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#9: Transition Table#9: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 B 0B 0 D 0D 0 A 0A 0

- -- - E 0E 0 D 0D 0 E 0E 0

F -F - A 0A 0 A 0A 0 E 0E 0

F 1F 1 B -B - - -- - B -B -

AA

BB

DD

EE

0000 0101 1111 1010

FF

D

A B

E F

Page 95: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#9: Transition Table#9: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 B 0B 0 G 0G 0 A 0A 0

- -- - E 0E 0 D 0D 0 E 0E 0

F -F - A 0A 0 A 0A 0 E 0E 0

F 1F 1 B -B - - -- - B -B -

- -- - - -- - H 0H 0 - -- -

- -- - - -- - D 0D 0 - -- -

AA

BB

DD

EE

0000 0101 1111 1010

FF

D

A B

E F

H

G

GG

HH

Page 96: Section 1.3 Asynchronous Circuits Exercises Alfredo Benso Politecnico di Torino, Italy Alfredo.benso@polito.it

#9: Transition Table#9: Transition Table

B 0B 0 A 0A 0 A 0A 0 A 0A 0

B 0B 0 B 0B 0 G 0G 0 A 0A 0

- -- - E 0E 0 D 0D 0 E 0E 0

F -F - A 0A 0 A 0A 0 E 0E 0

F 1F 1 B -B - - -- - B -B -

- -- - - -- - H 0H 0 - -- -

- -- - - -- - D 0D 0 - -- -

AA

BB

DD

EE

0000 0101 1111 1010

FF

110

000 001

010 011

111

101

GG

HH