[SCILLC] Soldering and Mounting Techniques. Refere(BookZZ.org)

Soldering and Mounting Techniques

SOLDERRM/DRev. 6, September2008

Reference Manual

SCILLC, 2008All Rights Reserved

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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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FULLPAK, ICePAK, MicroIntegration, MicroLeadless, MOSORB, MiniMOSORB, and POWERTAP are trademarks of SemiconductorComponents Industries, LLC (SCILLC). ChoTherm is a registered trademark of Chromerics, Inc. Grafoil is a registered trademark ofUnion Carbide. Kapton is a registered trademark of du Pont de Nemours & Co., Inc. KonDux and RubberDuc are trademarks of AavidThermal Technologies, Inc. PowerFLEX is a trademark of Texas Instruments Incorporated. Thermasil is a registered trademark and Ther-mafilm is a trademark of Thermalloy, Inc. Micro8 is a trademark of International Rectifier. Intel and Pentium are registered trademarks andItanium is a trademark of Intel Corporation. ChipFET is a trademark of Vishay Siliconix. POWERMITE is a registered trademark of andused under a license from Microsemi Corporation.

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Table of ContentsPage

Section 1:General Pb (Lead) Free Lead Finish/Plating Strategy 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 2:Soldering/Mounting Techniques 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Soldering Considerations for Surface Mount Packages 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprints for Soldering 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POWERMITE 14. . . . . . . . . . . . . . . . . . SMA 14. . . . . . . . . . . . . . . . . . . . . . . . . . . SMB 14. . . . . . . . . . . . . . . . . . . . . . . . . . .

SMC 14. . . . . . . . . . . . . . . . . . . . . . . . . . . SOD123 14. . . . . . . . . . . . . . . . . . . . . . . SOD323 14. . . . . . . . . . . . . . . . . . . . . . .

SOD523 15. . . . . . . . . . . . . . . . . . . . . . . SOD723 15. . . . . . . . . . . . . . . . . . . . . . . SC59 15. . . . . . . . . . . . . . . . . . . . . . . . . .

SC70/SOT323 15. . . . . . . . . . . . . . . . . SC75/SC89/SOT416 15. . . . . . . . . . SOT23 15. . . . . . . . . . . . . . . . . . . . . . . .

SOT723 16. . . . . . . . . . . . . . . . . . . . . . . SOT1123 16. . . . . . . . . . . . . . . . . . . . . . DPAK 16. . . . . . . . . . . . . . . . . . . . . . . . . .

D2PAK 16. . . . . . . . . . . . . . . . . . . . . . . . . . WDFN3 16. . . . . . . . . . . . . . . . . . . . . . . . . SC82AB 16. . . . . . . . . . . . . . . . . . . . . . .

SOT223 17. . . . . . . . . . . . . . . . . . . . . . . SOT553 17. . . . . . . . . . . . . . . . . . . . . . . SC88A/SC705/SOT353 17. . . . . . . .

SOT953 17. . . . . . . . . . . . . . . . . . . . . . . THIN SOT235/TSOP5/SC595 17. . 5LEAD D2PAK 17. . . . . . . . . . . . . . . . . .

5LEAD DPAK Central Lead Crop 18. . 6PIN FLIPCHIP 18. . . . . . . . . . . . . . . . SC88/SC706/SOT363 18. . . . . . . . .

SC74/SC74R 18. . . . . . . . . . . . . . . . . . SOT563 18. . . . . . . . . . . . . . . . . . . . . . . SOT963 18. . . . . . . . . . . . . . . . . . . . . . .

TSOP6 19. . . . . . . . . . . . . . . . . . . . . . . . UDFN6/WDFN6, 1.2 x 1 19. . . . . . . . . . DFN6, 2 x 2 19. . . . . . . . . . . . . . . . . . . . .

DFN6, 2 x 2.2 19. . . . . . . . . . . . . . . . . . . DFN6, 3 x 3, Single Flag 19. . . . . . . . . . DFN6, 3 x 3, Single Flag 19. . . . . . . . . .

DFN6, 3 x 3, Dual Flag 20. . . . . . . . . . . . CLCC6 20. . . . . . . . . . . . . . . . . . . . . . . . 7LEAD D2PAK 20. . . . . . . . . . . . . . . . . .

7LEAD D2PAK, Short Lead 20. . . . . . . Micro8 20. . . . . . . . . . . . . . . . . . . . . . . . Micro8 Leadless 20. . . . . . . . . . . . . . . . .

SO8 21. . . . . . . . . . . . . . . . . . . . . . . . . . . SO8 Exposed Pad 21. . . . . . . . . . . . . . SO8FL (DFN6), 5 x 6 21. . . . . . . . . . . . .

DFN8/UDFN8, 1.6 x 1.6 21. . . . . . . . . . . UDFN8, 1.8 x 1.2 21. . . . . . . . . . . . . . . . DFN8, 2 x 2 21. . . . . . . . . . . . . . . . . . . . .

UDFN8, 2 x 2.2 22. . . . . . . . . . . . . . . . . . DFN8, 3 x 3 22. . . . . . . . . . . . . . . . . . . . . DFN8, 4 x 4 22. . . . . . . . . . . . . . . . . . . . .

DFN8, 5 x 6 22. . . . . . . . . . . . . . . . . . . . . US8 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Bump (FlipChip) 22. . . . . . . . . . . . . .

9Bump 23. . . . . . . . . . . . . . . . . . . . . . . . Micro10 23. . . . . . . . . . . . . . . . . . . . . . . . . UQFN10/WQFN10, 1.4 x 1.8 23. . . . . .

WDFN10, 2.5 x 2 23. . . . . . . . . . . . . . . . . DFN10, 3 x 3 23. . . . . . . . . . . . . . . . . . . . UDFN10 23. . . . . . . . . . . . . . . . . . . . . . . .

UQFN12, 1.7 x 2 24. . . . . . . . . . . . . . . . . DFN12, 3 x 3 24. . . . . . . . . . . . . . . . . . . . WDFN12, 3 x 4 24. . . . . . . . . . . . . . . . . .

DFN12 24. . . . . . . . . . . . . . . . . . . . . . . . . PLLP12 24. . . . . . . . . . . . . . . . . . . . . . . . SOIC14 24. . . . . . . . . . . . . . . . . . . . . . . .

TSSOP14 25. . . . . . . . . . . . . . . . . . . . . . UQFN16/WQFN16, 1.8 x 2.6 25. . . . . . QFN16, 3 x 3/EP, 2 x 2 25. . . . . . . . . .

QFN16, 4 x 4 25. . . . . . . . . . . . . . . . . . . . SOIC16 25. . . . . . . . . . . . . . . . . . . . . . . . SOIC16EP 25. . . . . . . . . . . . . . . . . . . . .

DFN16 26. . . . . . . . . . . . . . . . . . . . . . . . . TSSOP16 26. . . . . . . . . . . . . . . . . . . . . . TSSOP20 26. . . . . . . . . . . . . . . . . . . . . .

UDFN20, 4 x 2 26. . . . . . . . . . . . . . . . . . . LLGA20, 6 x 5 26. . . . . . . . . . . . . . . . . . DFN22, 6 x 5 26. . . . . . . . . . . . . . . . . . . .

TLLGA32, 4 x 4 27. . . . . . . . . . . . . . . . . . QFN32, 5 x 5 27. . . . . . . . . . . . . . . . . . . . ChipFET 27. . . . . . . . . . . . . . . . . . . . . . . .

Board Level Application Notes for DFN and QFN Packages 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mounting Considerations for Power Semiconductors 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mounting Considerations for FlipChips 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 3:Handling of Semiconductor Packages 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 4:Semiconductor Package Reliability and Quality 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 5:Device Rework / Removal 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Section 1

General Pb (Lead) Free Lead Finish/Plating Strategy

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General Pb (Lead) Free Lead Finish/Plating Strategy

In order to provide maximum flexibility and conveniencefor our customers, ON Semiconductor is modifying itsstrategy to support the Pbfree global initiatives from theprevious General Announcement #12770.

Pbfree Plating Strategy ON Semiconductor nowoffers a portfolio of devices that are plated with Pbfreelead finishes. Many of our products were originallyreleased as Pbfree and do not have a comparable leadedversion available. For devices which have been Pbfreesince their inception, we do not intend to introduce anynew Pbcontaining lead finish versions of those devices.

For those customers that choose not to convert to ourPbfree offering according to our conversion plan,ON Semiconductor will continue to offer the current Pbcontaining devices until business conditions no longerprove feasible. We are committed to meeting the needs ofall of our customers as our industry transitions to Pbfreeover the next couple of years.

ON Semiconductor has qualified the majority of ourpackages in the Pbfree version and have made themavailable for sampling and production ordering. The listbelow shows the packages that have been qualified and thefew remaining with their targeted completion dates. Pleasecontact your ON Semiconductor Sales Representative if thisschedule does not meet your conversion needs, or if youwant to order Pbfree samples.

ON Semiconductor is fully compliant with the RoHSdirective for all of the parts for which it makes businesssense to do so. In other words, ON Semiconductor offers

Pbfree versions of all of the parts for which there issufficient demand. We will also continue to offer all ofthese parts in a standard TinLead (SnPb) lead finish untilmarket conditions necessitate a change in direction.

Moisture Sensitivity Level (MSL) Surface MountPackages are qualified to 260C, which is compliant tothe JEDEC standard JSTD020C. The majority of theMSL ratings will remain unchanged from the currentMSL 1 classification. If there is a change in the MSLrating of a package, the customer will be notified andappropriate packing precautions will be taken before anyproduct is shipped by ON Semiconductor.

Product Identification Devices offered without a Pbcontaining lead finish will be concatenated with a Gsuffix to denote Pbfree lead finish and qualifiedcompatibility with Pbfree board mount assemblyprocessing. Existing packages that are currently offeredsolely with a Pbfree finish will also change partnumbers. This is intended to clearly identify parts that arePbfree and qualified for compatibility with Pbfreeboard mount assembly processing. The MPN(Manufacturer Part Number) bar code label on the reel,tube or rail, and the intermediate boxes will have thePbfree 2LI logo printed on those labels compliant toJEDEC standard JESD97. Pbfree products may also beidentified by unique product marking. Pbfree productsare marked with a G suffix to the part number on thepackage. However, if the package is too small to includethe additional G character, the Pbfree package will bemarked with a micro dot.

Available Now

Axial Lead Button POWERMITE SO8 SSOP

Case 77 POWERTAP SOD123 SSOVP

ChipFET PSOP2 SOD323 Surge Special

D2PAK 3, 5, 7 QFN 5x5, 5x6, 7x7, 8x8 SOD523 Surmetic

D2PAK Discrete QFN 2x2.2, 3x3, 4x4 SOEIAJ 8/14/16/20 TO218

DFN 1.6x1.6, 3x1, 3x3, 3.3x3.3, 4x1.6 SC59 SOIC Narrow 7/8/14/16 TO220 3/5/7

DPAK SC70 3/5 SOIC Wide 16/18/20/24 TO247

FCDCA SC74 SOIC 16W EP TO264

LQFP 32/52 SC75 SON 6 B/S TO3

LQFP 52/64 EP SC82AB SOT223 TO92

Micro8/10 IC SC82 Dual SOT23 3 Pin Top Can

Micro8 FET SC88 SOT23 5 Pin TQFP 48 EP

Micro Leadless 3 SC88A SOT23 6 Pin TSOP5

MOSORB/MiniMOSORB SC89 SOT23L TSOP6

PDIP 7/8/14/16/18/20/24N/24W SIDAC 1 & 3 Amp SOT553 TSSOP 8/14/16/20/24/48

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Available Now

PLCC 20/28/44 SMA & SMA B/S SOT563 US8

SMB SOT723 PowerFLEX SMC SOT89

Planned

FCBGA 16/49 SOIC 32W SPAK 5/7

Not Planned

BGA CLCC QSOP CDIP PLLP (PQFN) SOT143

Qualification Plan:The qualification requirements for Pbfree external

lead finish differ for surfacemount device (SMD) orthroughhole devices (THD).

For the THDs the primary qualification requirement isto demonstrate forward compatibility with new Pbfreesolder pastes (based on SnCuAg). The tests performedtypically include:

Solderability with SnCuAg solder Resistance to Solder Heat

For the SMDs reclassification of the moisturesensitivity level (MSL) at a peak reflow temperature of260C is required in addition to solderability validation.The MSL reclassification is performed on the largestdie size that is used in the package. The tests performedtypically include:

Preconditioned Highly Accelerated Stress Testing(PCHAST) 96 hours minimum

Preconditioned Autoclave (PCAC) 96 hoursminimum

Preconditioned Temperature Cycling (PCTC) 500cycles minimum

(Preconditioning is performed at the target MSL for260 +5/0C)

Solderability with SnCuAg solder Resistance to Solder Heat (RSH Solder Immersion)

Backward CompatibilityBackward compatibility is the capability for our

customers to take one of our Pbfree products, mount it ontheir PC board and reflow it using solder containing lead(Pb). ON Semiconductor has conducted reflow tests ofPbfree parts using leaded solder reflow temperatures andprocesses to simulate this condition. Tests have beenconducted at 210 to 230C and results show that there willnot be solderability issues.

Please Note: This does not apply to BGA, bumped dieor FlipChip devices. If the parts are Pbfree theyneed to use a Pbfree reflow process.

Points of Contact: Your Local ON Semiconductor Sales Representative ON Semiconductor Technical Information Center

18002829855 (US & Canada) or via web athttp://www.onsemi.com/techsupport

http://www.onsemi.com/pbfree

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Section 2

Soldering / Mounting Techniques

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Soldering Considerations for Surface Mount PackagesRECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the totaldesign. The footprint for the semiconductor packages mustbe the correct size to ensure proper solder connection

interface between the board and the package. With thecorrect pad geometry, the packages will self align whensubjected to a solder reflow process.

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is afunction of the drain/collector pad size. These can vary fromthe minimum pad size for soldering to a pad size given formaximum power dissipation. Power dissipation for asurface mount device is determined by TJ(max), themaximum rated junction temperature of the die, RJA, thethermal resistance from the device junction to ambient, andthe operating ambient temperature, TA. Using the valuesprovided on the data sheet, PD can be calculated as follows:

PD =TJ(max) TA

RJA

The values for the equation are found in the maximumratings table on the data sheet. Substituting these values intothe equation for an ambient temperature TA of 25C, one cancalculate the power dissipation of the device. For example,for a SOT223 device, PD is calculated as follows.

PD =150C 25C

156C/W= 800 milliwatts

The 156C/W for the SOT223 package assumes the useof the recommended footprint on a glass epoxy printedcircuit board to achieve a power dissipation of 800milliwatts. There are other alternatives to achieving higherpower dissipation from the surface mount packages. One isto increase the area of the drain/collector pad. By increasingthe area of the drain/collector pad, the power dissipation canbe increased. Although the power dissipation can almost bedoubled with this method, area is taken up on the printedcircuit board which can defeat the purpose of using surfacemount technology. For example, a graph of RJA versusdrain pad area is shown in Figures 1, 2 and 3.

Another alternative would be to use a ceramic substrate oran aluminum core board such as Thermal Clad. Using aboard material such as Thermal Clad, an aluminum coreboard, the power dissipation can be doubled using the samefootprint.

TO A

MBI

ENT

(C

/W)

R

JA, T

HER

MAL

RES

ISTA

NC

E, J

UN

CTI

ON

0.8 Watts

1.25 Watts* 1.5 Watts

A, AREA (SQUARE INCHES)0.0 0.2 0.4 0.6 0.8 1.0

160

140

120

100

80

Figure 1. Thermal Resistance versus Drain PadArea for the SOT223 Package (Typical)

Board Material = 0.0625G-10/FR-4, 2 oz Copper

TA = 25C

*Mounted on the DPAK footprint

Figure 2. Thermal Resistance versus Drain PadArea for the DPAK Package (Typical)

1.75 Watts

Board Material = 0.0625G-10/FR-4, 2 oz Copper

80

100

60

40

201086420

3.0 Watts

5.0 Watts

TA = 25C

A, AREA (SQUARE INCHES)

TO A

MBI

ENT

(C

/W)

R

JA, T

HER

MAL

RES

ISTA

NC

E, J

UN

CTI

ON

Figure 3. Thermal Resistance versus Drain PadArea for the D2PAK Package (Typical)

2.5 Watts

A, AREA (SQUARE INCHES)

Board Material = 0.0625G-10/FR-4, 2 oz Copper TA = 25C

60

70

50

40

30

201614121086420

3.5 Watts

5 Watts

TO A

MBI

ENT

(C

/W)

R

JA, T

HER

MAL

RES

ISTA

NC

E, J

UN

CTI

ON

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SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printedcircuit board, solder paste must be applied to the pads.Solder stencils are used to screen the optimum amount.These stencils are typically 0.008 inches thick and may bemade of brass or stainless steel. For packages such as theSC59, SC70/SOT323, SOD123, SOT23, SOT143,SOT223, SO8, SO14, SO16, and SMB/SMC diodepackages, the stencil opening should be the same as the padsize or a 1:1 registration. This is not the case with the DPAKand D2PAK packages. If a 1:1 opening is used to screensolder onto the drain pad, misalignment and/ortombstoning may occur due to an excess of solder. Forthese two packages, the opening in the stencil for the pasteshould be approximately 50% of the tab area. The openingfor the leads is still a 1:1 registration. Figure 4 shows atypical stencil for the DPAK and D2PAK packages. The

pattern of the opening in the stencil for the drain pad is notcritical as long as it allows approximately 50% of the pad tobe covered with paste.

Figure 4. Typical Stencil for DPAK andD2PAK Packages

SOLDER PASTEOPENINGS

STENCIL

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the ratedtemperature of the device. When the entire device is heatedto a high temperature, failure to complete soldering withina short time could result in device failure. Therefore, thefollowing items should always be observed in order tominimize the thermal stress to which the devices aresubjected.

Always preheat the device. The delta temperature between the preheat and

soldering should be 100C or less.* When preheating and soldering, the temperature of the

leads and the case must not exceed the maximumtemperature ratings as shown on the data sheet. Whenusing infrared heating with the reflow solderingmethod, the difference should be a maximum of 10C.

The soldering temperature and time should not exceed260C for more than 10 seconds.

When shifting from preheating to soldering, themaximum temperature gradient shall be 5C or less.

After soldering has been completed, the device shouldbe allowed to cool naturally for at least three minutes.Gradual cooling should be used since the use of forcedcooling will increase the temperature gradient and willresult in latent failure due to mechanical stress.

Mechanical stress or shock should not be applied duringcooling.

* Soldering a device without preheating can causeexcessive thermal shock and stress which can result indamage to the device.

* Due to shadowing and the inability to set the wave heightto incorporate other surface mount components, the D2PAKis not recommended for wave soldering.

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TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group ofcontrol settings that will give the desired heat pattern. Theoperator must set temperatures for several heating zones anda figure for belt speed. Taken together, these control settingsmake up a heating profile for that particular circuit board.On machines controlled by a computer, the computerremembers these profiles from one operating session to thenext. Figure 5 shows a typical heating profile for use whensoldering a surface mount device to a printed circuit board.This profile will vary among soldering systems, but it is agood starting point. Factors that can affect the profileinclude the type of soldering system in use, density and typesof components on the board, type of solder used, and the typeof board or substrate material being used. This profile showstemperature versus time. The line on the graph shows the

actual temperature that might be experienced on the surfaceof a test board at or near a central solder joint. The twoprofiles are based on a high density and a low density board.The Vitronics SMD310 convection/infrared reflowsoldering system was used to generate this profile. The typeof solder used was 62/36/2 Tin Lead Silver with a meltingpoint between 177189C. When this type of furnace is usedfor solder reflow work, the circuit boards and solder jointstend to heat first. The components on the board are thenheated by conduction. The circuit board, because it has alarge surface area, absorbs the thermal energy moreefficiently, then distributes this energy to the components.Because of this effect, the main body of a component maybe up to 30 degrees cooler than the adjacent solder joints.

STEP 1PREHEATZONE 1RAMP

STEP 2VENT

SOAK

STEP 3HEATING

ZONES 2 & 5RAMP

STEP 4HEATING

ZONES 3 & 6SOAK

STEP 5HEATING

ZONES 4 & 7SPIKE

STEP 6VENT

STEP 7COOLING

200C

150C

100C

5C

TIME (3 TO 7 MINUTES TOTAL) TMAX

SOLDER IS LIQUID FOR40 TO 80 SECONDS

(DEPENDING ONMASS OF ASSEMBLY)

205 TO 219CPEAK ATSOLDER

JOINT

DESIRED CURVE FOR LOWMASS ASSEMBLIES

DESIRED CURVE FOR HIGHMASS ASSEMBLIES

100C

150C160C

170C

140C

Figure 5. Typical Tin Lead (SnPb) Solder Heating Profile

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Figure 6. Typical PbFree Solder Heating Profile

RAMPUP

25

tSPreheat

Critical ZoneTL to Tp

tp

TL

TE

MP

ER

AT

UR

E

TIME

Tp

Tsmax

Tsmin

t 25C to Peak

tL

RAMPDOWN

Profile Feature PbFree Assembly

Average RampUp Rate (Tsmax to Tp) 3C/second max

Preheat Temperature Min (Tsmin) Temperature Max (Tsmax) Time (tsmin to tsmax)

150C200C

60180 seconds

Time maintained above Temperature (TT) Time (tT)

217C60150 seconds

Peak Classification Temperature (Tp) 260C +5/0

Time within 5C of actual Peak Temperature (tp) 2040 seconds

RampDown Rate 6C/second max

Time 25C to Peak Temperature 8 minutes max

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Footprints for Soldering

POWERMITE

2.540.100

0.6350.025

1.270.050

2.670.105 0.762

0.030

mminches

SCALE 10:1

SMA

4.00.157

2.00.0787

2.00.0787

mminches

SCALE 8:1

SMB

mminches

SCALE 8:1

2.7430.108

2.1590.085

2.2610.089

SMC

4.3430.171

2.7940.110

3.8100.150

mminches

SCALE 4:1

1.600.063

1.220.048

0.630.025

mminches

SCALE 10:1

SOD123

0.910.036

2.360.0934.190.165

SOD323

mminches

SCALE 10:1

0.830.033

2.850.112

SOLDERRM

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Footprints for Soldering (continued)

0.400.0157

0.400.0157

1.400.0547

mminches

SCALE 10:1

SOD523

0.450.0177

0.500.0197

1.10.043

mminches

SCALE 10:1

SOD723

SC59

2.40.094

0.950.037

0.950.037

1.00.039

0.80.031

mminches

SCALE 10:1

SC70/SOT323

1.90.075

0.650.025

0.650.025

0.90.035

0.70.028

mminches

SCALE 10:1

SC75/SC89/SOT416

mminches

SCALE 10:1

0.80.031

0.90.035

0.950.0370.95

0.037

SOT23

2.00.079

0.7870.031

0.5080.020 1.000

0.039

mminches

SCALE 10:1

0.3560.014

1.8030.071

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SOT723

1.00.039

mminches

SCALE 20:1

0.400.0157

0.400.0157

0.400.0157

0.400.0157

0.400.0157

SOT1123

0.40

0.30

0.90

DIMENSIONS: MILLIMETERS

0.35

0.25

D2PAK

8.380.33

1.0160.04

17.020.67

10.660.42

3.050.12

5.080.20

mminches

SCALE 3:1

DPAK

5.800.228

2.580.101

1.60.063

6.200.244

3.00.118

6.1720.243

mminches

SCALE 3:1

1.300.512

mminches

SCALE 10:1

0.650.026

1.900.075

0.900.035

0.700.028

0.950.037

SC82ABWDFN3

0.600

1.300

0.300

0.250

0.400

1.600

1.100

0.4002X

0.275


SOLDERRM

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1.350.0531

0.50.0197

mminches

SCALE 20:1

0.50.0197

1.00.0394

0.450.0177

0.30.0118

SOT5531.5

0.059SOT223

mminches

SCALE 6:1

3.80.15

2.00.079

6.30.248

2.30.091

2.30.091

2.00.079

0.350.014

0.200.08

mminches

SCALE 20:1SOT953

0.900.0354

0.350.014

0.200.08 mm

inchesSCALE 20:1

0.650.025

0.650.025

0.500.0197

0.400.0157

1.90.0748

SC88A/SC705/SOT353

8.380.33

1.0160.04

16.020.63

10.660.42

3.050.12

1.7020.067

5LEAD D2PAK

SCALE 3:1 mminches

THIN SOT235/TSOP5/SC595

0.70.028

1.00.039

mminches

SCALE 10:1

0.950.037

2.40.094

1.90.074

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6 PIN FLIPCHIP(1.00 x 1.50 mm, 0.5 Pitch)

SCALE 20:1 mminches

1.00.0394

0.5000.0197

0.5000.0197

0.250 0.2750.0098 0.0108

6.40.252

0.80.031

10.60.417

5.80.228

5LEAD DPAK CENTRAL LEAD CROP

SCALE 4:1 mminches

0.340.013

5.360.217

2.20.086

SC74/SC74R

0.70.028

1.90.074

0.950.037

2.40.094

1.00.039

0.950.037

mminches

SCALE 10:1

SC88/SC706/SOT363

mminches

SCALE 20:1

0.650.025

0.650.025

0.500.0197

0.400.0157

1.90.0748

0.350.014

0.200.08

mminches

SCALE 20:1SOT963

0.900.0354

0.350.014

0.200.08

1.350.0531

0.50.0197

mminches

SCALE 20:1

0.50.0197

1.00.0394

0.450.0177

0.30.0118

SOT563

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UDFN6/WDFN6, 1.2 x 1

mminches

1.2990.0511

0.4000.0157

1.1240.0443

1.2120.0477

0.5750.0226

0.3240.0128

0.6500.0256

6X

PITCH

5X

0.950.037

1.90.075

mminches

SCALE 10:1

1.00.039

TSOP6

2.40.094

0.70.028

0.950.037

DFN6, 2 x 2.2

0.500.020

mminches

SCALE 10:1

0.400.016

1.90.075

0.650.025

0.650.025

0.500.020

mminches

DFN6, 2 x 2

0.3250.0128

6X

0.6500.0256

0.4750.0187

1.1000.0433

2.3000.0906

0.7700.0303

0.7700.0303

0.2000.0079

6X

PITCH

3.310.130

0.630.025

2.600.1023

0.4500.0177

1.7000.685

mminches

SCALE 10:1

0.9500.0374

DFN6, 3 x 3, Single Flag

3.310.130

0.630.025 0.65

0.025

0.350.014

2.450.964

1.7000.685

Exposed PadSMD Defined

DFN6, 3 x 3, Single Flag

mminches

SCALE 10:1

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CLCC6, 7 x 5 mm

PITCH2.54

1.506X

5.06

1.506X

DIMENSION: MILLIMETERS

DFN6, 3 x 3, Dual Flag

3.310.130

0.630.025 1.20

0.0472

0.350.014

0.4500.0177

1.7000.685

mminches

SCALE 10:1

0.9500.0374

0.8500.0334

8.260.325

10.540.415

0.960.038

7LEAD D2PAK, SHORT LEAD

SCALE 3:1 mminches

9.50.374

3.250.128

2.160.085

3.80.150

1.270.050

CL

CL

1

8.890.350MIN

15.460.609MIN

11.430.450MIN

1.270.050

7LEAD D2PAK

0.760.030TYP3.27

0.129TYP

SCALE 3:1 mminches

Micro8

8X 8X

6X mminches

SCALE 8:1

1.040.041

0.380.015

5.280.208

4.240.167

3.200.126

0.650.0256

Micro8 Leadless

2.75

1.50

0.33

8X

3.60

1.23

0.65 PITCH

0.58

8X

0.40


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SO8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

mminches

SCALE 6:1

ExposedPad

SO8Exposed Pad

1.520.060

2.030.08

0.60.024

1.2700.050

4.00.155

mminches

SCALE 6:1

7.00.275

2.720.107

SO8FL (DFN6), 5 x 6

1.270

2X

0.750

1.000

0.905

0.475

4.530

1.530

4.560

0.495

3.200

1.330

0.965

2X

2X

3X 4X

4X


DFN8/UDFN8, 1.6 x 1.6

mminches

SCALE 20:1

0.9020.0355

0.9240.0364

0.4900.0193

0.4000.0157PITCH

0.5020.0197

0.2000.0079

DFN8, 2 x 2UDFN8, 1.8 x 1.2

mminches

SCALE 15:1

1.3500.0531

1.1500.0453

0.5750.0226

0.5000.0197PITCH

0.7000.0276

0.3000.0118

0.2500.0098

0.22

0.32

8X

1.50

0.40 PITCH

0.66


7X

1

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UDFN8, 2 x 2.2 DFN8, 3 x 3

8X0.48

1.60

0.80

10.25

0.50PITCH

2.15

8X


8X

0.52

2.55

1.80

0.351

0.65PITCH

3.30

1.10

8X


1.28 1.15

DFN8, 5 x 6DFN8, 4 x 4


8X

0.632.21

2.39

2.75

1

8X

0.40

0.80PITCH

4.30

0.35

4.20

3.20

1.27 PITCH0.958X

6.30


0.64

0.718X

1

US8

mminches

SCALE 8:1

3.80.15

0.500.0197

1.00.0394

0.300.012

1.80.07

mminches

SCALE 20:10.2650.01

0.500.0197

0.500.0197

8Bump(FlipChip)

DIE SIZE MAY VARY

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mminches

SCALE 20:10.2650.01

0.500.0197

0.500.0197

9Bump(1.550 x 1.550 mm)

mminches

SCALE 8:1

Micro10

10X 10X

8X

1.040.041

0.320.0126

5.280.208

4.240.167

3.200.126

0.500.0196

UQFN10/WQFN10, 1.4 x 1.8 mm

10 XPITCH

1

9 X

SCALE 20:1

0.6630.0261

0.2000.0079

0.4000.0157

0.2250.0089

1.7000.0669

1.7000.0669 0.225

0.0089

mminches

WDFN10, 2.5 x 2 mm

1.13

2.50

0.50

0.05

0.73

10X


0.580.95

PITCH

0.30

10X

UDFN10

2.1746

2.6016

1.8508

0.5000 PITCH

0.565110X

3.3048

0.300810X


0.2800.011

mminches

SCALE 10:1

0.6300.025

DFN10, 3 x 3 mm

2.500.098

3.310.130

1.650.065

0.5000.0196

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DFN12, 3 x 3UQFN12, 1.7 x 2

0.32

11X2.30

0.69

0.40


1

0.22

2.00

PITCH

12X

3.30

2.50

1.70

0.400.55

12X

0.85

0.2012X


1.25

PITCH

WDFN12, 3 x 4

3.3012 X

1.75 0.5512 X0.30

3.35

0.50 PITCH


DFN12

2.3520.093

mminches

SCALE 16:1

0.2650.01

0.4790.019

0.3510.014

PLLP12

9.30512 X

5.652 1.05412 X0.551

7.652

1.270 PITCH


SOIC14

7.04

14X0.58

14X1.52

1.27


1

PITCH

7X

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TSSOP14

7.06

14X0.36 14X1.26

0.65


1

PITCH

mminches

SCALE 20:1

UQFN16/WQFN16, 1.8 x 2.6 mm

1

0.4000.0157

0.2250.0089

0.4630.0182

0.5620.0221

2.9000.1142

1.2000.0472

2.1000.0827

mminches

SCALE 10:1

0.500.02

0.5750.022

1.500.059

3.250.128

0.300.012

3.250.128

0.300.012

EXPOSED PAD

QFN16, 3 x 3 mm,EP 2 x 2 mm QFN16, 4 x 4 mm

4.30

1

0.50


2.80 4.30

2.80

0.40

0.65

16X

16X

PITCH

SOIC16

6.40

16X0.58

16X 1.12

1.27


1

PITCH

16

8 9

8X

SOIC16EP

0.350

0.175

0.050

0.376

0.188

0.200

0.074

DIMENSIONS: INCHES

0.024 0.145

ExposedPad

CL

CL

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DFN16

0.50

4.10

0.50 PITCH14X


1.91

0.5116X0.2816X

TSSOP16

7.06

16X0.36 16X1.26

0.65


1

PITCH

TSSOP20

7.06

16X0.36 16X1.26

0.65


1

PITCH

UDFN20, 4 x 2

0.22

0.88

19X

2.30

0.40 PITCH

0.78


20X

1

LLGA20, 6 x 5

4.05

2.10

0.80

19X0.35

1.95

4.60


1

3.70

3.10

20X 0.35

PITCH

1.200.45

0.80PITCH

0.35

0.25

2.63

DFN22, 6 x 5 mm

0.2800.011

mminches

SCALE 8:1

0.9800.039

4.3000.169

5.7700.227

3.1300.123

0.5000.020

0.3400.013

20X 22X

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QFN32, 5 x 5 mm

0.50 PITCH

3.20

0.28

3.20

32 X28 X

0.6332 X

5.30

5.30

TLLGA32, 4 x 4

32X

0.30

0.40PITCH

4.60

0.63

2.94

1


0.2031X

2X

2X

Basic

ChipFET

0.4570.018

2.0320.08

0.6350.025PITCH

0.660.026

mminches

2.3620.093

1

8X

8X

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Styles 1 and 4

ChipFET (continued)

2.0320.08

1.7270.068

0.660.026

2.3620.093

mminches

0.4570.018

1

2X

2X

0.4570.018

2.0320.08

0.6350.025PITCH

0.660.026

1.1180.044 mm

inches

1.0920.043

2.3620.093

Style 2

1

2X4X

2X

4X

Style 5

0.4570.018

2.0320.08

0.660.026

1.1180.044

mminches

1.0920.043

Style 3

1

2X

2X

0.6350.025PITCH

2.3620.093

0.4570.018

2.0320.08

0.660.026

1.1180.044

mminches

1.0920.043

1

2X

2X

0.6350.025PITCH

2.3620.093

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AND8211/D

Board Level ApplicationNotes for DFN and QFNPackages

Prepared by: Steve St. GermainON Semiconductor

INTRODUCTION

Various ON Semiconductor components are packaged inan advanced Dual or Quad FlatPack NoLead package(DFN/QFN). The DFN/QFN platform represents the latestin surface mount packaging technology, it is important thatthe design of the Mounting Pads of the Printed Circuit Board(PCB), Soldermask and Stencil pattern, along with theassembly process, all follow the suggested guidelinesoutlined in this document.

DFN/QFN Package OverviewThe DFN/QFN platform offers a versatility which allows

either a single or multiple semiconductor devices to beconnected together within a leadless package. Thispackaging flexibility is illustrated in Figure 7 where fourdevices are packaged together with a custom padconfiguration.

Figure 7. The Underside of a 4Chip 16 PinDFN Package

Figure 8 illustrates a single site DFN semiconductordevice package which allows for a large device.

Figure 8. The Underside of a SingleChip 10 PinDFN Package

WirebondDie

Leadframe

Figure 9. CrossSection of a SingleChipDFN Package

Figure 9 illustrates how the package height is reduced toa minimum by having both the die and wirebond pads on thesame plane. When mounted, the leads are directly attachedto the board without a spaceconsuming standoff, which isinherent in a leaded package.

Figure 9 also illustrates how the ends of the leads are flushwith the edge of the package. This configuration allows forthe maximum die size within a given footprint, whilemaximizing the board space efficiency.

In addition to these features, the DFN/QFN package hasexcellent thermal dissipation and reduced electricalparasitics due to its efficient and compact design.

APPLICATION NOTE

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Printed Circuit Board Solder Pad DesignGuidelines

Refer to the case outline (specification sheet) drawing forthe specific DFN/QFN package to be mounted. Based on thenominal package footprint dimensions from the casedrawing. The PCB mounting pads need to be larger than thenominal package footprint (see Figure 10).

Note: On the occasion that there is not enough room to growthe PCB mounting pads per these guidelines, therecommendation would be to come as close to theseguidelines as possible.

0.01270.0254(0.00050.001)

0.05080.0762(0.0020.003)

0.0762(0.003)

0.1524(0.006)

Device Footprint

Nominal Device Footprintand PCB Mounting Pads

Figure 10. 10 Pin DFN Package Footprint Shownwith PCB Mounting Pads

Printed Circuit Board Solder Mask DesignGuidelines

SMD and NSMD Pad ConfigurationsThere are two different types of PCB pad configurations

commonly used for surface mount leadless DFN/QFN stylepackages. The different configurations are:

1. Non Solder Masked Defined (NSMD)2. Solder Masked Defined (SMD)

NSMD SMD

Solder MaskOpening

Solder MaskOverlay

SolderablePad

Figure 11. Comparison of NSMD vs. SMD Pads

As their titles describe, the NSMD contact pads have thesolder mask pulled away from the solderable metallization,while the SMD pads have the solder mask over the edge ofthe metallization, as shown in Figure 11. With the SMDPads, the solder mask restricts the flow of solder paste on thetop of the metallization which prevents the solder fromflowing along the side of the metal pad. This is differentfrom the NSMD configuration where the solder will flowaround both the top and the sides of the metallization.

Typically, the NSMD pads are preferred over the SMDconfiguration since defining the location and size of thecopper pad is easier to control than the solder mask. This isbased on the fact that the copper etching process is capableof a tighter tolerance than the solder masking process. Thisalso allows for visual inspection of solder fillet.

In addition, the SMD pads will inherently create a stressconcentration point where the solder wets to the pad on topof the lead. This stress concentration point is reduced whenthe solder is allowed to flow down the sides of the leads inthe NSMD configuration.

Printed Circuit Board Solder Mask DesignGuidelines

When dimensionally possible, the solder mask shouldbe located within a range of 0.07620.1270 mm(0.0030.005 in) away from the edge of the PCB mountingpad (see Figure 12). This spacing is used to compensate forthe registration tolerances of the solder mask, as well as toinsure that the solder is not inhibited by the mask as itreflows along the sides of the metal pad.

The solder mask web (between openings) is thecontrolling factor in the pattern, and needs to be held to aminimum of 0.1016 mm (0.004 in). This minimum is thecurrent PCB suppliers standard minimum web formanufacturability. Because of this web restriction, soldermask openings around PCB pads may need to be less thanthe recommended shown. Whenever possible, keeping tothe range given will provide for the best results.

PCB MountingPads

0.07620.1270(0.0030.005)All aroundlarger than PCBmounting pads

0.1016(0.004)MinimumSoldermaskWeb

0.1016(0.004)

MinimumSoldermaskWeb

Soldermask Openings shownwith PCB Mounting Pads

Figure 12. Typical DFN Package PCB MountingPads Shown with Soldermask Openings

Soldermask OpeningsPCB Mounting Pads

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DFN/QFN Board Mounting ProcessThe DFN/QFN board mounting process is optimized by

first defining and controlling the following.

1. Solderable metallization on the PCB contacts.2. Choice of proper solder paste.3. Solder paste on the PCB.4. Package placement.5. Reflow of the solder paste.6. Final solder joint inspection.

Recommendations for each of these processes are locatedbelow.

PCB Solderable MetallizationThere are currently three common solderable coatings

which are used for PCB surface mount devices. In any case,it is imperative that the coating is uniform, conforming, andfree of impurities to insure a consistant solderable system.

The first coating consists of an Organic SolderabilityProtectant (OSP) applied over the bare copper feature. OSPcoating assists in reducing oxidation in order to preserve thecopper metallization for soldering. It allows for multiplepasses through reflow ovens without degradation of thesolderability. The OSP coating is dissolved by the flux whenthe solder paste is applied to the metal features. Coatingthickness recommended by OSP manufacturers is between0.25 and 0.35 microns.

The second coating is a metalized coating which consistsof plated electroless nickel over the copper pad, followed bya coat of immersion gold. The thickness of the electrolessnickel layer is determined by the allowable internal materialstresses and the temperature excursions the board will besubjected to throughout its lifetime. Even though the goldmetallization is typically a selflimiting process, thethickness should be at least 0.05 m thick, and not consist ofmore than 5% of the overall solder volume. Havingexcessive gold in the solder joint can create goldembitterment which may affect the reliability of the joint.

The third is a tinlead coating, commonly called Hot AirSolder Level (HASL).This type of PCB pad finish is notrecommended for DFN/QFN type packages. The majorissue is the inability to consistently control the amount ofsolder coating applied to each pad. This results indomeshaped pads of various heights. As the industry drivesfor finer and finer pitch, solder bridging becomes a commonproblem between mounting pads.

Solder TypeSolder paste such as Cookson Electronics WS3060 with

a Type 3 or smaller sphere size is recommended. TheWS3060 has a watersoluble flux for cleaning. CooksonElectronics PNC0106A can be used if a noclean flux ispreferred.

Solder Screening onto the PCBStencil screening the solder paste onto the PCB is

commonly used in the industry. The recommended stencilthickness used is 0.075 mm to 0.127 mm (0.003 in to0.005 in). The sidewalls of the stencil openings should betapered approximately 5 to facilitate the release of the pastewhen the stencil is removed from the PCB.

The stencil opening should be the same size as the PCBmounting pad. The exception is when there is a large centerflag on the device. Then the stencil opening should allow for7080% coverage of the PCB mounting pad. This openingshould also be divided into smaller cavities to aid in the flowof solder during the reflow process (see Figure 13). Dividingthe larger die pads into smaller screen openings reduces therisk of solder voiding and allows the solder joints for thesmaller terminal pads to be at the same height as the largerones.

Same Size asPCB Mounting Pad

PCB Center Mounting Pad

Package Outline

7080% of PCBcenter mounting padbroken up intosmaller openings

Stencil Pattern Over PCBMounting Pads

Figure 13. Typical DFN Package with StencilOpenings Shown Over PCB Mounting Pads

Package OutlinePCB Center Mounting PadsStencil Opening

Package Placement onto the PCBPick and place equipment with the standard tolerance of

0.05 mm (0.002 in) or better is recommended. Thepackage will tend to center itself and correct for slightplacement errors during the reflow process due to thesurface tension of the solder.

Solder ReflowOnce the package is placed on the PC board along with the

solder paste, a standard surface mount reflow process can beused to mount the part. Figures 14 and 15 are examples ofstandard reflow profiles for standard eutectic and lead freesolder alloys.

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The exact profile will be determined, and is available, bythe manufacture of the paste since the chemistry andviscosity of the flux matrix will vary. These variations willrequire small changes in the profile in order to achieve anoptimized process.

Figure 14. Typical Reflow Profile for EutecticTin/Lead Solder

0

50

100

150

200

0 100 200 300 400 500

Time (sec)

SoakZone

Peak of 225C

Less than2C/sec

183

Temperature (C)250

30 to 120 sec

TimeAbove

Liquidus

Figure 15. Typical Reflow Profile for PbFreeSolder

0

50

100

150

200

250

300

94 204 314

Time (sec)

Peak of 260CTemperature (C)

Lessthan 2C/sec

SoakZone

60180sec

Timeabove

liquidus

60150sec

425

In general, the temperature of the part should be raised notmore than 2C/sec during the initial stages of the reflowprofile. The soak zone then occurs when the part isapproximately 150C and should last for 60 to 180 secondsfor Pbfree profiles (30120 sec for Eutectic profiles).Typically, extending the time in the soak zone will reduce therisk of voiding within the solder. The temperature is thenraised and will be above the liquidus of the solder for 60 to150 seconds for Pbfree profiles (30100 sec for Eutecticprofiles) depending on the mass of the board. The peaktemperature of the profile should be between 245 and 260Cfor Pbfree solder alloys (205225C) for eutectic solders.

If required, removal of the residual solder flux can becompleted by using the recommended procedures set forthby the flux manufacturer.

Final Solder InspectionThe inspection of the solder joints is commonly

performed with the use of an Xray inspection system. Withthis tool, one can locate defects such as shorts between pads,open contacts, voids within the solder as well as anyextraneous solder.

In addition to searching for defects, the mounted deviceshould be rotated on its side to inspect the sides of the solderjoints with an Xray inspection system. The solder jointsshould have enough solder volume with the proper standoffheight so that an Hour Glass shaped connection is notformed as shown below in Figure 16. Hour Glass solderjoints are a reliability concern and must be avoided.

PCB

PreferredSolder Joint

UndesirableHour GlassSolder Joint

Figure 16. Side View of DFN Illustrating Preferredand Undesirable Solder Joints

Rework ProcedureDue to the fact that the DFN/QFNs are leadless devices,

the entire package must be removed from the PC board ifthere is an issue with the solder joints. It is important tominimize the chance of overheating neighboring devicesduring the removal of the package since the devices aretypically in close proximity with each other.

Standard SMT rework systems are recommended for thisprocedure since the airflow and temperature gradients canbe carefully controlled. It is also recommend that the PCboard be placed in an oven at 125C for four to eight hoursprior to heating the parts to remove excess moisture from thepackages. In order to control the region which will beexposed to reflow temperatures, the board should be heatedto a 100C by conduction through the backside of the boardin the location of the device. Typically, heating nozzles arethen used to increase the temperature locally.

Once the devices solder joints are heated above theirliquidus temperature, the package is quickly removed andthe pads on the PC board are cleaned. The cleaning of thepads is typically performed with a bladestyle conductivetool with a desoldering braid. A no clean flux is used duringthis process in order to simplify the procedure.

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Solder paste is then deposited or screened onto the site inpreparation of mounting a new device. Due to the closeproximity of the neighboring packages in most PC boardconfigurations, a miniature stencil for the individualcomponent is typically required. The same stencil designthat was originally used to mount the package can be appliedto the ministencil for redressing the pads.

Due to the small pad configurations of the DFN/QFN, andsince the pads are on the underside of the package, a manualpick and place procedure without the aid of magnification isnot recommended. A dual image optical system where theunderside of the package can be aligned to the PC boardshould be used instead.

Reflowing the component onto the board can beaccomplished by either passing the board through theoriginal reflow profile, or by selectively heating the packagewith the same process that was used to remove it. The benefitwith subjecting the entire board to a second reflow is that thenew part will be mounted consistently and by a profile thatis already defined. The disadvantage is that all of the otherdevices mounted with the same solder type will be reflowedfor a second time. If subjecting all of the parts to a secondreflow is either a concern or unacceptable for a specificapplication, than the localized reflow option would be therecommended procedure.

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AN1040/D

Mounting Considerationsfor Power SemiconductorsPrepared by: Bill Roehr

INTRODUCTIONCurrent and power ratings of semiconductors are

inseparably linked to their thermal environment. Except forleadmounted parts used at low currents, a heat exchangeris required to prevent the junction temperature fromexceeding its rated limit, thereby running the risk of a highfailure rate. Furthermore, the semiconductor industrysfield history indicated that the failure rate of most siliconsemiconductors decreases approximately by onehalf for adecrease in junction temperature from 160C to 135C.(1)Guidelines for designers of military power supplies imposea 110C limit upon junction temperature.(2) Propermounting minimizes the temperature gradient between thesemiconductor case and the heat exchanger.

Most early life field failures of power semiconductorscan be traced to faulty mounting procedures. With metalpackaged devices, faulty mounting generally causesunnecessarily high junction temperature, resulting inreduced component lifetime, although mechanical damagehas occurred on occasion from improperly mounting to awarped surface. With the widespread use of variousplasticpackaged semiconductors, the prospect ofmechanical damage is very significant. Mechanicaldamage can impair the case moisture resistance or crackthe semiconductor die.

Figure 17 shows an example of doing nearly everythingwrong. A tab mount TO220 package is shown being usedas a replacement for a TO213AA (TO66) part which wassocket mounted. To use the socket, the leads are bent anoperation which, if not properly done, can crack thepackage, break the internal bonding wires, or crack the die.The package is fastened with a sheetmetal screw througha 1/4 hole containing a fiberinsulating sleeve. The forceused to tighten the screw tends to pull the package into thehole, possibly causing enough distortion to crack the die. Inaddition the contact area is small because of the areaconsumed by the large hole and the bowing of the package;the result is a much higher junction temperature thanexpected. If a rough heatsink surface and/or burrs aroundthe hole were displayed in the illustration, most but not allpoor mounting practices would be covered.

PLASTIC BODY

PACKAGE HEATSINK

MICA WASHER

SPEED NUT(PART OF SOCKET)

SHEET METAL SCREW

SOCKET FORTO213AA PACKAGE

EQUIPMENTHEATSINK

LEADS

Figure 17. Extreme Case of Improperly Mounting aSemiconductor (Distortion Exaggerated)

In many situations the case of the semiconductor must beelectrically isolated from its mounting surface. Theisolation material is, to some extent, a thermal isolator aswell, which raises junction operating temperatures. Inaddition, the possibility of arcover problems is introducedif high voltages are present. Various regulating agenciesalso impose creepage distance specifications which furthercomplicates design. Electrical isolation thus placesadditional demands upon the mounting procedure.

Proper mounting procedures usually necessitate orderlyattention to the following:

1. Preparing the mounting surface 2. Applying a thermal grease (if required) 3. Installing the insulator (if electrical isolation is desired) 4. Fastening the assembly 5. Connecting the terminals to the circuit

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APPLICATION NOTE

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In this note, mounting procedures are discussed ingeneral terms for several generic classes of packages. Asnewer packages are developed, it is probable that they willfit into the generic classes discussed in this note. Uniquerequirements are given on data sheets pertaining to theparticular package. The following classes are defined:

Stud MountFlange MountPressfitPlastic Body MountTab MountSurface Mount

Appendix A contains a brief review of thermal resistanceconcepts. Appendix B discusses measurement difficultieswith interface thermal resistance tests. Appendix Cindicates the type of accessories supplied by a number ofmanufacturers.

MOUNTING SURFACE PREPARATIONIn general, the heatsink mounting surface should have a

flatness and finish comparable to that of the semiconductorpackage. In lower power applications, the heatsink surfaceis satisfactory if it appears flat against a straight edge and isfree from deep scratches. In highpower applications, amore detailed examination of the surface is required.Mounting holes and surface treatment must also beconsidered.

Surface FlatnessSurface flatness is determined by comparing the variance

in height (h) of the test specimen to that of a referencestandard as indicated in Figure 18. Flatness is normallyspecified as a fraction of the Total Indicator Reading (TIR).The mounting surface flatness, i.e., h/TlR, if less than 4mils per inch, normal for extruded aluminum, issatisfactory in most cases.

Surface FinishSurface finish is the average of the deviations both above

and below the mean value of surface height. For minimuminterface resistance, a finish in the range of 50 to 60microinches is satisfactory; a finer finish is costly toachieve and does not significantly lower contact resistance.Tests conducted by Thermalloy, Inc., using a copperTO204 (TO3) package with a typical 32microinchfinish, showed that heatsink finishes between 16 and 64in caused less than 2.5% difference in interfacethermal resistance when the voids and scratches were filledwith a thermal joint compound.(3) Most commerciallyavailable cast or extruded heatsinks will require spotfacingwhen used in highpower applications. In general, milledor machined surfaces are satisfactory if prepared with toolsin good working condition.

Mounting HolesMounting holes generally should only be large enough to

allow clearance of the fastener. The larger thick flange typepackages having mounting holes removed from thesemiconductor die location, such as the TO3, maysuccessfully be used with larger holes to accommodate aninsulating bushing, but many plastic encapsulatedpackages are intolerant of this condition. For thesepackages, a smaller screw size must be used such that thehole for the bushing does not exceed the hole in thepackage.

Punched mounting holes have been a source of troublebecause if not properly done, the area around a punchedhole is depressed in the process. This crater in theheatsink around the mounting hole can cause twoproblems. The device can be damaged by distortion of thepackage as the mounting pressure attempts to conform it tothe shape of the heatsink indentation, or the device mayonly bridge the crater and leave a significant percentage ofits heatdissipating surface out of contact with theheatsink. The first effect may often be detectedimmediately by visual cracks in the package (if plastic), butusually an unnatural stress is imposed, which results in anearlylife failure. The second effect results in hotteroperation and is not manifested until much later.

Although punched holes are seldom acceptable in therelatively thick material used for extruded aluminumheatsinks, several manufacturers are capable of properlyutilizing the capabilities inherent in both fineedgeblanking or shearedthrough holes when applied to sheetmetal as commonly used for stamped heatsinks. The holesare pierced using Class A progressive dies mounted onfourpost die sets equipped with proper pressure pads andholding fixtures.

TIR = TOTAL INDICATOR READING

SAMPLEPIECE

DEVICE MOUNTING AREAREFERENCE PIECE

TIRh

Figure 18. Surface Flatness Measurement

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When mounting holes are drilled, a general practice withextruded aluminum, surface cleanup is important.Chamfers must be avoided because they reduce heattransfer surface and increase mounting stress. However, theedges must be broken to remove burrs which cause poorcontact between device and heatsink and may punctureisolation material.

Surface TreatmentMany aluminum heatsinks are blackanodized to

improve radiation ability and prevent corrosion. Anodizingresults in significant electrical but negligible thermalinsulation. It need only be removed from the mounting areawhen electrical contact is required. Heatsinks are alsoavailable which have a nickel plated copper insert underthe semiconductor mounting area. No treatment of thissurface is necessary.

Another treated aluminum finish is iridite, orchromateacid dip, which offers low resistance because ofits thin surface, yet has good electrical properties because itresists oxidation. It need only be cleaned of the oils andfilms that collect in the manufacture and storage of thesinks, a practice which should be applied to all heatsinks.

For economy, paint is sometimes used for sinks; removalof the paint where the semiconductor is attached is usuallyrequired because of paints high thermal resistance.However, when it is necessary to insulate thesemiconductor package from the heatsink, hard anodizedor painted surfaces allow an easy installation for lowvoltage applications. Some manufacturers will provideanodized or painted surfaces meeting specific insulationvoltage requirements, usually up to 400 volts.

It is also necessary that the surface be free from allforeign material, film, and oxide (freshly bared aluminumforms an oxide layer in a few seconds). Immediately priorto assembly, it is a good practice to polish the mountingarea with No. 000 steel wool, followed by an acetone oralcohol rinse.

INTERFACE DECISIONSWhen any significant amount of power is being

dissipated, something must be done to fill the air voidsbetween mating surfaces in the thermal path. Otherwise theinterface thermal resistance will be unnecessarily high andquite dependent upon the surface finishes.

For several years, thermal joint compounds, often calledgrease, have been used in the interface. They have aresistivity of approximately 60C/W/in whereas air has1200C/W/in. Since surfaces are highly pockmarked withminute voids, use of a compound makes a significantreduction in the interface thermal resistance of the joint.However, the grease causes a number of problems, asdiscussed in the following section.

To avoid using grease, manufacturers have developeddry conductive and insulating pads to replace the moretraditional materials. These pads are conformal andtherefore partially fill voids when under pressure.

Thermal Compounds (Grease)Joint compounds are a formulation of fine zinc or other

conductive particles in a silicone oil or other synthetic basefluid which maintains a greaselike consistency with timeand temperature. Since some of these compounds do notspread well, they should be evenly applied in a very thinlayer using a spatula or lintless brush, and wiped lightly toremove excess material. Some cyclic rotation of thepackage will help the compound spread evenly over theentire contact area. Some experimentation is necessary todetermine the correct quantity; too little will not fill all thevoids, while too much may permit some compound toremain between well mated metal surfaces where it willsubstantially increase the thermal resistance of the joint.

To determine the correct amount, several semiconductorsamples and heatsinks should be assembled with differentamounts of grease applied evenly to one side of eachmating surface. When the amount is correct a very smallamount of grease should appear around the perimeter ofeach mating surface as the assembly is slowly torqued tothe recommended value. Examination of a dismantledassembly should reveal even wetting across each matingsurface. In production, assemblers should be trained toslowly apply the specified torque even though an excessiveamount of grease appears at the edges of mating surfaces.Insufficient torque causes a significant increase in thethermal resistance of the interface.

To prevent accumulation of airborne particulate matter,excess compound should be wiped away using a clothmoistened with acetone or alcohol. These solvents shouldnot contact plasticencapsulated devices, as they may enterthe package and cause a leakage path or carry in substanceswhich might attack the semiconductor chip.

The silicone oil used in most greases has been found toevaporate from hot surfaces with time and becomedeposited on other cooler surfaces. Consequently,manufacturers must determine whether a microscopicallythin coating of silicone oil on the entire assembly will poseany problems. It may be necessary to enclose componentsusing grease. The newer synthetic base greases show farless tendency to migrate or creep than those made with asilicone oil base. However, their currently observedworking temperature range are less, they are slightly pooreron thermal conductivity and dielectric strength and theircost is higher.

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Data showing the effect of compounds on severalpackage types under different mounting conditions isshown in Figure 1. The rougher the surface, the morevaluable the grease becomes in lowering contactresistance; therefore, when mica insulating washers areused, use of grease is generally mandatory. The jointcompound also improves the breakdown rating of theinsulator.

Conductive PadsBecause of the difficulty of assembly using grease and

the evaporation problem, some equipment manufacturerswill not, or cannot, use grease. To minimize the need forgrease, several vendors offer dry conductive pads whichapproximate performance obtained with grease. Data for a

greased bare joint and a joint using Grafoil, a drygraphite compound, is shown in the data of Figure 19through Figure 22. Grafoil is claimed to be a replacementfor grease when no electrical isolation is required; the dataindicates it does indeed perform as well as grease. Anotherconductive pad available from Aavid is called KonDux.It is made with a unique, grain oriented, flakelikestructure (patent pending). Highly compressible, itbecomes formed to the surface roughness of both theheatsink and semiconductor. Manufacturers data shows itto provide an interface thermal resistance better than ametal interface with filled silicone grease. Similar dryconductive pads are available from other manufacturers.They are a fairly recent development; long term problems,if they exist, have not yet become evident.

Table 1. Approximate Values for Interface Thermal Resistance Data from Measurements Performedin ON Semiconductor Applications Engineering Laboratory

Dry interface values are subject to wide variation because of extreme dependence upon surface conditions.Unless otherwise noted the case temperature is monitored by a thermocouple located directly under the die reached through

a hole in the heatsink. (See Appendix B for a discussion of Interface Thermal Resistance Measurements.)

Interface Thermal Resistance (C/W)

Package Type and Data

Test TorqueInLb

MetaltoMetal With Insulator

SeeNote

JEDECOutlines Description Dry Lubed Dry Lubed Type

DO203AA, TO210AATO208AB

1032 Stud7/16 Hex

15 0.3 0.2 1.6 0.8 3 milMica

DO203AB, TO210ACTO208

1/428 Stud11/16 Hex

25 0.2 0.1 0.8 0.6 5 milMica

DO208AA Pressfit, 1/2 0.15 0.1

TO204AA (TO3) Diamond Flange 6 0.5 0.1 1.3 0.36 3 milMica

1

TO213AA (TO66) Diamond Flange 6 1.5 0.5 2.3 0.9 2 milMica

TO126 Thermopad1/4 x 3/8

6 2.0 1.3 4.3 3.3 2 milMica

TO220AB Thermowatt 8 1.2 1.0 3.4 1.6 2 milMica

1, 2

NOTES: 1. See Figure 19 through Figure 23 for additional data on TO3 and TO220 packages.2. Screw not insulated. See Figure 36.

INSULATION CONSIDERATIONSSince most power semiconductors use are vertical device

construction it is common to manufacture powersemiconductors with the output electrode (anode, collectoror drain) electrically common to the case; the problem ofisolating this terminal from ground is a common one. Forlowest overall thermal resistance, which is quite importantwhen high power must be dissipated, it is best to isolate theentire heatsink/semiconductor structure from ground,rather than to use an insulator between the semiconductorand the heatsink. Heatsink isolation is not always possible,however, because of EMI requirements, safety reasons,instances where a chassis serves as a heatsink or where aheatsink is common to several non isolated packages. In

these situations insulators are used to isolate the individualcomponents from the heatsink. Newer packages, such asthe ON Semiconductor FULLPAK and EMS modules,contain the electrical isolation material within, therebysaving the equipment manufacturer the burden ofaddressing the isolation problem.

Insulator Thermal ResistanceWhen an insulator is used, thermal grease is of greater

importance than with a metaltometal contact, becausetwo interfaces exist instead of one and some materials, suchas mica, have a hard, markedly uneven surface. With manyisolation materials reduction of interface thermal resistanceof between 2 to 1 and 3 to 1 are typical when grease is used.

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Data obtained by Thermalloy, showing interfaceresistance for different insulators and torques applied toTO204 (TO3) and TO220 packages, are shown inFigure 19 through Figure 22, for bare and greased surfaces.Similar materials to those shown are available from severalmanufacturers. It is obvious that with some arrangements,the interface thermal resistance exceeds that of thesemiconductor (junction to case).

Referring to Figure 19 through Figure 22, one mayconclude that when high power is handled, beryllium oxideis unquestionably the best. However, it is an expensivechoice. (It should not be cut or abraded, as the dust is

highly toxic.) Thermafilm is a filled polymide materialwhich is used for isolation (variation of Kapton). It is apopular material for low power applications because of itslow cost ability to withstand high temperatures, and ease ofhandling in contrast to mica which chips and flakes easily.

A number of other insulating materials are also shown.They cover a wide range of insulation resistance, thermalresistance and ease of handling. Mica has been widely usedin the past because it offers high breakdown voltage andfairly low thermal resistance at a low cost but it certainlyshould be used with grease.

2

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(7)

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(1) Thermafilm, .002 (.05) thick.(2) Mica, .003 (.08) thick.(3) Mica, .002 (.05) thick.(4) Hard anodized, .020 (.51)

thick.(5) Aluminum oxide, .062 (1.57)

thick.(6) Beryllium oxide, .062 (1.57)

thick.(7) Bare joint no finish.(8) Grafoil, .005 (.13) thick.*

*Grafoil is not an insulating material.

(1) Thermafilm, .002 (.05) thick.(2) Mica, .003 (.08) thick.(3) Mica, .002 (.05) thick.(4) Hard anodized, .020 (.51)

thick.(5) Thermasil II, .009 (.23)

thick.(6) Thermasil III, .0076 (.15)

thick.(7) Bare joint no finish.(8) Grafoil, .005 (.13) thick.*

*Grafoil is not an insulating material.

MOUNTING SCREW TORQUE (IN-LBS)

0 21772 145 362290 435INTERFACE PRESSURE (psi)

0 2 3 4 5 61MOUNTING SCREW TORQUE (IN-LBS)

0 21772 145 362290 435INTERFACE PRESSURE (psi)

0 2 4 5 61MOUNTING SCREW TORQUE (IN-LBS)

(IN-LBS) 0 2 4 5 61MOUNTING SCREW TORQUE (IN-LBS)

3

Figure 19. TO204AA (TO3)Without Thermal Grease

Figure 20. TO204AA (TO3) WithThermal Grease

Figure 21. TO220 Without ThermalGrease

TO M

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( C

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INTERFACE THERMAL RESISTANCE FOR TO204, TO3 AND TO220 PACKAGES USING DIFFERENTINSULATING MATERIALS AS A FUNCTION OF MOUNTING SCREW TORQUE (DATA COURTESY THERMALLOY)

Figure 22. TO220 With ThermalGrease

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Silicone rubber insulators have gained favor becausethey are somewhat conformal under pressure. Their abilityto fill in most of the metal voids at the interface reduces theneed for thermal grease. When first introduced, theysuffered from cutthrough after a few years in service. Theones presently available have solved this problem byhaving imbedded pads of Kapton or fiberglass. Bycomparing Figure 21 and Figure 22, it can be noted thatThermasil, a filled silicone rubber, without grease, hasabout the same interface thermal resistance as greased micafor the TO220 package.

A number of manufacturers offer silicone rubberinsulators. Figure 2 shows measured performance of anumber of these insulators under carefully controlled,nearly identical conditions. The interface thermalresistance extremes are over 2:1 for the various materials.It is also clear that some of the insulators are much moretolerant than others of outofflat surfaces. Since the testswere performed, newer products have been introduced.The Bergquist K10 pad, for example, is described ashaving about 2/3 the interface resistance of the Sil Pad1000 which would place its performance close to theChomerics 1671 pad. Aavid also offers an isolated padcalled RubberDuc, however it is only availablevulcanized to a heatsink and therefore was not included inthe comparison. Published data from Aavid shows RCSbelow 0.3C/W for pressures above 500 psi. However,surface flatness and other details are not specified so acomparison cannot be made with other data in this note.

Table 2. Thermal Resistance of Silicone Rubber Pads

Manufacturer ProductRCS @3 Mils*

RCS @7.5 Mils*

Wakefield Delta Pad 1737 .790 1.175Bergquist Sil Pad K4 .752 1.470Stockwell Rubber 1867 .742 1.015Bergquist Sil Pad 4009 .735 1.205Thermalloy Thermasil II .680 1.045ShinEtsu TC30AG .664 1.260Bergquist Sil Pad 4007 .633 1.060Chomerics 1674 .592 1.190Wakefield Delta Pad 1749 .574 .755Bergquist Sil Pad 1000 .529 .935Ablestik Thermal Wafers .500 .990Thermalloy Thermasil III .440 1.035Chomerics 1671 .367 .655

*Test Fixture Deviation from flat from Thermalloy EIR861010.

The thermal resistance of some silicone rubber insulatorsis sensitive to surface flatness when used under a fairlyrigid base package. Data for a TO204AA (TO3) packageinsulated with Thermasil is shown on Figure 23. Observethat the worst case encountered (7.5 mils) yields resultshaving about twice the thermal resistance of the typicalcase (3 mils), for the more conductive insulator. In orderfor Thermasil III to exceed the performance of greased

mica, total surface flatness must be under 2 mils, a situationthat requires spot finishing.

1.2

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0.8

0.6

0.4

0.2

0

INTE

RFA

CE

THER

MAL

RES

ISTA

NC

E (

C/W

)

TOTAL JOINT DEVIATION FROM FLAT OVERTO-3 HEADER SURFACE AREA (INCHES)

0 0.002 0.004 0.0080.006 0.01

(1) Thermasil II, .009 inches (.23) thick.(2) Thermasil III, .006 inches (.15) thick.

(1)(2)

Data courtesy of Thermalloy

Figure 23. Effect of Total Surface Flatness onInterface Resistance Using Silicon Rubber Insulators

Silicon rubber insulators have a number of unusualcharacteristics. Besides being affected by surface flatnessand initial contact pressure, time is a factor. For example, ina study of the ChoTherm 1688 pad thermal interfaceimpedance dropped from 0.90C/W to 0.70C/W at the endof 1000 hours. Most of the change occurred during the first200 hours where RCS measured 0.74C/W. The torque onthe conventional mounting hardware had decreased to 3inlb from an initial 6 inlb. With nonconformal materials,a reduction in torque would have increased the interfacethermal resistance.

Because of the difficulties in controlling all variablesaffecting tests of interface thermal resistance, data fromdifferent manufacturers is not in good agreement. Figure 3shows data obtained from two sources. The relativeperformance is the same, except for mica which varieswidely in thickness. Appendix B discusses the variableswhich need to be controlled. At the time of this writingASTM Committee D9 is developing a standard forinterface measurements.

The conclusions to be drawn from all this data is thatsome types of silicon rubber pads, mounted dry, will outperform the commonly used mica with grease. Cost may bea determining factor in making a selection.

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Table 3. Performance of Silicon Rubber InsulatorsTested Per MILI49456

Measured Thermal Resistance(C/W)

MaterialThermalloy

Data(1)Bergquist

Data(2)

Bare Joint, greased 0.033 0.008BeO, greased 0.082 ChoTherm, 1617 0.233 Q Pad (noninsulated) 0.009Sil Pad, K10 0.263 0.200Thermasil III 0.267 Mica, greased 0.329 0.400Sil Pad 1000 0.400 0.300ChoTherm 1674 0.433 Thermasil II 0.500 Sil Pad 400 0.533 0.440Sil Pad K4 0.583 0.440

(1) From Thermalloy EIR 871030(2) From Bergquist Data Sheet

Insulation ResistanceWhen using insulators, care must be taken to keep the

mating surfaces clean. Small particles of foreign matter canpuncture the insulation, rendering it useless or seriouslylowering its dielectric strength. In addition, particularlywhen voltages higher than 300 V are encountered,problems with creepage may occur. Dust and other foreignmaterial can shorten creepage distances significantly; sohaving a clean assembly area is important. Surfaceroughness and humidity also lower insulation resistance.Use of thermal grease usually raises the withstand voltageof the insulation system but excess must be removed toavoid collecting dust. Because of these factors, which arenot amenable to analysis, hipot testing should be done onprototypes and a large margin of safety employed.

Insulated Electrode PackagesBecause of the nuisance of handling and installing the

accessories needed for an insulated semiconductormounting, equipment manufacturers have longed forcosteffective insulated packages since the 1950s. Thefirst to appear were stud mount types which usually have alayer of beryllium oxide between the stud hex and the can.Although effective, the assembly is costly and requiresmanual mounting and lead wire soldering to terminals ontop of the case. In the late eighties, a number of electricallyisolated parts became available from varioussemiconductor manufacturers. These offerings presentlyconsist of multiple chips and integrated circuits as well asthe more conventional single chip devices.

The newer insulated packages can be grouped into twocategories. The first has insulation between thesemiconductor chips and the mounting base; an exposedarea of the mounting base is used to secure the part. TheEMS (Energy Management Series) Modules, shown onFigure 32, Case 806 (ICePAK) and Case 388A(TO258AA) (see Figure 32) are examples of parts in thiscategory. The second category contains parts which have aplastic overmold covering the metal mounting base. Theisolated, Case 221C, illustrated in Figure 37, is an exampleof parts in the second category.

Parts in the first category those with an exposed metalflange or tab are mounted the same as their noninsulatedcounterparts. However, as with any mounting systemwhere pressure is bearing on plastic, the overmolded typeshould be used with a conical compression washer,described later in this note.

FASTENER AND HARDWARECHARACTERISTICS

Characteristics of fasteners, associated hardware, and thetools to secure them determine their suitability for use inmounting the various packages. Since many problems havearisen because of improper choices, the basiccharacteristics of several types of hardware are discussednext.

Compression HardwareNormal split ring lock washers are not the best choice for

mounting power semiconductors. A typical #6 washerflattens at about 50 pounds, whereas 150 to 300 pounds isneeded for good heat transfer at the interface. A very usefulpiece of hardware is the conical, sometimes called aBelleville washer, compression washer. As shown inFigure 24, it has the ability to maintain a fairly constantpressure over a wide range of its physical deflection generally 20% to 80%. When installing, the assemblerapplies torque until the washer depresses to half its originalheight. (Tests should be run prior to setting up the assemblyline to determine the proper torque for the fastener used toachieve 50% deflection.) The washer will absorb anycyclic expansion of the package, insulating washer or othermaterials caused by temperature changes. Conical washersare the key to successful mounting of devices requiringstrict control of the mounting force or when plastichardware is used in the mounting scheme. They are usedwith the large face contacting the packages. A newvariation of the conical washer includes it as part of a nutassembly. Called a sync nut, the patented device can besoldered to a PC board and the semiconductor mountedwith a 632 machine screw.(4)

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DEFLECTION OF WASHER DURING MOUNTING (%)0 20 40 60 10080

PRES

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ACKA

GE

(LB

F)280

40

0

240

200

160

120

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Figure 24. Characteristics of the ConicalCompression Washers Designed for Use with

Plastic Body Mounted Semiconductors

ClipsFast assembly is accomplished with clips. When only a

few watts are being dissipated, the small boardmounted orfreestanding heat dissipaters with an integral clip, offeredby several manufacturers, result in a low cost assembly.When higher power is being handled, a separate clip maybe used with larger heatsinks. In order to provide properpressure, the clip must be specially designed for aparticular heatsink thickness and semiconductor package.

Clips are especially popular with plastic packages suchas the TO220 and TO126. In addition to fast assembly,the clip provides lower interface thermal resistance thanother assembly methods when it is designed for properpressure to bear on the top of the plastic over the die. TheTO220 package usually is lifted up under the die locationwhen mounted with a single fastener through the hole inthe tab because of the high pressure at one end.

Machine ScrewsMachine screws, conical washers, and nuts (or sync nuts)

can form a troublefree fastener system for all types ofpackages which have mounting holes. However, propertorque is necessary. Torque ratings apply when dry;therefore, care must be exercised when using thermalgrease to prevent it from getting on the threads asinconsistent torque readings result. Machine screw headsshould not directly contact the surface of plastic packagestypes as the screw heads are not sufficiently flat to provideproperly distributed force. Without a washer, cracking ofthe plastic case may occur.

SelfTapping ScrewsUnder carefully controlled conditions, sheetmetal

screws are acceptable. However, during the tappingprocess with a standard screw, a volcanolike protrusionwill develop in the metal being threaded; an unacceptablesurface that could increase the thermal resistance may

result. When standard sheet metal screws are used, theymust be used in a clearance hole to engage a speednut. If aself tapping process is desired, the screw type must be usedwhich rollforms machine screw threads.

RivetsRivets are not a recommended fastener for any of the

plastic packages. When a rugged metal flangemountpackage or EMS module is being mounted directly to aheatsink, rivets can be used provided pressriveting isused. Crimping force must be applied slowly and evenly.Popriveting should never be used because the highcrimping force could cause deformation of mostsemiconductor packages. Aluminum rivets are muchpreferred over steel because less pressure is required to setthe rivet and thermal conductivity is improved.

The hollow rivet, or eyelet, is preferred over solid rivets.An adjustable, regulated pressure press is used such that agradually increasing pressure is used to pan the eyelet. Useof sharp blows could damage the semiconductor die.

SolderUntil the advent of the surface mount assembly

technique, solder was not considered a suitable fastener forpower semiconductors. However, user demand has led tothe development of new packages for this application.Acceptable soldering methods include conventionalbeltfurnace, irons, vaporphase reflow, and infraredreflow. It is important that the semiconductor temperaturenot exceed the specified maximum (usually 260C) or thedie bond to the case could be damaged. A degraded diebond has excessive thermal resistance which often leads toa failure under power cycling.

AdhesivesAdhesives are available which have coefficients of

expansion compatible with copper and aluminum.(5)

Highly conductive types are available; a 10 mil layer hasapproximately 0.3C/W interface thermal resistance.Different types are offered: high strength types fornonfield serviceable systems or low strength types forfield serviceable systems. Adhesive bonding is attractivewhen case mounted parts are used in wave solderingassembly because thermal greases are not compatible withthe conformal coatings used and the greases foul the solderprocess.

Plastic HardwareMost plastic materials will flow, but differ

Documents

[SCILLC] Soldering and Mounting Techniques. Refere(BookZZ.org)