C. Stroud 4/13 Scan-Based BIST 1

Scan-Based BIST - Organization ArchitectureFirst Scan-Based BISTRandom Test SocketSTUMPS

DependenciesLinearStructural

SolutionsReseeding LFSRsBit ManipulationTest Point InsertionPhase ShiftersMultiple Capture Cycles

Benefits and Limitations

C. Stroud 4/13 Scan-Based BIST 2

Basic Scan-Based BIST Approaches Manufacturing vs. System

level used determines complexity of architecture

For system-level useInput isolationBIST controller for

Scan/system mode clockingShift count control

Control number of test patternsPattern count

controlEnable MISR

compaction

C. Stroud 4/13 Scan-Based BIST 3

Scan BIST Controllers During BIST sequence,

must control Scan Mode for

shifting Test patternsOutput responses

System Mode forApplication of test

patternsMISR compaction

disableDuring initial test

patterns shiftAfter completion

of BIST sequence

C. Stroud 4/13 Scan-Based BIST 4

STUMPS by IBM Self-Test Using MISR/Parallel SRSG

Shift Register Sequence Generator (SRSG)

by Bardell, McAnney & Savir, 1987 Used in many IBM computers Centralized BISTCan be used at chip level

requires multiple scan chains

Can be used at board level requires all chip have scan design

Test-per-scan BIST MISR and LFSR combined in special purpose

test chip for board or system level test

LFSR

MISR

Chipor

ScanChain

1

Chipor

ScanChain

N

C. Stroud 4/13 Scan-Based BIST 5

Problems with Scan-Based BIST

Not all patterns generated by LFSR or CAR when applied to scan chainsResult of pseudo-random properties of LSFR/CARCritical test patterns for fault coverage may be missing

Structural DependenciesOccur in multiple scan chains

Linear DependenciesOccur in single and multiple scan chains

STUMPS architectures can have both structural and linear dependencies

C. Stroud 4/13 Scan-Based BIST 6

Structural Dependencies Recall the obvious shift in patterns in LFSR CARs also have shifting pattern properties near null boundary

conditions

External Feedback LFSR1 1 1 1 1 1 1 10 1 1 1 1 1 1 11 0 1 1 1 1 1 10 1 0 1 1 1 1 11 0 1 0 1 1 1 10 1 0 1 0 1 1 10 0 1 0 1 0 1 10 0 0 1 0 1 0 10 0 0 0 1 0 1 01 0 0 0 0 1 0 11 1 0 0 0 0 1 01 1 1 0 0 0 0 10 1 1 1 0 0 0 00 0 1 1 1 0 0 01 0 0 1 1 1 0 01 1 0 0 1 1 1 0

Internal Feedback LFSR1 1 1 1 1 1 1 11 0 1 1 1 0 0 11 0 0 1 1 0 1 00 1 0 0 1 1 0 11 1 1 0 0 0 0 00 1 1 1 0 0 0 00 0 1 1 1 0 0 00 0 0 1 1 1 0 00 0 0 0 1 1 1 00 0 0 0 0 1 1 11 1 0 0 0 1 0 11 0 1 0 0 1 0 00 1 0 1 0 0 1 00 0 1 0 1 0 0 11 1 0 1 0 0 1 00 1 1 0 1 0 0 1

Cellular Automata Register1 1 1 1 1 1 1 11 0 1 0 1 0 1 10 0 1 0 1 0 0 10 1 1 0 1 1 1 01 1 0 0 0 0 0 11 1 1 0 0 0 1 01 0 0 1 0 1 1 10 1 1 0 0 1 1 11 1 0 1 1 1 1 11 1 0 1 1 0 1 11 1 0 1 0 0 0 11 1 0 0 1 0 1 01 1 1 1 1 0 1 11 0 1 0 0 0 0 10 0 1 1 0 0 1 00 1 0 1 1 1 1 1

C. Stroud 4/13 Scan-Based BIST 7

Structural Dependencies Assume a 2×2 window of patterns

Would be case for a 4-input logic cone driven by 2 adjacent scan chains and 2 adjacent bits in those scan chains

Use LFSRs/CAR on previous page External FB LFSR

Produces 8/16 = 1/2 of patterns Produces 128/512 = 1/4

patterns in a 3×3 window Internal FB LFSR

Produces all possible patterns at adjacent non-0-coefficientsP(x)=x8+x6+x5+x+1

Similar to external FB at 0 coefficients

2×2 test pattern

External FB LFSR

Internal FB LFSR

CAR

00×00 any 2 adj bits bits 1&2, 4&5 bits 1&2, 7&810×00 not produced not produced bits 1&201×00 any 2 adj bits bits 1&2, 4&5 bits 7&811×00 not produced not produced not produced00×10 any 2 adj bits bits 4&5 bits 7&810×10 not produced bits 1&2 not produced01×10 any 2 adj bits bits 4&5 bits 1&2, 7&811×10 not produced bits 1&2 bits 1&200×01 not produced not produced bits 1&210×01 any 2 adj bits bits 1&2, 4&5 bits 1&2, 7&801×01 not produced not produced not produced11×01 any 2 adj bits bits 1&2, 4&5 bits 7&800×11 not produced bits 1&2 not produced10×11 any 2 adj bits bits 4&5 bits 7&801×11 not produced bits 1&2 bits 1&211×11 any 2 adj bits bits 4&5 bits 1&2, 7&8

CAR Produces all possible patterns

in middle of register Similar to external FB at null

boundary conditions

C. Stroud 4/13 Scan-Based BIST 8

Linear Dependencies LFSR produces 2n-1=15 patterns to a 10-bit scan chainOnly 3 unique vectors applied to NOR gate

Do not detect any of the inputs sa0 Some definitions for linear dependency design guidelines:Span = largest number of flip-flops in scan chain

between inputs to same logic coneSampling polynomial describes logic cone connections

to scan chain

D Qx1

CK

D Qx2

CK

D Qx3

CK

D Qx4

CK

91 2 3 4 5 6 7 8 10

Scan Chain101011001000111 101011001000111

repeat time

Scan Vectors#1 1001000111#2 0011110101#3 1010110010#1 1001000111 repeat

Sampling polynomialS(x) = x8+x7+x4 = x4+x3+1

|span=5|

C. Stroud 4/13 Scan-Based BIST 9

Linear Dependency Design Guidelines For the following design guidelines, let:n = degree of P(x)NFF = # flip-flops in longest scan chainNCC = # clock cycles in scan mode (NCC NFF)NTV = # scan vectors to be applied

Design Guidelines to reduce linear dependencies: Choose n such that 2n-1 & NFF do not have common divisor, or Choose NCC such that 2n-1 & NCC do not have common divisor Choose n such that 2n-1 NFF × NTV Choose n > largest span

In previous example, n=4 but span=5 Look at sampling polynomials, linear dependencies exist ifIf S(x) mod P(x) = 0

Similar to signature aliasing conditionsIf sub-polynomials of S(x) mod P(x) = 0

C. Stroud 4/13 Scan-Based BIST 10

Other Approaches to Linear Dependencies Note that design guidelines for

reducing linear dependencies tend to create large n, then 2n-1 is very largeLong test times, particularly for

test-per-scan BIST Other approaches includeReseeding LFSRMultiple polynomials for LFSRBit manipulation

Bit flippingBit fixing

Multiple capture cyclesTest point insertion

LFSR Scan Chain

Shift Cnt

Pattern Cnt

BitFlip

Logic

LFSR Scan Chain

Shift Cnt

Pattern Cnt

BitFix

Logic

fix-to-1 fix-to-0

C. Stroud 4/13 Scan-Based BIST 11

Partial Scan BIST by Lucent

by Lin et al., 1993 Requires near acyclic CUTfeedback loops have length = 1only a subset of FFs scanned

Separate BIST architecturemix of test-per-clock & test-per-scanprimary output values compressed every clock cycleresponses captured in scan chains every scan cycle

Uses multiple (k) capture cycles after each scan cycleuses different k values during testyields higher fault coverage (~1-1.5%) & shorter test

sequences (~60%) for small increase in area overhead (~1%)

LFSR

MISR

Scan Chain

CUTPIs POs

C. Stroud 4/13 Scan-Based BIST 12

Minimizing Structural Dependencies Design guidelines: choose n

such that 2n-1 NFF × NSCNFF = # flip-flops in

longest scan chainNSC = # scan chains

Incorporate phase shifterRemoves the shifting

pattern properties by adjusting phase of adjacent bits in LFSRSimilar results to CAR

Can be implemented with shift registersMore efficient

implementation with XORs

PhaseShift = 9

wrtpreviouschannel

C. Stroud 4/13 Scan-Based BIST 13

Phase Shifter Design1. Construct the dual of the TPG LFSR

Dual of internal FB LSFR is external FB LFSR with same polynomial,

And vice versa

2. Initialize dual LFSR with all-0s except for 1 in ith stage and simulate for k clock cycles where k is maximum possible phase shift desired for any channel wrt ith stage

3. The logic 1s contained in contents of dual LFSR at the jth clock cycle indicate outputs of original LFSR to be XORed to create channel with a phase shift of j clock cycles wrt ith stage

MISR

Chipor

ScanChain

1

Chipor

ScanChain

N

Phase Shifter

LFSR

C. Stroud 4/13 Scan-Based BIST 14

Example Phase Shifter Assume TPG is external FB LSFR with P(x)=x4+x+1then dual is internal FB LFSR with state diagram given below

Assume we want 5-channel phase shifter and the following phase shifts per channel wrt x1

c1 = 0, c2 = 6, c3 = 4, c4 = 12 = -3, c5 = 7 Using the design procedure we get:c1 = x1

c2 = x3x4

c3 = x1x2

c4 = x1x2x3x4 = c2c3

c5 = x1x2x4 = c3x4

Start here

c3=4ccsc2=6ccsc5=7ccs

c4=12ccs c1=0ccs

C. Stroud 4/13 Scan-Based BIST 15

Example Phase Shifter 4 XOR gates needed to produce 5 channels with specified phase

delays: c1 = 0 c2 = 6 c3 = 4 c4 = 12 = -3 c5 = 7

01234567

89101112 = -3

C. Stroud 4/13 Scan-Based BIST 16

Scan-Based BIST SummaryAdvantages Short test application time & at-speed testing Vertical testability – same for all levels of testing: device-

systemmay be applied hierarchically from device through system

High fault & defect coverage Provides embedded ATE reduces need for expensive

external ATE Reduced system diagnostic test development50% of BIST applications at Bell Labs initiated by

diagnosticians Growing support by CAD vendors

C. Stroud 4/13 Scan-Based BIST 17

Scan-Based BIST Summary (cont.)Disadvantages Area overhead typically 10-25%all costs of full scan in many BIST approaches plus more

extra logic for TPG & ORA BIST controller

Fault simulation may be lengthybut necessary to determine fault coverage

Additional risk to projectmust design BIST & system function

longer design time if no CAD automation available both must work for chip to ship

C. Stroud 4/13 Scan-Based BIST 18

Area Overhead of Scan-Based BIST