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© 2016 Renesas Electronics Corporation. All rights reserved.
Scalable Device SolutionsNew hardware features walkthrough
Renesas Synergy Engineering ConferenceLake Garda7-8 April 2016
© 2016 Renesas Electronics Corporation. All rights reserved.
AGENDA
Page 2
Synergy Hardware Concepts
Synergy Design Philosophy
Synergy Compatibility & Scalability
Synergy IP focus
Q&A
© 2016 Renesas Electronics Corporation. All rights reserved. Page 3
What is Synergy?
A complete and qualified platform that accelerates embedded development, inspiring innovation and enabling differentiation.
FasterTime toMarket
ReduceTotal Cost
of Ownership
LowerBarriersto Entry
Our Three ValuesA Solid Platform
SynergyMicrocontrollers
SynergyTools & Kits
SynergySolutions
SynergyGallery
Synergy Software
Software APIs
Synergy Software Package (SSP)
Board Support Package (BSP)
RTOS
HAL Drivers
Middleware & Stacks
Functional Libraries
Application Framework
Qualified Software Add-Ons
(QSA)
Verified Software Add-Ons
(VSA)
© 2016 Renesas Electronics Corporation. All rights reserved. Page 4
Synergy Hardware Concepts
• Synergy is the first ARM based general purpose microcontroller family from Renesas
• Designed from the beginning as a scalable platform
• Reuses proven Renesas IP
• Enhanced and new peripheral IP blocks to meet the needs of the embedded market
© 2016 Renesas Electronics Corporation. All rights reserved. Page 5
ARM Implementation
© 2016 Renesas Electronics Corporation. All rights reserved. Page 6
Cortex M Series
Synergy devices use Cortex-M cores
Cortex-M4 with single precision FPU (CM4F)
ARMv7E-M Architecture
Cortex-M0+ (CM0+)
ARMv6-M Architecture
In addition to “Core CPU”, additional ARM licensed IP
Nested Vectored Interrupt Controller (NVIC)
ARM Memory Protection Unit (MPU)
Debugger Subsystem (CoreSight)
System Tick Timer (SysTick)
© 2016 Renesas Electronics Corporation. All rights reserved. Page 7
Cortex M Series within Synergy
How much can we do at once?
© 2016 Renesas Electronics Corporation. All rights reserved. Page 8
Synergy Design Philosophy
© 2016 Renesas Electronics Corporation. All rights reserved. Page 9
Synergy Design Philosophy within Synergy Portfolio
Pin Count
PE
RF
OR
MA
NC
EF
las
h D
en
sit
y
4M
3M
2M
1M
512K
256K
128K
64K
36 48 64 100 121 144/145 176 224
© 2016 Renesas Electronics Corporation. All rights reserved. Page 10
Synergy Process Technology
Ultra-Low Power
Core Frequency
Up to 32MHz
High Efficiency
Core Frequency
33-100MHz
High Integration
Core Frequency
101-200MHz
High Performance
Core Frequency
201-300MHz
130nm MF3 40nm RV40F
© 2016 Renesas Electronics Corporation. All rights reserved. Page 11
Synergy Package Scalability
Scalability Within Series..
S1, S3 Package Types:
145-pin LGA
64-pin QFN
36, 40, 48, 64, 100, 144-pin LQFP
© 2016 Renesas Electronics Corporation. All rights reserved. Page 12
Synergy Package Scalability
A closer look at 64, 100, 144-pin packages:
© 2016 Renesas Electronics Corporation. All rights reserved. Page 13
Synergy Package Scalability
Similarly, on Right hand side of 64, 100,
144-pin packages
© 2016 Renesas Electronics Corporation. All rights reserved. Page 14
Scalability within Series..
S5, S7 Package Types:
145, 176, 224 LGA
100, 144, 176 LQFP
Synergy Package Scalability
© 2016 Renesas Electronics Corporation. All rights reserved. Page 15
Synergy Package Scalability
S7 & S5 have 100 pin and 144 pin LQFP
S3 has 100 pin and 144 pin LQFP
These are compatible, process technology permitting.
© 2016 Renesas Electronics Corporation. All rights reserved. Page 16
Synergy Package Scalability – Between Series
© 2016 Renesas Electronics Corporation. All rights reserved. Page 17
Synergy Package Scalability
© 2016 Renesas Electronics Corporation. All rights reserved. Page 18
240MHz CPU
80 MHz Flash
120MHz CPU
2.7-3.6V
80/40 MHz Flash
Cortex M4
48MHz CPU
FPU
CPU TimerUser
Interface
Graphic LCD controller
w/ 2D accelerator
Safety
High PerformanceRV40F
S7
Analog System
External Memory I/F (SDRAM)
Clock SecurityComm.Memory
Flash: 2MB-4MB
RAM:512KB/640KB
Data Flash: 64KB
High IntegrationRV40F
S5
ADC: 12b
HOCO16/18/20 MHz
PLL
TSIPAES 256
SHA1, SHA2RNG
USB 2.0 HSHost/Peripheral/
OTGRAM:16KB-
256KB
Data Flash: 16-32KB
Dual 10/100 Ethernet
Flash:128KB-2MB
High EfficiencyMF3S3
USB 2.0 FS(Host/Periph/OTG)
SDHI/SDIO
QSPI
External Memory I/F
(SRAM)
Flash: 768KB-1MB
RAM:16KB-192KB
Data Flash: 16KB
SSI
Cortex M0+
32MHz CPU
1.6- 5.5V
AGT
GPT: 32bGPT: 16b
ARM SysTick Timer
RTC + VBAT
WDT
iWDT
CAC
DOC
CRC
GPIO read back
ADC BIST
Low PowerMF3S1
DTC, DMA
POR, LVD
ELC
SNOOZE
MPC
Debug: 1-Wire,JTAG
HOCO24 - 64 MHz
LOCO32.768 KHz
LOCO15 kHz
for IWDT
Main clock1-20MHz
Sub Clock 32.768 KHz
SCIwith FIFO
I2C
SPI
IrDA
Flash: 8KB-64KB
RAM:4KB-32KB
Data Flash: 4KB
MPU (ARM) GPIO5V tolerant, high current
-40 to 105C
SFR GuardECC on Flash
Parity on RAMDebug Trace
Illegal Memory access
32MHz Flash
CAN
Sampling Rate Converter
Regulator (Switching)
PGA:6 channel
Comparator:6 channel
128-bitUnique ID
MPU (Renesas)
GHASHAES 128/256
TRNG
DAC: 12b
Op-amp: x4
Comparator: 4 channel
Temp sensor
Vref
Regulator(Linear)
ADC: 14b
MOCO8 MHz
PLL
Synergy Peripheral Compatibility
USB 2.0 FS(Peripheral)
GPT: 32b
Cap Touch
© 2016 Renesas Electronics Corporation. All rights reserved. Page 19
Synergy Peripheral Compatibility
Cortex M4
48MHz CPU
FPU
CPU TimerUser
Interface
Graphic LCD controller
w/ 2D accelerator
SafetyAnalog System
External Memory I/F (SDRAM)
Clock SecurityComm.Memory
Flash: 2MB-4MB
RAM:512KB/640KB
Data Flash: 64KB
ADC: 12b
HOCO16/18/20 MHz
PLL HOCO
TSIPAES 128/192256
SHA1, SHA2TRNG
USB 2.0 HSHost/Peripheral/
OTGRAM:16KB-
640KB
Data Flash: 16-32KB
Dual 10/100 Ethernet
Flash:128KB-2MB
Segment LCD52x8 max
SDHI/SDIO
QSPI
External Memory I/F
(SRAM)
Flash: 768KB-1MB
RAM:16KB-192KB
Data Flash: 16KB
SSI
1.6- 5.5V
Flash: 8KB-128KB
RAM:4KB-32KB
Data Flash: 4KB
-40 to 105C
ECC on Flash
Parity on RAM
CAN
Sampling Rate Converter
Regulator (Switching)
PGA:6 channel
Comparator:6 channel
MOCO8 MHz
PLL
AGT
GPT: 32bGPT: 16b
ARM SysTick Timer
RTC
WDT
iWDT
CAC
DOC
CRC
GPIO read back
ADC BIST
DTC, DMA
POR, LVD
ELC
SNOOZE
MPC
Debug: 1-Wire,JTAG
LOCO32.768 KHz
LOCO15 kHz
for IWDT
Main clock1-20MHz
Sub Clock 32.768 KHz
GPIO5V tolerant, high current
SFR Guard
Debug Trace
Illegal Memory access
128-bitUnique ID
MPU (Renesas)
GHASHAES 128/256
TRNG
DAC: 12b
Op-amp: x4
Comparator: 4 channel
Temp sensor
Vref
Regulator(Linear)
ADC: 14b
High PerformanceRV40F
S7
High IntegrationRV40F
S5
High EfficiencyMF3S3
Low PowerMF3S1
MPU (ARM)
SCIwith FIFO
I2C
SPI
IrDA
USB 2.0 FS(Peripheral)
USB 2.0 FS(Host/Periph/OTG)
HOCO24 - 64 MHz
+ MOCO 8MHz
GPT: 32b
Cap Touch
VBatt
240MHz CPU
2.7-3.6V
120MHz CPU
2.7-3.6V
32MHz CPU
Cortex M0+
© 2016 Renesas Electronics Corporation. All rights reserved. Page 20
Synergy Peripheral Compatibility
240MHz CPU
120MHz CPU
Cortex M4
48MHz CPU
FPU
CPU TimerUser
InterfaceSafetyAnalog SystemClock SecurityComm.Memory
Flash: 2MB-4MB
RAM:512KB/640KB
Data Flash: 64KB
ADC: 12b
HOCO16/18/20 MHz
PLL HOCO
TSIPAES 128/192256
SHA1, SHA2TRNG
USB 2.0 HSHost/Peripheral/
OTGRAM:16KB-
640KB
Data Flash: 16-32KB
Dual 10/100 Ethernet
Flash:128KB-2MB
SDHI/SDIO
QSPI
Flash: 768KB-1MB
RAM:16KB-192KB
Data Flash: 16KB
SSI
1.6- 5.5V
AGT
GPT: 32bGPT: 16b
ARM SysTick Timer
RTC
WDT
iWDT
CAC
DOC
CRC
GPIO read back
ADC BIST
DTC, DMA
POR, LVD
ELC
SNOOZE
MPC
Debug: 1-Wire,JTAG
LOCO32.768 KHz
LOCO15 kHz
for IWDT
Main clock1-20MHz
Sub Clock 32.768 KHz
Flash: 8KB-128KB
RAM:4KB-32KB
Data Flash: 4KB
GPIO5V tolerant, high current
-40 to 105C
SFR GuardECC on Flash
Parity on RAMDebug Trace
Illegal Memory access
CAN
External Memory I/F (SDRAM)
Graphic LCD controller
w/ 2D accelerator
Sampling Rate Converter
Regulator (Switching)
PGA:6 channel
Comparator:6 channel
GHASHAES 128/256
TRNG
DAC: 12b
Op-amp: x4
Comparator: 2 channel
Temp sensor
Vref
Regulator(Linear)
ADC: 14b
MOCO8 MHz
PLL
MPU (Renesas)
128-bitUnique ID
High PerformanceRV40F
S7
High IntegrationRV40F
S5
High EfficiencyMF3S3
Low PowerMF3S1
MPU (ARM)
SCIwith FIFO
I2C
SPI
IrDA
USB 2.0 FS(Peripheral)
USB 2.0 FS(Host/Periph/OTG)
HOCO24 - 64 MHz
+ MOCO 8MHz
GPT: 32b
Cap Touch
Segment LCD52x8 max
External Memory I/F
(SRAM)
VBatt
2.7-3.6V
2.7-3.6V
32MHz CPU
Cortex M0+
© 2016 Renesas Electronics Corporation. All rights reserved. Page 21
Synergy Peripheral Compatibility
R64CNT40044000h
RYRCNT4004400EhRSECAR40044010h
RYRAREN4004401EhRSECAR40044010h
RYRAREN4004401EhRCR140044022h
RADJ4004402EhRCR140044022h
RADJ4004402Eh
...
...
...
...
...
RTCCRy40044040h
RMONCPy4004405Ch...
R64CNT40044000h
RYRCNT4004400EhRSECAR40044010h
RYRAREN4004401Eh
RSECAR40044010h
RYRAREN4004401EhRCR140044022h
RADJ4004402EhRCR140044022h
RADJ4004402Eh
...
...
...
...
...
RTCCRy40044040h
RMONCPy4004405Ch...
ClockDividerLOCO
Calendar Count
ReducedAlarm
Function
InterruptController
BUS INTERFACE
RTC implementation
Sub-Clock
Physical features of the peripheral in the S1 MCU is a pure orthogonal subset of the features in the S7 MCU
The control registers have no dependencies as they are scaled down to a lower feature set
The control register address offsets are constant even as features are removed
RTC implementation
ClockDividerLOCO
Calendar Count
AlarmFunction
InterruptController
BUS INTERFACE
Sub-Clock
Time Capture
Tamper Detect
© 2016 Renesas Electronics Corporation. All rights reserved. Page 22
Synergy IP
© 2016 Renesas Electronics Corporation. All rights reserved. Page 23
Synergy IP – Compressed..
© 2016 Renesas Electronics Corporation. All rights reserved. Page 24
Synergy IP: Proven technology
DMAC/DTC
RTC
WDT/iWDT
CGC/CAC/DOC
USB/Ethernet
CAN/RIIC/RSPI
DAC
I2S/SRC
ISI – Image Sensor Interface
CTC – Capacitive Touch Controller
SLCD – Segment LCD Controller
© 2016 Renesas Electronics Corporation. All rights reserved. Page 25
Synergy IP: Proven technology - Enhanced
ELC - Event Link Controller
IOPC - I/O Port Control
ADC
SCI - Serial Communication Interface
CRC
SD/MMC Controller
© 2016 Renesas Electronics Corporation. All rights reserved. Page 26
Synergy IP: New MCU technology
HMI : GLCDC/2D-DRW/JPEG
SCEx - Secure Crypto Engine
QSPI - QuadSPI Serial Flash Interface
MMF - Memory Mirror Function
Information Memory
RMPU - Renesas Memory Protection Unit collection
AGT - Asynchronous General Purpose Timer
GPTx / POE / OPS - General PWM Timer / Port Output Enable / Output Phase Switching
© 2016 Renesas Electronics Corporation. All rights reserved. Page 27
Synergy IP Highlights
© 2016 Renesas Electronics Corporation. All rights reserved. Page 28
Graphics LCD Controller (GLCDC)
Supports alpha-blended background and 2x layers
Layers up to 800x480x32bpp
Many Layer formats
1bpp CLUT to 32bpp ARGB8888
Layers sourced from internal RAM/Flash or external SDRAM
SDRAM 16bits x 120Mhz
High function output control
Brightness, Contrast, Dither, Gamma
Configurable control pins (HS,VS,DEN)
Simplified implementation of
Graphics LCD Controller
TCON 0123[VSYNC, HSYNC, DEN]
Graphics LCD Controller
Background Screen Generation Block
Graphics Plane 1
Graphics Plane 2
Output control block
32 APB
32 AHB
LCDDATA0-23
LCD_CLK
Image Data Display Control Signals
Data Format Conversion
BlockTCON Block
Graphics Data IF Block
AlphaBlend Block
AlphaBlend Block
Graphics Data IF Block
Screen Generation
Block
Panel-oriented
Correction Process
Block
Regis
ters
Regis
ters
Regis
ters
Regis
ters
Dithering
Desired Color Gradient
Color Banding(Abrupt color
changes,poor gradient reproduction)
Dithered Image(Quantization
noise randomization,
improved gradient
reproduction)
Alpha Blending
New Blended Color
Opaque Foreground
Transparent Foreground
© 2016 Renesas Electronics Corporation. All rights reserved. 29
2D Drawing Engine (DRW) (7,5)
Module to update the frame buffer with graphical content to off load CPUSupports a variety of 2D graphics including lines, circles, ellipses, polygons, custom geometry, etc.
Simplified rendering setup showing efficient
decoupling of CPU (for other system tasks) &
2D Drawing Engine (for graphics rendering)
Coordinate Transformation
Edge Setup
Anti-aliasedRasterization
Texturing
Colorization
Blending
Memory Write
Texture Setup
Texture Cache
Run Length Encoded Unit
Memory Read
2D Drawing Engine
Core
Dra
win
g F
ea
ture
s
Vector Drawing Allows for easier implementation of edge anti-aliasing and blurring with reduced
overhead Uses half plane rendering approach Can be used to combine non-linear, quadratic equation-based primitives (conic
sections, quadratic curves, etc.)
BitBLT (Bit Boundary Block Transfer) Allows combination of two bitmaps; for example, combining a rectangle and a
texture. Results in fill, copy, rotate, scale, alpha blending, color conversion, bilinear
filtering, etc.
Anti-Aliasing
Vector Image Raster Image(Aliased)
Anti-aliased Image
Engine can achieve results 20x faster than CPU
© 2016 Renesas Electronics Corporation. All rights reserved. 30
JPEG Codec (7,5)
Hardware accelerator for JPEG encode/decode
Supports streaming of source and destination data
Fast decode permits MJPEG
20x faster than CPU
Supports subsampling for thumbnails and simple scaling
Simplified implementation of JPEG
Codec
Pix
el F
orm
ats
Compression YCbCr422 (H = 2:1:1, V = 1:1:1)
Decompression YCbCr444 (H = 1:1:1, V = 1:1:1)8 lines by 8 pixels minimum coded unit for each decompression YCbCr422 (H = 2:1:1, V = 1:1:1)8 lines by 16 pixels MCU YCbCr411 (H = 4:1:1, V = 1:1:1)8 lines by 32 pixels MCU YCbCr420 (H = 2:1:1, V = 2:1:1)16 lines by 16 pixels MCUOutput pixel format ARGB8888, RGB565
Synergy MCU
JPEG Codec
Discrete Cosine T/f
Quantizer
Core Register
JPEG CoreData Input Bus Interface
Input Bus
Control Register
Data Output
Bus Interface
Output Bus
Control Register
Internal Peripheral Bus
Module Data Bus
Internal Graphics Bus
Huffman Coder Marker
Processing
© 2016 Renesas Electronics Corporation. All rights reserved. Page 31
QuadSPI Serial Flash Interface (QSPI)
Dedicated serial memory interface
Normal operation maps read requests into MCU Linear Memory
QSPI provide 64Mbyte window serial memory
For S7 device running 4-bit data and 60Mhz clocking
Sequential accesses
faster than 80ns 16-bit parallel NOR flash
Eliminates external bus in many applications
Great for bulk graphics resource storage
Code can also be executed directly from this space
Erase and programming operations
Available through QSPI “direct mode”
Simplified implementation of QSPI
Synergy MCU
Clock Generation
IO1
IO2
IO3
IO4
CLK
SS
BusInterface
Unit
Internal Bus
Signal Generation
Port Control
Registers & Control
QSPI
RX
TX
© 2016 Renesas Electronics Corporation. All rights reserved. Page 32
Memory Mirror Function (MMF)
Physical address in Flash can be mapped to a
virtual address in memory map by write to a
single register
Benefits:
Supports safe firmware updates - Multiple
versions of application firmware can be held in
Flash
Switch instantly between firmware version images
- No need to copy new firmware image to specific
link location
No requirement to build firmware for position
independent code (PIC)
© 2016 Renesas Electronics Corporation. All rights reserved. Page 33
Memory Mirror Function (MMF)
Simple hardware implementation and
easy to use in application firmware
Synergy MCU
0x0000 0000
Flash
0x0003 FFFF
0x027F FFFF
Virtual Address
User’s Code
0x0200 0000
Memory MappingSpace
Application 2
Application 1
BaseAdd1
Boot Code
Virtual Address
BaseAdd2
8 M
B
© 2016 Renesas Electronics Corporation. All rights reserved. Page 34
Information Memory (Factory Flash)
Programmed in read-only flash area at final test
Product Information
Unique ID (128 bits)
Part Number and Product Marking (ASCII 32 characters)
Part Data (package, pin count, temperature spec, etc)
Peripheral Data
Base address, channel count, version for every peripheral
Availability in package of ports, ADC, CTSU, etc
Memory type, start, size
Firmware API to simplify access and future version updates
Synergy Framework will utilize to become “smarter”
© 2016 Renesas Electronics Corporation. All rights reserved. Page 35
General PWM Timer (GPTx)
Scalable family of timers to meet application needs and costs
GTU16: 16bit timer unit with timer/capture/compare/count/motor
GTU32: TU16 functions with 32bit registers
GTU32E: TU32 functions with additional high end motor control
GTU32EHx: TU32x functions with pico second delay comparators
Event Sources:
2x I/O pins per channel
Up to 8x ELC events shared across all channels
Events can cause TUx to start/stop/clear/count/capture
TUx channels can be assigned to larger groups for multi-channel functions (inverter control)
Up to 4x TUx POE pins that are shared across all channels
Counter
Control and Setting
Registers
Comparator
3-Phase PWM Generator
/1024
/256
/64
/16
/4/1
GT
ET
RG A
B
CD
PC
LK
INT
Output Disable Request/Signal
Output Disable Signal
ELC
ELC
GTIOCB
GTIOCA
Comparator
Ext
ern
al
Triggers
8
GTIx
GTOxUP
3
3
General PWM Timer 32-Bit Enhanced High ResolutionADC StartRequestClock Frequency
Divider
Simplified implementation example of
General PWM Timer 32-Bit Enhanced High Resolution
© 2016 Renesas Electronics Corporation. All rights reserved.
Features GPT32-EH GPT32-E GPT32 GPT16
Counter Bits 32 32 32 16
ClocksPCLK
(/4, /16, /64, /256, /1024)PCLK
(/4, /16, /64, /256, /1024)PCLK
(/4, /16, /64, /256, /1024)PCLK
(/4, /16, /64, /256, /1024)
Counting Mode Up, Down Up, Down Up, Down Up, Down
Max. No. of Units 4 4 10 6
Input Capture Available Available Available Available
Compare Match Output Available Available Available Available
ADC Start Request Available Available - -
Interrupt Sources 13 TBD 13 TBD 10 TBD 10
Interrupt Skipping Available Available - -
3-Phase PWM Generator Available Available Available Available
Pico Second Delay Available - - -
Available In
36
Comparison Between GPTs
© 2016 Renesas Electronics Corporation. All rights reserved. 37
Asynchronous General Purpose Timer (AGT) (7,5,3,1)
True asynchronous behavior, does not rely on PCLK active
Widely selectable count sources : LOCO, SUBOsc, PCLK, external
Can operate in standby modes (and wake system)
Works on Vbatt on S3 devicesSimplified implementation of
Asynchronous General Purpose Timer
Mo
de
s o
f o
pe
ratio
n
Pulse Period Measurement modeAn external pulse period is measured
Pulse Width Measurement modeAn external pulse width is measured
Event Counter modeAn external event is counted
Pulse Output modeCount source is counted and output is inverted upon timer underflow
Timer modeCount source is counted
Synergy MCU
Compare and Match A
Compare and Match B
Clocking
Counter Control
16-BitDown Counter
PC
LK
f SU
B
LO
CO
Tim
er
Underf
low
Output Comp Match A
Pulse Output
External Event Input/PulseOutput
Output Comp Match B
Com
pare
M
atc
h B
ELC
Underf
low
/ M
easu
rem
en
t C
om
ple
te E
LC
Com
pare
M
atc
h A
ELC
Internal Peripheral Bus
Asynchronous General Purpose Timer
Reload Register B
Reload Register A
© 2016 Renesas Electronics Corporation. All rights reserved. Page 38
Memory Protection Unit collection
Multiple needed to get the job done
© 2016 Renesas Electronics Corporation. All rights reserved. Page 39
MPU Collection
ARM MPU
Cortex Standard MPU
Provides access rights for up to 8x regions
Only protects access from CPU
Aware of processor operations
Execute .vs Data, Read .vs Write, Privileged .vs User
Regions are “blocky”
Requires RTOS support for full benefit
© 2016 Renesas Electronics Corporation. All rights reserved. Page 40
MPU Collection
Bus Master MPU
Renesas MPU
Only applies to Non-CPU masters
Provides fine control of bus master memory accesses
When disabled, all memory is considered read/write
When enabled, all memory is protected (only enabled areas accessible)
Address ranges fine grained (32-bit boundaries)
Configuration based on driver requirements…examples:
Limit EDMAC to configured buffers
Limit DTC/DMAC to some peripheral areas and buffers
Limit HMI to video buffers, resources and scratchpad
© 2016 Renesas Electronics Corporation. All rights reserved. Page 41
MPU Collection
Bus Slave MPU
Renesas MPU
Provides permission for a master to access a slave…
Examples:
Prevent DMAC/DTC from accessing external bus
Prevent HMI from accessing flash
Address ranges are inherent in what is blocked
Simple configuration based on application requirements
Done once at startup
© 2016 Renesas Electronics Corporation. All rights reserved. Page 42
MPU Collection
Synergy Microcontrollers are designed to be highly scalable and compatible
Include all the peripherals you need, with enhancements to well-proven Renesas IP
And a few ‘gems’ that I hopefully have given you a glimpse of!
© 2016 Renesas Electronics Corporation. All rights reserved. Page 43
THANK YOU FOR YOUR ATTENTION
PLEASE REMEMBER TO COMPLETE THE FEEDBACK
SURVEY IN YOUR SMARTPHONE APP
© 2016 Renesas Electronics Corporation. All rights reserved. Page 44
Synergy MCU S7 Series
Code Flash (4 MB)Data Flash (64 KB)
SRAM (640 KB)Flash CacheSecurity MPU
Memory Mirror Function
Memory
12-Bit A/D Converter x2 (25 ch.)
12-Bit D/A Converter x2High-Speed Analog
Comparator x6PGA x6
Temperature Sensor
DMA Controller (8 ch.)Data Transfer Controller
Event Link ControllerLow Power Modes
Switching Regulator
ECC in SRAM
Analog Timing & Control HMI
Connectivity System & Power Mgmt Safety Security& Encryption
General PWM Timer 32-bitEnhanced High Resolution x4
Asynchronous General Purpose Timer x2
General PWM Timer 32-bit Enhanced x4
WDT
Capacitive Touch Sensing Unit (18 ch.)
Graphics LCD Controller2D Drawing Engine
JPEG CodecParallel Data Capture
Ethernet MAC Controller x2Ethernet DMA ControllerEthernet PTP Controller
CAN x2 SDHI/MMC x2USBHS USBFS
Serial Communications Interfacex10
QSPI SPI x2IIC x3 SSI x2
Sampling Rate ConverterExternal Memory Bus
Multiple ClocksPort Function Select
RTCSysTick
SRAM Parity Error CheckFlash Area Protection
ADC DiagnosticsClock Frequency Accuracy
Measurement CircuitCRC Calculator
Data Operation CircuitPort Output Enable for GPT
IWDT
128-bit Unique IDTRNG
AES (128/192/256)3DES/ARC4
RSA/DSASHA1/SHA224/SHA256
240-MHz ARM® Cortex®-M4 CPU
IrDA Interface
General PWM Timer 32-bit x6
FPU | MPU | NVIC | ETM | JTAG | SWD | Boundary Scan
GHASH
© 2016 Renesas Electronics Corporation. All rights reserved. Page 45
Synergy MCU S5 Series
Memory Analog Timing & Control HMI
Connectivity System & Power Mgmt Safety Security& Encryption
Code Flash (2 MB)Data Flash (64 KB)
SRAM (640 KB)Flash CacheSecurity MPU
Memory Mirror Function
120-MHz ARM® Cortex®-M4 CPU
Capacitive Touch Sensing Unit (18 ch.)
Graphics LCD Controller2D Drawing Engine
JPEG CodecParallel Data Capture
Ethernet MAC ControllerEthernet DMA ControllerEthernet PTP Controller
CAN x2 SDHI/MMC x2USBHS USBFS
Serial Communications Interface x10
QSPI SPI x2IIC x3 SSI x2
Sampling Rate ConverterExternal Memory Bus
IrDA Interface
General PWM Timer 32-bitEnhanced High Resolution x4
Asynchronous General Purpose Timer x2
General PWM Timer 32-bit Enhanced x4
General PWM Timer 32-bit x6
FPU | MPU | NVIC | ETM | JTAG | SWD | Boundary Scan
128-bit Unique IDTRNG
AES (128/192/256)3DES/ARC4
RSA/DSASHA1/SHA224/ SHA256
WDT
12-Bit A/D Converter x2(21 ch.)
12-Bit D/A Converter x2High-Speed Analog
Comparator x6PGA x6
Temperature Sensor
DMA Controller (8 ch.)Data Transfer Controller
Event Link ControllerLow Power Modes
ECC in SRAM
Multiple ClocksPort Function Select
RTCSysTick
SRAM Parity Error CheckFlash Area Protection
ADC DiagnosticsClock Frequency Accuracy
Measurement CircuitCRC Calculator
Data Operation CircuitPort Output Enable for GPT
IWDT
GHASH
© 2016 Renesas Electronics Corporation. All rights reserved. Page 46
Synergy MCU S3 Series
HMITiming & ControlAnalogMemory
Code Flash (1 MB)Data Flash (16 KB)
SRAM (192 KB)Flash CacheSecurity MPU
Memory Mirror Function
14-Bit A/D Converter(28 ch.)
12-Bit D/A Converter x2Low-Power Analog
Comparator x2
OPAMP x4Temperature Sensor
General PWM Timer 32-bit x10
Asynchronous General Purpose Timer x2
128-bit Unique IDTRNG
AES (128/256)GHASH
Connectivity System & Power Mgmt Safety Security& Encryption
WDT
Capacitive Touch Sensing Unit (35 ch.)
Segment LCD Controller
DMA Controller (4 ch.)Data Transfer Controller
Event Link ControllerLow Power Modes
Multiple ClocksPort Function Select
RTCSysTick
ECC in SRAMSRAM Parity Error Check
Flash Area ProtectionADC Diagnostics
Clock Frequency Accuracy Measurement Circuit
CRC CalculatorData Operation Circuit
Port Output Enable for GPTIWDT
High-Speed AnalogComparator x2
USBFS
Serial Communications Interface x6
QSPI SPI x2IIC x3 SSI x2External Memory Bus
CAN SDHI/MMC
IrDA Interface
48-MHz ARM® Cortex®-M4 CPUFPU | MPU | NVIC | ETM | JTAG | SWD | Boundary Scan
© 2016 Renesas Electronics Corporation. All rights reserved. Page 47
Synergy MCU S1 Series
HMITiming & ControlAnalogMemory
Code Flash (128 KB)Data Flash (4 KB)
SRAM (16 KB)
14-Bit A/D Converter (18 ch.)12-Bit D/A ConverterLow-Power Analog
Comparator x2Temperature Sensor
Asynchronous General Purpose Timer x2
32-MHz ARM® Cortex®-M0+ CPU
Data Transfer ControllerEvent Link ControllerLow Power Modes
128-bit Unique IDTRNG
AES (128/256)
Connectivity System & Power Mgmt Safety Security& Encryption
WDT
Capacitive Touch Sensing Unit (32 ch.)
CANUSBFS
Serial Communications Interface x3
SPI x2IIC x2
Multiple ClocksPort Function Select
RTCSysTick
SRAM Parity Error CheckFlash Area Protection
ADC DiagnosticsClock Frequency Accuracy
Measurement Circuit
CRC CalculatorData Operation Circuit
Port Output Enable for GPTIWDT
General PWM Timer 32-bitGeneral PWM Timer 16-bit
x6
NVIC | SWD | MTB
© 2016 Renesas Electronics Corporation. All rights reserved. 48
Core
Core
FPU
ARM MPU
NVIC
ETM
JTAG
SWD
Boundary Scan
© 2016 Renesas Electronics Corporation. All rights reserved. 49
ARM® Cortex®-M4 Integration (7)
Ultra-high performance and high integrationMaximum system clock frequency: 240 MHz Performance CoreMark™/MHz: 3.28 @ 200 MHz CoreMark™ at maximum system frequency: 681 @ 240 MHzARM ® v7E-M architecture profile High code density with 32-bit performance Low gate count Thumb-2 instruction set17 core registers 13 general purpose registers Stack pointer, link register, program counter, program status registersBit-banding supportFloating Point Unit ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic compliant 32-bit instructions for single-precision (C float) data-processing operations Multiply and accumulate instructions for increased precision (fused MAC)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
ARM® Cortex®-M4 Processor
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Nested Vector Interrupt
Controller
Instrumentation Trace Macrocell
(ITM)
Trace Port Interface Unit
(TPIU)
Data Watchpoint and Trace
(DWT)
Flash Patch Breakpoint
(FPB)
Cortex®-M4 Core + Floating Point Unit
ARM® Memory Protection Unit(ARM® MPU)
© 2016 Renesas Electronics Corporation. All rights reserved. 50
ARM® Cortex®-M4 Integration (5)
Ultra-high performance and high integrationMaximum system clock frequency: 100 MHz – 200 MHzPerformance CoreMark™/MHz: TBD CoreMark™ at maximum system frequency: TBDARM ® v7E-M architecture profile High code density with 32-bit performance Low gate count Thumb-2 instruction set17 core registers 13 general purpose registers Stack pointer, link register, program counter, program status registersBit-banding supportFloating Point Unit ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic compliant 32-bit instructions for single-precision (C float) data-processing operations Multiply and accumulate instructions for increased precision (fused MAC)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Nested Vector Interrupt
Controller
Instrumentation Trace Macrocell
(ITM)
Trace Port Interface Unit
(TPIU)
Data Watchpoint and Trace
(DWT)
Cortex®-M4 Core + Floating Point Unit
Flash Patch Breakpoint
(FPB)
ARM® Cortex®-M4 Processor
ARM® Memory Protection Unit(ARM® MPU)
© 2016 Renesas Electronics Corporation. All rights reserved. 51
ARM® Cortex®-M4 Integration (3)
Ultra-high performance and high integrationMaximum system clock frequency: 48 MHz Performance CoreMark™/MHz: 3.31 @ 48 MHz CoreMark™ at maximum system frequency:158.9 @ 48 MHzARM ® v7E-M architecture profile High code density with 32-bit performance Low gate count Thumb-2 instruction set17 core registers 13 general purpose registers Stack pointer, link register, program counter, program status registersBit-banding supportFloating Point Unit ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic compliant 32-bit instructions for single-precision (C float) data-processing operations Multiply and accumulate instructions for increased precision (fused MAC)
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Nested Vector Interrupt
Controller
Flash Patch Breakpoint
(FPB)
Instrumentation Trace Macrocell
(ITM)
ROM Table
Cortex®-M4 Core + Floating Point Unit
Data Watchpoint and Trace
(DWT)
ARM® Cortex®-M4 Processor
ARM® Memory Protection Unit(ARM® MPU)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 52
ARM® Cortex®-M0+ Integration (1)
Maximum system clock frequency: 32 MHzPerformance CoreMark™/MHz: 2.49 @ 32 MHz CoreMark™ at maximum system frequency: 79.8 @ 32 MHzARM ® v6-M architecture profile High code density with 32-bit performance Low gate count Supports Thumb and many Thumb-2 subset instructions19 core registers 13 general purpose registers Stack pointer, link register, program counter, program status register, control, priority maskOptimized for ultra-low power Power control of system components Integrated sleep modes Fast code execution permits longer sleep time Optimized code fetching reduces flash and ROM power consumptionDeterministic, high-performance interrupt handlingSingle-cycle IO accessSingle-cycle hardware integer multiplier
Macro Trace Buffer(MTB)
ROM Table
Cortex®-M0+ CoreDebugger Interface
Breakpoint andWatch Unit
Nested Vector Interrupt
Controller(NVIC)
ARM® Cortex®-M0+ Processor
Debug Access Port (DAP)Serial Wire
Debug (SWD)
ARM® Cortex®-M0+ CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 53
ARM® Cortex®-M4 NVIC and ARM® MPU (7,5)
Nested Vector Interrupt Controller (NVIC) Provides configurable interrupt-handling abilities to the processor Facilitates low latency exception and interrupt handing Controls power management using Wake-up Interrupt Controller (WIC) Supports 96 interrupts Enables tail-chaining Supports priority grouping Level-sensitive and pulse-sensitive interruptsARM® Memory Protection Unit (ARM® MPU) Supports ARMv7 Protected Memory System Architecture model 8 protect regions (0-7 priority) Access permissions Generates a fault if restricted area of memory is accessed Use to enforce privilege rules, to separate processes, and to enforce access rules
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Instrumentation Trace Macrocell
(ITM)
Trace Port Interface Unit
(TPIU)
Data Watchpoint and Trace
(DWT)
Nested Vector Interrupt
Controller
Cortex®-M4 Core + Floating Point Unit
Flash Patch Breakpoint
(FPB)
ARM® Cortex®-M4 Processor
ARM® Memory Protection Unit(ARM® MPU)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 54
ARM® Cortex®-M4 NVIC and ARM® MPU (3)
Nested Vector Interrupt Controller (NVIC) Provides configurable interrupt-handling abilities to the processor Facilitates low latency exception and interrupt handing Controls power management using Wake-up Interrupt Controller (WIC) Supports 64 interrupts Enables tail-chaining Supports priority grouping Level-sensitive and pulse-sensitive interruptsARM® Memory Protection Unit (ARM® MPU) Supports ARMv7 Protected Memory System Architecture model 8 protect regions (0-7 priority) Access permissions Generates a fault if restricted area of memory is accessed Use to enforce privilege rules, to separate processes, and to enforce access rules
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Nested Vector Interrupt
Controller
Flash Patch Breakpoint
(FPB)
Instrumentation Trace Macrocell
(ITM)
ROM Table
Cortex®-M4 Core + Floating Point Unit
Data Watchpoint and Trace
(DWT)
ARM® Cortex®-M4 Processor
ARM® Memory Protection Unit(ARM® MPU)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 55
ARM® Cortex®-M0+ NVIC (1)
Nested Vector Interrupt Controller (NVIC) Provides configurable interrupt handling abilities to the processor Supports up to 32 external interrupts Dedicated non-maskable interrupt (NMI) pin Level-sensitive and pulse-sensitive interrupts Vector table can be relocated.
Macro Trace Buffer(MTB)
ROM Table
Cortex®-M0+ Core
Breakpoint andWatch Unit
Nested Vector Interrupt
Controller(NVIC)
Debug Access Port (DAP)Serial Wire
Debug (SWD)
ARM® Cortex®-M0+ Processor
Debugger Interface
ARM® Cortex®-M0+ CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 56
ARM® Cortex®-M4 Debug (7,5)
JTAG and Serial Wire Debug (SWD) port Uses CoreSight™ Debug Access Port (DAP) Provides debug access to all memory and registers in the system, memory-mapped devices,
internal core, and debug control registers JTAG interface maximum speed: 25 MHz SWD interface maximum speed: 25 MHzFlash patch and breakpoint Use to implement hardware breakpoints Patches code and data from code space to system space 6 instruction comparators 2 literal comparators
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Nested Vector Interrupt
Controller
Instrumentation Trace Macrocell
(ITM)
Trace Port Interface Unit
(TPIU)
Data Watchpoint and Trace
(DWT)
Cortex®-M4 Core + Floating Point Unit
Flash Patch Breakpoint
(FPB)
ARM® Cortex®-M4 Processor
ARM® Memory Protection Unit(ARM® MPU)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 57
ARM® Cortex®-M4 Debug (3)
JTAG and Serial Wire Debug (SWD) port Uses CoreSight™ Debug Access Port (DAP) Provides debug access to all memory and registers in the system, memory mapped devices,
internal core, and debug control registers JTAG interface maximum speed: 25 MHz SWD interface maximum speed: 25 MHzFlash patch and breakpoint Use to implement hardware breakpoints Patches code and data from code space to system space 6 instruction comparators 2 literal comparators
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Nested Vector Interrupt
Controller
ROM Table
Flash Patch Breakpoint
(FPB)
Instrumentation Trace Macrocell
(ITM)
Cortex®-M4 Core + Floating Point Unit
Data Watchpoint and Trace
(DWT)
ARM® Cortex®-M4 Processor
ARM® Memory Protection Unit(ARM® MPU)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 58
ARM® Cortex®-M0+ Debug (1)
CoreSight™ Debug Access Port (DAP) Provides a 25-MHz serial wire debug port Full system-level debug accessBreakpoint and Watch Unit Use to implement breakpoints and watchpoints 4 instruction comparators 2 comparators for watchpointsDebug registers Reset control Halt controlCoreSight™ ETB-M0 + Revision: r0p1-00rel0 MTB RAM: 1 KB
Macro Trace Buffer(MTB)
ROM Table
Cortex®-M0+ Core
Breakpoint andWatch Unit
Nested Vector Interrupt
Controller(NVIC)
ARM® Cortex®-M0+ Processor
Debugger Interface
Debug Access Port (DAP)Serial Wire
Debug (SWD)
ARM® Cortex®-M0+ CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 59
ARM® Cortex®-M4 Trace (7,5)
CoreSight™ Embedded Trace Macrocell and Buffer (ETM and ETB) Useful for instruction trace CoreSight™ ETM™-M4 Revision: r0p1-00rel0 ARM ETM architecture version 3.5 Embedded trace buffer (ETB) ETB RAM: 2 KBTrace Port Interface Unit (TPIU) Bridge ETM and ITM to a data stream required by a trace port analyzer (TPA) Can output data in 4-bit serial wire output formatData Watchpoint Trace (DWT) Use to implement watchpoints, data tracing, and system profiling 4 comparators for watchpoints and triggersCoreSight™ Instrumentation Trace Macrocell (ITM) Supports printf style debugging to trace operating systems Generates diagnostic system information
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Nested Vector Interrupt
Controller
Trace Port Interface Unit
(TPIU)
Data Watchpoint and Trace
(DWT)
Cortex®-M4 Core + Floating Point Unit
Flash Patch Breakpoint
(FPB)
Instrumentation Trace Macrocell
(ITM)
ARM® Cortex®-M4 Processor
ARM® Memory Protection Unit(ARM® MPU)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 60
ARM® Cortex®-M4 Trace (3)
CoreSight™ Embedded Trace Macrocell and Buffer (ETM and ETB) Useful for instruction trace CoreSight™ ETM™-M4 Revision: r0p1-00rel0 ARM ETM architecture version 3.5 Embedded trace buffer (ETB) ETB RAM: 1 KBData Watchpoint Trace (DWT) Use to implement watch points, data tracing and system profiling 4 comparators for watchpoints and triggersCoreSight™ Instrumentation Trace Macrocell (ITM) Supports printf style debugging to trace operating systems Generates diagnostic system information
JTAG, Serial Wire Debug
Port
Embedded Trace
Macrocell and Buffer
(ETM and ETB)
AHB Access Port
Bus Matrix
Nested Vector Interrupt
Controller
Flash Patch Breakpoint
(FPB)
Data Watchpoint and Trace
(DWT)
Instrumentation Trace Macrocell
(ITM)
ROM Table
Cortex®-M4 Core + Floating Point Unit
ARM® Cortex®-M4 Processor
ARM® Memory Protection Unit(ARM® MPU)
ARM® Cortex®-M4 CPU integration
in Synergy MCUs
© 2016 Renesas Electronics Corporation. All rights reserved. 61
Boundary Scan (7,5,3)
Provides a serial IO interface for diagnostic and debugging Sub-blocks internal to the MCU Interconnects external to the MCU Infrastructure integrityComplies with IEEE Standard 1149.1 and IEEE Standard Test Access Port and Boundary-Scan ArchitectureJTAG clock speed: up to 25 MHzSupports various modes Bypass, Extest, Sample/Preload, Clamp, High Z, IDCODE
Simplified implementation of boundary scan
Another Device External Host
Synergy MCU
Digital Logic
Boundary Scan Chain
IO Driver
TCK TMS TDOTDI
TDI
TDI TDO
TDO
IO Pin
Boundary Scan Cell
JTAG Boundary Scan Controller
© 2016 Renesas Electronics Corporation. All rights reserved. 62
Memory
Code Flash
Data Flash
SRAM
Flash Cache
MPUs
Memory Mirror Function
© 2016 Renesas Electronics Corporation. All rights reserved. 63
Code and Data Flash (7)
On-chip code and data flash for storing user applications and data
Programming methods SCI, SWD, USB, and JTAG FACI commands for self-programmingSecurity and protection features ID Code for authentication and connection to debugger, etc. Erase/program/read protection
Memory map of a device with 4 MB Code
Flash and 64 KB Data Flash
Synergy MCUCode and Data Flash0x4011 0000
Co
de
Fla
sh
4 M
B
Block 0 (8 KB)
Block 1 (8 KB)
:
Block 7 (8 KB)
Block 8 (32 KB)
::
Block 133 (32 KB)
Block 0 (64 B)
Block 1 (64 B)
:
Block 1023 (64 B)
Da
ta F
lash
64
K
0x4010 0000
0x0003 FFFF
0x0000 0000
0x0004 0000
0x4010 FFFF
0x0000 FFFF
0x0001 0000
Key parameters for on-chip Code and Data Flash
Parameter Code Flash Data Flash
Maximum Size (KB) 4096 64
Min. Program/Erase Cycles (cycles) 1 K 125 K
Data Retention Period (years) 20 20
Read Cycles 3 @ 240 MHz 7 @ 60 MHz
Minimum Prog. Unit (B) 256 4
Minimum Erasing Unit (KB) 8 or 32 64
Value After Erase 0xFF Undefined
© 2016 Renesas Electronics Corporation. All rights reserved. 64
Code and Data Flash (5)
On-chip code and data flash for storing user applications and data
Programming methods SCI, SWD, USB, and JTAG FACI commands for self-programmingSecurity and protection features ID Code for authentication and connection to debugger, etc. Erase/program/read protection
Synergy MCUCode and Data Flash0x4011 0000
Co
de
Fla
sh
2 M
B
Block 0
Block 1
:
Block 7
Block 8
::
Block m
Block 0
Block 1
:
Block n
64
K
0x4010 0000
0x0001 FFFF
0x0000 0000
0x0002 0000
0x4010 FFFF
Da
ta F
lash
Key parameters for on-chip Code and Data Flash
Parameter Code Flash Data Flash
Maximum Size (KB) 2048 64
Min. Program/Erase Cycles (cycles) TBD TBD
Data Retention Period (years) TBD TBD
Read Cycles TBD TBD
Minimum Prog. Unit (B) TBD TBD
Minimum Erasing Unit (KB) TBD TBD
Value After Erase TBD TBD
Memory map of a device with 2 MB Code
Flash and 64 KB Data Flash
© 2016 Renesas Electronics Corporation. All rights reserved. 65
Code and Data Flash (3)
On-chip code and data flash for storing user application and data
Programming methods SCI, SWD, USB, and JTAG FACI commands for self-programmingSecurity and protection features ID Code for authentication and connection to debugger, etc. Erase/program/read protection
Synergy MCU
Co
de
Fla
sh
1 M
B
Block 0 (2 KB)
Block 1 (2 KB)
:
Block 7 (2 KB)
Block 8 (2 KB)
::
Block 511 (2 KB)
Block 0 (1 KB)
Block 1 (1 KB)
:
Block 15 (1 KB)
16
KB
0x4010 0000
0x0000 0000
0x4010 3FFF
Code and Data Flash0x4010 4000
0x0010 0000
0x000F FFFF
Da
ta F
lash
Key parameters for on-chip Code and Data Flash
Parameter Code Flash Data Flash
Maximum Size (KB) 1024 16
Min. Program/Erase Cycles (cycles) 1 K 100 K
Data Retention Period (years) 20 20
Read Cycles 2 @ 48 MHz 4 @ 48 MHz
Minimum Prog. Unit (B) 8 1
Minimum Erasing Unit (KB) 2 1
Value After Erase 0xFF 0xFF
Memory map of a device with 1 MB Code
Flash and 16 KB Data Flash
© 2016 Renesas Electronics Corporation. All rights reserved. 66
Code and Data Flash (1)
On-chip code and data flash for storing user application and data
Programming methods SCI and SWD FACI commands for self-programmingSecurity and protection features ID Code for authentication and connection to debugger, etc. Erase/program/read protection
Synergy MCU0x4010 1000
Co
de
Fla
sh
12
8 K
B
Block 0 (1 KB)
Block 1 (1 KB)
:
Block 127 (1 KB)
Block 0 (1 KB)
Block 1 (1 KB)
:
Block 3 (1 KB)
4 K
B
0x4010 0000
0x0000 0000
0x4010 0FFF
0x0001 FFFF
0x0002 0000
Code and Data Flash
Da
ta F
lash
Key parameters for on-chip Code and Data Flash
Parameter Code Flash Data Flash
Maximum Size (KB) 128 4
Min. Program/Erase Cycles (cycles) 1 K 100 K
Data Retention Period (years) 20 20
Read Cycles 1 @ 32 MHz 2 @ 32 MHz
Minimum Prog. Unit (B) 4 1
Minimum Erasing Unit (KB) 1 1
Value After Erase 0xFF 0xFF
Memory map of a device with
128 KB Code Flash and 4 KB Data Flash
© 2016 Renesas Electronics Corporation. All rights reserved. 67
SRAM (7,5)
On-chip static RAMSupports no wait read and write accessUp to 640 KB divided in three sections SRAM1: 256 KB SRAM0: 256 KB (includes 32 KB ECCRAM) High Speed RAM: 128 KBParity error checking A parity bit is added to each word at the time of writing Even parity test is performed at the time of reading to detect parity errorsAutomatic error checking and correction (ECC) mechanism Detects 2-bit errors Corrects 1-bit errorNMI generation or reset assertion on error detection Parity error 1-bit ECC error 2-bit ECC error
Memory map of a device with
640 KB SRAM
SRAM
High Speed RAM
(if applicable)
0x0000 0000
FlashEtc.
SRAM1
0x1FFE 0000
0x1FFF FFFF
0x2000 0000
0x2000 7FFF
0x2000 8000
0x2003 FFFF
0x2004 0000
0x2007 FFFF
SRAM0
128 K
B256 K
B
32 K
B
256 K
B
0x1FFD FFFF
ECCRAM
Parity Check
*No wait states are inserted during reading at up to 200 MHz
© 2016 Renesas Electronics Corporation. All rights reserved. 68
SRAM (3)
On-chip static RAMSupports no wait read and write access192 divided in two sections SRAM1: 64 KB SRAM0: 128 KB (includes 16 KB ECCRAM)Parity error checking A parity bit is added to each word at the time of writing Even parity test is performed at the time of reading to detect parity errorsAutomatic error checking and correction (ECC) mechanism Detects 2-bit errors Corrects 1-bit errorNMI generation or reset assertion on error detection Parity error 1-bit ECC error 2-bit ECC error
SRAM
0x0000 0000
FlashEtc.
SRAM1
0x2000 0000
0x2000 3FFF
0x2000 4000
0x2001 FFFF
0x2002 0000
0x2002 FFFF
SRAM0
64 K
B
16 K
B
128 K
B
ECCRAM
Parity Check
Memory map of a device with
192 KB SRAM
© 2016 Renesas Electronics Corporation. All rights reserved. 69
SRAM (1)
On-chip static 16 KB RAMSupports no wait read and write accessParity error checking A parity bit is added to each word at the time of writing Even parity test is performed at the time of reading to detect parity errors
SRAM
0x0000 0000
Flash,etc.
0x2000 0000
0x2000 3FFF
SRAM0
16 K
B
Memory map of a device with
16 KB SRAM
© 2016 Renesas Electronics Corporation. All rights reserved. 70
Flash Cache (7,5,3)
Mechanism to speed up data and instructions read accessUseful at higher system clock frequenciesFrequently used data and instructions are cached in three caches 16 B data (operand and DMA) cache 32 B instruction pre-fetch cache 256 B CPU instruction fetch cacheFlash acceleration is required after 32 MHz and 120 MHz depending on the flash technology
Simplified implementation of Flash Cache
Synergy MCU
Other Bus Masters
Flash
Core
Flash Cache
Bus matrix
32
-bit
Instr
uctio
n
32
-bit
Da
ta
32
-bit
Sys
tem
© 2016 Renesas Electronics Corporation. All rights reserved. 71
Memory Protection Units (MPUs) (7,5,3)
Bus-Master MPUBus Master MPU monitors the addresses of bus master access to the overall address spaceInternal reset or non-maskable interrupts will be generated if access to the protected region is detectedMaster groups Group A: DMA bus Group B: EHER bus* Group C: GPX bus*Number of regions Group A: 32 regions** Group B: 8 regions* Group C: 8 regions*Setting the address where regions start and endSetting to make memory protection effective/ineffective in individual regionsAccess-control information setting for individual regionsRegister can be detected from illegal writing
Simplified implementation of
Bus-Master MPU
Memory Protection Units
Bus Master MPU
Security MPU
Bus Slave MPU
ARM MPU
CPU DMACDTC
EDMAC* GLCDC*
Slave Function 0
Slave Function 1
Slave Function 2
Slave Function 3….
* Available in S7,S5 series. **S3 series has 16 regions
M-MPUGroup B
M-MPUGroup A
M-MPUGroup C
© 2016 Renesas Electronics Corporation. All rights reserved. 72
Memory Protection Units (MPUs) (7,5,3)
Bus-Slave MPUBus Slave MPU checks access to bus slave function (for example, Flash, SRAM)Internal reset or non-maskable interrupts or exception will be generated if access to the protected region is detectedProtect bus master Group A: DMA bus Group B: EHER bus* Group C: GPX bus*Protect slave function Code flash, data flash, SRAM, peripherals, external memory, and external
deviceAccess-control information setting for individual regionsRegister can be detected from illegal writing
Simplified implementation of
Bus-Slave MPU
© 2015 Renesas Electronics Corporation. All rights reserved.
* Available in S7,S5 series.
Memory Protection Units
Bus Master MPU
Security MPU
Bus Slave MPU
ARM MPU
CPU DMACDTC
EDMAC* GLCDC*
Slave Function 0
Slave Function 1
Slave Function 2
Slave Function 3….
S-MPU S-MPU S-MPU S-MPU
© 2016 Renesas Electronics Corporation. All rights reserved. 73
Memory Mirror Function (MMF) (7,5,3)
Maps the desired application codebase address in the flash memory to a virtual address in the memory mirror space (8 MB)Provides mechanism to Map load address of multiple application code images to a common virtual
address Execute multiple versions of the application code in the flashUser application code Resides at different physical addresses in the flash memory Is always developed and linked to run from a virtual address Requires no context of its physical base address and can be stored into
arbitrary flash location at load time
Memory Mirror Function
© 2015 Renesas Electronics Corporation. All rights reserved.
Synergy MCU
0x0000 0000
Flash
0x0003 FFFF
0x027F FFFF
Virtual Address
User’s Code
0x0200 0000
Memory MappingSpace
Application 2
Application 1
BaseAdd1
Boot Code
Virtual Address
BaseAdd2
8 M
B
© 2016 Renesas Electronics Corporation. All rights reserved. 74
Connectivity
Ethernet MAC Controller
Ethernet DMA Controller
Ethernet PTP Controller
CAN SDHI
USBHS USBFS
Serial Communications Interface
QSPI SPI
IIC SSI
Sampling Rate Converter
External Memory Bus
IrDA Interface
© 2016 Renesas Electronics Corporation. All rights reserved. 75
Ethernet MAC Controller (ETHERC) (7)
Two integrated Ethernet MACsIEEE 802.3x-compliant flow controlProvides IEEE 802.3u-compliant Media Independent Interface (MII) and Reduced MII (RMII) for connection with external PHY (optical, twisted wire, etc.) in both ports10 Mbps or 100 Mbps data transfer rateSupports IEEE 1588v2 PTPDedicated Ethernet DMA controller for data transfer without CPU interventionSupports full-duplex and half-duplex transfer modesSupports Magic PacketTM detection and Wake-on-LAN (WOL) functionality Enables remote activation of peripheralsPause frame flow control Automatic transmission Manual transmission Reception
Connecting an external PHY with the Synergy
MCU via MII and RMII interfaces
Mgmt. Data I/O
Mgmt. Data Clk
External Output
Wake On LAN
TX Enable
TX Data1
RX Clk
RX Error
RX Data1
Link Detect
Carrier Sense
RX Data3
RX Data Valid
Collision Detect
TX Data2
TX Data3
TX Error
TX Data0
RX Data0
RX Data2
TX Clk
RM
II
EthernetPort 1
EthernetPort 2
MII
MII
RM
II
PHY and Magnetics
PHY and Magnetics
Synergy MCU
© 2016 Renesas Electronics Corporation. All rights reserved. 76
Ethernet MAC Controller (ETHERC) (5)
Integrated Ethernet MACIEEE 802.3x-compliant flow controlProvides IEEE 802.3u-compliant Media Independent Interface (MII) and Reduced MII (RMII) for connection with external PHY (optical, twisted wire, etc.) in both ports10 Mbps or 100 Mbps data transfer rateSupports IEEE 1588v2 PTPDedicated Ethernet DMA controller for data transfer without CPU interventionSupports full-duplex and half-duplex transfer modesSupports Magic PacketTM detection and Wake-on-LAN (WOL) functionality Enables remote activation of peripheralsPause frame flow control Automatic transmission Manual transmission Reception
Connecting an external PHY with the
Synergy MCU via MII and RMII interfaces
Mgmt. Data I/O
Mgmt. Data Clk
External Output
Wake On LAN
TX Enable
TX Data1
RX Clk
RX Error
RX Data1
Link Detect
Carrier Sense
RX Data3
RX Data Valid
Collision Detect
TX Data2
TX Data3
TX Error
TX Data0
RX Data0
RX Data2
TX Clk
EthernetPort
MII
RM
II
PHY and Magnetics
Synergy MCU
© 2016 Renesas Electronics Corporation. All rights reserved. 77
Ethernet DMA Controller (EDMAC) (7)
3-channel DMA controller for Ethernet 2 channels for Ethernet controllers 1 channel for Ethernet PTP controllerIndependent TX and RX FIFO per channel enable simultaneous use of multiple channelsControls TX and RX buffer management for communication to enable efficient data transmission and reception
Uses information (buffer size, address, TX and RX status) in TX and RX descriptor for data transmission and receptionRound-robin channel priority assignment
Simplified implementation of
Ethernet DMA Controller
Transmission and Reception Modes
Single Buffer Per Frame
Multiple Buffers Per Frame
Synergy MCU
Ethernet PTP Controller
Ethernet MAC Controller 1
Ethernet MAC Controller 0
Ethernet DMA Controller Arbiter
ENET Port 2ENET Port 1
Ethernet DMA Controller 0
PTP Ethernet DMA Controller
Ethernet DMA Controller 1
TX/RXControl
TX
FIF
O
RX
FIF
O
TX/RXControl
TX
FIF
O
RX
FIF
O
TX/RXControl
TX
FIF
O
RX
FIF
O
Internal Main Bus
© 2016 Renesas Electronics Corporation. All rights reserved. 78
Ethernet DMA Controller (EDMAC) (5)
2-channel DMA controller for Ethernet 1 channels for Ethernet controllers 1 channel for Ethernet PTP controllerIndependent TX and RX FIFO per channel enable simultaneous use of multiple channelsControls TX and RX buffer management for communication to enable efficient data transmission and reception
Uses information (buffer size, address, TX and RX status) in TX and RX descriptor for data transmission and receptionRound-robin channel priority assignment
Synergy MCU
Ethernet PTP Controller
Ethernet MAC Controller 0
Ethernet DMA Controller Arbiter
ENET Port
Ethernet DMA Controller 0
PTP Ethernet DMA Controller
TX/RXControl
TX
FIF
O
RX
FIF
O
TX/RXControl
TX
FIF
O
RX
FIF
O
Transmission and Reception Modes
Single Buffer Per Frame
Multiple Buffers Per Frame
Internal Main Bus
Simplified implementation of
Ethernet DMA Controller
© 2016 Renesas Electronics Corporation. All rights reserved. 79
Ethernet PTP Controller (EPTPC) (7)
Provides a synchronization clock for decentralized communication networksPerforms packet analysis and field extraction, and generates PTP packetsComplies with IEEE 1588-2008 v2 Precision Time ProtocolUsed with Ethernet MAC controller and PTP Ethernet DMA controller
Uses packet filtering by MAC address to separate PTP packetsSupports promiscuous modeMultiple interrupt sources
Simplified implementation of the
Ethernet PTP Controller
Clock Devices Supported
End-to-EndTransparent Clock
Peer-to-PeerTransparent Clock
Ordinary Clock
Boundary Clock
Synergy MCU
PTP Ethernet DMA Controller
Ethernet DMA Controller 1
Ethernet DMA Controller 0
Packet Relation Controller Unit
Synchronization Frame Processing
Unit 1
Statistical Time Correction
Algorithm Unit
Ethernet DMA Controller Arbiter
Synchronization Frame Processing
Unit 0
Ethernet PTP Controller
Ethernet MAC Controller 1
Ethernet MAC Controller 0
Internal Main Bus
Ethernet Port 2Ethernet Port 1
© 2016 Renesas Electronics Corporation. All rights reserved. 80
Ethernet PTP Controller (EPTPC) (5)
Provides a synchronization clock for decentralized communication networksPerforms packet analysis and field extraction, and generates PTP packetsComplies with IEEE 1588-2008 v2 Precision Time ProtocolUsed with Ethernet MAC controller and PTP Ethernet DMA controller
Uses packet filtering by MAC address to separate PTP packetsSupports promiscuous modeMultiple interrupt sources
Clock Devices Supported
End-to-EndTransparent Clock
Peer-to-PeerTransparent Clock
Ordinary Clock
Boundary Clock
Synergy MCU
PTP Ethernet DMA Controller
Ethernet DMA Controller 0
Packet Relation Controller Unit
Statistical Time Correction
Algorithm Unit
Ethernet DMA Controller Arbiter
Synchronization Frame Processing
Unit 0
Ethernet Controller 0
Internal Main Bus
Ethernet Port 1
Ethernet PTP Controller
Simplified implementation of the
Ethernet PTP Controller
© 2016 Renesas Electronics Corporation. All rights reserved. 81
USB 2.0 High-Speed Module (USBHS) (7,5)
Integrated USBHS controller and transceiver480 Mbps transfer speedSelf-powered and bus-powered operation
Host mode (HS, FS and LS) Automatic SOF and packet transmission scheduling Programmable intervals for isochronous and interrupt transfersDevice mode (HS and FS) Control transfer stage control function Device state control function SOF interpolation functionCompliant with Battery Charging Class specification Rev 1.2Transfer types Control, bulk, interrupt, isochronousIntegrated buffer memory providing 10 pipesFlexible endpoint assignment
Simplified block diagram of
USB 2.0 High-Speed Module
USB_DP
USB_DM
VBUS
USBID
OVC
REF
Clocking
InterruptController
FIFOUS
B E
ngin
e
PH
Y/T
ran
sce
ive
r
VCC
VSS
AVCC
AVSS
PVSS
Bus Interface
Internal Peripheral Bus
Synergy MCU
USB 2.0 High-Speed Module
USB
Operation modes
Host
Device
On-The-Go
VBUSEN
EXCEN
Control and System Reg.
© 2016 Renesas Electronics Corporation. All rights reserved. 82
USB 2.0 Full-Speed Module (USBFS) (7,5,3,1)
Integrated USBFS controller and transceiverCrystal-less operation*12 Mbps transfer speedSelf-power and bus-powered operation
Host mode Automatic SOF and packet transmission scheduling Programmable intervals for isochronous and interrupt transfersDevice mode Control transfer stage control function Device state control function SOF interpolation functionCompliant with Battery Charging Class specification Rev 1.2***Transfer types Control, bulk, interrupt, isochronousIntegrated buffer memory providing 10 pipes****On-chip pull-up and pull-down resistors for D+ and D- signals
Simplified block diagram of
USB 2.0 Full-Speed Module
© 2015 Renesas Electronics Corporation. All rights reserved.
Operation Modes
Host**
Device
On-The-Go**
* Available in device mode in S1 series only. ** Not available on S1 series. *** Not available on S7,S5 series. ****S1 series has 5 pipes
USB_DP
USB_DM
VBUS
USBID
OVC
REF
Clocking
InterruptController
FIFOUS
B E
ngin
e
PH
Y/T
ran
sce
ive
r
VCC
VSS
Bus Interface
Internal Peripheral Bus
Synergy MCU
USB 2.0 Full-Speed Module
USB
VBUSEN
EXCEN
Control and System Reg.
© 2016 Renesas Electronics Corporation. All rights reserved. 83
Comparison Between USB Modules)
FeaturesUSB2.0 High-Speed
ModuleUSB2.0 Full-Speed Module
Host Speed (Mbps) 480,12, and1.5 12 12 and 1.5 -
Device Speed (Mbps) 480 and 12 12 12 and 1.5 12 and 1.5
On-The-Go Available Available Available -
Communication Data Transfer Type
Control transferBulk transfer
Interrupt transferIsochronous transfer
Control transferBulk transfer
Interrupt transferIsochronous transfer
Control transferBulk transfer
Interrupt transferIsochronous transfer
Control transferBulk transfer
Interrupt transfer
Buffer Memory(no. of pipes)
10(includes control pipe)
10(includes control pipe)
10(includes control pipe)
5(includes control pipe)
Battery charging revision 1.2
Available - Available Available
Clock Recovery - - - Available
External Power Supply(LDO)
- - Available Available
Internal Registers D+/D- line, Pull-up/Pull-down D+/D- line, Pull-up/Pull-down D+/D- line, Pull-up/Pull-down D+/D- line, Pull-up/Pull-down
Available In
© 2016 Renesas Electronics Corporation. All rights reserved. 84
CAN Module
Bus standard for multi-master, message-based protocolISO 11898-1, CAN 2.0A, CAN 2.0B compliantSupports standard (11-bit) and extended ID (29-bit) messaging formats32 mailboxes, 2 mailbox modes Normal mailbox mode: 32 mailboxes FIFO mailbox mode: 24 mailboxesUp to 1 Mbps transmission bit rate8 independent acceptance filters16-bit time stampingError status monitoringMultiple interrupt sources
CAN operation using Synergy MCUs
(as a simple communication gateway)
Additional Modes
Sleep
Listen-only
Loopback
External
Internal
CAN Bus0
Rt
Rt
Synergy MCU
CAN RX/TX
CAN Module 0
TX
RX
DMADTC
CAN Bus1
Rt
Rt
CAN RX/TX
Ethernet MAC
Controller
Ethernet PHY/ Network
CAN Module 1
TX
RX
© 2016 Renesas Electronics Corporation. All rights reserved. 85
SD/MMC Host Interface (SDHI) (7,5,3)
Provides Secure Digital Host Interface (SDHI) and Multi Media Card (MMC) interfaceSDHI Supports 1-bit and 4-bit bus Supports SD, SDHC, SDXC formatsMMC Supports 1-bit, 4-bit and 8-bit MMC bus Supports eMMC 4.51 device access High speed SDR mode availableWrite protect support Command based Switch basedError checking function CRC7 for command and response CRC16 for dataCard detection supportMultiple interrupt requests
Simplified block diagram of the
SD/MMC Host Interface
Synergy MCU
External SD Card
Secure Digital Interface
HostInterface
INT DMA Interface
SD/MMC Host Interface
Bus
© 2016 Renesas Electronics Corporation. All rights reserved. 86
Serial Communications Interface (SCI) (7,5,3,1)
Combination of 5 independent asynchronous and synchronous serial interface blocks
Bit rate modulationIntegrated noise cancellingMultiple interrupt sourcesEvent Link Controller function output
Functional block diagram of the
Serial Communications Interface
Baud Rate Generator
InternalClock
Smart Card
RX/SCL
TX/SDA
External Clock Input/Output
SS
Module Data Bus Internal Peripheral
Bus
UART
Smart Card
Simple IIC
Simple SPI
Serial Communications Interface
ControlELC
INT
Mo
de
s of O
pera
tion
Simple IIC Mode Single master only Up to 400 kbps transmission rate
Clock Synchronous Mode 8-bit data length only Receive error detection
Asynchronous Mode (UART) Receive error and break detection Multi-processor communication function
Simple SPI Mode 8-bit data length only Overrun error detection
Smart Card Mode ISO/IEC 7816-3 Error processing
Clock Synchronous
© 2016 Renesas Electronics Corporation. All rights reserved. 87
Infrared Data (IrDA) Interface (7,5,3)
Wireless infrared serial communicationIrDA 1.0-compliant encoding and decodingUp to 115200 bps transmission rateRX and TX pins multiplexed with SCITransfer rate controlled through software
IrDA operation using Synergy MCUs
Phase Inverter
RX
TX
PulseDecoder
PulseEncoder
IR Transceiver
RX
TX
SCI/ UART
TX
RX
Synergy MCU
Infrared Data Interface
© 2016 Renesas Electronics Corporation. All rights reserved. 88
Quad Serial Peripheral Interface (QSPI) (7,5,3)
4-bit multiplexed serial interface with greater bandwidth over SPI
8-bit, 16-bit, 24-bit, and 32-bit address widthFaster and easier access to external serial flash, EEPROM, FeRAM 64-MB external QSPI device space Timing adjustment function Supports various ROM/flash read instructions Direct communication functionMultiple interrupt sources
Simplified implementation of QSPI
Protocol
Quad-SPI
Dual-SPI
Extended-SPI
Synergy MCU
Clock Generation
IO1
IO2
IO3
IO4
CLK
SS
BusInterface
Unit
Internal Bus
Signal Generation
Port Control
Registers & Control
QSPI
RX
TX
© 2016 Renesas Electronics Corporation. All rights reserved. 89
Serial Peripheral Interface (SPI) (7,5,3,1)
Legacy serial communication interfaceConfiguration Multi-master Single-master Slave 3-Wire 4-WireModes of operation Full-duplex Transmit only LoopbackUp to 30 Mbps data transmission rate128-bit RX/TX buffersConfigurable TX word size from 8 to 32 bitsError detection Mode fault Overrun ParityMultiple interrupt sourcesEvent Link Controller function output
Multi-master, multi-slave SPI operation
using Synergy MCUs
SS0
CLKMOSIMISO
SS1SS2SS3
GPIO
SS0
CLKMOSIMISO
SS1SS2SS3GPIO
CS
CLKMOSIMISO
CS
CLKMOSIMISO
CS
CLKMOSIMISO
SPIMaster 1
SPISlave 1
SPISlave 2
SPISlave 3
SPIMaster 0
Synergy MCU
Synergy MCU
© 2016 Renesas Electronics Corporation. All rights reserved. 90
I2C Bus Interface (IIC) (7,5,3,1)
Multi-master, serial, single-ended busConfiguration Legacy IIC System Management Bus (SMBus) v2.0Modes of operation Master TX/RX Slave TX/RXUp to 1 Mbps data transmission rate7-bit or/and 10-bit address formatsAddress match detection Slave General call Device ID SMBus host addressIntegrated noise cancellingAutomatic clock low-holdBus hanging timeoutMultiple interrupt sourcesEvent Link Controller function output
IIC operation using Synergy MCUs
SDA
SCL
Master 0
SDA
SCL
Master 1
VDD (5 V for SMBus,3.3 V for IIC)
Synergy MCU
VDD (5 V for SMBus,3.3 V for IIC)
SDA
SCL
Slave 0
SDA
SCL
Slave 1
© 2016 Renesas Electronics Corporation. All rights reserved. 91
Serial Sound Interface (SSI) (7,5,3)
Serial interface to transfer PCM/audio dataSupports non-compressed serial audio streams Slave receiver Slave transmitter Slave transceiver Master receiver Master transmitter Master transceiverClock master and slave modes1 MHz to 50 MHz oversampling clockIncludes 8-stage FIFO buffers in TX and TRSupports interrupt and DMA driven data reception and transmission
SSI operation using Synergy MCUs
Master/Oversampling
Clock
SSI0
SCK
WS
TX
RX
SSI1
SCK
WS
DATA
Module Data Bus
Interrupts
Synergy MCU
AudioCodec
Audio Codec
© 2016 Renesas Electronics Corporation. All rights reserved. 92
Sampling Rate Converter (SRC) (7,5)
Converts the sampling rate of data produced by various decoders (for example, WMA, MP3, or AAC)16-bit data size for stereo and monaural dataIndependent input and output FIFOsSelectable sampling rate:
Processing capacity: 7.7 µs (max) sample output interval80 dB SNRTwo DMA transfer sourcesMultiple interrupt sources
Simplified implementation of the
Sampling Rate Converter
Synergy MCU
Co
eff
icie
nts
Peripheral Bus
Inp
ut F
IFO
Memory
Ou
tpu
t F
IFO
Sta
tus
an
d
Co
ntr
ol
FIR Filter
INT
Sampling Rate Converter
Main Bus
Sampling Rates
Input (KHz)
8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48
Output (KHz)
8, 16, 32, 44.1, 48
© 2016 Renesas Electronics Corporation. All rights reserved. 93
External Memory Bus (7,5,3)
Allows MCU bus master access to external slave memories and peripheralsArbitrates requests for bus mastership on external address space and external bus control registers on the CPU bus and other bus mastersUp to 120 MHz external bus speedSupports division of external address space into 8 CS areas and an SDRAM area
CS area controller Configurable bus width, 8 or 16 bits Up to 15 cycles for read and write recovery CS area up to 16 MBSDRAM area controller Up to 120 MHz burst transfers Self-refresh and auto-refresh selection SDRAM area up to 64 MB
Interfacing an external memory with the
Synergy MCU using the External Memory Bus
External Bus Controller
CS Area Controller
SDRAM Area Controller
Synergy MCU
External Bus Controller
External Master Bus
External Bus Interface Unit
Bus Matrix
MPU
Core
Peripheral Bus
System Bus
DMA Bus
External Memory
© 2016 Renesas Electronics Corporation. All rights reserved. 94
Analog
PGA
14-Bit A/D Converter
12-Bit D/A Converter
Low-Power Analog Comparator
OPAMP
Temperature Sensor*
High-Speed AnalogComparator
12-Bit A/D Converter
© 2016 Renesas Electronics Corporation. All rights reserved. 95
14-Bit A/D Converter (ADC14) (1,3)
14-bit resolution, 1.4-Msps, SAR ADCInputs Up to 28 external multiplexed analog input channels Internal temperature sensor Internal reference voltage
Multiple trigger sources Internal: ELC (PWM, timer, etc.) External: (via ELC)Built-in ADC Diagnostics Hardware averaging/oversamplingMultiple interrupt sourcesEvent Link Controller function output
Sa
mp
ling M
od
es
Group Scan AD conversion is performed one by one only on the input channels in the group
Continuous Scan AD conversion is performed continuously on the input channels
Single Scan AD conversion is performed only once on the input channels
Int.System
Bus
ELC
ELCTRIG
INT
AINx
Bu
ffer
Mu
x
VREFH
VREFL
AVCC
AVSS
Voltage Reference
andBand Gap
Status and
Control
Up to28
Temp. Sensor
ADC
14-Bit A/D Converter
Power Generator(for Self-Diagnosis)
Simplified block diagram of the
14-Bit A/D Converter
© 2016 Renesas Electronics Corporation. All rights reserved. 96
12-Bit A/D Converter (ADC12) (7,5)
23 (max.) external analog input channels12-bit resolution, 2.5-MSPS, SAR ADCInputs Multiplexed analog input channels Internal temperature sensor Internal reference voltage
Multiple trigger sources Internal: ELC (PWM, timer, etc.) External: (via ELC)Built-in ADC Diagnostics Hardware averaging/oversamplingMultiple interrupt sourcesEvent Link Controller function output
Int.System
Bus
ELC
ELCTRIG
INT
AINx
AINx Bu
ffer
Mu
x
VREFH
VREFL
AVCC
AVSS
Voltage Reference
andBand Gap
Status and
Control
10
3PGA
Sa
mp
ling M
od
es
Group Scan AD conversion is performed one by one only on the input channels in the group
Continuous Scan AD conversion is performed continuously on the input channels
Single Scan AD conversion is performed only once on the input channels
Temp. Sensor
ADC
12-Bit A/D Converter
Power Generator(for Self-Diagnosis)
Simplified block diagram of the
12-Bit A/D Converter
© 2016 Renesas Electronics Corporation. All rights reserved.
Features 14-Bit A/D Converter 12-Bit A/D Converter
Max. No. of Input Channels 28 18 13 (Unit0), 12 (Unit1) TBD
A/D Conversion Method Successive approximation method Successive approximation method
Resolution (bits)14 (default)
Can be selected between 12 and 1412 (default)
Can be selected between 8, 10, and 12
Conversion Time (μs/ channel) 0.7 0.4 TBD
Maximum A/D Conversion Clock (MHz)
PCLKB = 48PCLKC = 64
PCLKB = 32PCLKC= 64
PCLKB = 60PCLKC = 60
TBD
Modes of OperationSingle scan mode
Continuous scan modeGroup scan mode
Single scan modeContinuous scan mode
Group scan mode
A/D Conversion Start TriggersSoftware trigger
Asynchronous triggerFrom Event Link Controller
Software triggerAsynchronous trigger
From Event Link Controller
Channel-Dedicated Sample and Hold Circuit
- Available
Programmable Gain Amplifier - Available
ADC Diagnostics Available Available
Available in
97
Comparison Between A/D Converters (7,3,5,1)
© 2016 Renesas Electronics Corporation. All rights reserved. 98
12-Bit D/A Converter (DAC12) (7,5,3,1)
12-bit resolutionIntegrated output amplifierReference voltage inputs Internal External16-bit R/W data registersCan be operated in-sync or out-of-sync with ADCOutput retention in low power modesEvent Link Controller function output
Simplified block diagram of the
12-Bit D/A Converter
12-Bit D/A Converter
Status and Control
ELC Input
VREFH
VREFL
AVCC
AVSS
Voltage Reference
andBand Gap
DAC
Amp Da
ta R
egis
ter
Mu
xData Register
Internal Main Bus
© 2016 Renesas Electronics Corporation. All rights reserved. 99
High-Speed Analog Comparator (ACMPHS) (7,5)
Compares a test voltage with a reference voltage and provides a digital outputAnalog input voltage Output of DAC, input from ADC, output of PGA*, and internal VREF**Reference voltage Output of DAC, input from ADC, and internal VREFIntegrated noise filter Selectable sampling frequencyMultiple interrupt sourcesEvent Link Controller function output
Simplified block diagram of the High-
Speed Analog Comparator
VCOUT
Synergy MCU
Control
Int. VREF
DAC
IVR
EF
IVC
MP
-
+
ELCINT
Mu
xM
ux
No
ise
Filt
er
High-Speed Analog Comparator
PGA
CMPOUT
Digital Output
ReferenceVoltage
+
-
Analog comparator
* Available on S7,S5 series only. ** Available on S3 series only
Analog inputVoltage
© 2016 Renesas Electronics Corporation. All rights reserved. 100
Low-Power Analog Comparator (ACMPLP) (1,3)
Compares a test voltage with a reference voltage and provides a digital outputAnalog input voltage Input from CMPIN pinReference voltage Input from CMPREF pin, Internal reference voltageIntegrated noise filter Selectable sampling frequencyMultiple interrupt sourcesEvent Link Controller function output
Simplified block diagram of the
Low-Power Analog Comparator
Analog inputVoltage
Digital Output
ReferenceVoltage
+
-
Analog comparator
VCOUT
Synergy MCU
Control
Int. VREF
CM
P
RE
FC
MP
IN
-
+
ELCINT
Mu
x
No
ise
Filt
er
Low-Power Analog Comparator
CMPOUT
© 2016 Renesas Electronics Corporation. All rights reserved.
FeaturesHigh-Speed Analog
ComparatorLow-Power Analog
Comparator
Number of Channels 6 TBD 2 2
Analog Input VoltageOutput of internal PGA
Output of internal D/A converterInput of internal A/D converter
Output of internal D/A converterInput of internal A/D converter
Internal reference voltage (Vref)Input of CMPIN pin
Reference VoltageInternal reference voltage (Vref)
Output from internal D/A converterInput from internal A/D converter
Output from internal D/A converterInput from internal A/D converterInternal reference voltage (Vref)
Internal reference voltage Input of CMPREF pin
Window Mode - Available
Event Link Output Available Available
Output Delay Time (ns) 50 5000*
Operating Current (μA) 70 2*
Available In
101
Comparison Between Analog Comparators
* At low speed mode
© 2016 Renesas Electronics Corporation. All rights reserved. 102
Programmable Gain Amplifier (PGA) (7,5)
Integrated programmable gain amplifier with differential inputsAmplifies analog input signals to enable conversions using the ADC Biases differential input signals with the reference voltage generated by the on-chip DAC and then amplifies them Selectable bias voltage (AVCC*0.5 or AVCC*0.6)
Gain error = 1 @ gain 4.00Offset error = 8 mVUseful in data acquisition, signal conditioning, and instrumentation applications
Simplified implementation of
Programmable Gain Amplifier
Mo
de
s
Single Input Mode Gain can be selected from one of 16 values. 2, 2.5, 2.667, 2.857, 3.077, 3.333, 3.636, 4, 4.444, 5, 5.714, 6.667, 8, 10, 13.33
Differential Input Mode Gain can be selected from one of the four values. 1.5, 2.333, 4, 5.667
Synergy MCU
Dm
ux
Programmable Gain Amplifier
PGA
AINx
PGAVSSy
+
-
Inverting Input
PGA Control
Registers
ADC
CMP
© 2016 Renesas Electronics Corporation. All rights reserved. 103
Operational Amplifier (OPAMP) (1,3)
Integrated small signal operational amplifier with a differential input pairOp-amp’s output can be used as input to the analog comparator or the ADCSupports high-speed and low-speed operationActivated by the asynchronous timer and de-activated by the ADC conversion end trigger
Simplified block diagram of the
Operational Amplifier
Synergy MCU
ADC Conversion End Trigger
Dm
ux
ADC
OPAMPActivation/ Stop
Control and Monitor
Cmp
Operational Amplifier
OPAMP
AMP+
AMP-
AMPO
-
+
Timer Trigger
Activation Trigger
Internal Main Bus
© 2016 Renesas Electronics Corporation. All rights reserved. 104
Temperature Sensor (7,5)
Outputs a voltage directly proportional to the die temperatureUsed to determine and monitor die temperature for reliable operation of the deviceThe output voltage is provided to the ADC±1°C accuracy over the operating range4.1 mV/°C temperature gradientFairly linear relationship between the die temperature and output voltage
Te
mp
era
ture
De
term
inatio
n
Two Point Method Calculate temperature gradient for your device to eliminate error due to variation
induced from device to device. m = (v2 - v1) / (t2 - t1) t = (v - 1157.5) / m where(v1, t1) and (v2, t2): voltage and temperature measured at two experimental points,m: calculated temperature gradient,t: predicted die temperature,v: output voltage of temperature sensor.
Slope Method Use pre-calculated temperature gradient. t = (v - 1157.5) / 4.1wheret: predicted die temperature,v: output voltage of temperature sensor.
Ou
tpu
t V
olta
ge
(m
V)
-40Die Temperature (°C)
105
99
3.5
15
88
4.1 mV/°C
(v1, t1)
(v2, t2)
25
(v, t)
12
60
Temperature Sensor
ADC
Register and
Control
Bus Interface
Internal Main Bus
Synergy MCU
Temperature Sensor
Simplified block diagram and characteristics
of the Temperature Sensor
© 2016 Renesas Electronics Corporation. All rights reserved. 105
Temperature Sensor (1,3)
Outputs a voltage inversely proportional to the die temperatureUsed to determine and monitor die temperature for reliable operation of the deviceThe output voltage is provided to the ADC±1°C accuracy over operating range-3.65 mV/°C temperature gradientFairly linear relationship between the die temperature and the output voltage
Simplified block diagram and characteristics
of the Temperature Sensor
Ou
tpu
t V
olta
ge
(m
V)
-40Die Temperature (°C)
105
75
8
-3.65 mV/°C
(v1, t1)
(v2, t2)
25
(v, t)
12
60
Te
mp
era
ture
De
term
inatio
n
Two Point Method Calculate temperature gradient for your device to eliminate error due to variation
induced from device to device. m = (v2 - v1) / (t2 - t1) t = (1141.25 - v) / m where(v1, t1) and (v2, t2): voltage and temperature measured at two experimental points,m: calculated temperature gradient,t: predicted die temperature,v: output voltage of temperature sensor.
Slope Method Use pre-calculated temperature gradient. t = (1141.25 – v) / 3.65wheret: predicted die temperature,v: output voltage of temperature sensor.
12
87
.25
Temperature Sensor
ADC
Register and
Control
Bus Interface
Internal Main Bus
Synergy MCU
Temperature Sensor
© 2016 Renesas Electronics Corporation. All rights reserved. 106
System & Power Management
DMA Controller
Data Transfer Controller
Event Link Controller
Low Power Modes
Switching Regulator
Multiple Clocks
Port Function Select
RTC
SysTick
© 2016 Renesas Electronics Corporation. All rights reserved. 107
SysTick (7,5,3,1)
24-bit, decrementing, clear-on-write, reload-on-zero timerIntegrated into the NVICClock source Processor’s clock from main oscillator Low-Speed On-Chip Oscillator (32.788 kHz)Flexible control mechanismUse for System heartbeat for RTOS System task-scheduling using a periodic SysTick interrupt Dynamic clock management Real-time interval measurement Typical counter/general timer
Simplified implementation of
SysTick timer
Synergy MCU
Reload
0x10 0000
Current
0x10 0000
0x00 0000
Processor’s Clock
LOCO 32.768 kHz
Clock Select
ARM® Cortex® Core
© 2016 Renesas Electronics Corporation. All rights reserved. 108
Clock Management (7)
Multiple clock sources enable flexible operation and optimization of devices across a variety of power and performance points
Clo
ck G
en
era
tion
So
urc
es
Main Clock Oscillator 8 to 24 MHz resonator frequency Up to 24 MHz external clock frequency Drive capability switching Automatic clock switching upon oscillation stop detection
Sub-Clock Oscillator Requires 32.768 kHz external crystal Drive capability switching
PLL 8 to 24 MHz input frequency 120 to 240 MHz output frequency
On-Chip Oscillator High-speed: 16, 18, 20 MHz Middle-speed: 8 MHz Low-speed:32.768 kHz
Independent Watchdog Timer Oscillator Dedicated for watchdog timer operation 15 kHz
External Debugging Clock For JTAG, SWD Up to 25 MHz
PLL
Sub Clock Osc.
Main Clock Osc.
Independent Watchdog Osc.
Synergy MCU
Clo
ck D
ivid
er,
Multi
ple
xer
and C
ontr
ol
CAN
RTC
Other Peripherals
SysTick
CAC
External Bus Ctrl.
SDRAM
ADC, 16-bit Timers
Flash
IWDT
JTAG, SWDTCK
XTALM0
XTALS0
XTALS0
XTALM1
High-speed On-chip Osc.
Middle-speed On-chip Osc.
Low-speed On-chip Osc.
Oscillator Stop Detection
CPU, DMAC, SRAM, Flash
USBFS and HS
Clock distribution tree in the
Synergy MCU
© 2016 Renesas Electronics Corporation. All rights reserved. 109
Clock Management (5)
Multiple clock sources enable flexible operation and optimization of devices across a variety of power and performance points
Clo
ck G
en
era
tion
So
urc
es
Main Clock Oscillator 8 to 24 MHz resonator frequency Up to 24 MHz external clock frequency Drive capability switching Automatic clock switching upon oscillation stop detection
Sub-Clock Oscillator Requires 32.768 kHz external crystal Drive capability switching
PLL 8 to 24 MHz input frequency
On-Chip Oscillator High-speed: 16, 18, 20 MHz Middle-speed: 8 MHz Low-speed:32.768 kHz
Independent Watchdog Timer Oscillator Dedicated for watchdog timer operation 15 kHz
External Debugging Clock For JTAG, SWD Up to 25 MHz
PLL
Sub Clock Osc.
Main Clock Osc.
Independent Watchdog Osc.
Synergy MCU
Clo
ck D
ivid
er,
Multi
ple
xer
and C
ontr
ol
CAN
RTC
Other Peripherals
SysTick
CAC
External Bus Ctrl.
SDRAM
ADC, 16-bit Timers
Flash
IWDT
JTAG, SWDTCK
XTALM0
XTALS0
XTALS0
XTALM1
High-speed On-chip Osc.
Middle-speed On-chip Osc.
Low-speed On-chip Osc.
Oscillator Stop Detection
CPU, DMAC, SRAM, Flash
USBFS and HS
Clock distribution tree in the
Synergy MCU
© 2016 Renesas Electronics Corporation. All rights reserved. 110
Clock Management (3)
Multiple clock sources enable flexible operation and optimization of devices across a variety of power and performance points
Clo
ck G
en
era
tion
So
urc
es
Main Clock Oscillator 1 to 20 MHz resonator frequency Up to 20 MHz external clock frequency Drive capability switching Automatic clock switching upon oscillation stop detection
Sub-Clock Oscillator Requires 32.768 kHz external crystal Drive capability switching
PLL 4 to 12.5 MHz input frequency 24 to 64 MHz output frequency
On-Chip Oscillator High-speed: 24, 32, 48, 64 MHz Middle-speed: 8 MHz Low-speed:32.768 kHz
Independent Watchdog Timer Oscillator Dedicated for watchdog timer operation 15 kHz
External Debugging Clock For JTAG, SWD Up to 25 MHz
PLL
Sub Clock Osc.
Main Clock Osc.
Independent Watchdog Osc.
Synergy MCU
Clo
ck D
ivid
er,
Multi
ple
xer
and C
ontr
ol
CAN
RTC
Other Peripherals
SysTick
CAC
External Bus Ctrl.
ADC, 16-bit Timers
Flash
IWDT
JTAG, SWDTCK
XTALM0
XTALS0
XTALS0
XTALM1
High-speed On-chip Osc.
Middle-speed On-chip Osc.
Low-speed On-chip Osc.
Oscillator Stop Detection
CPU, DMAC, SRAM, Flash
USBFS
Clock distribution tree in the
Synergy MCU
© 2016 Renesas Electronics Corporation. All rights reserved. 111
Clock Management (1)
Multiple clock sources enable flexible operation and optimization of devices across a variety of power and performance points
Clock distribution tree in the
Synergy MCU
Clo
ck G
en
era
tion
So
urc
es
Main Clock Oscillator 1 to 20 MHz resonator frequency Up to 20 MHz external clock frequency Drive capability switching Automatic clock switching upon oscillation stop detection
Sub-Clock Oscillator Requires 32.768 kHz external crystal Drive capability switching
On-Chip Oscillator High-speed: 24, 32, 48, 64 MHz Middle-speed: 8 MHz Low-speed:32.768 kHz
Independent Watchdog Timer Oscillator Dedicated for watchdog timer operation 15 kHz
External Debugging Clock For SWD Up to 25 MHz
Sub Clock Osc.
Main Clock Osc.
Independent Watchdog Osc.
Synergy MCU
Clo
ck D
ivid
er,
Multi
ple
xer
and C
ontr
ol
CAN
RTC
Other Peripherals
SysTick
CAC
ADC, 16-bit Timers
Flash
IWDT
SWDTCK
XTALM0
XTALS0
XTALS0
XTALM1
High-speed On-chip Osc.
Middle-speed On-chip Osc.
Low-speed On-chip Osc.
Oscillator Stop Detection
CPU, DMAC, SRAM, Flash
USBFS
© 2016 Renesas Electronics Corporation. All rights reserved. 112
Data Transfer Controller (DTC) (7,5,3,1)
Transfers data between memory and peripherals without CPU interventionDTC is activated by peripheral interrupts
Data transfer unit size: 1 byte (8 bits), 1 word (16 bits), 1 longword (32 bits)1 to 256 data units (word) per blockSupports chained transfers and sophisticated data scatter/gatheringInterrupt generation upon transfer completionEvent Link Controller function output
Simplified implementation of the
Data Transfer Controller
Mo
des
of T
ran
sfe
r
Block Transfer Mode One block data transfer per activation Max. block size = 1 KB
Repeat Transfer Mode One data transfer per transfer request Max. no. of repeat t/f: 256 Max. t/f data size = 256 x 32 bit = 1 KB
Normal Transfer Mode One data transfer per activation
Synergy MCU
Inte
rrupt an
d E
ven
t Lin
k C
ontr
olle
r
Flash
Data Transfer Controller
RAM
Bus Interface
DMA Controller
NVICCore
DMA Bus
Inte
rna
l Periph
era
l Bu
s
Activation and
Response Control
DTC Registers
Ext. Bus Controller
© 2016 Renesas Electronics Corporation. All rights reserved. 113
DMA Controller (DMAC) (7,5,3,1)
Allows data transfer without CPU interventionUp to 8 independent channels with pre-assigned priority8, 16, and 32 bits per wordMaximum 64 M words per data transfer
Multiple interrupt outputs to CPU or DTC upon transfer completionInterrupt generation upon completion of transfer
Simplified implementation of the
DMA Controller
Synergy MCU
Inte
rrupt an
d E
ven
t Lin
k C
ontr
olle
r
DMA Core
Flash
DMA Controller
RAM
Bus Interface
DMA Bus
Inte
rnal P
eriph
era
l Bu
s
Mo
de
s o
f T
ran
sfe
r
Block Transfer Mode One block data transfer per activation Max. block capacity = 1024 (1 K words) Max. block transfer = 64 K blocks (that is 64 M words)
Repeat Transfer Mode One data transfer per transfer request Repeat size: 1024 (1 K words)
Normal Transfer Mode One data transfer per activation Free running mode supported
Ext. Bus Controller
Activation and
Response Control
DMARegisters
© 2016 Renesas Electronics Corporation. All rights reserved. 114
Event Link Controller (ELC) (7,5,3,1)
Allows direct interaction between different modules without CPU interventionRoutes source events generated by a peripheral to event inputs on other peripheralsEvent signal can activate a peripheral for the desired operation Start/stop/clear timer, up/down counting Start ADC and DAC conversion Start cap touch measurement Start DMA/DTC transfer Issue interrupts to the CPU Change state of GPIOsMost peripherals generate event signals
Simplified implementation of the
Event Link Controller
Synergy MCU
Event Link
Controller
DMAC
Timers
CTSU
ADC12/14
GPIO
DAC12
AGT SDHI
CAC MOSC
CAN QSPI
ACMP RTC
DOC SCI
DTC SPI
FCU SRC
IIC SSI
JPEG Codec
VBAT
LVD WDT
USB (FS, HS)
PDC
DRW
Ethernet MAC Controller
Peripheral classification based on event signals
Peripherals
Event Link Controller
Only GenerateEvent Signals
Only AcceptEvent Signals
Generate and Accept Event Signals
Event Signals
Internal Bus
© 2016 Renesas Electronics Corporation. All rights reserved. 115
Low Power Modes (7,5,3,1)
Low power modes provide operational flexibility which can dramatically reduce current consumptionIndependent wake-up signals for data acquisition and data transmission peripheralsAllow operation of a peripheral while keeping the CPU and other peripherals disabledData and state retention
Mode of Operation
Core Flash SRAMRTC, AGT, Vbatt, LVD
Other Peripherals
IO Pins Snooze
Normal Operating Selectable Selectable Selectable Selectable Selectable NA
Sleep Clock Gated Selectable Selectable Selectable Selectable Selectable NA
Software Standby
Clock GatedData
RetainedData
RetainedSelectable
State Retained
State Retained
Available
Deep Software Standby
Powered Off Powered Off Powered Off Selectable Powered OffState
RetainedNA
Comparison among various modes of operation Typical current consumption in various modes of operation (target values)
Mode of Operation
Normal (mA) 41 TBD 15.8 3.8
Sleep (mA) 23 TBD 6.8 1.9
Software Standby (µA)
2000 TBD 1.7 0.8
Deep Software
Standby (µA)4.5 TBD NA NA
Po
we
r C
onsum
ptio
n
Throughput
Normal Mode
Sleep Mode
Deep Software Standby Mode
Software Standby Mode
© 2016 Renesas Electronics Corporation. All rights reserved. 116
Low Power Modes (7)
Transition between variousmodes of operation
Po
we
r C
on
sum
ptio
n
Throughput
Mode of Operation →Normal Sleep
Software Standby
Deep Software Standby
Test Conditions ↓
Current Consumption (mA) 41 23 2 0.0045
VCC (V) 3.3 3.3 3.3 3.3
Vbatt (V) 3.3 3.3 3.3 3.3
System Frequency (MHz) 240 240 NA NA
Code While (1) NA NA NA
Systems State
CPU Operating Clock Gated Clock Gated Power Off
Flash Selectable Selectable Data Retained Power Off
SRAM Selectable Selectable Data Retained Power Off
RTC, LVD, OSC Selectable Selectable Disabled Disabled
Other Peripherals Disabled Disabled Retained Power Off
Current consumption (target, typical) andtest conditions for various modes of operation
Deep Software Standby(4.5 µA)
Normal(41 mA)
Sleep(23 mA)
300 μs**
*ICLK=60 MHz** wake up by MOCO
Reset
0.2 μs*
Snooze
Software Standby(2 mA)
© 2016 Renesas Electronics Corporation. All rights reserved. 117
Low Power Modes (5)
Transition between variousmodes of operation
Current consumption (target, typical) andtest conditions for various modes of operation
Deep Software Standby
Normal
Sleep
Snooze
Reset
Po
we
r C
on
sum
ptio
n
Throughput
Software Standby
Mode of Operation →Normal Sleep
Software Standby
Deep Software Standby
Test Conditions ↓
Current Consumption (mA) TBD TBD TBD TBD
VCC (V) TBD TBD TBD TBD
Vbatt (V) TBD TBD TBD TBD
System Frequency (MHz) TBD TBD NA NA
Code While (1) NA NA NA
Systems State
CPU Operating Clock Gated Clock Gated Power Off
Flash Selectable Selectable Data Retained Power Off
SRAM Selectable Selectable Data Retained Power Off
RTC, LVD, OSC Selectable Selectable Disabled Disabled
Other Peripherals Disabled Disabled Retained Power Off
© 2016 Renesas Electronics Corporation. All rights reserved. 118
Low Power Modes (3)
Transition between variousmodes of operation
Mode of Operation →Normal Sleep
Software Standby
Test Conditions ↓
Current Consumption (mA) 15.8 6.8 0.0017
VCC (V) 3.3 3.3 3.3
Vbatt (V) 3.3 3.3 3.3
System Frequency (MHz) 48 48 NA
Code While (1) NA NA
Systems State
CPU Operating Clock Gated Clock Gated
Flash Selectable Data Retained Data Retained
SRAM Data Retained Data Retained Data Retained
RTC, LVD, OSC Disabled Disabled Selectable
Other Peripherals Disabled Disabled Retained
Current consumption (target, typical) andtest conditions for various modes of operation
Normal(15.8 mA)
Sleep(6.8 mA)
5.5 μs**
*ICLK=32 MHz** wake up by MOCO
0.38 μs*
Po
we
r C
on
sum
ptio
n
Throughput
Snooze
Software Standby(1.7 μA)
© 2016 Renesas Electronics Corporation. All rights reserved. 119
Low Power Modes (1)
Transition between variousmodes of operation
Current consumption (target, typical) andtest conditions for various modes of operation
Mode of Operation →Normal Sleep
Software Standby
Test Conditions ↓
Current Consumption (mA) 3.8 1.9 0.0008
VCC (V) 3.3 3.3 3.3
Vbatt (V) NA NA NA
System Frequency (MHz) 32 32 NA
Code While (1) NA NA
Systems State
CPU Operating Clock Gated Clock Gated
Flash Selectable Data Retained Data Retained
SRAM Data Retained Data Retained Data Retained
RTC, LVD, OSC Disabled Disabled Selectable
Other Peripherals Disabled Disabled Retained
Normal(3.8 mA)
Sleep(1.9 mA)
5.5 μs**
*ICLK=32 MHz** wake up by MOCO
0.38 μs*
In Bus 7 state,ICC=2.46mA @ 32 MHz77 μA/MHz
Po
we
r C
on
sum
ptio
n
Throughput
Snooze
Software Standby(0.8 μA)
© 2016 Renesas Electronics Corporation. All rights reserved. 120
Port Function Select (PFS) (7,5,3,1)
Controls routing and assignment of multiple digital signals from different peripherals to different IO pinsMost pins* are multiplexed among different peripherals; that is, many peripherals have their signals mapped to different pin groupsProvides design flexibility to help simplify PCB layout and routing to optimize system performanceCan enable easier migration to different MCU products within the same product family.
Signal routing and peripheral mapping
using the Port Function Select
Interrupt RTC
Mu
x 1
Mu
x 2
IO Pin 4
IO Pin 3
IO Pin 2
IO Pin 1
Synergy MCU
Port Function Select
Mu
x 3
Mu
x 4
Ground
Interrupt
GPIO
RSPI
Power
IIC
* Except power, clock, and analog signals** Conceptual demonstration only. Please refer to the product documentation for exact pin multiplexing.
Peripheral multiplexing on the same device**GPIO CTSU
© 2016 Renesas Electronics Corporation. All rights reserved. 121
Realtime Clock (RTC) (7,5,3,1)
Integrated RTC with calendar functionalityOperates using a 128 Hz clock from either Sub-Clock Oscillator, or Low-Speed On-Chip Oscillator (LOCO)
Clock error correction function1 or 64 Hz clock output via RTCOUT pinTime (year, month, day, date, hour, minute and second) capture upon activity on RTC input pinsSend event signals to other peripherals while CPU is in sleep modeInterrupt on alarm, periodic interrupt, and several other interrupts
Simplified block diagram of the RTC
Mo
de
s o
f o
pe
ratio
n
Binary Count Mode Count seconds serially in 32 bits
Calendar Count Mode Supports 100 year calendar (2000 to 2099) Automatic adjustment for leap year 12/24 hour, AM/PM switching function Year, month, day, date, minute and second counting
Synergy MCU
ELC
RTC
Sub Clock Osc.
XTALS1
XTALS0
Low-speed On-chip
Osc.
Bus Interface
128 Hz Clock
Generator
Interrupt Control
Time Capture Control Input
Alarm
Counter
ALM
PRDCUP
RT
C Inpu
t C
aptu
re 012
32.7
68 k
Hz
128 Hz
RTCOUT
1 or 64 Hz
Peripheral Bus
© 2016 Renesas Electronics Corporation. All rights reserved. 122
Switching Regulator (7)
Integrated DC-DC buck converter for high-efficiency operation (~ typ. 80% at 100 mA)Reduces power dissipation in the dieInternal digital power rail selection Switching Regulator LDO Linear RegulatorILoad = 200 mA (typ., in PWM mode)fSwitching = 1 MHz (typ., in PWM mode)IQuiescient = 100 µA (typ., in PFM mode)
Power distribution in Synergy MCUs
VREFH
AVCC
VCC
Synergy MCU
Analog Peripherals
Core
Memory
Digital Peripherals
LDO Linear
Regulator
Switching Regulator
Analog Power Digital Power
3.3 V
3.3 V 1.25 V
Switching Regulator
External components connections for power regulator
Load
VCC
VLO
VCL
10 µH, 150 mΩ
0.45 V, 1 A
22 µF, 4 mΩ
VSS
© 2016 Renesas Electronics Corporation. All rights reserved. 123
Timing & Control
General PWM Timer 32-bitEnhanced High Resolution
Asynchronous General Purpose Timer
General PWM Timer 32-bitEnhanced
WDT
General PWM Timer 32-bit
General PWM Timer 16-bit
© 2016 Renesas Electronics Corporation. All rights reserved. 124
General PWM Timer 32-Bit Enhanced High Resolution (GPT32EH) (7,5)
32-bit high-resolution timers with PWM Up to 4 independent timers 8.3 ns (minimum) resolution Capable of adjusting the duty cycle of PWM output in increments of 260 ps delay*Independent clock selection per timer2 input/output pins per timer
3-phase PWM generator for high-speed, brushless DC motor control functionProtection features Register write protection Output pins disable controlAbility to trigger ADC conversionMultiple interrupt sources Data transfer controller (DTC) and DMA activation by all interruptsInputs to/outputs from ELCModes of Operation, Comparison Table
Simplified implementation of
General PWM Timer 32-Bit Enhanced High Resolution
Inpu
ts
Input Event Actions Counter start, counter stop, counter clear, count up and count down
Input 4 external pin triggers 8 ELC events Counter
Control and Setting
Registers
Comparator
3-Phase PWM Generator
/1024
/256
/64
/16
/4/1
GT
ET
RG A
B
CD
PC
LK
INT
Output Disable Request/Signal
Output Disable Signal
ELC
ELC
GTIOCB
GTIOCA
Comparator
Ext
ern
al
Triggers
8
GTIx
GTOxUP
3
3
* Only available when used with Picosecond Delay function
General PWM Timer 32-Bit Enhanced High ResolutionADC StartRequestClock Frequency
Divider
© 2016 Renesas Electronics Corporation. All rights reserved. 125
General PWM Timer 32-Bit Enhanced (GPT32E) (7,5)
32-bit high-resolution timers with PWM Up to 4 independent timers 8.3 ns (minimum) resolutionIndependent clock selection per timer2 input/output pins per timer
3-phase PWM generator for high-speed, brushless DC motor control functionProtection features Register write protection Output pins disable controlAbility to trigger ADC conversionMultiple interrupt sources Data transfer controller (DTC) and DMA activation by all interruptsInputs to/outputs from ELCModes of Operation, Comparison Table
Simplified implementation of
General PWM Timer 32-Bit Enhanced
Inp
uts
Input Event Actions Counter start, counter stop, counter clear, count up and count down
Input 4 external pin triggers 8 ELC events
Counter
Control and Setting
Registers
Comparator
3-Phase PWM Generator
/1024
/256
/64
/16
/4/1
GT
ET
RG A
B
CD
PC
LK
INT
Output Disable Request/Signal
Output Disable Signal
ELC
ELC
GTIOCB
GTIOCA
Comparator
Ext
ern
al
Triggers
8
GTIx3
3
ADC StartRequest
GTOxUP
General PWM Timer 32-Bit Enhanced
Clock Frequency Divider
© 2016 Renesas Electronics Corporation. All rights reserved. 126
General PWM Timer 32-Bit (GPT32) (7,5,3,1)
A simplified derivative of 32-bit high-resolution timersIndependent clock selection per timer2 input/output pins per timer
Up to 10 independent timersAutomatic dead time insertion (no dead time buffer)PWM generator for brushless DC motor control functionProtection features Register write protectionMultiple interrupt sources Data transfer controller activation and DMA (S3) by all interruptsInputs to/outputs from ELCModes of Operation, Comparison Table
Simplified implementation of
General PWM Timer 32-Bit
Counter
General PWM Timer 32-Bit
Control and Setting
Registers
Comparator
3-Phase PWM Generator
/1024
/256
/64
/16
/4/1
GT
ET
RG A
B
CD
PC
LK
INT
Output Disable Request/Signal
Output Disable Signal
ELC
ELC
GTIOCB
GTIOCA
GTIx3
3
Inp
uts
Input Event Actions Counter start, counter stop, counter clear, count up and count down
Input 4 external pin triggers 8 ELC events
GTOxUP
Clock Frequency Divider
© 2016 Renesas Electronics Corporation. All rights reserved. 127
General PWM Timer 16-Bit (GPT16) (1)
A simplified 16-bit timerIndependent clock selection per timer2 input/output pins per timer
Up to 6 independent timersAutomatic dead time insertion (no dead time buffer)PWM generator for brushless DC motor control functionProtection features Register write protectionMultiple interrupt sources Data transfer controller activation by all interruptsInputs to/outputs from ELCModes of Operation, Comparison Table
Simplified implementation of
General PWM Timer 16-Bit
Counter
Control and Setting
Registers
Clock Frequency Divider
Comparator
3-Phase PWM Generator
/1024
/256
/64
/16
/4/1
GT
ET
RG A
B
CD
PC
LK
INT
Output Disable Request/Signal
Output Disable Signal
ELC
ELC
GTIOCB
GTIOCA
GTIx3
3
Inp
uts
Input Event Actions Counter start, counter stop, counter clear, count up and count down
Input 4 external pin triggers 8 ELC events
GTOxUP
General PWM Timer 16-Bit
© 2016 Renesas Electronics Corporation. All rights reserved. 128
GPTx Modes of Operation (7,3,5,1)
GPT32-EH, GPT32-E, GPT32, and GPT16
Modes Description
1. Counter
1. Periodic count (up and down): Up-counting and down-counting is performed by an internal clock. Up-counting is resumed upon overflow. Down-counting is resumed upon underflow.
2. Event count (up and down): Up-counting and down-counting is performed by an external counting source. Up-counting is resumed upon overflow. Down-counting is resumed upon underflow.
2. Waveform output by compare match
1. Low and high: Timer outputs can be asserted low or high upon match comparison.
2. Toggle: Timer outputs can be asserted low or high upon count match.
3. Input captureTimer count value can be captured in registers upon detection of signals on external pins on both the rising edge and the falling edge of the count clock.
4. Phase counting The phase difference between a timer’s two input pins is detected and used to determine the counting direction.
5. PWM
Automatic dead-time insertion | Count direction function | Hardware stop clear | Synchronized outputs
1. Sawtooth wave PWM: The PWM is generated with a saw tooth wave, and the duty cycle is set by a match value in the register.
2. Sawtooth wave one shot: The PWM is generated with a saw tooth wave, and the pulse width is set by two match values.
3. Triangular 1, 2, 3: The PWM is generated with a triangular wave, and the pulse width is set by two match values at crests or troughs.
© 2016 Renesas Electronics Corporation. All rights reserved.
Features GPT32-EH GPT32-E GPT32 GPT16
Counter Bits 32 32 32 16
ClocksPCLK
(/4, /16, /64, /256, /1024)PCLK
(/4, /16, /64, /256, /1024)PCLK
(/4, /16, /64, /256, /1024)PCLK
(/4, /16, /64, /256, /1024)
Counting Mode Up, Down Up, Down Up, Down Up, Down
Max. No. of Units 4 4 10 6
Input Capture Available Available Available Available
Compare Match Output Available Available Available Available
ADC Start Request Available Available - -
Interrupt Sources 13 TBD 13 TBD 10 TBD 10
Interrupt Skipping Available Available - -
3-Phase PWM Generator Available Available Available Available
Pico Second Delay Available - - -
Available In
129
Comparison Between GPTs
© 2016 Renesas Electronics Corporation. All rights reserved. 130
Asynchronous General Purpose Timer (AGT) (7,5,3,1)
16-bit asynchronous timer for pulse output, external pulse width (period) measurement, and external event counting
Multiple clock sources Peripheral clock (PCLK) Low-Speed On-Chip Oscillator (LOCO) Sub-clock (fSUB) Underflow signal of timerCan be operated asynchronously in low power mode without the PCLK
Simplified implementation of
Asynchronous General Purpose Timer
Mo
de
s o
f o
pe
ratio
n
Pulse Period Measurement modeAn external pulse period is measured
Pulse Width Measurement modeAn external pulse width is measured
Event Counter modeAn external event is counted
Pulse Output modeCount source is counted and output is inverted upon timer underflow
Timer modeCount source is counted
Synergy MCU
Compare and Match A
Compare and Match B
Clocking
Counter Control
16-BitDown Counter
PC
LK
f SU
B
LO
CO
Tim
er
Underf
low
Output Comp Match A
Pulse Output
External Event Input/PulseOutput
Output Comp Match B
Com
pare
M
atc
h B
ELC
Underf
low
/ M
easu
rem
en
t C
om
ple
te E
LC
Com
pare
M
atc
h A
ELC
Internal Peripheral Bus
Asynchronous General Purpose Timer
Reload Register B
Reload Register A
© 2016 Renesas Electronics Corporation. All rights reserved. 131
Watchdog Timer (WDT) (7,5,3,1)
14-bit down-counter, window watchdog timerOperates using peripheral clock
Issues reset on down-counter underflow and refresh error ORGenerates interrupt on down-counter underflow and refresh error
Simplified implementation of
Watchdog Timer
Sto
p C
on
diti
on
s ResetDown-counter and other registers return to their initial values
Underflow or Refresh ErrorCounter underflows or a refresh error is generated
Sta
rt C
on
diti
on
s Auto-Start ModeCounting automatically starts after a reset or underflow or refresh error
Register-Start ModeCounting starts by refreshing the counter in the register
Synergy MCU
Watchdog Control Circuit
Registers
14-Bit Down Counter
INT
RST
/81
92
/20
48
/51
2/1
28
/64
/4
Clock Frequency Divider
PCLK
Internal Peripheral Bus
Watchdog Timer
© 2016 Renesas Electronics Corporation. All rights reserved. 132
HMI
Capacitive Touch Sensing Unit
Graphics LCD Controller
2D Drawing Engine
JPEG Codec
Parallel Data Capture
Segment LCD Controller
© 2016 Renesas Electronics Corporation. All rights reserved. 133
Capacitive Touch Sensing Unit (CTSU) (7,5,3,1)
Capacitive Touch Sensing Unit allows detection of touch by measuring the change in parasitic electrostatic capacitance of the sensing electrodeLow pass filter inputMeasurement triggered by software or the Event Link Controller
Simplified block diagram of
Capacitive Touch Sensing Unit
Me
asu
rem
en
t M
eth
od
s a
nd
Mo
de
s
Self-Capacitance Method Single-Scan ModeElectrostatic capacitance between finger and a single electrode is measured per channel. Multi-Scan ModeElectrostatic capacitance between finger and a single electrode is measured per channel successively.
Mutual-Capacitance Method Full-Scan ModeChannel capacitance is measured successively by using mutual-capacitance method for higher sensitivity.
Synergy MCU
Status and ControlINTCLKELC
MeasurementSensor Drive
PulseGenerator
Channel Control
Port Control
Diffusion Clock
Power Supply
Sensor ICO
Ref. ICO
Capacitive Touch Sensing Unit
Data Bus
Touch IO
TS Cap IO
© 2016 Renesas Electronics Corporation. All rights reserved. 134
Graphics LCD Controller (GLCDC) (7,5)
Highly configurable peripheral to drive a variety of TFT LCDs; useful for HMI applicationsSupports various types of data formats 32-bpp formats: αRGB:8888, αRGB:0888 16-bpp formats: αRGB:4444, αRGB:1555, αRGB:0565 Look-up table formats: CLUT8, CLUT4, CLUT1Layer blending control Superimposition of multiple graphic layers Display plane selection RGB index chroma key Alpha blendingOutput control Dither correction Brightness/contrast correction Gamma correction Flexible generation of external timing control signals (TCON 0123)Supports digital interface signal output for video image size of WVGA or greater* Up to 1024 horizontal lines, 16-line resolution Up to 1024 vertical lines, 16-line resolutionPixel clock source: external clock or internal clock
Simplified implementation of
Graphics LCD Controller
TCON 0123[VSYNC, HSYNC, DEN]
Graphics LCD Controller
Background Screen Generation Block
Graphics Plane 1
Graphics Plane 2
Output control block
32 APB
32 AHB
LCDDATA0-23
LCD_CLK
Image Data Display Control Signals
Data Format Conversion
BlockTCON Block
Graphics Data IF Block
AlphaBlend Block
AlphaBlend Block
Graphics Data IF Block
Screen Generation
Block
Panel-oriented
Correction Process
Block
Regis
ters
Regis
ters
Regis
ters
Regis
ters
*with limited functionality
© 2016 Renesas Electronics Corporation. All rights reserved. 135
Graphics LCD Controller (7,5)
Image manipulation usingGraphics LCD Controller
Examples of display configurations supported by GLCDC
Alpha Blending
Anti-Aliasing
Dithering
New Blended Color
Opaque Foreground
Transparent Foreground
Vector Image Raster Image(Aliased)
Anti-aliased Image
Desired Color Gradient
Color Banding(Abrupt color
changes,poor gradient reproduction)
Dithered Image(Quantization noise
randomization, improved gradient
reproduction)
Resolution (pixels) Layers
Refresh Rate (Hz)
Color Depth(bits per pixel)
Dynamic Graphics Manipulation
(Animation)
320 x 240(QVGA)
2 60 32 Full*
480 x 272(WQVGA)
2 60 16 Full
480 x 272 1 60 32 Full
640 x 480(VGA)
1 60 16 Good
640 x 480 1 60 32 Good
640 x 480 2 60 32 Limited
800 x 480(WVGA)
2 60 16 Good
800 x 480 1 60 32 Good
800 x 480 2 60 32 Limited
800 x 600(SVGA)
1 60 32 Very limited
*Data buffer: on-chip memory
© 2016 Renesas Electronics Corporation. All rights reserved. 136
Segment LCD Controller (SLCDC) (3)
Generates AC voltage to drive an LCD screen based on the potential difference between common and segment signalsProvides up to 48 segment signals and 8 common signalsLCD driver voltage generation External resistance division External capacitor split Internal voltage boostingAutomatic output of segment and common signals based on the contents of display data registerHardware blink functionalityContrast adjustment in 16 stepsGenerates multiple waveforms to support variety of display types
Simplified implementation of
Segment LCD Controller
Synergy MCU
Internal Data Bus
Segment LCD Controller
Voltage Control
n
Clock Control and Registers
Segment Drivers
Number of LCD signals for each pin count
Pin CountNo. of Segment
SignalsNo. of Common
SignalsNo. Segments that can
be driven
144 48 8 384
120 34 8 272
100 22 8 176
Data Register
Common Driver
© 2016 Renesas Electronics Corporation. All rights reserved. 137
2D Drawing Engine (DRW) (7,5)
Module to update the frame buffer with graphical content to off load CPUSupports a variety of 2D graphics including lines, circles, ellipses, polygons, custom geometry, etc.
Simplified rendering setup showing efficient
decoupling of CPU (for other system tasks) &
2D Drawing Engine (for graphics rendering)
Coordinate Transformation
Edge Setup
Anti-aliasedRasterization
Texturing
Colorization
Blending
Memory Write
Texture Setup
Texture Cache
Run Length Encoded Unit
Memory Read
2D Drawing Engine
Core
Dra
win
g F
ea
ture
s
Vector Drawing Allows for easier implementation of edge anti-aliasing and blurring with reduced
overhead Uses half plane rendering approach Can be used to combine non-linear, quadratic equation-based primitives (conic
sections, quadratic curves, etc.)
BitBLT (Bit Boundary Block Transfer) Allows combination of two bitmaps; for example, combining a rectangle and a
texture. Results in fill, copy, rotate, scale, alpha blending, color conversion, bilinear
filtering, etc.
Example of objects rendered by2D Drawing Engine
© 2016 Renesas Electronics Corporation. All rights reserved. 138
JPEG Codec (7,5)
On-chip JPEG Codec allows for high-speed compression of image data and decoding of JPEG dataConforms to JPEG baseline compression and decompression standard, JPEG Part 2, ISO-IEC 10918-2Block interleaved image input/output method4 quantization tables, 4 Huffman tablesOutput pixel format: ARGB8888, RGB565
Multiple markers supported SOI (start of image), SOF0 (start of frame type 0), SOS (start of scan), DQT
(define quantization tables), DHT (define Huffman tables), DRI (define restart interval), RSTm (restart marks), and EOI (end of image)
Simplified implementation of JPEG
Codec
Pix
el F
orm
ats
Compression YCbCr422 (H = 2:1:1, V = 1:1:1)
Decompression YCbCr444 (H = 1:1:1, V = 1:1:1)8 lines by 8 pixels minimum coded unit for each decompression YCbCr422 (H = 2:1:1, V = 1:1:1)8 lines by 16 pixels MCU YCbCr411 (H = 4:1:1, V = 1:1:1)8 lines by 32 pixels MCU YCbCr420 (H = 2:1:1, V = 2:1:1)16 lines by 16 pixels MCU
Synergy MCU
JPEG Codec
Discrete Cosine T/f
Quantizer
Core Register
JPEG CoreData Input Bus Interface
Input Bus
Control Register
Data Output
Bus Interface
Output Bus
Control Register
Internal Peripheral Bus
Module Data Bus
Internal Graphics Bus
Huffman Coder Marker
Processing
© 2016 Renesas Electronics Corporation. All rights reserved. 139
Parallel Data Capture (PDC) (7,5)
Peripheral to transfer parallel data (image output) from external I/O devices (image sensors) to Synergy MCU’s SRAM or external address space (SDRAM) via DTC or DMAOn-chip image handling Wide range of parallel data capture Vertical: 1 line to 4095 lines Horizontal: 4 bytes to 4095 bytesOperating frequency: 30 MHz*VSYNC and HSYNC signal monitoringSupports power consumption reduction functionGenerates interrupt on multiple events
Functional block diagram of the
Parallel Data Capture
PIXCLK
VSYNC
HSYNC
PCK0
Registers and Control
Interrupt Controller
22-Stage FIFO
(32-bit size)
Parallel Data Capture
PIXD7 to 0
Prescaler
Interface Controller
Bus Interface Controller
Internal Peripheral Bus
PCDFI
PCFEIPCERI
Peripheral Clock
CMOSCamera
Simplified application using Parallel Data Capture*If peripheral clock is 60 MHz
SRAM DMA/DTC
Synergy MCU
CMOSCamera
SDRAM
Parallel Data Capture
External Memory Bus
© 2016 Renesas Electronics Corporation. All rights reserved. 140
Security & Encryption
128-bit Unique ID
TRNG
AES (128/192/256)
3DES/DES/ARC4
RSA
SHA1/SHA224/SHA256
© 2016 Renesas Electronics Corporation. All rights reserved. 141
Secure Crypto Engine 7 (SCE7) (7,5)
Provides several security features and NIST-compliant, primitive cryptographic algorithmsTypical application use cases: Authentication and secure channel communication between the MCU
and an external communication device Encryption of confidential and sensitive data for storage in the MCU
Simplified implementation of
Secure Crypto Engine 7
Typical application of security and encryption block
Secure Channel Communication
Plain Data
Encryption Key
CipherAlgorithm
Transmitter
Decrypted Data
Decryption Key
CipherAlgorithm
Receiver
Encrypted Data and Key11101010100001110
Flash RAM
Firmware
Secure Data
Data
Secure Firmware
RSA DSA
Asymmetric Algorithms
Symmetric Algorithms
Secure Crypto Engine 7
AES ARC4AES ARC43DES
TRNGCryptographic Hash
Functions
Unique ID
Bus
Clock
DMA
INT
MPU
CPU
© 2016 Renesas Electronics Corporation. All rights reserved. 142
Secure Crypto Engine 7 (7,5)
Unique ID 128-bit identification word unique per device Assigned by Renesas during manufacturing (can’t be modified) Generates secure keys using a variety of encryption algorithmsTrue RNG (TRNG) Generates cryptographically secure 128-bit random numbers at the
rate of 0.1 Mbps to 5 Mbps Use as seed to other deterministic random number generators (such
as the NIST SP800-90A DRBG)Cryptographic Hash functions Generates hash values that provide a digital fingerprint of data
Simplified implementation of
Secure Crypto Engine 7
Hash Function Data Block Length* Clock Cycles/Data Block
SHA1 512 bits 80
SHA224, SHA256 512 bits 64
GHASH 128 bits 9
* Other data block lengths are also possible.
Throughput of generating hash functions
Flash RAM
Data
RSA DSA
Asymmetric Algorithms
Symmetric Algorithms
Secure Crypto Engine 7
AES ARC4AES ARC43DES
TRNG
Bus
Clock
Unique ID
Cryptographic Hash Functions
Firmware
Secure Data
Secure Firmware DMA
INT
MPU
CPU
© 2016 Renesas Electronics Corporation. All rights reserved. 143
Secure Crypto Engine 7 Symmetric Algo. (7,5)
Symmetric-key cryptography Encryption/decryption key that is secretly shared between transmitter and
receiverAdvanced Encryption Standard (AES) Supports 128-bit, 192-bit, and 256-bit key lengths Supports various chaining modes: ECB, CBC, CTR, GCM, GCTR, and XTS Throughput for 128-bit data For 128-bit key, 11 clocks/data block For 256-bit key, 15 clocks/data block
3 Data Encryption Standard (3DES) Supports 56-bit key length, operates on a fixed 8-byte block of data Supports ECB and CBC chaining modes Used in legacy secure socket layer (SSL) and transport layer security (TLS)
protocols Throughput for 64-bit data (for 3DES) For 56-bit key, 16 clocks/data block
Alleged RC4 (ARC4) Supports 2048-bit key length Used in TLS and wired equivalent privacy (WEP) Throughput for 128-bit data For 2048-bit key, 16 clocks/data block
Simplified implementation of
Secure Crypto Engine 7
Flash RAM
Data
RSA DSA
Asymmetric Algorithms
Symmetric Algorithms
Secure Crypto Engine 7
3DES
TRNGCryptographic Hash
Functions
Unique ID
Bus
Clock
AES ARC4
Firmware
Secure Data
Secure Firmware DMA
INT
MPU
CPU
© 2016 Renesas Electronics Corporation. All rights reserved. 144
Secure Crypto Engine 7 Asymmetric Algo. (7,5)
Public-key cryptography Generates two keys: public and private Transmitter encrypts using the public key Receiver decrypts using the private keyRivest, Shamir, and Adleman (RSA) Supports up to 2048-bit key length Used in digital verification for authentication, signature generation and
verification, encryption/decryption for key exchange and wrapping, etc.Digital Signature Algorithm (DSA) Supports up to 2048-bit key length Used in authentication applications for digital signature generation and
verification Supports Diffie-Hellman key exchange
Simplified implementation of
Secure Crypto Engine 7
Flash RAM
Data
RSA DSA
Asymmetric Algorithms
Symmetric Algorithms
Secure Crypto Engine 7
AES ARC4AES ARC43DES
TRNGCryptographic Hash
Functions
Unique ID
Bus
Clock
Firmware
Secure Data
Secure Firmware DMA
INT
MPU
CPU
© 2016 Renesas Electronics Corporation. All rights reserved. 145
Secure Crypto Engine 5 (SCE5) (3)
Unique ID 128-bit unique identification word Generates secure keys using a variety of encryption algorithms Assigned by Renesas during manufacturing (can’t be modified)True RNG (TRNG) Generates cryptographically secure 128-bit random numbers at 0.1 Mbps to
5 Mbps rate Use as seed to other deterministic random number generators (such as
NIST SP800-90A DRBG)Cryptographic GHASH function Used with AES-GCTR algorithm in authenticated encryption applications Throughput for 128-bit data 33 clocks/data block
Advanced Encryption Standard (AES) Supports 128-bit and 256-bit key lengths Supports various chaining modes: ECB, CBC, CTR, GCTR, and XTS Throughput for 128-bit data For 128-bit key, 44 clocks/data block For 256-bit key, 61 clocks/data block Simplified implementation of
Secure Crypto Engine 5
Flash RAM
Data
Unique ID
Secure Crypto Engine 5
Clock
TRNGCryptographic
GHASH Function
Symmetric Algorithm
AESAES
Bus
Firmware
Secure Data
Secure Firmware DMA
INT
MPU
CPU
© 2016 Renesas Electronics Corporation. All rights reserved. 146
Security and Encryption (1)
Unique ID 128-bit unique identification word Generates secure keys using a variety of encryption algorithms Assigned by Renesas during manufacturing (can’t be modified)True RNG (TRNG) Generates cryptographically secure 128-bit random numbers at 0.1 Mbps to 5 Mbps rate Use as seed to other deterministic random number generators (such as NIST SP800-90A DRBG)Advanced Encryption Standard (AES) Supports 128-bit and 256-bit key lengths Supports various chaining modes: ECB, CBC, CTR, GCTR, and XTS Throughput for 128-bit data For 128-bit key, 44 clocks/data block For 256-bit key, 61 clocks/data block
Security and encryption
DMA
Flash RAM
Data
Security and Encryption
Clock
TRNG
Symmetric Algorithm
AESAES
Bus
Firmware
Secure Firmware
Secure Data
Unique ID
INT
MPU
CPU
© 2016 Renesas Electronics Corporation. All rights reserved. 147
Safety
ECC in SRAM
SRAM Parity Error Check
Flash Area Protection
ADC Diagnostics
Clock Frequency Accuracy Measurement Circuit
CRC Calculator
Data Operation Circuit
Port Output Enable Modulefor GPT
IWDT
© 2016 Renesas Electronics Corporation. All rights reserved. 148
ECC in SRAM (7,5,3)
Mechanism to detect and correct the data corruption in a section of on-chip extended SRAM known as ECCRAMECCRAM can be independently enabled or disabled Disabled by defaultEach user data is handled as 32-bit unit for ECCError detection: 2-bit errorError correction: 1-bit errorAvailable for a section on SRAM Up to 32 KB in sizeInterrupt generation upon error 1-bit or 2-bit error detection
Memory map of 640 KB SRAM with
32 KB ECCRAM
Synergy MCU
High Speed RAM
(if applicable)
0x0000 0000
FlashEtc.
SRAM1
0x1FFE 0000
0x1FFF FFFF
0x2000 0000
0x2000 7FFF
0x2000 8000
0x2003 FFFF
0x2004 0000
0x2007 FFFF
SRAM0
128 K
B256 K
B
32 K
B
256 K
B
0x1FFD FFFF
ECCRAM
Parity Check
No E
CC
EC
C
© 2016 Renesas Electronics Corporation. All rights reserved. 149
SRAM Parity Error Check (7,5,3,1)
Checks SRAM for parity errors upon readingAdds single-bit parity bit to each 8-bit word in SRAM at the time of writingPerforms even parity check upon readingReset assertion or NMI generation upon error detectionAsserts an optional system reset upon error detectionAvailable for entire SRAM except ECCRAM*Suitable for IEC 60730 Safety Standard for Household Appliances
Simplified operation of
SRAM Parity Error Check
SRAM1
0x2000 0000
0x2000 8000
0x2004 0000
0x2007 FFFF
256 KB
32 KB
SRAM0
ECCRAM
224 KB
SRAM Parity Check
Available
Write Operation
Read Operation
8-Bit Data Word
Calculated 1 Parity Bit
9 Bits are Written to SRAM
9-Bit Data Word Read From SRAM
Parity Check?
INT/ RSTNo Action
7 6 5 4 3 2 1 0 P
7 6 5 4 3 2 1 0 P
7 6 5 4 3 2 1 0 P
FailPass
SRAM Parity Error Check availability (example)
* Not available on S1 series
© 2016 Renesas Electronics Corporation. All rights reserved. 150
ADC Diagnostics (7,5,3,1)
Self-diagnosis for the sample-and-hold circuit and the input multiplexer Multiple test voltages generated from the internal reference voltage are applied
to the A/D Converter as one of its inputs The output of the ADC is compared against known good values to signal
erroneous or improper operation of the input multiplexer or signal conversion in limited range
ADC Diagnostics is executed once at the beginning of each scanSuitable for IEC 60730 Safety Standard for Household Appliances Can help improve reliability and qualityExample application: a fail-safe mechanism for temperature or rotor-positioning control
ADC Diagnostics for sample and hold
circuits and input multiplexers
Sca
nn
ing M
od
es
Fixed Mode A fixed voltage is used for self diagnosis
Rotating Mode Three voltages, 0, VREFH/2 and VREFH are used for self diagnosis. Allows for increased fault coverage. 12
ADCMux
Compare?VREFH*0 = 0x0
VREFH*1/2 = 0x7FFVREFH*1 = 0xFFF
FlagNo Action
FailPass
VREFH*0
VREFH*1
VREFH*1/2
DIAGVALFixed mode
Rotating mode
Power Generator
© 2016 Renesas Electronics Corporation. All rights reserved. 151
ADC Diagnostics (7,5,3,1)
Input disconnect detection assist Allows for controlled charging/discharging of input circuit to effectively detect
an input disconnection Discharging sample and hold (CADC) capacitor allows disconnected input to
be read as 0 Integrated functionality to pre-charge (pull up) and discharge (pull down)
eliminates the need for an external discharging path and components Reduces complexity, system BOM cost, and PCB footprintExternal voltage reference check Allows detecting unusual variations in the external reference voltage The internal reference voltage is periodically applied to the input of the ADC,
and the output of the ADC is compared against a known good value. Automatic data clearing ADC data register is cleared after it is read Prevents repeated reading of a “previous” value when the ADC is not
converting in the absence of a trigger
Input disconnect detection assist
ADC
A/D Convertor
Precharge Control
Discharge Control
Analog Input to
ADC
VCC
CADC
Start of Conversion
TC TCTSTSTDA TDA
TDA: Detection Assist TimeTS: Sample and Hold TimeTC: Conversion Time
Time to Pre-Charge or Discharge CADC
© 2016 Renesas Electronics Corporation. All rights reserved. 152
Flash Area Protection (7,5,3,1)
Write-protects an area within the code flash to prevent undesired self-programmingAccess window can be configured in boot mode, self-programming mode, and debugger mode onlyArea protection can be enabled only during self-programming in single-chip mode per block basisAvailable for code flash only; not available for data flashSuitable for IEC 60730 Safety Standard for Household Appliances
Example of Flash Area Protection
Flash Area Protection
Block 1
Block 2
Block 3
Block 5
Block 7
…
Block N
0x3FFF
0x4000
0x2000
0x1FFF
0x0000
End Block
Start Block
Accessi
ble
Pro
tect
ed
Pro
tect
ed
Accessi
ble
Block 4
Block 6
Block Access Status
In Boot Mode
In Self- Programming Mode
Access
Win
dow
Block 0
Note: Addresses shown in the diagram are device dependent.
© 2016 Renesas Electronics Corporation. All rights reserved. 153
CRC Calculator (7,5,3,1)
CRC code generator for error detectionCode is generated for 8 bits or 32 bits in parallel for data in 8n-bit or 32n-bit unitsSelectable LSB-first or MSB-firstSnoop functionality Reads from and writes to specific addresses can be monitored for automatic
CRC updateVariety of polynomials to choose from
Simplified implementation of the
CRC Calculator
CR
C g
en
era
tion
Po
lyn
om
ials
CRC-8X8 + X 2+ X +18
-bit
CRC-16X16 + X15 + X2 +1
CRC-CCITTX16 + X12 + X5 +1
16
-bit
CRC-32X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+ X5+X4+X2+X+1
CRC32-CX32+X28+X27+X26+ 25+X23+X22+ X20+X19+ X18+X14+X13+X11+X10 +X9+X8+X6+1
32
-bit
Synergy MCU
Output Register
CRC Code Generator
Input Register
EN?
Control and
Status
CRC Calculator
Snoop
Data Bus
Address Bus
Snoop Address
© 2016 Renesas Electronics Corporation. All rights reserved. 154
Clock Frequency Accuracy Measurement Circuit (CAC) (7,5,3,1)
Checks the system clock frequency based on a reference clock for accuracyCounts the number of pulses of the measurement clock within the time generated by reference clockSuitable for IEC 60730 Safety Standard for Household Appliances to implement a failsafe mechanismMultiple interrupt outputs
Simplified implementation of the Clock
Frequency Accuracy Measurement Circuit
Re
fere
nce
Clo
ck S
ou
rce
s Internal1. Main clock oscillator2. Sub-clock oscillator (fSUB)3. High-Speed On-Chip Oscillator (HOCO)4. Middle-Speed On-Chip Oscillator (MOCO)5. Low-Speed On-Chip Oscillator (LOCO)6. Peripheral module clock (PCLKB)7. Independent watchdog timer clock
ExternalApplied through CACREF pin
Clock Frequency Accuracy Measurement Circuit
Edge Detector and 16-bit Counter
Interrupt Control
Filter
Reference Signal Generator
Frequency Measurement Clk
IWD
TLO
CO
Main
Clo
ck
f SU
B
HO
CO
MO
CO
LO
CO
PC
LK
B
Divider/1 /4 /8 /32
Divider
CA
CR
EF
Measurement End
Comp
MuxMux
Overflow
Frequency Error
/32 /128 /1024 /8192
Count Clock
Internal Data Bus
© 2016 Renesas Electronics Corporation. All rights reserved. 155
Data Operation Circuit (DOC) (7,5,3,1)
Dedicated hardware to perform 16-bit addition, subtraction, and comparison without CPU interventionSpecifically reduces CPU load while performing memory testsSuitable for IEC 60730 Safety Standard for Household AppliancesInterrupt generation on multiple events based on the result of data operationEvent Link Controller function outputExample applications: Smart refrigerators Smart dishwashers Smart cooking products Smart washer and dryers Smart HVAC Smart building control
Simplified implementation of the
Data Operation Circuit
Synergy MCU
CPU
DMA
Input
Setting/ Output
Control
Data Operation
Data Operation Circuit
INT
ELC
Da
ta B
us
© 2016 Renesas Electronics Corporation. All rights reserved. 156
Independent Watchdog Timer (IWDT) (7,5,3,1)
Independent watchdog timer with a dedicated low-speed clock source
14-bit down counter supports clock division by 16, 32, 64, 128, and 256 Supports window functionalityEvent Link Controller function output Issues reset or non-maskable interrupt on down-counter underflow and refresh error
Simplified implementation of the
Independent Watchdog Timer
Sto
p C
on
diti
ons*
ResetDown-counter and other registers return to their initial values
Underflow or Refresh ErrorCounter underflows or a refresh error is generated
Sta
rt C
on
diti
on Auto-Start Mode
Counting automatically starts after reset. Initialization options:1) Clock frequency division ratio after a reset2) Timeout period3) Window start or end position5) Reset output or interrupt request6) Down-count stop function at transition to a low power mode
Synergy MCU
Independent Watchdog Timer
Clock Divider
Control and Registers
14-bit Counter
RESET
INTR
Clock Control
ELC
Watchdog Clock
/256/128/64/32/16/1
Inte
rna
l Pe
riph
era
l Bu
s
© 2016 Renesas Electronics Corporation. All rights reserved. 157
Comparison Between Watchdog Timers (7,3,5,1)
Features Watchdog Timer Independent Watchdog Timer
Counter Operation 14-bit down counter 14-bit down counter
Count Source Peripheral clock (PCLK) IWDT-dedicated clock (IWDTCLK)
Counter Stop ConditionsAuto-start* (after a reset/after a underflow/ refresh
error occurs)Register start (writing to register)
Auto start* after a reset
Counter Start ConditionsReset
A counter underflows or refresh error is generatedReset
A counter underflows or refresh error is generated
Window Functionality Available Available
Reset SourcesDown counter underflows
Refresh errorDown counter underflows
Refresh error
Non-Maskable Interrupt sourcesDown counter underflows
Refresh errorDown counter underflows
Refresh error
Event Link Function (output) - Available
Available In
*Need Initialization
© 2016 Renesas Electronics Corporation. All rights reserved. 158
Port Output Enable Module for GPT (POEG) (7,5,3,1)
Can disable timer output pins in response to several events in order to implement safety mechanisms
Event Link Controller function outputSuitable for IEC 60730 Safety Standard for Household Appliances
Simplified implementation of
Port Output Enable Module for GPT
Ou
tpu
t d
isa
ble
co
ntr
ol s
ourc
es
Comparator Interrupt DetectionUpon change of comp. op. result
Disable Request From TimersUpon detection of dead time error
Input Level DetectionBy sampling GTETRGA…D pins
Oscillator Stop DetectionBy setting registers
SoftwareBy setting registers
Time Output
Pin
GT
ET
RG
Synergy MCU
Cmp
Port Output Enable Module for GPT
ELC
ABCD
Timer Dis. Req.
Input Level Detection
Osc. Stop
Detection
Software
Output Disable Control
© 2016 Renesas Electronics Corporation. All rights reserved. 159
Package Navigator
LGA
QFN
LQFP
BGA
22417614514412110064484036PackageType
PinCount
Click on the check box to view package details.
© 2016 Renesas Electronics Corporation. All rights reserved. 160
LGA-36
Reference SymbolDimension (typ, mm)
D 4.0
E 4.0
w 0.20
e 0.50
A 0.69
b 0.24
x 0.05
y 0.08
y1 0.20
ZD 0.75
ZE 0.75
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023 LM
Package dimensions
Package drawing
© 2016 Renesas Electronics Corporation. All rights reserved. 161
LGA-100
Reference SymbolDimension (typ, mm)
D 7.0
E 7.0
v 0.15 (max)
w 0.20 (max)
A 1.06 (max)
e 0.65
b 0.35
b1 0.435
x 0.08 (max)
y 0.1 (max)
ZD 0.575
ZE 0.575
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-TFLGA100-7x7-0.65 PTLG0100JA-A 100F0G 0.1 LA
Package drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 162
LGA-145
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-TFLGA145-7x7-0.50 PTLG0145KA-A 145F0G 0.1 LK
Reference SymbolDimension (typ, mm)
D 7.0
E 7.0
v 0.15 (max)
w 0.20 (max)
A 1.05 (max)
e 0.5
b 0.25
b1 0.34
x 0.08 (max)
y 0.1 (max)
ZD 0.5
ZE 0.5
Package drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 163
QFN-40
Reference SymbolDimension (typ, mm)
D 6.0
E 6.0
A 0.80 (max)
A1 0
b 0.25
e 0.50
Lp 0.40
x 0.05 (max)
y 0.05 (max)
ZD 0.75
ZE 0.75
c2 0.20
D2 4.50
E2 4.50
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-5 0.09 NF
Package drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 164
QFN-48
Reference SymbolDimension (typ, mm)
D 7.0
E 7.0
A 0.80 (max)
A1 0
b 0.25
e 0.50
Lp 0.40
x 0.05 (max)
y 0.05 (max)
ZD 0.75
ZE 0.75
c2 0.20
D2 5.50
E2 5.50
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A ,P48K8-50-5B4-6 0.13 NE
Package drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 165
QFN-64
Reference SymbolDimension (typ, mm)
D 8.0
E 8.0
A 0.80 (max)
A1 0
b 0.20
e 0.40
Lp 0.40
x 0.05 (max)
y 0.05 (max)
ZD 1.00
ZE 1.00
c2 0.20
D2 6.50
E2 6.50
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-HWQFN64-8x8-0.40 PWQN0064LA-A P64K8-40-9B5-3 0.16 NB
Package drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 166
LQFP-48
Reference SymbolDimension (typ, mm)
D 7.0
E 7.0
A2 1.4
HD 9.0
HE 9.0
A 1.7 (max)
A1 0.1
bp 0.22
b1 0.20
c 0.145
c1 0.125
ϴ 8 (max)
e 0.5
x 0.08 (max)
y 0.10 (max)
ZD 0.75
ZE 0.75
L 0.5
L1 1.0
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-LFQFP48-7x7-0.50 PLQP0048KB-A 48P6Q-A 0.2g FL
Note:1. Dimension “*1” and “*2” do not include mold flash2. Dimension “*3” does not include trim offsetPackage drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 167
LQFP-64
Reference SymbolDimension (typ, mm)
D 10.0
E 10.0
A2 1.4
HD 12.0
HE 12.0
A 1.7 (max)
A1 0.1
bp 0.20
b1 0.18
c 0.145
c1 0.125
ϴ 8° (max)
e 0.5
x 0.08 (max)
y 0.08 (max)
ZD 1.25
ZE 1.25
L 0.5
L1 1.0
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-LFQFP-10x10-0.50 PLQP0064KB-A 64P6Q-A/FP-64K/FP-64KV 0.3 FM
Package drawing
Note:1. Dimension “*1” and “*2” do not include mold flash2. Dimension “*3” does not include trim offset
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 168
LQFP-100
Reference SymbolDimension (typ, mm)
D 14.0
E 14.0
A2 1.4
HD 16.0
HE 16.0
A 1.7 (max)
A1 0.1
bp 0.20
b1 0.18
c 0.145
c1 0.125
ϴ 8° (max)
e 0.5
x 0.08 (max)
y 0.08 (max)
ZD 1.0
ZE 1.0
L 0.5
L1 1.0
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-LFQFP100-14x14-0.50 PLQP0100KB-A 100P6Q-A/FP-100U/FP-100UV 0.6 FP
Package drawing
Note:1. Dimension “*1” and “*2” do not include mold flash2. Dimension “*3” does not include trim offset
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 169
LQFP-144
Reference SymbolDimension (typ, mm)
D 20.0
E 20.0
A2 1.4
HD 22.0
HE 22.0
A 1.7 (max)
A1 0.1
bp 0.22
b1 0.20
c 0.145
c1 0.125
ϴ 8° (max)
e 0.5
x 0.08 (max)
y 0.01 (max)
ZD 1.25
ZE 1.25
L 0.5
L1 1.0
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-LFQFP144-20x20-0.50 PLQP0144KA-A 144P6Q-A/FP-144L/FP-144LV 1.2 FB
Package drawing
Note:1. Dimension “*1” and “*2” do not include mold flash2. Dimension “*3” does not include trim offset
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 170
LQFP-176
Reference SymbolDimension (typ, mm)
D 24.0
E 24.0
A2 1.4
HD 26.0
HE 26.0
A 1.7 (max)
A1 0.1
bp 0.20
b1 0.18
c 0.145
c1 0.125
ϴ 8° (max)
e 0.5
x 0.08 (max)
y 0.10 (max)
ZD 1.25
ZE 1.25
L 0.5
L1 1.0
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-LFQFP176-24x24-0.50 PLQP0176KB-A 176P6Q-A/FP-176E/FP-176EV 1.8 FC
Package drawing
Note:1. Dimension “*1” and “*2” do not include mold flash2. Dimension “*3” does not include trim offset
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 171
BGA-121
Reference SymbolDimension (typ, mm)
D 8.00
E 8.00
w 0.20
A 0.99
A1 0.30
A2 0.69
e 0.65
b 0.40
x 0.08
y 0.10
y1 0.20
ZD 0.75
ZE 0.75
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-TFBGA121-8X8-0.65 PTBG0121JB-A P121F1-65-CA7-2 0.13 BJ
Package drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 172
BGA-176
Reference SymbolDimension (typ, mm)
D 13.0
E 13.0
v 0.15 (max)
w 0.20 (max)
A 1.9 (max)
A1 0.40
e 0.80
b 0.50
x 0.08 (max)
y 0.10 (max)
y1 0.20 (max)
SD -
SE -
ZD 0.9
ZE 0.9
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-FBGA176-13x13-0.80 PRBG0176GA-A - 0.5 BG
Package drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved. 173
BGA-224
Reference SymbolDimension (typ, mm)
D 13.0
E 13.0
v 0.15 (max)
w 0.20 (max)
A 1.4 (max)
A1 0.35
e 0.8
b 0.45
x 0.08
y 0.10
Zd 0.9
Ze 0.9
JEITA Package Code Renesas Code Previous Code Mass (typ, g) Package Type
P-LFBGA224-13x13-0.80 PLBG0224GA-A 224FHE 0.4 BD
Package drawing
Package dimensions
© 2016 Renesas Electronics Corporation. All rights reserved.
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