DFT forfor

Embedded Memory10/20/2010

Sangmin BaeSangmin, BaeDFX Group

IDC, System LSI, Samsung Electronics Co Ltd

Samsung Property

Samsung Electronics Co, Ltd

Contents» Introduction

• Environments and Scopes

» Technical Items• Integration complexity• MBIST design consideration• Design flow consideration• Repair and ECC• Repair and ECC

» More Technical Items

» Summary

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Introduction

» Status on eMemory Testing • Driver

» Complex advanced design flow with limited TAT» Complex, advanced design flow with limited TAT• Design capacity : Mega SOC, near NoC product

» Hierarchical, modular design flow

Ad anced lo po e design techniq e• Advanced low-power design technique• Design reuse : Heterogeneous IP integration

R id i i i h l» Rapid process migration into nano-technology• Performance gain and yield goal is more challenging than before• Reliability, test escape reduction• Bit-cell engineering requires efficient channel for si. analysis

» Well tuned DFx technique • Typically, DFT resources are re-purposed for DFx

» Productivity, Reliability, Debug, etc.

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Introduction

» Scope and limitation on eMemory Testing • Typically, memory is not fully controllable and we have

fewer knobs than logic dft (scan) technique fewer knobs than logic dft (scan) technique.

• Memory BISTy» MBIST is classical and well-defined technique, but most of

eMemory design and test issues are tightly coupled with DFT logic (MBIST). So, re-visiting of MBIST is still occurred g ( ) , g

» Not easy to maintain current through-put within the previous DFT resource (test cost H/W area)DFT resource (test cost, H/W area)

• Providing flexible MBIST automation tool is not sufficient

• SiP, TSV testing is still challenging area in the real action» Evolution of existing technique is not sufficient

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Integration Complexity

» Difficulty on SRAM Tests• Layout is more crucial compare with logic std. cell• Each 6 tr. has very strong relationship :y g p

» Trade-off exists between area, performance, yield• Bit-cell array and peri. circuit is controlled by self-timed logic • SRAM configuration widely varies on their usagesSRAM configuration widely varies on their usages• Most SRAM are deeply embedded in a chip• MBIST just do functional test on SRAMs

Roow

-Deco

der

Column mux +

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Sense Amp

Integration Complexity

» Who is DFT player? • Example : test lvcc problem

full chip level DFT planning

IO + package spec.

Vector and screening condition

SoC DFT

IP or package eng’r

Test eng’r

Design methodology +Sign-off rules

full-chip level DFT planning

FE/BEeng’r

SoC DFTdesign’r

MBIST

power-clock network

SRAM core

6T bit-cell w/SNM DNM

Process eng’r

eng reng’r

+ peri. design w/ self-timing margin

SNM, DNM eng r

SRAM designer

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Integration Complexity

» Memory BIST Limitation• Typically, MBIST is implemented on ASIC flow

» Test is based on functional test» Without memory changes, very difficult to obtain useful knobs on test

• Example : Controlling clock skew between multi-port memories» Each type could requires extra implementation overhead

Sacrifice parallelism for area reduction• Sacrifice parallelism for area reduction• Poor resolution• Pattern development difficulties

» ROI perspective : Trade-off b/w implementation efforts and TATp p / p

mem.

BISTA

BISTB

mem.

BIST

0 1 mem.

BIST

direct control clock

Port APort B

A Type

1 0

B Type

01

10

C Type

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Integration Complexity» MBIST complexity

• Increased memory counts» Hierarchical/multi-step generation and insertion capacity» Redundancy strategy

• Multiple power-domain and various power-gating scheme» Repair-information distribution

T di i l i l i l l l l» Test condition control in multiple voltage level

• Light-weight clock-domain crossing control is required» JTAG is just simple std.» Programmability control

SoC JTAG Top controller w/ repair function block» Programmability control

» Redundancy information handling

» Solution approaches

IP i/fIP i/ffunction blockfunction block

mbist mbist

mbist

mbist mbist

mbist

IP i/f

» Solution approaches• JTAG + IEEE1500 interface

with tricky interface blocks• MBIST insertion variation

Block A

Block C

IP i/fIP i/f

IP i/fIP i/f

mbist

mbist mbist

mbist

» GL vs. RTL insertion• Hierarchical test-bus

Big hard-macro IP inc. memoriesBig hard-macro IP inc. memoriesBlock B

Typical SoC MBIST Architecture

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Memory BIST Design» Memory BIST Design

• MBIST using HDL based ASIC flow» Common features :

• Programmable, at-speed fail-bit map• High-speed option : PLL, data-path pipelining, FSM design

• MBIST generator : easily adapted and deployed in industry» Script or GUI based input form : memory and MBIST lib. format» Based on configurable and parameterized templateased o co gu ab e a d pa a e e ed e p a e» IDE fasten DK iteration : planning, insertion, verification

• Several consideration : mainly automation and flow issuesSeveral consideration : mainly automation and flow issues» Customization can not be avoidable

• Different DFT budgets and targets by different customer• Clock scheme and scan mode isolation• Clock scheme, and scan mode isolation

» Seamless automation flow requires continuous efforts• Hard to be properly hidden during implementation flow

» Timing closure STA Verification» Timing closure, STA, Verification

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Design Flow Consideration» RTL vs. GL MBIST Flow

• TAT is a main driving factor : IP and tools status• Selection could different depends on design-flow and tool-chain• It mainly depends on other constraints, not by MBIST

» HDL interface capability is mandatory» No leading/full standards existsg/

• JTAG + IEEE1500 style is very popular but, loose standards

RTL design planningl lRTL

Logic- synthesis

design planningTop-level integration

IP integration

Scan Synthesis

Boundary Scan

Timing closureflow automation

ECO & verification

Simple Concept

Complex Execution

EDA tool integration

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Si. Diagnosis of SRAM

» eMemory Si. Diagnosis• eMemory Si. diagnosis motivation

» Low yield, poor device characteristics, test escape, etc.

• Several approachespp» Initial statistical analysis» Extract exact fail bit-map» Parametric analysis using memory operation mode» Parametric analysis using memory operation mode» MBIST logic fails

• Typically, detected by design verification review and work-around can be exists work around can be exists

» Test escape• Re-producing fail on DFT@ATE test is technical goal• Re producing fail on DFT@ATE test is technical goal• Main barrier : lacks of fail modeling and MBIST flexibilities • Diagnosis time is most important

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Programmable MBIST

» Programmable MBIST• Flexibility depends on structures

» FSM-based» FSM based» ALPG like (micro-code based)» Extension of general micro-controller ISA w/ custom module

• Needs of programmable MBIST» Control of complex memory IP : eDRAM, KGD(SiP, TSV)» Si diagnosis repair analysis : diagnostic pattern repair analysis» Si. diagnosis, repair analysis : diagnostic pattern, repair analysis

• Pattern level programmability seems to be not sufficientALPG ( i i ATE) h i l» ALPG (mini. memory ATE) approaches is popular

» Pattern development costs» Well defined flexible ISA

• ATE or on-chip control interface is one of issues» JTAG or AMBA-bus based» Vector and simulation flow is required

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Repair and ECC

» General Memory Redundancy Scheme1D Redundancy 2D (Row/Column)

RedundancyHier. Redundancy

Redundancy

1D Redundancy 2D Redundancy 2.5D Redundancy

Red. Type Single (Row / Column / IO) Row + Column (Row + Column) * M

# of Red. N 2N 2N * M

BIRA Simple Medium Complex

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Repair and ECC» Typical MBIST structure on SOC

• Top DFT controller inc. JTAG interface• Local Memory BISTs• Fuse related logic for repair

» Features on MBIST designFeatures on MBIST design• Memory isolation and clocking scheme• Interface between Top DFT controller and Local BIST logics• Repair policy and repair-bus structure• Repair policy and repair bus structure

Wrapper Wrapper Wrapper

JTAGIEEE 1500

SRAMSRAM

SRAM ...BIST

Fuse

Top DFTControllerJTAG

JTAG

Repair Analysis

or custom control

Repair AddressRepair Address

FuseRelatedController

Serial or Parallel Bus

General MBIST Structure

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Repair and ECC

» ECC• Typically, SRAM ECC regarded as having big-overhead technique

» Area, timing overhead» Area, timing overhead» Increase complexities of test condition and repair flow

• Popular ECC code : SEC-DED, SEC-SEDArchitectural approaches are trends for eMemory ECC• Architectural approaches are trends for eMemory ECC

» Combined with redundancy and other design constraints/techniques

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Memory Test Bus i i» Memory Test Bus Motivation

• Traditional memory isolation and MBIST insertion are can be performance, implementation TAT intrusiveW ll d fi d d fi d i t t b t l ill t h b th f • Well-defined and find-grain test-bus protocol will catch both performance and DFT productivity goals

• Current MBIST solution is not suitable for this kind of approachesEarly stage of its adaption on several IPs• Early stage of its adaption on several IPs

Serial F/Frepair interconnectionep

air-

us

Pre-designed Re-configurable IP

MemoryInstanceem

ory

stan

ce

emory

stan

ceMem

ory

Inst

ance

e

MemoryInstance

Re

Bu

Configurable

BIST

normal memory busnormal memory bus

Me

Ins

Me

Ins

Mem

ory

Inst

anc eMemory

Instance

F/Fest-

Bus

orBIRA

w/o

Memory normal memory busnormal memory bus

normal memory bus

BIST vs. Memory Interconnection

F/FF/F

F/F

Mem

ory

TeMemory

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MBIST Planning and Test Scheduling

» Backgrounds• For multiple MBISTs in a chip, how to merge/split MBIST(s)?• Trades-off is exists (accuracy or q&d solution)( y q )

» Approaches Candidates• Memory BIST grouping/scheduling automation

» Both, spec. and run-time level required, p q» Should consider BIST generation, pattern, repair

• Run-time scheduling flow should reflect other constraints» ATE interface overhead» Diagnosis

» Flow Considerations• Accuracies Peak Peak

PowerPowerRunRun #1#1 RunRun #2#2 Run Run RunRun

» Average vs. peak power based» Clock skew and timing dependency» P&R floor-planning back-annotation» Memory operations

RunRun #1#1 RunRun #2#2 uu#3#3

RunRun#4#4

» Memory operations

• Capacities» MILP or graph-based solver» Graph-based : bin-packing problem

Test Test TimeTime

» Graph based : bin packing problem

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More Technical Items

» Several topics on eMemory DFT• Bit-cell related

» Reliability and manufacturability issues• NBTI, Hot-carrier, TDDB

• Memory related» Multi port memory related » Multi-port memory related » Parametric diagnosis structure» Memory test-assist function support» Design-assist function using BIST/BIRA resourceg g /

• BIST-BIRA related» BISR(self-repair)

• Repair analysis algorithm• fuse-compress and repair-bus structure

» BIST/BIRA planning and schedulingShared BIST or hierarchical BIST architecture • Shared BIST or hierarchical BIST architecture

• BIST/BIRA planning w/ design constraints» TSV, SiP memory test support

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Summary

» DFT for Memories• Memory BIST for eSRAM

» On-product diagnostic features in mass volume» On product diagnostic features in mass volume» Fluent and flexible design flow

• Memory BIST for SiP, TSV» KGD test is still challenging on real execution» KGD test is still challenging on real execution

• Memory BIST for DFx» Basic infra structure for eSRAM DFT

» Technical requirements on current MBIST• Well-designed memory test-busg y• Matured programmable MBIST for SiP, TSV• Latest full-chip DFT architecture compliance

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