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CSE 577 Spring 2011
Sample & Hold CircuitsSample & Hold Circuits
CSE 577 Spring 2011
Sample & Hold Circuits Sample & Hold Circuits
Insoo Kim, Kyusun ChoiMixed Signal CHIP Design Lab.Department of Computer Science & EngineeringDepartment of Computer Science & EngineeringThe Pennsylvania State University
Basic Sample and Hold Circuit ConfigurationBasic Sample and Hold Circuit ConfigurationConcept
MOSFET S&H Circuit
Insoo Kim3/14/2011
Design Issues of CMOS S&HDesign Issues of CMOS S&HSampling Moment Distortion
Finite Clock rising/falling time results in distortion
riseclock
s tV
at 2=Δ
Clock Feed-throughOverlap cap. of MOS Switch creates an sampling error during clock transition time
MOS Switch Charge InjectionSome charge in the MOS channel flow to Source and Drain, then result in an error.
holdThGSoxQVVVCQ Δ
=Δ−=Δ ),(
Insoo Kim3/14/2011
HholdThGSox C
Q ),(
Solutions for Reducing Sampling DistortionSolutions for Reducing Sampling DistortionDifferential S&H Circuit
Sample Clock BootstrappingSampling distortion can be reduced by increasing clock amplitude
Insoo Kim3/14/2011
Sample Clock Bootstrap Circuits (I)Sample Clock Bootstrap Circuits (I)Basic clock bootstrap circuit
Booted Clock
Clock
Simulation Result
Insoo Kim3/14/2011
Sample Clock Bootstrap Circuits (II)Sample Clock Bootstrap Circuits (II)Differential sampling clock bootstrap circuit
Differential Sampling Booted Clock
Single sampling booted Clock
Clock
Simulation Result
Insoo Kim3/14/2011
Signal Dependent Clock Bootstrapping (I)Signal Dependent Clock Bootstrapping (I)The problem of clock bootstrap circuit
Vgs of MOS switch can vary according to the input voltage levelRon of MOS Switch also varyRon of MOS Switch also varyIt can cause an error in holding voltage
Signal Dependent clock bootstrap circuit
Insoo Kim3/14/2011
Signal Dependent Clock Bootstrapping (II)Signal Dependent Clock Bootstrapping (II)Modified Circuit
Insoo Kim3/14/2011
Low Signal FeedLow Signal Feed--through Switchthrough SwitchSchematic
Offset: 30 mVOffset: 30 mV
Simulation Result
Insoo Kim3/14/2011
Charge injection Compensation Switch (I)Charge injection Compensation Switch (I)
Offset: 2.5 mV
Vin Vout
Simulation Result
Insoo Kim3/14/2011
Charge injection Compensation Switch (II)Charge injection Compensation Switch (II)
Offset: 0.72 mV
Vin Vout
Offset: 0.72 mV
Simulation Result
Insoo Kim3/14/2011
Actual Implementation S&HActual Implementation S&HActual Implementation S&H Actual Implementation S&H CircuitsCircuits
Double Buffered S&H ConfigurationDouble Buffered S&H Configuration
Advantages:Advantages:
- Obtain a low droop rate during holding mode
- Stability is determined by the stabilities of OP Amps
Disadvantages:
- OP Amps offset can constrain the accuracy of SHA
Insoo Kim3/14/2011
Double Buffered S&H Circuit with CMOS SwitchDouble Buffered S&H Circuit with CMOS SwitchSchematic
Insoo Kim3/14/2011
Double Buffered S&H Circuit with CMOS SwitchDouble Buffered S&H Circuit with CMOS SwitchSimulation Result
Input OutputInput
VSS (-1.65V)
VDD (1.65V)
Insoo Kim3/14/2011
Feedback Improved S&H CircuitFeedback Improved S&H Circuit
Advantages:
Off t f M t th d bl b ff d SHA- Offset free More accurate than double buffered SHA
Disadvantages:
Common Mode Rejection of the Input OP amp must be high- Common Mode Rejection of the Input OP amp must be high
- Special Care must be taken to obtain stability of SHA
- Needs a special circuitry to stabilize the input amplifier during the holding mode
Insoo Kim3/14/2011
during the holding mode
(cont’d) Feedback Improved S&H Circuit(cont’d) Feedback Improved S&H Circuit
Simple stabilization circuit for input amplifier
Insoo Kim3/14/2011
(cont’d) Feedback Improved S&H Circuit(cont’d) Feedback Improved S&H Circuit
Feedback improved S&H w/o input amp stabilizationinput amp stabilization
F db k i d S&HFeedback improved S&H with input amp stabilization
Simulation Result
Insoo Kim3/14/2011
Simulation Result
Integrating S&H CircuitIntegrating S&H Circuit
Advantages:
- Switching moment and charge feed-through can be t ll d llcontrolled very well
Disadvantages:
- Common Mode Rejection of the Input OP amp must be high- Common Mode Rejection of the Input OP amp must be high
- Special Care must be taken to obtain stability of SHA
- Needs a special circuitry to stabilize the input amplifier during the holding mode
Insoo Kim3/14/2011
during the holding mode
Switched Capacitor S&H CircuitSwitched Capacitor S&H CircuitBasic Configuration
Common implementation for pipelined ADCs
Insoo Kim3/14/2011