Professor Muller Fall 2016 Sameet Ramakrishnan Eric Chang Adapted from prior EE140 and EE141 labs

EE 140/240A Lab 0 ­ Full IC Design Flow

In this lab, you will walk through the full process an analog designer engineer might use for chip design. This includes inputting a design schematic, creating a testbench, doing the physical layout of the design, and simulating the layout with parasitic elements. 1. Remote Server Login

In this class, you may want to access the servers from home in order to use Cadence for future homeworks and the project. We recommend using X2Go instead of using ssh, as Cadence can be very graphics intensive and slow on ssh. For this lab, feel free to work either on the lab machines in front of you, or from your own laptops. To setup X2Go on your laptops:

1. From their website ( http://wiki.x2go.org/doku.php ) , download the appropriate (for your

operating system) installation of the X2go client.

2. Create a new connection. Fill out the session preferences as below, replacing Login: with your username, and press OK. In this class, you remotely log in to the hpse­9 through hpse­12 machines, as well as the c125m­x (replace x with 1 to 15) machines, which are the physical ones located in the lab.

6. To connect to the session you just configured, press the seal icon on the right. When

the authentication window opens, provide your instructional account login info.

7. When the open desktop window opens, either create a new desktop (and select

GNOME option or your favorite UNIX desktop) or log back into an existing session.

The nice thing about X2Go is that it lets you suspend a session (by just closing the

window and selecting the suspend option in the dialog) and then pick up your work later. 2. Cadence Setup and Launch Cadence is the one ­stop shop for nearly all of your analog circuits needs. To set up Cadence on your instructional account, navigate to your home directory (you can do this by typing cd ~), and type the following commands: cp ­r /home/ff/ee140/fa16/cadence . cd cadence bash source cadence_setup virtuoso & NOTE: Next time you need to start cadence, navigate into this directory, retype the source command, and type virtuoso ­ no need to remake the cadence directory! If you remake it, you will lose your existing libraries. You should see the following screens pop up:

For Cadence documentation, go to https://inst.eecs.berkeley.edu/~inst/pub/ or click the “help” button in Cadence. 3. Creating a Schematic View If the Library Manager doesn’t open automatically with the icfb console window, open it by clicking Tools → Library Manager. In Cadence, there is a relatively straightforward hierarchical organizational structure. Libraries (the furthest left column in the library manager) are collections of Cells, and Cells are collections of Views. For example, you might have an “ee140” library which has several cells such as “op­amp” or “current mirror”, with each cell having views for “schematic” and “layout”. The first thing that you will need is a new library. To do this, go to the library manager and click File → New → Library. A new window will pop up. Type “lab0” in the name field and press OK.

At this point, Cadence will prompt you for something called a Technology File. The technology file is collection of information and libraries that define the layers and devices available for a given process technology.

To import the technology file for this class, click the ‘Attach to an existing techfile’ button, press ok, and use the menu to select ‘gpdk090’. This stands for general­ purpose design kit, 90nm. General purpose refers to the type of process (typical choices are general purpose GP, low power LP, high performance HP, and radio frequency RF), and the 90nm refers to the minimum feature size available.

Now that you have a library, you can create your first schematic. Select your new ‘lab0’ library in the library manager, and click File → New → Cell View.

When prompted, name the new cell view “common_source_amp” and enter “schematic” in the view field and select “schematic” from the drop down menu for the Type field, as shown below.

The schematic editor should open up. Now we can build a schematic representation of our circuit at the transistor level. To instantiate circuit elements in the schematic, press the ‘i’ key. This will bring up a menu with fields ‘Library’, ‘Cell’, ‘View’, and ‘Names’. To put an NMOS transistor into your schematic, use the “Browse” button to get to gpdk090 → nmos1v → symbol. You can also type these references into the fields manually. As soon as you do this, you will be prompted with lots of new options. What you are actually doing at this point is instantiating a parameterized cell, or P cell for short. You can parameterize the transistor gate width, length, and fingers. Your choices will be reflected in the schematic. Instantiate a transistor of total width = 2u with 2 fingers and length = 100n. The number of fingers is essentially the number of parallel devices. Generally, the number of fingers is chosen to minimize parasitics, constrain layout area, or improve matching. Press the ‘hide’ button or hit the Enter key in the instantiate menu and put the transistor into your schematic.

If you ever want to change a p cell’s properties after placing it in the schematic, select it by clicking on it and pressing the ‘q’ key. Following those same instructions, instantiate a polysilicon resistor (resnsppoly) with 2 series segements 3um long and 500nm wide. Note that there are many possibly widths and length yeilding the same resistance ­ in practice, you may decide based on factors such as area/form factor, mismatch, or electromigration (maximum current density). Now that all of our components are in the schematic, you will need to connect them together. Press the ‘w’ key to open up the ‘Add Wire’ window. This will allow you to make connections between nodes. Simply click on the red squares the contacts in the schematic view, and make the connections needed for an common source amplifier circuit. Remember to connect the bulk terminals of the NMOS and the poly resistor to gnd. To navigate the schematic, use the arrow keys on the keyboard to pan around. You can zoom in/out by clicking the magnifying glass buttons on the toolbar, or with the hotkeys control Z/shift Z. You can also zoom to a specific area by click dragging with the right mouse around the region of interest. The last thing that you need is two pins to indicate the input and output of your amplifier. This way you cell view can interface with higher level schematics (more on this later). There are 4 ports we will want to expose out of the amplifier ­ the gate (input), the drain (output), the source (ground), and the top of the resistor (vdd).

Press the ‘p’ key to open up the ‘Add Pins’ window, type the names of your pins ­ here I used “input”, “output”, “myVDD”, and “myGND” .Make sure that you select ‘InputOutput’ in the direction drop down menu, click ‘Hide’, place your pins in the schematic, and wire them up. If you followed the instructions carefully, your schematic should look like this:

When it does, press the ‘Check and Save’ button (in the top left, it like a box with a check mark). Leave the schematic editor open for now; we’ll need it for the later portions of the lab. One more quick thing to note before you create a symbol. Sometimes it is useful to label nodes instead of directly connecting them with a wire. To connect two nodes, just label them with the same name! To create a label, press the ‘l’ key, type in the desired node name, and click on the wire in the schematic. 4. Creating a Symbol View Now that your amplifier is finished, we’re going to wrap it in a symbol, so that we can use it in other schematic cells, such as testbenches. To create a symbol, in the schematic editor window, click on Create → Cellview → From Cellview

Populate the window as below, and press OK.

If you’d like, you can edit the symbol to better visually represent an amplifier, as shown below. Some useful hotkeys are “m” for moving objects, and “r” for rotating. Again, check and save (the button on the top left), and close this window.

5. Circuit Simulation with ADE In order to simulate your amplifier, you will need to build a test bench. To do this, create a schematic called ‘common_source_amp_tb’ in the lab0 library. First, instantiate your amplifier, again by pressing i, and then filling in Library: lab0 Cellview: common_source_amp View: Symbol. Instantiate a “gnd” from the analogLib library and connect it to myGND. Instantiate a “vdc” also from the analogLib library, set its DC voltage property to 1V, and connect it betwen myVDD and gnd. Finally, instantiate another “vsin” from the analogLib library ­ this will serve as the input to our amplifier. When you instantiate the voltage source, enter the string vin for the ‘DC Voltage’ property, ‘vamp’ for Amplitude, and ‘freq_in’ for frequency as show below.

Assigning parameters to variables allows you to change them easily and sweep them in the simulator. You should also label the input and output nets to easily identify them when viewing the simulation results. Finally, check and save your schematic ­ you may get 2 warnings, which are safe to ignore. Your testbench schematic should look like this:

Now you can finally set up the simulation for your amplifier. Click Launch → ADE L to open up the Virtuoso Analog Design Environment (ADE). This tool is a little bit obtuse (it was designed in around 1995) but extremely powerful. Let’s start with two simple simulations: a dc simulation to determine our amplifier’s DC operating point, and a transient simulation to determine its gain. There are essentially 3 steps in running a simulation in ADE, corresponding to the 3 panes in the ADE Design Environment window: 1) setting up the design variables/parameters, 2) setting up the Analyses (simulation types), and 3) setting up the simulation outputs. Let’s first set up our input parameters. Right click in the ‘Design Variables’ pane and select ‘Copy from Cellview’.

For now, set freq_in at 1G, vamp at 10m, and vdc at 450m. We’ll next set up our first simulation, a DC simulation to measure the operating point. Right click in the ‘Analyses’ pane, and click ‘Edit’ (or press the top Choose Analyses button on the right side), and select ‘dc’. Check ‘Save DC Operating Point’ as shown below.

We’ll also set up a transient simulation ­ again right click in the “Analyses” pane, and click edit as before, this time select tran, and set stop time to 10n (10 cycles of the 1G period), and accuracy to ‘conservative’, and hit OK.

Finally, we’re going to set up an output to measure gain. Right click in the Outputs pane and click “Edit”, or press the “Setup Outputs” button on the right side. The easiest way to set outputs is through the calculator. This is one of the most powerful features of ADE ­ it allows you to not only view and plot the signals in your schematic, but also apply a set of built in functions to those signal (for example, divide signal, view crossing times of signals, get the amplitude, etc.). To open the calculator, press “Open” next to the Calculator line in the Setting Outputs window below.

Here, we first want to record the transient output voltage, so click on the “‘VT” button representing “transient VOLTAGE expresision”.

The schematic will pop up and you must select a node to get it’s voltage ­ select the output node. This should populate the calculator window as shown below:

Finally, click the “Send buffer expression to ADE” button, which looks like the gear with the green arrow as below, and close the calculator.

Finally, we can double click on our output in the ADE window, and name it something sensible, like “Vout”.

The nice part about the calculator, is now we can write match functions of our outputs, to compute relevant output parameters ­ we’re going to write one to compute transient gain. Open up the calculator again, and this time, click on the “Fn” function button underneath the text entry window to open the function panel. In the function panel window, change the dropdown menu function type to “All” as shown below, to view all the functions you can apply to your outputs. In this case, we want to get the maximum and minimum of the waveform, in order to compute the gain. Enter the gain expression into the window as shown below:

Again, click the “Send buffer expression to ADE” button, and name this output Gain. We’re finally ready to run our simulation! Click the green play button in the ADE window, and save the resulting plot for the check off. Another way to view results is the Results dropdown menu of the ADE window. Simulation results can be viewed through either “print”, “annotate”, or “direct plot”. Click annotate, DC Node Voltages and view the schematic, and record the DC operating point.

You can save the state of your testbench in order to bring it back up at any time. Let’s save our testbench now, as we’ll use it later in the lab. In the ADE window, go to Session → Save State, and click on the Cellview button. Populate the fields as shown below, giving your state a reasonable description so you can easily remember it later. Note that if you want to save multiple states for the same schematic testbench, you can simply give them different names (eg. spectre_state2).

To later in this ADE state, you can simply launch ADE, go to Session → Load State, select the state and press ‘OK’. 6. Creating a Layout View We’re now ready to create the physical layout of our design. Go back to the library manager and create a new cell view for common_source_amplifier as you did previously. This time, select ‘layout’ for your new cell view.

This will open up an empty layout editing view. Press the ‘e’ key to get to the display options menu. We will need to change the snap spacing so we can move our cursor with sufficient resolution. Change it to 0.005 microns for now. Also, we will need to change our display levels to see underneath the hierarchical blocks. You can change display levels to stop at 32 so that we don’t run into any problems. Mechanically, the layout is performed by drawing rectangles corresponding the metal mask, as well as to indicate doping regions, polysilicon regions, etc. The layout is done in a 2D environment ­ as we have no control of the process thickness. Vias serve to connect different vertical layers. The technology also provides several pre­laid out cells for us to use. We’re going to lay out the common source amplifier as shown below. If you’re comfortable doing layout, feel free to skip the instructions provided here to produce your own layout.

The key operations are “k” to measure distances with a ruler, “p” to create paths, “r” to create rectangles, “c” to copy, “m” to move an object. To bring up more options while performing any of these operations, you can press the “f3” key. To change layers, select the appropriate layer on the menu on the left (as shown below). Selecting an object and pressing “q” allows you to edit its properties. You can navigate around by zooming and panning with the scroll wheel or Shift+Z/Ctrl+Z, or by right clicking and selecting a zoom region. Pressing f zooms to fit the drawn layout within your screen.

First, let’s instantiate our transistor. Press ‘i” and create a 2um device with 2 fingers as in your schematic, and as shown below. Place this in your layout.

Notice the layers used ­ the green layer corresponds to the poly gate ­ the blue is m1 contacts for the source and drain regions. The red shading is the oxide layer and the yellow layer indicates the the n doping. We want to connect the gates of the 2 fingers. Do this using the ruler by drawing a rectangle of width .52 as shown below.

Then, use the “o” key to create vias to connect up to the metals from the poly. We’re going to connect up to metal 2, which requires a via from poly to M1, and M1 to M2. First create the M1_POv by changing the via definition, and then create an M2_M1 via. Place them on top of each other and centered in the gate connection, as shown below. Note that you may have to rotate the via to get it to fit.

Draw a centered M1 rectangle of width .48 and height .15 on the vias, in order to ensure sufficient M1 area, as shown below.

Route out an M2 path of width 1.6um, and height .15 as shown below to form the input line. Then copy this trace down by .3 (such that the spacing is .15). This trace will by our ground trace.

Connect the source M1 contacts of the amplifier to the ground trace, and via up from M1 to M2 to connect to the horizontal ground trace we just copied, as shown below. Also, add M1_PSUB contacts here. It is important that the substrate near the amplifier have a low impedance path to ground, so that the transistor bulk (defined by the substrate) is held at a well defined voltage.

We’re now going to connect the drain and supply. Press i and instantiate the gpdk090 resnsppoly with 2 fingers, 500n width and 3u length as shown below. Place the resistors center to be aligned with the transistors center, at a height of .24 um above it. The resistor is p doped polysilicon, and includes a layer “SiProt” which is a marking layer indicating that the poly should not be salicided, which gives it a higher resistance for the same area than the poly used for transistor gates.

Now, draw 2 M2 traces of width .15 and spaced .15 apart. Via down the top one to one side of the resistor (this is the drain to resistor connection), and the bottom one to the other side of the resistor using an M2_M1 via and M1 trace, as shown below. This bottom M2 trace is the is the VDD connection.

Finally, connect the top M2 trace to the transistor drain with an M1 trace and M2_M1 via.

Remember that, in the schematic and symbol, we had pins for the input and output of the inverter. Select the “Metal2” layer, then on the menu bar, click Create → Pin. Type the terminal names myVDD, myGND, input, and output as you did in the schematic. Now you can draw metal squares onto the relevant nets of the inverter.

7. Design Rule Checking (DRC) Now that your amplifier cell layout is finished, we will run the DRC checker to verify that your drawn layers obey all of the design rules. Design rules are provided by the foundry performing the IC fabrication to (ideally) ensure that the IC devices you have drawn will perform as desired after the chip is made. Open the Design Rules Manual (DRM) to get a feel for some of the design rules for the various layers. The DRM can be opened with with the following shell command: evince /home/ff/ee141/gpdk090_v3.9/docs/gpdk090_DRM.pdf When you are done looking through the DRM, you can start the DRC tool. First, From the Virtuoso layout menu bar, click Assura → Technology. In the “Assura Technology File” dialog box, enter the following:

/home/ff/ee140/fa16/gpdk/90nm/gpdk090_v4.5/assura/assura_tech.lib and press ok. This tells the Assura tool where to look for the relevant technology information, such as the design rules and layer information. Then go to Assura → Run DRC. Populate the DRC run window as shown below, changing technology to gpdk090.

The results of the DRC run will be displayed in the icfb window. You will likely have errors after your first DRC attempt. The errors can be difficult to understand initially; try to decode what needs to be fixed, and ask your GSI if you get stuck. When you have no DRC errors in your layout, you will see the pop up below following the DRC run:

8. Layout vs. Schematic Verification The next step in the IC design flow is to check whether the polygons you drew in your layout view actually create the devices and connections you made in the schematic view of the circuit. To do this, we will run a layout vs. schematic (LVS) checker.

When you have no LVS errors in your layout, you will see the pop up below following the LVS run:

If you have any LVS errors, please correct them by making the appropriate adjustments to your layout. Remember to run DRC check again to verify that the update doesn’t violate any design rules. At this point, your layout now passes DRC and LVS – a huge milestone in the IC design

process. Next, we will examine how the physical placement of transistors (layout) impacts circuit performance. 9. Parasitic Extraction with Assura This tool allows us to extract parasitic resistances and capacitances from the layout view. From the menu, click Assura → Open Run, and make sure “Run Name” lists the current cell you are working on (“common_source_amp”). Click OK. Now, click Assura → Run RCX. Adjust the settings in the setup, extraction, and netlisting tabs to match the screenshots below. Click OK to run the parasitic extractor. A successful extraction should give you a message similar to:

Return to the library manager, and your common_source_amp cell should have a new view named “av_extracted”. 10. Parasitic Extracted Circuit Simulation To close the full loop on the design, we finally simulate our extracted layout, to see if our performance changed. In a typical chip design, the designer usually iterates between schematic design and layout a few times before being able to converge to the desired performance. To use our extracted view for simulation, we create a “config” view, which is a file that tells the ADE simulator what view (extracted or schematic) to use for each of the blocks in simulation. To create a config view, click on the common_source_amp_tb in the library manager, and click File→ new→ Cellview. Under “type”, select config, as shown below: In the popup window, first change view to Schematic. Then click “Use Template” and select spectre and hit OK in the “Use Template” and “New Configuration” Windows.

In the Hierarchy editor window, change the view for common_source_amp to “av_extracted” as shown below, save with the floppy disk button in the top left, and exit.

Re­open your testbench, launch ADE, and load in your saved spectre state from earlier. Go to Setup→Design.

Finally, choose view name config, and click ok. If you later want toggle back to the unextracted, return to Setup→Design, but choose view name schematic.

Get an extracted netlist by doing to Setup→Netlist→Recreate, and re­run the simulation.

11. Deliverables

A. Schematic transient simulation B. Screenshot of finished amplifier layout C. Netlist with extracted parasitics D. Extracted netlist/simulation