SAM9X60 Hardware Design Considerationsww1.microchip.com/downloads/en/Appnotes/AN_3311_SAM9X60... · 2019-11-05 · AN3311 SAM9X60 Hardware Design Considerations Scope This document

AN3311 SAM9X60 Hardware Design Considerations

ScopeThis document is intended to facilitate the bring-up of any hardware design featuring a SAM9X60 MPU by providing ashort checklist intended for the hardware designer.

Abbreviation List• SDRAM – Synchronous Dynamic Random-Access Memory• SDR – Single Data Rate• DDR – Double Data Rate• LP – Low Power• PCB – Printed Circuit Board

References

Type Name Literature No. Available

Data sheet SAM9X60 DS60001579 https://www.microchip.com/wwwproducts/en/SAM9X60

Errata SAM9X60 Device Silicon Errataand Data Sheet Clarification DS80000846https://www.microchip.com/wwwproducts/en/SAM9X60

Board design files SAM9X60-EK board design files –https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/DT100126

© 2019 Microchip Technology Inc. Application Note DS00003311A-page 1

https://www.microchip.com/wwwproducts/en/SAM9X60https://www.microchip.com/wwwproducts/en/SAM9X60https://www.microchip.com/wwwproducts/en/SAM9X60https://www.microchip.com/wwwproducts/en/SAM9X60https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/DT100126https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/DT100126https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/DT100126

Table of Contents

Scope............................................................................................................................................................. 1

Abbreviation List.............................................................................................................................................1

References.....................................................................................................................................................1

1. Design Checklists....................................................................................................................................3

1.1. Schematic Checklist.....................................................................................................................31.2. Layout Checklist...........................................................................................................................3

2. Schematic Checklist Description and Examples..................................................................................... 4

2.1. Provide Adequate Voltage and Sufficient Current........................................................................ 42.2. Ensure Correct Power-up and Power-down Sequences..............................................................52.3. Ensure that the Power Supply Pins have Adequate Decoupling Capacitors............................... 52.4. Check MPU Configuration............................................................................................................62.5. Check the DDR Controller Configuration..................................................................................... 7

3. Layout Checklist Description and Examples........................................................................................... 9

3.1. Check that the Board has an Uninterrupted GND Plane..............................................................93.2. Define a Layer Stack-up so that Line Impedances are matched to Driver Impedances............ 103.3. Place Decoupling Capacitors as Close as Possible to IC Pins.................................................. 123.4. Length-Match High-Speed Signals.............................................................................................15

4. Revision History.................................................................................................................................... 17

4.1. Rev. A - 11/2019.........................................................................................................................17

5. Appendix............................................................................................................................................... 18

5.1. Bit and Byte Swapping............................................................................................................... 185.2. Good Practices...........................................................................................................................19

The Microchip Website.................................................................................................................................20

Product Change Notification Service............................................................................................................20

Customer Support........................................................................................................................................ 20

Microchip Devices Code Protection Feature................................................................................................ 20

Legal Notice................................................................................................................................................. 20

Trademarks.................................................................................................................................................. 21

Quality Management System....................................................................................................................... 21

Worldwide Sales and Service.......................................................................................................................22

AN3311


1. Design Checklists

1.1 Schematic Checklist• Is the MPU supplied with the correct voltage levels?• Does the power management IC provide enough current for the system?• Are the correct power supply power-up and power-down sequences implemented?• Are the decoupling capacitors adequate?• Is the MPU configured correctly?• Is the DDR controller configured correctly?

1.2 Layout Checklist• Does the board feature an uninterrupted GND plane?• Is a proper layer stack-up defined?• Are the decoupling capacitors placed as close as possible to the IC pins?• Are high-speed signal lengths matched and routed over continuous planes (USB, SDCARD, DDR, etc.)?

AN3311Design Checklists


2. Schematic Checklist Description and ExamplesThis section describes each item in the schematic checklist and provides implementation examples.

2.1 Provide Adequate Voltage and Sufficient Current

2.1.1 RequirementsRefer to table “Recommended Operating Conditions on Power Supply Inputs”, in chapter “Electrical Characteristics”of the SAM9X60 data sheet, for the power supplies needed to power the MPU.

The MPU requires three main voltage values:

• 1.15V for VDDCORE• 1.8V for VDDIOM*, VDDNF*, VDDQSPI*, VDDIOP[0,1]* and VDDBU*• 3.3V for VDDIOM*, VDDNF*, VDDQSPI*, VDDIOP[0,1]*, VDDANA, VDDIN33 and VDDBU*

* These voltage rails can be connected to either 1.8V or 3.3V, depending on the application.

2.1.2 Implementation ExampleThe MIC2800-G8S was designed especially for this type of application, as it can output the three power supplydomains required by the MPU.

Figure 2-1. MIC2800-G8S

Customers who need extra power in their design should consider the MCP16501/2, which offers four independentbuck converters, each capable of outputting up to 1A of current, plus two other separate 300 mA LDOs.

AN3311Schematic Checklist Description and Examples


2.2 Ensure Correct Power-up and Power-down Sequences

2.2.1 RequirementsRefer to figures “Recommended Power Sequence at Power-up” and “Recommended Power Sequence at Power-down” in chapter “Electrical Characteristics” of the SAM9X60 data sheet for the applicable power supply sequencing.

The “Power-up Timing Requirements” table shows that:

• VDDBU must not come after VDDIN33 later than 0.2 ms,• VDDIN33 must be stable before (not after) all other power supplies except VDDBU,• The NRST line must be kept low for at least 8 ms after all other power supplies have become stable.

The “Power-down Timing Requirements” table shows that:

• The NRST line must be pulled low before the power supplies are powered off.

2.2.2 Implementation ExampleAgain, the MIC2800-G8S makes this task easy. The enable (EN) pin eases the implementation of a correct power-upsequence and the possibility of shutting down the PMIC to switch the system to a low-power consumption state,operating off a small battery.

The Power-On Reset (POR) pin with adjustable delay time keeps the MPU in reset until the power rails are stable,therefore ensuring a correct power-up sequence.

Figure 2-2. Power Management Integrated Circuit

GND GNDGND GND

VDD_1V15

VDD_MAIN_5V

2.2uH

L1

GND

GNDGND

VDD_1V8

GND

GND

GND

MIC2800_nRST

GND

0.1uF50V0402

C170.1uF50V0402

C180.1uF50V0402

C19

LOWQ1

BIAS2

SGND 3PGND4

SW 5

VIN6

VIN7

LDO2 8

FB 9

LDO 10

LDO1 11

POR 12

CSET 13

CBYP14

EN115

EN216

U3

MIC2800-G8SYML-TR

600mA

300mA

300mAVDD_3V3_LDO

POWER_EN

10uF25V1206

C1010uF25V1206

C1110uF25V1206

C12

10uF25V1206

C2110uF25V1206

C2210nF16V0402

C20

1N4148D120k 0402 1%R11

100k04025%

R29PIC1001 PIC1002

COC10 PIC1101 PIC1102

COC11 PIC1201 PIC1202

COC12

PIC1701

PIC1702

COC17 PIC1801

PIC1802

COC18 PIC1901

PIC1902

COC19 PIC2001

PIC2002

COC20 PIC2101

PIC2102

COC21 PIC2201

PIC2202

COC22

PID101 PID102 COD1

PIL101 PIL102

COL1

PIR1101 PIR1102 COR11

PIR2901

PIR2902 COR29

PIU301

PIU302

PIU303 PIU304

PIU305

PIU306

PIU307

PIU308

PIU309

PIU3010

PIU3011

PIU3012

PIU3013

PIU3014

PIU3015

PIU3016

COU3

PIC1002 PIC1102 PIC1202

PIC1702 PIC1802 PIC1902 PIC2002 PIC2102 PIC2202

PIU303 PIU304

PIU3012 POMIC28000nRST

PIC1701

PIU3014

PIC1801 PIU302

PIC1901

PID101

PIR1102 PIU3015

PIC2001 PIU3013

PIL101 PIU305

PIR2901

PIU301

PID102

PIR1101

PIU3016 NLPOWER0EN

PIC1101 PIC1201

PIL102

PIU309

PIU3010

PIC2201

PIU3011

PIC2101

PIU308

PIC1001 PIR2902 PIU306

PIU307

POMIC28000nRST

The 20 KΩ resistor (R11) and the 0.1 µF capacitor (C19) provide a low-pass filter connected to the EN1 pin thatintroduces the necessary delay between the 3.3V and 1.15V rails needed for the proper operation of the MPU. Thediode (D1) ensures that the capacitor discharges rapidly during the power-down sequence.

2.3 Ensure that the Power Supply Pins have Adequate Decoupling Capacitors

2.3.1 RequirementsAs described in the SAM9X60 data sheet (“Electrical Characteristics”), low-impedance decoupling of the devicepower supply inputs must be provided. A 10 nF to 220 nF ceramic X7R (or X5R) capacitor placed very close to eachpower supply input is a minimum requirement.

In the SAM9X60-EK, we have opted for 100 nF 0201, X5R rated at 16V multilayer ceramic capacitors with goodresults.

Additionally, the internal LDO that generates VDDOUT25 requires two extra capacitors. As stated in table“VDDOUT25 Voltage Regulator Characteristics” in the SAM9X60 data sheet (“Electrical Characteristics”):



• A 2.2 µF (min) capacitor should be connected at its input (at VDDIN33).• A 2.2 µF (typ) capacitor should be connected at its output (at VDDOUT25).• The output capacitor should have a low ESR.

2.3.2 Implementation ExampleFigure 2-3. Processor Power Supplies

GND

0.1uF16V0201 C320.1uF16V0201 C33

SAM

9X60

PO

WER

SU

PPLY

4.7uF10V0402 C31VDDCOREL6

VDDCOREF6

VDDCOREF11

VDDIOMG14

VDDIOMC10

VDDIOMC13

VDDANAC4

VDDIN33P13

VDDOUT25P10

VDDIN33L11

GND J8

GND E7

GND G12

GNDANA B4

GNDIN33 R13

VDDNFK14

VDDIOP0G3

GND E10

GND B13

GND K5

GND G5

GND N15

VDDQSPIC7

VDDIOP0K3

GND H8

GND H9

GNDIN33 M10

GND K12

GND T16

GND A1

GND A16

GND T1

VDDBUP7 GND M7

VDDIOP1N3 GND N2

U5G

SAM9X6_TFBGA-228

VDDOUT25

VDDBU

VDDCORE

VDDIOM0.1uF16V0201 C34

0.1uF16V0201 C360.1uF16V0201 C370.1uF16V0201 C38

0.1uF16V0201 C410.1uF16V0201 C42

0.1uF16V0201 C430.1uF16V0201 C440.1uF16V0201 C45

0.1uF16V0201 C46

0.1uF16V0201 C480.1uF16V0201 C49

4.7uF10V0402 C47

0.1uF16V0201 C50

0.1uF16V0201 C51

GND

Decoupling caps should be placed as close as possible to their corresponding power balls

Place C19 close to L11 or P13, and place C30 close to P10

4.7uF10V0402 C35

VDDIN33

VDDIN33

2.2uF10V0402 C52

4.7uF10V0402 C404.7uF10V0402 C39

0R 0402

R30

VDD_3V3_MPU

VDD_3V3_MPU

PIC3101 PIC3102 COC31






















PIR3001 PIR3002

COR30

PIU50A1

PIU50A16

PIU50B4

PIU50B13

PIU50C4

PIU50C7

PIU50C10

PIU50C13

PIU50E7

PIU50E10

PIU50F6

PIU50F11

PIU50G3 PIU50G5

PIU50G12 PIU50G14

PIU50H8

PIU50H9

PIU50J8

PIU50K3 PIU50K5

PIU50K12 PIU50K14

PIU50L6

PIU50L11

PIU50M7

PIU50M10

PIU50N2 PIU50N3

PIU50N15

PIU50P7

PIU50P10

PIU50P13

PIU50R13

PIU50T1

PIU50T16

COU5G

PIC3101

PIC3202

PIC3302

PIC3402

PIC3501

PIC3602

PIC3702

PIC3802

PIC3901

PIC4001

PIC4102

PIC4202

PIC4302

PIC4402

PIC4502

PIC4602

PIC4701

PIC4802

PIC4902

PIC5002

PIC5102

PIC5202

PIU50A1

PIU50A16

PIU50B4

PIU50B13

PIU50E7

PIU50E10

PIU50G5

PIU50G12

PIU50H8

PIU50H9

PIU50J8

PIU50K5

PIU50K12

PIU50M7

PIU50M10

PIU50N2

PIU50N15

PIU50R13

PIU50T1

PIU50T16

PIC3902

PIC4002

PIC4101

PIC4201

PIC4301

PIC4401

PIC4501

PIC4601

PIR3001

PIU50C4

PIU50C7

PIU50G3

PIU50K3

PIU50K14

PIU50N3

PIC5001 PIU50P7

PIC3102

PIC3201

PIC3301

PIC3401

PIU50F6

PIU50F11

PIU50L6

PIC4702

PIC4801

PIC4901

PIR3002

PIU50L11

PIU50P13

PIC3502

PIC3601

PIC3701

PIC3801

PIU50C10

PIU50C13

PIU50G14

PIC5101

PIC5201

PIU50P10

In addition to the 100 nF capacitors, we used several 4.7 µF 0402, X5R rated at 10V MLCCs to serve as bulk/storageelements.

While not compulsory, it is good practice to separate the input of the internal LDO (VDDIN33) from the rest with a 0Rresistor. This configuration acts as a low-pass filter and is designed to attenuate any voltage spikes that can appearon the main 3.3V rail that powers the rest of the board. This helps meet the requirement stated in Note 1 of the“Recommended Operating Conditions on Power Supply Inputs” table in the SAM9X60 data sheet (”ElectricalCharacteristics”). The same filtering is recommended on VDDANA if the internal ADC is used.

2.4 Check MPU Configuration

2.4.1 Requirements• A 5.62 kΩ resistor is connected to the RTUNE pin for USB external tuning and an adequate voltage divider is

placed on USB VBUS to transform the 5V into the PIO voltage.→ Refer to section “Typical Connection” in chapters “USB High Speed Device Port (UDPHS)” and “USB HostHigh Speed Port (UHPHS)” of the SAM9X60 data sheet.

• The TST pin is grounded.• The ADVREFN pin is connected to the PCB ground plane.• If the design does not need JTAG boundary scan, tie the JTAGSEL pin to GND or leave it floating.



• A 32.768 kHz crystal is placed between XIN32 and XOUT32.→ Refer to section “32.768 kHz Crystal Oscillator” in chapter “Electrical Characteristics” of the SAM9X60 datasheet.

• A high-frequency clock source is provided either through a crystal placed between XIN and XOUT or through anexternal clock generator.

• If the clock generator option is chosen, it is recommended to ground XOUT to improve stability.→ Refer to section “Main Crystal Oscillator” in chapter “Electrical Characteristics” of the SAM9X60 data sheet.

• Clock sources should be chosen with great care. → Refer to section “Crystal Oscillator Design Considerations” in chapter “Electrical Characteristics” of theSAM9X60 data sheet.

2.4.2 Implementation ExampleFigure 2-4. Processor Configuration

JTAG_TCKJTAG_TDIJTAG_TDOJTAG_TMSJTAG_RTCK

USBA_NUSBA_P

USBB_NUSBB_P

USBC_NUSBC_P

0R0402

R26

VDDBU

5.62k0402 1%R23

SHDNWAKE_UP

XINXOUT

XIN32XOUT32

GND

GNDSAM9X60CONFIG

GND

1uF10V0201

C28 10R02011%

R25

0R 0402

R22DNP

VDD_3V3_MPU

MPU_nRST

XINR10XOUTT10

XIN32T9XOUT32R9SHDNR11WKUPT11JTAGSELP9

nRSTR1

TST J9

HHSDPA T12HHSDMA R12

HHSDPB T13HHSDMB T14

HHSDPC P12HHSDMC N12

TCKR3TDIF3TDOH5TMSF5RTCKT2

ADVREFP D5

RTUNE P11

ADVREFN C5

U5F

SAM9X60_TFBGA-228

0.1uF50V0402

C29

GND

TP2

VDD_3V3

GND

XIN

STB 1GND2OUT 3VDD4

24MHzDSC1001CI5-024.0000

Y3

GND

XOUT

0R0402

R28

32.768KhzABS06-32.768KHZ-T

Y2GND

XIN32

XOUT32

20pF0402C26

20pF0402C27

1M04025%

R24DNP

51R0402

R149

The SAM9X60-EK board features the ABS06-32.768KHZ-T crystal loaded with 20 pF capacitors to provide the32.786 kHz slow clock and the DSC1001CI5-024.0000 MEMS oscillator to provide a 24 MHz signal to the main clockoscillator.

2.5 Check the DDR Controller Configuration

2.5.1 Requirements• Connect the external memory chosen as required in table “EBI Pins and External Device Connections” in

chapter “Electrical Characteristics” of the SAM9X60 data sheet.• Select the correct value for DDR_CAL depending on the memory used:

– 20 kΩ for LPSDRAM, LPDDR and DDR2– 16.9 kΩ for SDRAM

• Connect the DDR_VREF pin to the correct voltage:– VDDIOM/2 for DDR2 and LPDDR– GND for (LP)SDR

Refer to section “DDR/SDR I/O Calibration and DDR Voltage Reference” in chapter “Memories” of the SAM9X60 datasheet.



2.5.2 Implementation Example for DDR2Figure 2-5. DDR Controller Configuration

DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11

DDR_A13DDR_A14DDR_A15


DDR_D0DDR_D1DDR_D2DDR_D3DDR_D4DDR_D5DDR_D6DDR_D7

DDR_D8DDR_D9DDR_D10DDR_D11DDR_D12DDR_D13DDR_D14DDR_D15

DDR_RASDDR_CASDDR_WEDDR_CS

DDR_CKEDDR_CLK_PDDR_CLK_N

DDR_DQM0

DDR_DQM1

DDR_DQS0_PDDR_DQS0_N


DDR_SDA10

A0M8A1M3A2M7A3N2A4N8A5N3A6N7A7P2A8P8A9P3A10M2A11P7A12R2A13R8

BA0L2BA1L3BA2L1

CKEK2CK_PJ8CK_NK8

RASK7CASL7WEK3CSL8

DQ0 G8DQ1 G2DQ2 H7DQ3 H3DQ4 H1DQ5 H9DQ6 F1DQ7 F9

DQ8 C8DQ9 C2DQ10 D7DQ11 D3DQ12 D1DQ13 D9DQ14 B1DQ15 B9

LDQS_P F7LDQS_N E8

UDQS_P B7UDQS_N A8

LDM F3

UDM B3

VDD1 A1VDD2 E1VDD3 J9VDD4 M9VDD5 R1

VDDQ1 A9VDDQ2 C1VDDQ3 C3VDDQ4 C7VDDQ5 C9VDDQ6 E9VDDQ7 G1VDDQ8 G3VDDQ9 G7VDDQ10 G9

VDDL J1

VSS1A3VSS2E3VSS3J3VSS4N1VSS5P9

VSSQ1A7VSSQ2B2VSSQ3B8VSSQ4D2VSSQ5D8VSSQ6E7VSSQ7F2VSSQ8F8VSSQ9H2VSSQ10H8

VSSDLJ7

WBGA-84U10

DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11


DDR_D3DDR_D6DDR_D4DDR_D1DDR_D5DDR_D2DDR_D7DDR_D0DDR_D12DDR_D15DDR_D13DDR_D8DDR_D9DDR_D10DDR_D14DDR_D11

DDR_DQM0DDR_DQM1



DDR_RASDDR_CASDDR_WE

DDR_CSDDR_CLK_PDDR_CLK_N

DDR_CKE

22pF50V0402

C62


20k04021%

R119

GND

DDR_SDA10

SDCKnB14SDCKA15

SDCKEF13

nWR0E8

SDA10D12

nRDF12

nWR1A10

DDR_CALB8

A1G16

A15G15

A8F16

A4B12

A0B10

A13B11

A10C11

A6A12

A2A13

A17F14

A12A11

A19H14

A16E14

A18C16

A3D15

A7B16A5E11

A14C15

A9D14

A11E13D10 F9D9 D8

D13 B9D14 D11

D6 J16

D11 A9

D8 G9

D12 F10

D3 H11D4 J14

D1 H10

D7 J13

D0 H16

D2 H15

D5 J11

D15 C9

DDR_VREF A14

nCS1 E16nCS0 F15

DQS1 D9

SDWE D16

nDQS1 E9

RAS E15

nDQS0 H13DQS0 H12

CAS C12

DQM1 C8DQM0 G11

nWR3L14

U5E

SAM9X60_TFBGA-228

DDR_VREF

SAM9X60DDRController

4.7k02011%

R120

4.7k02011%

R121

0.1uF16V0201

C63

0.1uF16V0201

C66

GND

4.7uF10V0402

C65

GND

VDDIOM

DDR_VREF

In the above figure, the data bits connected to the DDR2 memory appear to be scrambled. This is called “bitswapping” and was done on purpose to ease up the layout routing. Refer to 5.1 Bit and Byte Swapping.

For other examples, refer to section “Implementation Examples” in chapter “External Bus Interface (EBI)” of theSAM9X60 data sheet.



3. Layout Checklist Description and ExamplesThis section describes each item in the layout checklist and provides implementation examples.

The implementation examples are based on the SAM9X60-EK (Evaluation Kit).

3.1 Check that the Board has an Uninterrupted GND Plane

3.1.1 RequirementsAs described in the SAM9X60 data sheet (“Electrical Characteristics”), a PCB with a low-impedance ground planemust be provided. A single unbroken ground plane is a minimum requirement.

3.1.2 Implementation ExampleFigure 3-1. Correct GND Plane

2

L2 - GND

AN3311Layout Checklist Description and Examples


Figure 3-2. Incorrect GND Plane2

L2 - GND

The first image depicts a solid/uninterrupted GND plane that stretches all over the board. This is the idealimplementation.

The only exception to this rule can be seen in the lower right corner of the board where a small plane cut-out hasbeen made. This is acceptable because there are no other signals routed over that area that could capture undesiredexternal ElectroMagnetic Interference (EMI).

The second image shows several cut-outs assigned to a different power supply and also a couple of signals routedon this layer.

Such arrangement is to be avoided by all means, as it is a proven source of EMI, therefore prone to failing the EMCcompliance tests.

3.2 Define a Layer Stack-up so that Line Impedances are matched to DriverImpedances

3.2.1 RequirementsMatch the PCB line impedances to their corresponding driver impedances to reduce line reflections:

• Single-ended lines should have 50 Ω +/-10% single-ended impedance.



• USB lines should have 90 Ω +/-15% differential impedance.• DDR CLOCK and STROBE should have 100 Ω +/-10% differential impedance.

3.2.2 Implementation ExampleThe SAM9X60 was especially engineered to be placed on a four-layer PCB.

To achieve the best performance, we recommend using the following layer stack-up and line width and clearances.

Figure 3-3. Four-Layer Stack-up

Material Layer Thickness Dielectric Material Type GerberTop Overlay Legend GTO

Surface Material Top Solder 0.020mm Solder Resist Solder Mask GTS

Copper L1 - Top Layer 0.035mm Signal GTL

Prepreg 0.085mm Dielectric

Copper L2 - GND 0.035mm Signal G1Core 1.200mm FR-4 DielectricCopper L3 - PWR 0.035mm Signal G2

Prepreg 0.085mm Dielectric

Copper L4 - Bottom Layer 0.035mm Signal GBL

Surface Material Bottom Solder 0.020mm Solder Resist Solder Mask GBS

Bottom Overlay Legend GBOTotal thickness: 1.560 mm ± 10%

Layer Stack Legend

TYPEDIFFDIFFDIFFDIFFSESE

IMPEDANCE90Ω90Ω100Ω100Ω50Ω50Ω

TOLERANCE± 10%± 10%± 10%± 10%± 10%± 10%

LAYERL1L4L1L4L1L4

REFERENCEL2L3L2L3L2L3

WIDTH [um]125125100100125125

GAP [um]200200200200

PCB Impedance Information

This stack-up was chosen because it can provide all the required impedances by using minimum 100 µm-widetraces.

The minimum trace width is 100 µm (~4 mil) which is relatively standard nowadays for PCB manufacturers. This alsoensures that the routing does not take much space on the board.

3.2.3 Extra Tips

Important: Make sure that your PCB manufacturer can produce that specific stack-up.

The PCB manufacturer may not have the required materials in stock, and have to order it specifically, which canincrease the overall production cost.



Also, the manufacturer can recommend a different layer stack-up that they can produce cheaper with the materials instock.

In such cases, you can easily adapt your layout to the proposed stack-up by changing the width of the traces so therequired impedances are preserved. With the help of an impedance calculator tool, make sure that therecommendations previously given can still be respected (e.g. check that enlarging the traces will satisfy theimpedance while not infringing the minimal spacing).

Designing proper transmission lines is easier nowadays with the help of impedance calculators available on themarket.

The following example shows the Altium Designer impedance calculator.

Here, after defining the PCB stack-up, you can either use the software to compute the ideal trace width that will yielda specific impedance, or input the trace width so that the tool calculates the resulting impedance.

Figure 3-4. Impedance Calculation

The SAM9X60-EK was designed so that the final thickness of the board should be 1.6 mm. In designs that do nothave this constraint, we recommend reducing the thickness of the inner core from 1.2 mm to as low as possible. Thisdoes not impact the previously calculated trace impedances, but it allows the creation of a better plane capacitorcreated by the close-neighboring power layer and GND layer. This plane capacitor will then be very efficient to filterhigh-frequency noise, as it should have a very low ESR.

3.3 Place Decoupling Capacitors as Close as Possible to IC Pins

3.3.1 RequirementsAs described in the SAM9X60 data sheet (“Electrical Characteristics”), low-impedance decoupling of the devicepower supply inputs must be provided. A 10 nF to 220 nF ceramic X7R (or X5R) capacitor placed very close to eachpower supply input is a minimum requirement.

3.3.2 Implementation ExampleIn the following figure, capacitors are the green rectangles.



Figure 3-5. SAM9X60 Capacitor Placement



Figure 3-6. SAM9X60 Power Planes

The SAM9X60 had some of its balls strategically depopulated in order to fit 0201 decoupling capacitors on the bottomlayer, right next to the power balls among the BGA array.

The power is supplied through solid copper polygons placed on the inner layer (power layer). These polygons areformed in such a way that the signals on the bottom layer have their return path through them.

In the SAM9X60-EK design files, the 3.3V plane is split to allow the user to measure the MPU power consumption.This was one of the evaluation board requirements. However, if this is not a requirement in your design, we highlyrecommend connecting the two planes together as depicted above.



3.4 Length-Match High-Speed Signals

3.4.1 RequirementsHigh-speed signals must be length-matched and routed over an uninterrupted reference plane (power or ground).

3.4.2 Implementation Example for DDR2Figure 3-7. DDR2 Address and Control

TOP



Figure 3-8. DDR2 Data Lanes

BOTTOM

Special care was taken when designing the SAM9X60 stand-alone MPU package ball-out to ease an optimal routingpath for the DDR2 memory.

It is also good practice to route signals that belong to the same group on the same layers. The above figure shows areusable layout, where all address and control signals (green) are routed on the top layer, and all data signals(orange and light blue) are routed on the bottom layer.



4. Revision History

4.1 Rev. A - 11/2019First issue.

AN3311Revision History


5. Appendix

5.1 Bit and Byte SwappingDDR2 memories support bit swapping, a technique the designer can use to interchange data lines with one another,provided that they correspond to the same byte lane (e.g. any bits inside the D[0..7] lane). This is very useful whentrying to optimize a DDR layout routing.

The following figure shows an example of the bit swapping technique implemented in the SAM9X60-EK boarddesign.

Figure 5-1. DDR2 Bit Swapping

Byte swapping is another technique that can be used on DDR2 memories. It allows the designer to swap the datalanes with one another, also for the purpose of optimizing the layout. Remember to also swap the DQMx and DQSxsignals corresponding to the swapped byte lanes, as illustrated below.

Figure 5-2. DDR2 Byte Swapping

AN3311Appendix


5.2 Good PracticesThe following is a list of suggestions for designing with high-speed signals:

• Use controlled impedance PCB traces that match the specified single-ended (50Ω) and differential (100Ω)impedance.

• Keep the trace lengths of the differential signal pairs as short as possible.• The differential signal pair traces should be trace-length matched and the maximum trace-length mismatch

should not exceed the specified values. Match each differential pair per segment.• Maintain parallelism and symmetry between differential signals with the trace spacing required to achieve the

specified differential impedance.• Maintain maximum possible separation between the differential pairs, any high-speed clocks/periodic signals

(CMOS/TTL) and any connector leaving the PCB (such as I/O connectors, control and signal headers, or powerconnectors).

• Route differential signals on the signal layer nearest the ground plane using a minimum of vias and corners. Thiswill reduce signal reflections and impedance changes. Use GND stitching vias when changing layers.

• Route CMOS/TTL and differential signals on different layers, which should be isolated by the power and groundplanes.

• Avoid tight bends. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of a single 90°turn.

• Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices or ICs that useand/or generate clocks.

• Stubs on differential signals should be avoided due to the fact that stubs will cause signal reflections and affectsignal quality.

• Keep the length of high-speed clock and periodic signal traces that run parallel to high-speed signal lines at aminimum to avoid crosstalk. Based on EMI testing experience, the minimum suggested spacing to clock signalsis 50 mils.

• Use a minimum of 20 mils spacing between the differential signal pairs and other signal traces for optimal signalquality. This helps to prevent crosstalk.

• Route all traces over continuous planes (VCC or GND), avoiding cross splits or openings in those planes.• For microstrip or stripline transmission lines, keep the spacing between adjacent signal paths at least twice the

line width.• Keep all traces at least five line widths away from the edge of the board.• Follow the return path of each signal and keep the width of the return path under each signal path at least as

wide, and preferably at least three times as wide, as the signal trace.• To avoid EMIs, avoid routing switching signals across splits or openings in ground planes. Routing around them

is preferable even if it results in longer paths.• Minimize the loop inductance between the power and ground paths.• Allocate power and ground planes on adjacent layers with as thin a dielectric as possible to create plane

capacitance.• Route the power and ground planes as close as possible to the surface where the decoupling capacitors are

mounted.• Supply voltages must be composed of planes only, not traces. Short connections (≈ 8 mils) are commonly used

to attach vias to planes. Any connections required from supply voltages to vias for device pins or decouplingcapacitors should be as short and as wide as possible to minimize trace impedance (20 mils trace width).

AN3311Appendix


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Customers should contact their distributor, representative or ESE for support. Local sales offices are also available tohelp customers. A listing of sales offices and locations is included in this document.

Technical support is available through the website at: http://www.microchip.com/support

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• Microchip products meet the specification contained in their particular Microchip Data Sheet.• Microchip believes that its family of products is one of the most secure families of its kind on the market today,

when used in the intended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these

methods, to our knowledge, require using the Microchip products in a manner outside the operatingspecifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft ofintellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code

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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protectionfeatures of our products. Attempts to break Microchip’s code protection feature may be a violation of the DigitalMillennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, youmay have a right to sue for relief under that Act.

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AN3311


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AN3311


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ScopeAbbreviation ListReferencesTable of Contents1. Design Checklists1.1. Schematic Checklist1.2. Layout Checklist

2. Schematic Checklist Description and Examples2.1. Provide Adequate Voltage and Sufficient Current2.1.1. Requirements2.1.2. Implementation Example

2.2. Ensure Correct Power-up and Power-down Sequences2.2.1. Requirements2.2.2. Implementation Example

2.3. Ensure that the Power Supply Pins have Adequate Decoupling Capacitors2.3.1. Requirements2.3.2. Implementation Example

2.4. Check MPU Configuration2.4.1. Requirements2.4.2. Implementation Example

2.5. Check the DDR Controller Configuration2.5.1. Requirements2.5.2. Implementation Example for DDR2

3. Layout Checklist Description and Examples3.1. Check that the Board has an Uninterrupted GND Plane3.1.1. Requirements3.1.2. Implementation Example

3.2. Define a Layer Stack-up so that Line Impedances are matched to Driver Impedances3.2.1. Requirements3.2.2. Implementation Example3.2.3. Extra Tips

3.3. Place Decoupling Capacitors as Close as Possible to IC Pins3.3.1. Requirements3.3.2. Implementation Example

3.4. Length-Match High-Speed Signals3.4.1. Requirements3.4.2. Implementation Example for DDR2

4. Revision History4.1. Rev. A - 11/2019

5. Appendix5.1. Bit and Byte Swapping5.2. Good Practices

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SAM9X60 Hardware Design Considerationsww1.microchip.com/downloads/en/Appnotes/AN_3311_SAM9X60... · 2019-11-05 · AN3311 SAM9X60 Hardware Design Considerations Scope This document