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PERFORMANCE COMPARISON AND EVALUATION OF 802.11A AND ITS IMPLEMENTATION IN RECONFIGURABLE ENVIRONMENT. Project Advisor: Dr. N. D Gohar (HOD CSE, SEECS, NUST) Committee Members: Mr. Imtiaz Khokhar (Asst. Prof, EE, MCS, NUST) Dr. Adnan Khan (Asst. Prof, EE, MCS, NUST) - PowerPoint PPT Presentation
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PERFORMANCE COMPARISON AND EVALUATION OF 802.11A AND ITS IMPLEMENTATION IN
RECONFIGURABLE ENVIRONMENT
SABA ZIA2007-NUST-MS-PHD-TE-05
Project Advisor: Dr. N. D Gohar (HOD CSE, SEECS, NUST)
Committee Members:Mr. Imtiaz Khokhar (Asst. Prof, EE, MCS, NUST)
Dr. Adnan Khan (Asst. Prof, EE, MCS, NUST)Mr. Bilal Saqib (lecturer, CSE, SEECS, NUST)
Outline Introduction
SDR, OFDM based standards, WLAN Reconfigurable Environment Performance Evaluation in a Reconfigurable
Environment Reconfigurable Kernels
Implementation Overview Kernel Algorithm Kernel Simulation Results Kernel Synthesis: Max Frequency, Area requirements
Simulated and Synthesized Example WLAN PHY (802.11a)
2
Introduction
3
Introduction Performance Comparison and Evaluation of 802.11a
and its Implementation in a Reconfigurable Environment
Software Defined Radio Development using a Network-On-Chip based Rapid Prototyping Platform
4
Radio Frequency
(RF)
Analog to Digital
Conversion(A/D)
Baseband Processing
Control (Parameterization)Control (Parameterization)
Transmit
ReceiveRF Front End
55
Physical Layer Architecture and Kernel Physical Layer Architecture and Kernel Identification (802.11a)Identification (802.11a)
Ref: IEEE Std 802.11a-1999(R2003)
66
Physical Layer Architecture and Kernel Physical Layer Architecture and Kernel IdentificationIdentification
Data Scrambler/ Descrambler
Data Scrambler/ Descrambler
Convolutional Encoder / Viterbi decoder
Convolutional Encoder / Viterbi decoder
Data interleaver/ De-interleaverData interleaver/ De-interleaver
Guard interval insertion/ Removal
Guard interval insertion/ Removal
OFDM modulationIFFT/FFT
OFDM modulationIFFT/FFT
Subcarrier Modulation Mapping/ De-mapping
Subcarrier Modulation Mapping/ De-mapping
Puncturing / De-puncturingPuncturing / De-puncturing
Point ArrangementPoint Arrangement
Bit ReversalBit Reversal
Individual Properties of each KernelIndividual Properties of each KernelData Scrambler/DescramblerData Scrambler/Descrambler
77
S (x)=xS (x)=x77 +x +x44 +1 +1
Ref: IEEE Std 802.11a-1999(R2003)
Individual Properties of each KernelIndividual Properties of each KernelConvolutional Encoder/ Viterbi DecoderConvolutional Encoder/ Viterbi Decoder
88
R = ½, 2/3 , ¾R = ½, 2/3 , ¾ For R= 1/2, GFor R= 1/2, G00=133=13388 G G11 = 171 = 17188
Decoding by Viterbi AlgorithmDecoding by Viterbi AlgorithmRef: IEEE Std 802.11a-1999(R2003)
Individual Properties of each KernelIndividual Properties of each KernelPuncturing/De-puncturing PatternsPuncturing/De-puncturing Patterns
99
Ref: IEEE Std 802.11a-1999(R2003)
Individual Properties of each KernelIndividual Properties of each KernelData Interleaver/ De-interleaverData Interleaver/ De-interleaver
Block size corresponding to the number of bits Block size corresponding to the number of bits in a single OFDM symbol, NCBPSin a single OFDM symbol, NCBPS
Two-step permutationTwo-step permutation i = (Ni = (NCBPSCBPS/16) (k mod 16) + floor(k/16) where k = 0,1,…,N/16) (k mod 16) + floor(k/16) where k = 0,1,…,NCBPS CBPS – 1– 1
j = s × floor (i/ s) + (i + Nj = s × floor (i/ s) + (i + NCBPSCBPS – floor(16 × i/N – floor(16 × i/NCBPSCBPS)) mod s where i = )) mod s where i =
0,1,… N0,1,… NCBPSCBPS – 1 – 1
The value of s is determined by the number of coded bits per subcarrier, The value of s is determined by the number of coded bits per subcarrier, NNBPSCBPSC, according to s = max(N, according to s = max(NBPSCBPSC/2,1)/2,1)
1010
Individual Properties of each KernelIndividual Properties of each KernelSubcarrier Modulation MappingSubcarrier Modulation Mapping
BPSK,QPSK,16 QAM or 64 QAM depending on BPSK,QPSK,16 QAM or 64 QAM depending on the rate requestedthe rate requested
Gray coded constellation mappingsGray coded constellation mappings Resultant, d = (I + jQ) X KResultant, d = (I + jQ) X KMODMOD
1111
Ref: IEEE Std 802.11a-1999(R2003)
Individual Properties of each KernelIndividual Properties of each KernelOFDM modulation (IFFT)OFDM modulation (IFFT)
Divide the complex number string into Divide the complex number string into groups of 48 complex numbers. Each groups of 48 complex numbers. Each such group will be associated with one such group will be associated with one OFDM symbol.OFDM symbol.
Each complex number is mapped into Each complex number is mapped into OFDM subcarriers numbered –26 to –OFDM subcarriers numbered –26 to –22, –20 to –8, –6 to –1, 1 to 6, 8 to 20, 22, –20 to –8, –6 to –1, 1 to 6, 8 to 20, and 22 to 26. and 22 to 26.
The “0” subcarrier, associated with The “0” subcarrier, associated with center frequency, is omitted and filled center frequency, is omitted and filled with zero value. with zero value.
Four subcarriers are inserted as pilots Four subcarriers are inserted as pilots into positions –21, –7, 7, and 21. The into positions –21, –7, 7, and 21. The total number of the subcarriers is 52 total number of the subcarriers is 52 (48 + 4). (48 + 4).
For each group of subcarriers –26 to 26, For each group of subcarriers –26 to 26, convert the subcarriers to time domain convert the subcarriers to time domain using inverse Fourier transformusing inverse Fourier transform
1212
Individual Properties of each KernelIndividual Properties of each KernelOFDM modulation (FFT-DIT)OFDM modulation (FFT-DIT)
1313
Ref: IEEE Std 802.11a-1999(R2003)
-1
-1
-1
j
-j
-1
-1
-1
j
-j
W0
W1
W2
W3
W4
W5
W6
W7
TimeDomainSamples
FrequencyDomainOutputs
Individual Properties of each KernelIndividual Properties of each KernelGuard Interval InsertionGuard Interval Insertion
Prepend to the Fourier-transformed waveform a circular extension of Prepend to the Fourier-transformed waveform a circular extension of itself thus forming a GI, and truncate the resulting periodic waveform itself thus forming a GI, and truncate the resulting periodic waveform to a single OFDM symbol length by applying time domain windowing. to a single OFDM symbol length by applying time domain windowing.
1414
Ref: IEEE Std 802.11a-1999(R2003)
Rate Dependent ParametersRate Dependent Parameters
1515
Ref: IEEE Std 802.11a-1999(R2003)
Reconfigurable Environment
16
Reconfigurable Environment
17
System on Chip (SoC)
Putting all the functions of a complete system (processor, memory, analog functions, external interfaces, timers, counters, voltage regulators, etc.) all on a single silicon chip, enabling the chip to operate as a standalone system
Communication Structures in System-on-Chip
18
Bus based Architecture
µP
Memory
RF
DSPKeyboard
Point to Point Links
µP
Memory
RF
DSPKeyboard
Network based Connections
µP Memory RF
DSP Keyboard
Reconfigurable Environment
19
Network on Chip (NOC)
Resource Resource Resource
Resource Resource Resource
Resource Resource Resource
Router or Switch
RNI
Reconfigurable Kernels
20
Algorithmic size functionality
Reused across several standards
Combined Spatially or Temporally for bigger dimension
Fulfills overall performance constraints of multiple standards
SDR supporting OFDM based wireless Standards
21
Role of Kernel and 802.11a in SDR
802.11a is an OFDM based standard Each individual block of the 802.11a at
physical layer will serve the functionality of the basic kernel of OFDM block
Kernel would be expanded spatially or temporally
Implementation allows reconfiguration to meet the constraints of other wireless standards
22
Performance Evaluation in Reconfigurable Environment
Size Performance Cost Power
23
WLAN TX Controller Initialization signals for datapath
Scrambler Convolutional Encoder Interleaver Modulation Mapper Point Arrange FFT Bit Reversal Guard Insertion
State Machine Short Preamble Long Preamble Header Data Initialization Signals for Controller
WLAN TX CONTROLLER
WLAN TX DATAPATH
24
Simulated and Synthesized Datapath
IEEE STD 802.11a
25
Synthesis ResultsScrambler
ScramblerScrambler
startstart
rstrst
dindin
clkclk
doutdout
Kernel SlicesXC4VSX25
Max Frequency (MHz)XC4VSX25
Scrambler 5 505
Simulation ResultsScrambler/ Descrambler
Synthesis ResultsConvolutional Encoder
clk
Punc_en
rst
start
Start
puncture
Encoding
clk
rst
dout
Encoding
Puncturing
din
clk
rst
out
rate
Start
puncture
dout
Puncturing
Synthesis ResultsConvolutional Encoder
29
Parameter Xilinx Logic Corev6.0
XCV4-10
Designed Kernel
XCV4-10
Area (slices) 32 14
Maximum Clock Frequency (MHz)
342 384 (512 MHz XC4VSX25)
Simulation ResultsConvolutional Encoder with Puncturing
Synthesis ResultsInterleaver
Ncbps
Change Ncbps
clk
Serial_in
Start First Permutation
Addrb_0
Addrb_1
Permuted data1_0
Permuted data1_1
Ncbps
Change Ncbps
clk
Permute d data_2
Start Second Permutation
Addra_0
Addra_1
Permuted data1_0
Permuted data1_1
addra
addrb
clk
dinb
douta addra
addrb
clk
dinb
douta
Synthesis ResultsInterleaver
Kernel SlicesXC4VSX25
Max Frequency (MHz)XC4VSX25
Interleaver 633 188
Simulation Results Interleaver
Simulation ResultsInterleaver
Synthesis ResultsModulation Mapper
Data_from_mem_bpsk
Data_from_mem_qpsk
Data_from_mem_16QAM
Data_from_mem_64QAM
Modulation
64QAM_input
16QAM_input
Bpsk_input
Qpsk_input
clk
rst
Start
Imaginary_data
Real_data
Mem_addr_bpsk
Mem_addr_qpsk
Mem_addr_16QAM
Mem_addr_64QAM
addr
clk
dout
addr
clk
dout
addr
clk
dout addr
clk
dout
Synthesis ResultsModulation Mapper
Kernel SlicesXC4VSX25
Max Frequency (MHz)XC4VSX25
Modulation Mapper 65 275
Simulation ResultsModulation Mapper
FFT-DIF State Machine
Synthesis ResultsFFT-DIF
Wnk Factor LUT
Wnk Factor LUT
Dual Port RAM
Port A
Dual Port RAM
Port A
Stage and Butterfly Controller
+
Data Memory Controller
+
Twiddle Memory Controller
Stage and Butterfly Controller
+
Data Memory Controller
+
Twiddle Memory Controller
Dual Port RAM
Port
B
Dual Port RAM
Port
B
Radix-2 CellRadix-2 Cell
-1
Wnk
Comparison of Synthesis ResultsFFT-DIF
Platform
TSMC 90nm standard cell
Areamm2
ClockMHz
PowermW
Morphable Data Unit .5 1001 188
Reconfigurable Kernel 0.62 1100 38
Ref: M. Ali Shami, A Hemani “Morphable datapath Unit: Smart and efficient datapath for Signal Processing Applications”, 2008
Simulation ResultsFFT-DIF
Simulation ResultsFFT-DIF
Simulated and Synthesized Controller
IEEE STD 802.11a
43
Pipelined Data Flow
Short PreambleShort Preamble Long PreambleLong Preamble HeaderHeader ServiceService DataDataKernel
FFT
Convolutional Encoder
Scrambler
Interleaver
Modulation Mapper
Point arrangement
Bit Reversal
Guard Insertion
128 clocks128 clocks
2 clocks2 clocks
48 clocks48 clocks
172 clocks172 clocks
4 clocks4 clocks
151 clocks151 clocks
66 clocks66 clocks
Controller Review
46
Conclusion
NOC based radio prototyping platform Flexibility and scalability of FPGAs Performance of ASICs Paper submitted in conference IEEE
INFOCOM, 2010 titled “Reconfigurable FFT Kernel for Network on Chip based Radio System Prototyping Platform ”
47
Questions
48
