S8 QUAD DAC UPSAMPLER · S8 QUAD DAC UPSAMPLER 7/31 engineered SA - Switzerland doc. v.153e/rev. Oct-18 1 Introduction 1.1 Highlights The S8 Module is an ultra-high performance Quad

S8QUAD DAC UPSAMPLER

DATASHEET

Allrightsreserved.NopartofthisworkcoveredbytheengineeredSAcopyrightmaybereproducedorcopiedinanyform or by anymeans (graphic, electronic ormechanical, including photocopying, recording, taping or informationretrievalsystems)withoutthewrittenpermissionofengineeredSA.Copyright©engineeredSAAvenuedesSports28,1400Yverdon-les-BainsSwitzerland+41215433966 [email protected]/www.engineered.ch doc.v.153e/rev.Oct-18

S8QUADDACUPSAMPLER 2/31

engineeredSA-Switzerland doc.v.153e/rev.Oct-18



Table of contents Tableofcontents..........................................................................................................................................................................................31 Introduction.........................................................................................................................................................................................71.1 Highlights........................................................................................................................................................................................71.2 FunctionalBlockDiagram.......................................................................................................................................................71.3 SonicUpsampling........................................................................................................................................................................81.4 SonicScrambling.........................................................................................................................................................................81.5 DSDtoPCMConversion...........................................................................................................................................................91.6 DSF™Filtering..............................................................................................................................................................................9

2 CharacteristicsandSpecifications...........................................................................................................................................102.1 ElectrostaticDischargeWarning.......................................................................................................................................102.2 RecommendedOperatingConditions.............................................................................................................................102.3 AbsoluteMaximumRatings.................................................................................................................................................102.4 ElectricalSpecifications.........................................................................................................................................................102.5 DigitalAudioSpecifications.................................................................................................................................................112.6 DigitalFilterCharacteristics................................................................................................................................................112.7 Pinassignments........................................................................................................................................................................122.8 HousingDimensions...............................................................................................................................................................122.9 Pindescriptions........................................................................................................................................................................13

3 InterfacingandOperation...........................................................................................................................................................143.1 GeneralDescription................................................................................................................................................................143.2 TypicalConnections................................................................................................................................................................153.3 InterfacingtoDigitalAudioReceivers............................................................................................................................153.4 InterfacingtoD/AConverters............................................................................................................................................163.5 ReferenceMasterClock.........................................................................................................................................................173.6 ResetandPowerOn................................................................................................................................................................173.7 AudioSerialInputPort(RX)...............................................................................................................................................183.8 AudioOutputPorts(OUTLandOUTL)...........................................................................................................................193.9 DataResolutionandDither..................................................................................................................................................203.10 IncomingSamplingRateandLocking.............................................................................................................................203.11 Muting...........................................................................................................................................................................................213.12 PhaseInversion.........................................................................................................................................................................213.13 StereoDSDtoPCMConversion..........................................................................................................................................213.14 DigitalFilterSelection............................................................................................................................................................213.15 DataValidflag(DSP_MODE3).............................................................................................................................................223.16 SerialPortInterface(SPIPort)...........................................................................................................................................23

4 HardwareMode...............................................................................................................................................................................254.1 GeneralDescription................................................................................................................................................................254.2 HardwareConfiguration.......................................................................................................................................................25

5 SoftwareMode.................................................................................................................................................................................265.1 GeneralDescription................................................................................................................................................................265.2 InputStatusRegister..............................................................................................................................................................265.3 FilterControlRegister............................................................................................................................................................275.4 ProcessControlRegister.......................................................................................................................................................275.5 LevelAttenuatorLeftChannelControlRegister.........................................................................................................285.6 LevelAttenuatorRightChannelControlRegister......................................................................................................285.7 ScratchRegister........................................................................................................................................................................285.8 SoftwareRevisionRegister..................................................................................................................................................295.9 ProductIDRegister.................................................................................................................................................................295.10 ProductSub-IDRegister........................................................................................................................................................29



5.11 DCOffsetLeftChannelControlRegister........................................................................................................................305.12 DCOffsetRightChannelControlRegister.....................................................................................................................30

6 Relatedproducts.............................................................................................................................................................................316.1 BackwardCompatibility........................................................................................................................................................316.2 Q8UpsamplerModule...........................................................................................................................................................316.3 Customapplications................................................................................................................................................................31



Preface

I. About This Datasheet

ThisdocumentprovidestheinformationneededtodesignandintegratetheS8UpsamplerModuleintoyourproduct.Formoreinformation,pleaserefertotheproductdescriptionavailablefromtheengineeredWebsiteat:www.engineered.ch

II. Company Information

engineeredSAAvenuedesSports281400Yverdon-les-BainsSwitzerland+41215343966info@engineered.ch/www.engineered.ch

III. Notice

engineeredSAprovidestheenclosedproduct(s)underthefollowingconditions:Theuserassumesallresponsibilityandliabilityforproperandsafehandlingofthegoods.Further,theuserindemnifiesengineeredfromallclaimsarisingfromthehandlingoruseofthegoods.Informationprovidedbyengineeredisbelievedtobeaccurateandreliable.However,noresponsibilityisassumedbyengineeredforitsuse.Pleasebeawarethattheproductsreceivedmaynotberegulatorycompliantoragencycertified.EXCEPTTOTHEEXTENTOFTHEINDEMNITYSETFORTHABOVE,NEITHERPARTYSHALLBELIABLETOTHEOTHERFOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. engineered currently deals with avariety of customers for products, and therefore our arrangement with the user is NOT EXCLUSIVE.engineered assumesNO LIABILITY FOR APPLICATIONS ASSISTANCE, CUSTOMER PRODUCT DESIGN, SOFTWAREPERFORMANCE,ORINFRINGEMENTOFPATENTSORSERVICESDESCRIBEDHEREIN.Pleasereadthedatasheetand,specifically,the“ProductWarningsandRestrictions”noticeinthedatasheetprior to handling the product. This notice contains important safety information. Persons handling theproduct must have electronics training and observe good laboratory practice standards. No license isgrantedunderanypatentrightorotherintellectualpropertyrightofengineeredcoveringorrelatingtoanymachine,process,orcombinationinwhichsuchengineeredproductsorservicesmightbeorareused.

IV. Product Warnings and Restrictions

It is important to operate this product within the specified input and output range described in thisdocument.Exceedingthespecifiedinputrangemaycauseunexpectedoperationand/orirreversibledamagetotheproduct.If you have questions regarding the input range, please contact engineered customer support prior toconnectingthepowersupply.Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperation and/or possible permanent damage to the product. Please consult the datasheet prior toconnecting any load. If you have doubts concerning the load specification, please contact engineeredcustomersupport.



V. Repair and Maintenance

Routinemaintenance is not required. This product iswarranted to be free of any defectwith respect toperformance,quality,reliabilityandworkmanshipforaperiodofSIX(6)monthsfromthedateofshipmentfromengineered.In the event your product proves to be defective in anyway during thiswarranty period,wewill gladlyrepairorreplacethispieceofequipmentwithaunitofequalorsuperiorperformancecharacteristics.Shouldyoufindthisproducthasfailedafteryourwarrantyperiodhasexpired,wewillrepairyourdefectivepieceofequipmentaslongassuitablereplacementcomponentsareavailable.You,theowner,willbearanylabourand/orcomponentcostsincurredintherepairorrefurbishmentofsaidequipment,beyondtheSIX(6)monthswarrantyperiod.Anyattempttorepairthisproductbyanyoneduringthisperiodotherthanbyengineeredoranyauthorized3rdpartywillvoidyourwarranty.engineered reserves the right to assess anymodifications or repairsmade by you and decide if they fallwithin warranty limitations, should you decide to return your product for repair. In no event shallengineered be liable for direct, indirect, special, incidental, or consequential damages (including loss andprofits)incurredbytheuseofthisproduct.Impliedwarrantiesareexpresslylimitedtothedurationofthiswarranty.

VI. Documentation Release Notice

Thisdocumentisunderrevisioncontrolandupdateswillonlybeissuedasareplacementdocumentwithanewversionnumber.Productspecificationsaresubjecttochangewithoutnotice.



1 Introduction

1.1 Highlights

TheS8Moduleisanultra-highperformanceQuadDACUpsamplerdesignedforhighend,proandconsumeraudioapplications.KeyfeaturesfortheS8Moduleinclude:

• Superiorperformanceasynchronous24-bit/384kHzupsamplingbasedonanenhancedversionofthepatentedQ5technology.

• IntegrateswithDSS™synchronizationtechnologyforefficientjitterrejection.• Scrambling™technologyprovidingenhancedlow–levelsignallinearityandhighestqualitydigitalto

analogconversionusingtwoDAC'sperchannelindifferentialmode.• DSDtoPCMconversion.• DoPdecoding.• Automaticinputsamplingfrequencysensing.• Supportssampleratesinputfrom44.1kHzto384kHzandwordlengthfrom16-to24-bit.• Twodigital8xFSupsampledoutputportsareavailableforinterfacingtoexternalD/Ahardware.• Inputformat:I2Sor2-channelDSD.• Outputformat:mono-frameddataformat,32-bit.• Standalonehardwareandconfigurablesoftwaremodesavailable.• TX0-PortandTX1-Portconfigurableinmaster/slavemode.• Programmableattenuator.• CompatiblewithS2Module.

1.2 Functional Block Diagram

TheS8Moduleintegratesfourkeytechnologies:SonicUpsampling(enhancedversionofthepatentedQ5),DSS™Synchronization, Sonic Scrambling™andDSF™ filtering todeliver ahighly integrated asynchronousupsampler and digital synchronizerwith best low-level signal linearity and high performancemulti-DACdifferentialoutput.ThemodulefeaturesasingleaudioinputportcapableofsupportingPCMdataupto24-bitfromfrequenciesupto384kHzorstereoDSD64(2.8224MHz)andDSD128(5.6448MHz).Ineithercase,theDSDsignalorthedirectPCMinputareupsampledtoacommon8xFSPCMformat.

Figure1-1-functionalblockdiagram

PCM/DSD audio input

control interface

reclocking&

upsampling

multi-DACdata

distribution

multi-DACdata

distribution

S8 Module

I2S / DSD

SPI+GPIOs

Low Jitter AudioMaster Clock

Left Data +

Left Data -

Right Data +

Right Data -

Digital Audio

Source

Micro controller

Dual DAC& analog

filter

Dual DAC& analog

filter

24.576MHz oscillator



1.3 Sonic Upsampling

TheS8UpsamplerModuleincludesseveralproprietarytechnologies:adaptivetimefiltering,data-to-systemsynchronization,andaninnovativevirtualtime-domainmodel.Thesetechnologieseffectivelyreducenoiseartefactscausedbyimperfectdigitalsystemsandallowthedigitalsignaltocloserrepresentthetrueanalogsoundofthestudiomasteredaudiodata.Adaptivetimefilteringallowsthesystemtoadapttosmall fluctuationsinthesystemsaudiomasterclock.Themasterclockistheheartofanydigitalaudiosystem,howeverasallcomponentsthatareconstructedfrom physical materials, they will at some point in time deviate from their ideal generalized behaviourcausing, in this case variation in frequency and system jitter in this important internal timing reference.Typically,thesevariationswillnotbecorrectedfor,howeverinS8enableddevicesthesystemautomaticallyadaptstothesesmallfluctuationsresultinginperfect“glitch”freeanalogsoundevenafterendlesshoursofcontinuousplayback.Data-to-Systemsynchronizationallowsany incomingaudiostreamtoberesynchronizedandretimedtoalocalhighqualityclock.Byusingastableclockreference,thenegativeeffectsofinter-componentjittercanbe minimized. When converting the digital audio to an analog signal through high performance D/Aconverters, this reduction in jitter has enormous benefits in the level of detail and clarity in thereconstructedanalogsound.Combingthisprocesswithavirtualtimedomainmodelthatusesanadvancedcubic interpolation algorithm to resample the incoming audio data, timing errors in this signal can becompensatedforatamazinglevelsofaccuracy.Theresultisatighterandmorefocusedbass,anincreasedstereoimaging,aswellasclarityandseparationforallmusicalinstrumentsandvoices.

1.4 Sonic Scrambling

TheS8ModuleoutputstageisbasedontheSonicScrambling™,adatadistributiontechnologythatimproveslinearity inmulti-DAC designs. The idea of the Sonic Scrambling™ is to provide highest qualityDigital toAnalogconversionusing twoDAC'sper channel indifferentialmode.However, thekey is that the signalssenttobothDAC'sofagivenchannel(Data+andData-)areidentical.Theyareexactsignoppositesofeachotherwitha(lowlevel)randombiasingsignal,whichisrespectivelyaddedtoDAC+andDAC-tode-correlatethe signal’s LSBs from its content. By doing so, low-level signal linearity is enhanced, as these signalsreproducedbytheDACwillbeofrandomnature,thusspreadingpossiblesignalrelateddistortioneffects.

Figure1-2-SonicScramblingstandardoutputconfiguration

analogoutput

Data -

Data +

Sonic Scrambler

multi-DACdata

distribution

384kHzDAC #1

384kHzDAC #2

+

+

I-to-Vconverter

I-to-Vconverter

differentiallow-pass

filter

S8 Module D/A converters current summing Analog stage

(one single channel is shown)

+

-

-

++

-

+

-



1.5 DSD to PCM Conversion

TheS8ModulecanuseaDirectStreamDigital(DSD)audiostreamat2.8224MHzor3.072MHz(64x44.1kHzor48kHz),5.6448MHzor6.144MHz(128x44.1kHzor48kHz)asinputaudiosource.ADSDstreamisaone-bitdelta-sigmamodulateddigitalaudiosignalsampledinasequenceofveryhighfrequency.Thisformatisused to store audio on Super Audio Compact Disc (SACD) and is now popular on high-resolutionmusicavailable for download. Audio processing of the input DSD stream inside the S8Module is done by firstconverting the DSD data to PCM format thanks to the DSF™ Filtering, then using standard PCM audioprocessing techniques. The audio channel configuration supported by the S8Module is 2-channel stereoDSD.For seamless audio format integration, DoP (DSD over PCM) encoded input streams are automaticallydetected and decoded. Detection is based on the specific DoP marker code. Stereo DSD data are thenextractedfromthepseudoPCMdatastreamandsenttotheDSDtoPCMconverterunit.

1.6 DSF™ Filtering

Due to its veryhigh sampling rate (2.8224MHz,3.072MHz,5.6448MHzor6.144MHz) andone-bitnature,DSDisincompatiblewithalreadyimplementedsignalprocessingfunctionstargetingstandardPCMdata.TheDirectStreamFiltering (DSF™Filtering)algorithmconvertsDSDstreams toPCMup to8xFSwithsuperbquality.TheS8ModuleintegratesthisfeatureinordertosupplyveryhighaudioqualityfromaDSD64orDSD128audiostreamandthereforesignificantlyenhancesperformanceofanyaudioapplicationsusingthissingle-bitencoding.



2 Characteristics and Specifications

2.1 Electrostatic Discharge Warning

Many of the components in this product are subject to be damaged by electrostatic discharge (ESD).Customers are advised to observe proper ESD precautions when unpacking and handling the board,includingtheuseofagroundedwriststrapatanapprovedESDworkstation.Caution:FailuretoobserveESDhandlingproceduresmayresultindamagetothedevice.

2.2 Recommended Operating Conditions

Table2-1indicatestherecommendedconditionsunderwhichtheproductshouldrunproperly.

Parameter Recommend ConditionPower supply voltage 3.30V DC

Input signal voltage VIL (min/max) : 0.0V / 0.5V VIH (min/max) : 2.4V / 3.3V

Operating free-air temperature TA(min/max): 0°C / 60°C

Table2-1-recommendedoperatingconditions

2.3 Absolute Maximum Ratings

TheusershouldbeawareoftheabsolutemaximumoperatingconditionsfortheS8Module.Stressbeyondmaximumratingsmaycausepermanentdamagetothedevice.Table2-2summarizesthecriticaldatapoints.

Parameter Min. Max. Power supply voltage -0.30V 3.60V

Input signal voltage -0.30V 3.60V

Input current (any pins excepts supplies) -10mA +10mA

Output signal load impedance 180Ω -

Operating free-air temperature -20°C 60°C

Storage temperature -20°C 85°C

Table2-2-absolutemaximumratings

2.4 Electrical Specifications

Parameter Min. Typ. Max. DC supply voltage 3.10V 3.30V 3.60V

DC supply current 350mA 500mA

Input logic level high VIH 2.4V

Input logic level low VIL 0.5V

Input logic current -0.5mA 0.5mA

Output logic level high VIH VDD - 0.6V 3.10V VDD

Output logic level low VIL 0 0.2V 0.4V

Output logic current -15mA 15mA

Table2-3-electricalspecifications



2.5 Digital Audio Specifications

Parameter Min. Typ. Max. Master clock input frequency 24.5760MHz

PCM input resolution 16-bit 24-bit

PCM input sample rate 44.1kHz 384kHz

PCM input format I2S

DSD input frequency 2.8224MHz 6.144MHz

DSD input format 2-channel 1-bit DSD (direct stream digital)

PCM output format mono-framed left-justified mode / mono-framed right-justified mode

PCM output clocking master / slave

PCM output sample rate (1) 384kHz

Dynamic range 24-bit

THD+N -140dB -144dB -147dB

Table2-4–digitalaudiospecifications

2.6 Digital Filter Characteristics

Filter type N taps Norm. Fs Pass-band [x Norm. FS]

Stop-band [x Norm. FS] Ripple Att.

Linear Phase 160 2 0.454 0.546 0.005dB 160dB

Minimum Phase 160 2 0.454 0.546 0.005dB 146dB

Linear Phase Apodizing 160 2 0.41 0.501 0.005dB 160dB

Minimum Phase Apodizing 160 2 0.41 0.501 0.005dB 146dB

Linear Phase Short 84 2 0.371 0.546 0.005dB 160dB

Minimum Phase Short 84 2 0.371 0.546 0.005dB 146dB

Linear Phase Short Apodizing 84 2 0.325 0.498 0.005dB 160dB

Minimum Phase Short Apodizing 84 2 0.325 0.498 0.005dB 146dB

Table2-5–digitalfiltercharacteristics



2.7 Pin assignments

Figure2-1-pinassignments

2.8 Housing Dimensions

Figure2-2-housingdimensions



2.9 Pin descriptions

Pin # Name Type Description 1 VDD Power Digital core and I/O power supply: +3.30V

2 VDD Power Digital core and I/O power supply: +3.30V

3 RESET%%%%%%%%% Input Reset – active low, internal pull-up resistor

4 SPI_CS%%%%%%%%% Input Reset – active low, internal pull-up resistor

5 SPI_SCK Input Control port SPI clock

6 SPI_MOSI Input Control port SPI data input

7 SPI_MISO Output Control port SPI data output, open-collector, internal pull-up resistor

8 DGND Ground Digital core and I/O ground

9 CLKIN Input Master clock input

10 NC Do not connect Cut pin

11 DSP_MODE0 Input Output port data format Low: mono-framed left justified output mode High: mono-framed right justified output mode

12 DSP_MODE1 Input DSD/PCM input format Low: PCM or DoP input stream High: native DSD input stream

13 DSP_MODE2 Input Output port clock master/slave Low: master mode, BITCLK and FSYNC are outputs High: slave mode, BITCLK and FSYNC are inputs

14 DSP_MODE3 Input Data Valid flag – active low Low: incoming audio data stream is valid High: incoming audio data stream is not valid, output is muted

15 NC Do not connect Reserved for factory use


17 RX_WDCLK Input PCM serial audio input Word Clock Do not connect in DSD mode

18 RX_BITCLK Input PCM/DSD serial audio input Bit Clock

19 RX_SDATA0 Input PCM serial audio input stereo data DSD serial audio input left channel data

20 RX_SDATA1 Input DSD serial audio input right channel data

21 DNGD Ground Digital core and I/O ground

22 OUTR_FSYNC Input/Output Serial audio output Frame Sync for right channel

23 OUTR_BITCLK Input/Output Serial audio output Bit Clock for right channel

24 OUTR_SDATA0 Output Serial audio output data+ for right channel

25 OUTR_SDATA1 Output Serial audio output data- for right channel

26 DNGD Ground Digital core and I/O ground

27 OUTL_FSYNC Input/Output Serial audio output frame sync for left channel

28 OUTL_BITCLK Input/Output Serial audio output Bit Clock for left channel

29 OUTL_SDATA0 Output Serial audio output data+ for left channel

30 OUTL_SDATA1 Output Serial audio output data- for left channel


32 IRQ%%%%% Output Control port interrupt request – active low

Table2-6–pindescriptions



3 Interfacing and Operation

3.1 General Description

The S8 Module is a 2-channel, asynchronous digital data stream upsampler with D/A conversion errorminimizationandmulti-DACdatadistribution.OperationatPCMinputsamplingfrequenciesfrom44.1kHzto384kHz,DSDat2.8224MHzor5.6448MHzandoutputat384kHzare supported.Best-in-classdynamicrangeandTHD+Nareachievedbyemployingan innovativeupsamplingkernelwithbetter than147dBofimage rejection. Excellent low-level signal linearity and accuracy is provided by the Sonic Scrambling™technology,whichallowsdrivingupto2DAC'sperchannelconfiguredindifferentialmode.TheaudioinputportsupportstheI2Sstandardandthe2-channelDSDaudiodataformatwhiletheoutputportisconfiguredonmono-framedaudiodataformat.Inputwordlengthsfrom16-to24-bitaresupported.Input ports are operated in Slavemode, deriving their word and bit clocks from external input devices.Output ports are operated in Master mode allowing the incoming data stream to be re-clocked andsynchronizedaroundasinglehighqualitymasterclock,referredtoasDSSsynchronization. In theMastermodeoftheoutputports,theFSYNCandBITCLKclocksarederivedfromthesystemmasterclockCLKIN.TheS8Moduleincludesafour-wireSPIport,whichisusedtoaccesson-chipcontrolandstatusregistersinSoftware mode. The SPI port facilitates interfacing to microprocessors or digital signal processors thatsupportsynchronousserialperipherals. InHardwaremode,dedicatedcontrol flagsareprovided forbasicfunctions.Thesepinscanbehard-wiredordrivenbylogicorhostcontrol.Inadditiontothenormalcontrolinterfaces,theS8Moduleprovidesanartefact-freesoftmutefunctioninsoftwaremodeaswellasautomaticinputfrequencysensing.



3.2 Typical Connections

TheS8ModulecanbeoperatedinhardwaremodewherebytheSPIport(*)isnotneededtoconfigurethemodulebutrathertheFLAGpins.PleasenotethatsomefeaturesareaccessedonlybytheSPIportthereforehardwaremodeoffers reduced functionalities. Figure3-1 illustrates typical connexionswithdigital audioreceiver,ahostMCUandtwodualDAC’s.

Figure3-1-typicalconnexions

3.3 Interfacing to Digital Audio Receivers

Audio input and output ports are designed to interface to a variety of audio devices, including receiverscommonly used for AES/EBU and S/PDIF communications. Figure 3-2 illustrates the interface between aCirrusLogicWM8804receiverandtheS8inputportwherebytheS8ModuleworksasSlaveandthereceiverasMaster.Careful impedance matching must be maintained between drivers, transmission lines and receivers tominimizesignalovershoot,undershootorringing.Figure3-2showssourcedamping-resistorterminationsof33Rasanexample.Properimpedancematchingandterminationdependsupondesignandlayout.

Figure3-2-interfacingwithadigitalreceiver

S8 Module

dual D/A converter

dual D/A converter

FSYNCBITCLKSDATA0SDATA1

FSYNCBITCLKSDATA0SDATA1

digital audio

receiver

WDCLKBITCLKSDATA0SDATA1DATA VALID

RX A

UDIO

PO

RT

LEFT

-CHA

NNEL

TX A

UDIO

PO

RTRI

GHT

-CHA

NNEL

TX A

UDIO

PO

RT

CO

NTRO

L PO

RT

host processor

MODE0MODE1MODE2SPI_CS(*)SPI_SCK(*)SPI_MISO(*)SPI_MOSI(*)IRQ(*)RESET

low-jitterhigh quality

master clock

S8 Module

RX_WDCLK

WM8804

LRCLKBCLKDOUT

GP0 (GEN_FLAG)

RX_BITCLKRX_SDATA0RX_SDATA1

DSP_MODE3

DSP_MODE1

33R33R33R

DATA VALID



Inthiscase,DSP_MODE1islowforPCMandDoPinputsupport.ADoPencodedstreamwillbeseenbythedigitalaudioreceiverasaPCMdataflow,buttheS8ModulewilldetectitandextractDSDdata.DSP_MODE3isusedformutingtheS8outputwhenthereceiverisunlockedortransmittingnon-audiodata.

3.4 Interfacing to D/A Converters

TheS8Moduleisdesignedspecificallytodrivefourhighperformance384kHzD/Aconverters.Connectionto fourDAC's is illustrated inFigure3-3. In thatcase theS8worksasMasterandtheDAC'sasSlave.Thepairs IDAC_LEFT+/IDAC_LEFT- and IDAC_RIGHT+/IDAC_RIGHT- represent respectively the analogdifferential current outputs for left and right channels. Figure 3-3 illustrates connexionswith PCM1794AfromTexas Instruments Incorporated, but otherDACmodels from variousmanufacturers, or any similarproprietarysolutionscanbeimplementedbyapplyingthesameconcept.

Figure3-3-interfacingtoD/Aconverters

TheS8isconfiguredformono-framedrightjustifiedoutput,Mastermode.ThePCM1794AD/AconverterisconfiguredforExternalDigitalFilter(InternalDFBypassMode)inmonauralmode.Master clockdistributionmustbe carefullydesigned tominimise jitter.Best result isusually achievedbyusingaclockfan-outbufferandpoint-to-pointconnexionstoeachdevicewithproperimpedancematching.

S8 Module

DSP_MODE2DSP_MODE0+3.3V

33R33R33R33R

Output ports configuration:- right justified- master mode

OUTL_FSYNCOUTL_BITCLKOUTL_SDATA0OUTL_SDATA1

OUTR_FSYNCOUTR_BITCLKOUTR_SDATA0OUTR_SDATA1

33R33R33R33R

PCM1794A

LRCKBCKDATASCK

PCM1794A

LRCKBCKDATASCK

PCM1794A

LRCKBCKDATASCK

PCM1794A

LRCKBCKDATASCK

24.576MHzoscillator

and fan-out buffer

CLKIN

Master Clock IOUTL+IOUTL-

IOUTR+IOUTR-

IOUTL+IOUTL-

IOUTR+IOUTR-

IOUTL+IOUTL-

IOUTR+IOUTR-

IOUTL+IOUTL-

IOUTR+IOUTR-

IDAC_LEFT_P

IDAC_LEFT_N

IDAC_RIGHT_P

IDAC_RIGHT_N



Figure3-4herebelowshowsanFFTplotachievedwithanimplementationoftheS8ModulewithfourmonoDACs.Measurementconditions: 24-bit48kHzPCMI2Sinputsignal 1kHz0dBFSsinewave Balancedanalogoutput,4VRMS PrismeD-ScopeIIIaudioanalyser,20Hz–20kHzbandwidth

Figure3-4-FFTmeasurementexample

3.5 Reference Master Clock

TheS8Modulerequiresa low-jittermasterclock foroperation.Thisclockmustbesuppliedat theCLKINinput(pin9)directlyfromanexternalcrystaloscillatororbyaclockbuffer.TheS8Moduleisdesignedtoworkwithasinglefrequencyat24.5760MHz.Asaresult,alltheaudiooutputsamplingfrequencieswillbederivedfromamultipleof48kHz.Themasterclocksignalmustbecarefullyroutedtominimisejitter.Apoint-to-pointconnectionwithproperimpedancematchingisrecommended.

3.6 Reset and Power On

TheS8ModulemayberesetusingtheRESET%%%%%%%%%input(pin3).Ithastobeheldlowforaminimumof500nstoguaranty a proper reset. TheRESET%%%%%%%%%has an internal pull-up resistor. Furthermore, the S8 integrates aninternalpower-onresetmanagement,sotheuserdoesn’tneedtoforcearesetsequenceafterpowerupinordertoinitializethemodule.Oncethereset isreleased,thereisa400msdelayforthemoduletobeoperational. Insoftwaremode,thehost MCU must observe this delay before attempting to write to the SPI port due to internal logicrequirements.



3.7 Audio Serial Input Port (RX)

TheRXaudioinputportisafour-wiresynchronousserialinterfaceworkinginSlavemode.InPCMmode,theport uses three signals, namely RX_WDCLK (pin 17), RX_BITCLK (pin 18) and RX_SDATA0 (pin 19).RX_WDCLK provides the frame synchronization clock while RX_DATA0 and RX_BITCLK are used torespectively transfer the serial audio data and clock the serial data into the port. This latter supportssamplingfrequenciesupto384kHz.Theaudiodatawordlengthmaybeupto24bitandtheaudiodata isalwaysbinarytwo’scomplementwiththeMSBfirst.InDSDmode,threesignalsoutoffourareused,RX_BITCLK(pin18),RX_SDATA0(pin19)andRX_SDATA1(pin20)pins.RX_BITCLKprovides theDSD clock synchronization (2.8224MHz, 3.072MHz, 5.6448MHzor6.144MHz)whileRX_SDATA0andRX_SDATA1are respectively the left andright channeldata.Figure3-5illustratestheaudiodatastreamofeachmode.Insoftwaremode,theInputControlRegisterallowstoselecttheinputaudiodataformatmode.Twobitsareusedtochoosethemode,namelyFMT0andFMT1.TheconfigurationintheInputControlregisterisOR-edwiththeDSDInputpinDSP_MODE1.

Inhardwaremode,itistheDSDInputpinDSP_MODE1thatallowstheinputaudiodataformatmodetobeconfigured.WhenDSDInputpinishigh,theDSDmodeisselectedasopposedtolowwherethePCMmodeisenabled.DoPdataandclockingisequivalenttoPCM,thereforeDSP_MODE1mustbelowforDoPstream.

Figure3-5-audioinputportdataformat



3.8 Audio Output Ports (OUTL and OUTL)

The OUTL and OUTR audio output ports are four-wire synchronous serial interfaces working inMaster/SlavemodeandtheyareconfiguredinamonodataformatcalledhereMonoFramedDataFormat.OUTL_SDATA0(pin29)andOUTL_SDATA1(pin30)outputsaretheupsampledPCMserialdataoutputsfortheleftchannel.OUTR_SDATA0(pin24)andOUTL_SDATA0(pin25)outputsaretheupsampledPCMserialdataoutputsfortherightchannel.TheOUTL_BITCLK(pin28)andOUTR_BITCLK(pin23)areconfiguredasoutputsinMastermodeorinputinSlave mode, they operate at a rate of 32x FSYNC. The left/right word clocks referred to as frame sync,OUTL_FSYNC(pin27)andOUTR_FSYNC(pin22),arealsoconfiguredasoutputpinsinMastermodeorinputpinsinSlavemodeandtheyaresettooperateatrate8xFS.

Figure3-6-MonoFramedDSPMode

The audio output ports are configured either inMonoFramed DSPMode orMonoFramed Right-JustifiedMode.Theaudiodatawordlengthissetto32-bit.TheaudiodataisalwaysBinaryTwo’sComplementwiththeMSBfirst.RefertoFigure3-6andFigure3-7fortheoutputdataformats.

Figure3-7-MonoFramedRight-JustifiedDSPMode



3.9 Data Resolution and Dither

WhenusingtheserialaudioinputportinI2Smode,allinputdataisprocessedas32-bitwide.Anyaudiodatawidth truncation (compared to theoriginalaudiodatasource),performedprior to theS8Module, shouldhavebeendoneusinganappropriateditheringprocess.ThereisnoditheringmechanismontheinputsideoftheS8Module,socaremustbetakentoensurethatnotruncationoccurs.Theaudiooutputportsaresetto32-bit.

3.10 Incoming Sampling Rate and Locking

WhentheS8Moduleprocessestheincomingaudiodatastream,itcalculatestheratiobetweentheinputandoutputsampleratesandusesthisinformationtosetupvariousinternalparameters.InPCMinputmode,theS8Moduleaccepts standardsampling frequenciesof32,44.1,48,88.4,96,176.4, 192,352.8and384kHzwitha±2%deviationfromthenominalvalue.WhereasinDSDinputmode,theS8Moduleacceptssamplingfrequenciesof2.8224,3.072,5.6448and6.144MHzwitha±2%deviationfromthenominalvalue.Ifanon-standardinputsamplingfrequencyisfoundorthestandardsamplingratedeviatesmorethan2%fromthenominalvalue,theS8ModulewillNOTprocesstheincomingdataandwillbeastatusofunlocked.The S8 Module can dynamically compensate for drift and fluctuations in the incoming input samplingfrequencywhere theprocessingwill track the incoming sample rate and automatically adjust the samplerateconversionprocessinordertomaintainthehighestlevelofaudioquality.InSoftwaremode,InputControlRegisterfunctionsasstatusregisters,whichcontainstheinputfrequencysamplingdetected.The INTREQpin reflects the lockstateof themodule. If there isa change in the inputsamplingratetheINTREQsignalgoeslowtoindicateanunlockstateuntiltheS8Modulereacquiresavalidratio.Atthispoint,theINTREQwilltransitionhigh.



3.11 Muting

The OUTx_SDATA0, OUTx_SDATA1, OUTx_BITCLK and OUTx_FSYNC pins are all low (hard mute) whenmoduleiseitherinresetstateorunlocked(noaudiosourceorDataValidflaghigh).ThesepinsbecomevalidassoonastheS8Modulegetslocked.Whenthemoduleislocked,OUTx_SDATA0,OUTx_SDATA1pinscanbesettoallzerobyapplyingasoftmutethroughtheconfigurationofthe“Mute”bitintheSPIprocesscontrolregister.InthiscaseOUTx_BITCLKandOUTx_FSYNCarestillactive.Thus, inhardwaremode,onlytheDataValid flagpincanbeusedwhereas insoftwaremode,therearetwowaystoputthemoduleinmute,whicharetheDataValidflagorthe“Mute”bitintheSPIregister.

3.12 Phase Inversion

TheS8Moduleincludesaphaseinversionfunctionwherebytheoutputdatacanbeinvertedcomparedwithaudioinputsignal.Bydefault,thisfunctionisdisabledandcanonlybeenableinsoftwaremode.Theselectedconfiguration can be changed through the LSB bit called PHI of the Process Control Register. All otherfeaturesofthemoduledon’taffectthisfunction.

3.13 Stereo DSD to PCM Conversion

TheS8ModuleincludesastereoDSDtoPCMconverter.ThisgivesthepossibilityofconnectingaDSDinputstreamon theRX input port andusing this streamasmain audio source. The selection of theDSD inputformat is done by settingDSP_MODE1 pin in hardware. In softwaremode, the FMT bits in Input controlregisterallowstoenabletheDSDinputformat.As described in chapter 3.7 “Audio Serial Input Port (RX)”, the RX audio input port is a four-wiresynchronous serial interface that is configured to operate in SlaveMode.Only three out of four lines areused.TheRX_SDATA0andRX_SDATA1linesaretheserialaudiodatainputsforDSDleftandrightchannelsrespectively.DSDdataformatis1bitstream,thereforenoframesynchisneeded.DoP(DSDoverPCM)isreceivedbytheinputportRXasaPCMstreamandaccordinglyDSP_MODE1mustbelow.DoPencodedinputstreamisautomaticallydetectedbythePCMinputunitaccordingtothespecificDoPmarkercode.StereoDSDdataarethenextractedfromthepseudoPCMdatastreamandsenttotheDSDtoPCMconverterunit.

3.14 Digital Filter Selection

The S8 Module implements an enhanced version of the patented Q5 Upsampling technology. It offers achoiceof8digitalfiltertypes,whichselectioncanbeaccessinSoftwareModeonly.RefertoTable2-5foracomparisonofthefilterscharacteristics.Linear Phase filter only affects signal amplitude. The phase response of the filter is a linear function offrequencyandconsequentlythereisnophasedistortion.However,suchfilterresponseintroducesmoderateamountofpre-ringingandpost-ringingasshowninFigure3-8.Figure3-9illustratesaMinimumPhasefilter.Thisfiltertypeonlyaddspost-ringingartefacts,butshowsahigher amount of post-ringing than that of a Linear Phase filter with the same frequency response.Furthermore,MinimumPhasefiltersintroduceaslightphaseshiftthatincreaseswithfrequency.ApodizingfiltersaredesignedforafullattenuationattheNyquistfrequencyinordertoavoidanyaliasingartefacts.Thecut-offfrequencyisslightlylowercomparedtoanon-apodizingfilter.Filter taps represent thenumberof samplesused in theFIRdelaychain.160 taps filtersprovide sharpertransitionbandbutintroducelongerpre/postringing.



Figure3-8–ResponseofaLinearPhaseApodizingfilterwith160taps

Figure3-9-ResponseofaMinimumPhasefilterwith160taps

3.15 Data Valid flag (DSP_MODE3)

The S8 Module uses the Data Valid flag (DSP_MODE3) input pin to know whether it should attempt tosynchronizewiththeincomingaudiodatastream.IftheDataValidflagishigh,thenthemodulewillneverattempttolockandtheoutputswillbehardmuted.IftheDataValidflagislow,thenthemodulewillattempttofindtheinputsamplingfrequencyandprocesstheaudiodataaslongastheyarevalid.TheINTREQpincanbeusedtotrackthemodulestate(lock/unlock).



3.16 Serial Port Interface (SPI Port)

TheSPIportistheinterfaceusedtooperatetheS8Moduleinsoftwaremode.ThisportallowsthesystemhostMCUtoaccessS8Moduleinternalregistersforreadandwriteoperations.ThehostMCUisreferredastheMasterDeviceandtheS8ModuleisreferredasSlaveDevice.The operation of the SPI port may be completely asynchronous with respect to the audio stream rates.However,itisrecommendedtokeeptheportpinsstaticifnooperationisrequired.The SPI port is a four-wires serial interface whereSPI_CS%%%%%%%%%(active low) is the module chip select signal,SPI_SCKisthecontrolportbitclock(inputintothemodulefromtheMasterDevice),SPI_MOSIistheinputdatalinefromMasterDeviceandSPI_MISOistheoutputdatalinetotheMasterDevice.DataisclockedinontherisingedgeofSPI_SCKandclockedoutonthefallingedge.

Figure3-10-SPIprotocolforregisterread/writeoperations



Table3-1andFigure3-10illustratetheoperationoftheSPIportaswellastheprotocolforregisterreadandwriteoperations.

Byte Name MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Header Byte 0 0 0 RW 0 A2 A1 A0

Data Byte D7 D6 D6 D4 D3 D2 D1 D0

Table3-1-SPIbytedefinitionforregisterread/writeoperations

A2–A0 RegisteraddressselectionRW Read/Writecontrol 0: RegisterRead 1: RegisterWriteD0–D7 Registerdata



4 Hardware Mode


TheS8Modulecanwork inhardwaremodewhichallows thedevice tooperatewithoutahost systemorserialcommunicationontheSPIport.ThedeviceisconsideredinHardwaremodewhentheMD_CSpinisleftunconnectedorpulledupwitha resistor (10kΩ) toVDD. In thismode, themodule starts inadefaultconfiguration.However,thefourDSP_MODExpinsremainvalidandareusedforsettingtheS8Moduleinthecorrectoperationmode.

4.2 Hardware Configuration

To work in hardware mode, the SPI port can be left unconnected. DSP_MODEx pins are described herebelow.

Pin # Name Type Description 11 DSP_MODE0 Input Output port data format

12 DSP_MODE1 Input DSD/PCM input format

13 DSP_MODE2 Input Output port clock master/slave

14 DSP_MODE3 Input Data Valid flag – active low

Table4-1-DSP-MODExhardwarecontrolsummary

DSP_MODE0 Outputportdataformat 0: mono-framedleftjustifiedoutputmode 1: mono-framedrightjustifiedoutputmodeDSP_MODE1 DSD/PCMinputformat 0: PCMorDoPinputstream 1: nativeDSDinputstreamDSP_MODE2 Outputportclockmaster/slave 0: mastermode,BITCLKandFSYNCareoutputs 1: slavemode,BITCLKandFSYNCareinputsDSP_MODE3 DataValidflag 0: incomingaudiodatastreamisvalid 1: incomingaudiodatastreamisnotvalid,outputismuted



5 Software Mode


TheS8Modulesoftwaremoderequests thedevicetooperatewithahostsystemhavinganSPIport.ThismodeallowsthehostsystemtoconfigureorreadinformationfromtheS8ModulebyaccessingitsinternalregistersthroughtheSPIport(seechapter3.16“SerialPortInterface(SPIPort)”forfurtherdetailsonSPIoperational port). The following chapters give details and bits definition of each register aswell as theirdefaultsettingafterreset.S8ModuleRegistersOverview

Addr Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 Input Status SFMT0 x XFS3 XFS2 XFS1 XFS0 FMT1 FMT0

0x01 Filter Control x x x x x FLT2 FLT1 FLT0

0x02 Process Control x x x x x DATA MUTE PHI

0x03 Level Attenuator Left LCL7 LCL6 LCL5 LCL4 LCL3 LCL2 LCL1 LCL0

0x04 Level Attenuator Right LCR7 LCR6 LCR5 LCR4 LCR3 LCR2 LCR1 LCR0

0x05 Scratch Register SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0

0x06 Software Revision REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0

0x07 Product ID ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

0x08 Reserved for factory use - - - - - - - -

0x09 Sub Product ID SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

0x0A Reserved for factory use - - - - - - - -

0x0B DC Offset Left DCL7 DCL6 DCL5 DCL4 DCL3 DCL2 DCL1 DCL0

0x0C DC Offset Right DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0

Table5-1–registermap

5.2 Input Status Register

Registeraddress:0x00

MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name SFMT0 x XFS3 XFS2 XFS1 XFS0 FMT1 FMT0

Access type R R R R R R R R

Default value 0 0 0 0 0 0 0 0 FMT1..0 InputFormat 00: I2S 01: reserved 10: reserved 11: DSDXFS3..0 InputSamplingFrequency 0000: Unlock 0001: 32kHz 0010: 44.1kHz



0011: 48kHz 0100: 88.2kHz 0101: 96kHz 0110: 176.4kHz 0111: 192kHz 1000: 352.8kHz 1001: 384kHzSFMT0 InputSubFormat 0: PCM 1: DoP(PCMframecontainingencapsulatedDSDdata)

5.3 Filter Control Register


MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name x x x x x FLT2 FLT1 FLT0

Access type R/W R/W R/W R/W R/W R/W R/W R/W

Default value 0 0 0 0 0 0 1 0 FLT2..0 Oversamplingfilterselection 000: Linearphase160taps 001: Minimumphase160taps 010: Linearphaseapodizing160taps 011: Minimumphaseapodizing160taps 100: Linearphase84taps 101: Minimumphase84taps 110: Linearphaseapodizing84taps 111: Minimumphaseapodizing84taps

5.4 Process Control Register


MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name x x x x x DATA MUTE PHI


Default value 0 0 0 0 0 0 0 0 PHI PhaseInversion 0: PhaseinversionOFF 1: PhaseinversionONMUTE Audiooutputportsmute 0: MuteOFF 1: MuteONDATA DataInputMode 0: 352.8kHz/384kHzPCMinputstreamusestwodatalines



1: 352.8kHz/384kHzPCMinputstreamusesonesingledataline

5.5 Level Attenuator Left Channel Control Register


MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name LCL7 LCL6 LCL5 LCL4 LCL3 LCL2 LCL1 LCL0


Default value 0 0 0 0 0 0 0 0 LCL7..0 Levelattenuatorforleftchannel 0: 0.0dB 1: -0.5dB 2: -1.0dB … 253: -126.5dB 254: -127.0dB 255: Mute

5.6 Level Attenuator Right Channel Control Register


MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name LCR7 LCR6 LCR5 LCR4 LCR3 LCR2 LCR1 LCR0


Default value 0 0 0 0 0 0 0 0 LCR7..0 Levelattenuatorforrightchannel 0: 0.0dB 1: -0.5dB 2: -1.0dB … 253: -126.5dB 254: -127.0dB 255: Mute

5.7 Scratch Register


MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0


Default value 0 0 0 0 0 0 0 0 SCR7..0 Scratchregisterfordebuggingpurpose



5.8 Software Revision Register


MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0


Default value - - - - - - - - REV7..4 MajorrevisionREV3..0 Minorrevision

5.9 Product ID Register


MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0


Default value 0 0 0 0 0 1 0 0 ID7..0 ProductIDcode Permanentlysetto0x04forbackwardcompatibilitywithSonic2Module

5.10 Product Sub-ID Register


MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0


Default value 0 0 0 0 1 0 0 0 SID7..0 ProductSUB-IDcode Permanentlysetto0x08forS8Module



5.11 DC Offset Left Channel Control Register

Registeraddress:0x0B

MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name DCL7 DCL6 DCL5 DCL4 DCL3 DCL2 DCL1 DCL0


Default value 0 0 0 0 0 0 0 0 DCL7..0 DCoffsetforleftchannel Signedintegernumberwith0.5mVsteps 0: 0.0mV 1: 0.5mV 2: 1.0mV … 255: -0.5mV 254: -1.0mV 253: -1.5mV …

5.12 DC Offset Right Channel Control Register

Registeraddress:0x0C

MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit name DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0


Default value 0 0 0 0 0 0 0 0 DCL7..0 DCoffsetforrightchannel Signedintegernumberwith0.5mVsteps 0: 0.0mV 1: 0.5mV 2: 1.0mV … 255: -0.5mV 254: -1.0mV 253: -1.5mV …



6 Related products

6.1 Backward Compatibility

TheS8ModuleofferssimilarfunctionalityasthepreviousEdelS2UpsamplerModuleandhasbeendesignedwithbackwardcompatibility inmind.Thereforproductsusing theEdelS2willworkwith theS8withoutrequiring any redesign effort. Compatibility consideration between the Edel S2 and the S8 Modules aredetailedherebelow:

• Identicalhousingandpin-out• Identicalfunctionality• Similarelectricalspecifications• Hardwaremodecontrolisidentical• Softwaremodecontroloffersthesameregistersandaddsmoreoptions• TheS8offersincreasedcalculationpowerandenhancedprocessingalgorithmsforbettersound

quality

6.2 Q8 Upsampler Module

The Q8Module shares the software and hardware technology with the S8 Module, but is optimized forprojectsrequiringadown-sampledoutput.Thefirstdigitalaudiooutputportprovidesup-sampleddataat384kHzfordrivingadual-DACsystem.Theseconddigitalaudiooutputportprovidesadirectdown-sampledstreamconfigurablefor1xFS(48kHz),2xFS(96kHz)or4xFS(192kHz)operation.TheQ8ModuleisbackwardcompatiblewiththepreviousEdelQ5upsamplerModule.

6.3 Custom applications

The S8 Module is based on a modern digital platform which runs engineered’s software framework fordigital audio processing. This core system can be used for many custom applications where specificprocessingisrequired:

• Cross-over• Time/phasecorrection• Equalization• Compensationforloudspeakercharacteristics• Etc.

Please checkourweb site formore information and contactus fordevelopmentof customsolutions thatmeetsyourproductrequirements.

Documents

S8 QUAD DAC UPSAMPLER · S8 QUAD DAC UPSAMPLER 7/31 engineered SA - Switzerland doc. v.153e/rev. Oct-18 1 Introduction 1.1 Highlights The S8 Module is an ultra-high performance Quad