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1 Ryan Kastner ASIC/SOC, September 2000 Coupling Aware Routing Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer Engineering Northwestern University

Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

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Page 1: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

1

Ryan Kastner

ASIC/SOC, September 2000

Coupling Aware RoutingCoupling Aware RoutingCoupling Aware RoutingCoupling Aware Routing

Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh

Department of Electrical and Computer Engineering

Northwestern University

Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh

Department of Electrical and Computer Engineering

Northwestern University

Page 2: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

2

Ryan Kastner

ASIC/SOC, September 2000

OutlineOutlineOutlineOutline

Coupling Definition Effects

Coupling-Free Routing Definition Uses

Algorithms for Coupling-Free Routing Greedy Forcing

Results Conclusion

Coupling Definition Effects

Coupling-Free Routing Definition Uses

Algorithms for Coupling-Free Routing Greedy Forcing

Results Conclusion

Page 3: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

3

Ryan Kastner

ASIC/SOC, September 2000

CouplingCouplingCouplingCoupling

Definition - capacitance between adjacent wires Deep submicron trends:

Interconnect has more dominant role Scale wire height at slow rate compared to width

Definition - capacitance between adjacent wires Deep submicron trends:

Interconnect has more dominant role Scale wire height at slow rate compared to width

Coupling can account for up to 70% of interconnect capacitance even in .25 micron designsCoupling can account for up to 70% of interconnect capacitance even in .25 micron designs

Page 4: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

4

Ryan Kastner

ASIC/SOC, September 2000

Effects of couplingEffects of couplingEffects of couplingEffects of coupling Delay deterioration

Total capacitance seen by a gate is no longer a constant value Causes uncertainty in delay calculation

Crosstalk Noise caused by coupling Leads to circuit failure and increased delay

Delay deterioration Total capacitance seen by a gate is no longer a constant value Causes uncertainty in delay calculation

Crosstalk Noise caused by coupling Leads to circuit failure and increased delay

Ce= 0Ce= 0 Ce= 2Cc Ce= 2Cc

aggressor

victim

Page 5: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

5

Ryan Kastner

ASIC/SOC, September 2000

Interconnect delayInterconnect delayInterconnect delayInterconnect delay

resistivity of the conductor = insulator dielectric constantw,t,h = conductor’s width, thickness and separationl, s = coupled length and spacing of interconnect

During routing, we can control l and s

resistivity of the conductor = insulator dielectric constantw,t,h = conductor’s width, thickness and separationl, s = coupled length and spacing of interconnect

During routing, we can control l and s

Page 6: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

6

Ryan Kastner

ASIC/SOC, September 2000

How can we avoid coupling?How can we avoid coupling?How can we avoid coupling?How can we avoid coupling?

Interconnect spacing Increasing the spacing between wires can reduce coupling Much work on this subject (Wong @ U. Texas, Cong @ UCLA)

Coupled interconnect length Coupling directly depends on the parallel length of adjacent

wires Route wires to avoid long parallel overlaps

Interconnect spacing Increasing the spacing between wires can reduce coupling Much work on this subject (Wong @ U. Texas, Cong @ UCLA)

Coupled interconnect length Coupling directly depends on the parallel length of adjacent

wires Route wires to avoid long parallel overlaps

HighlycoupledHighlycoupled No couplingNo coupling

Page 7: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

7

Ryan Kastner

ASIC/SOC, September 2000

Simplify definition of couplingSimplify definition of couplingSimplify definition of couplingSimplify definition of coupling

Two wires couple if the segments forming them are closer than d units for more than l units

Two wires couple if the segments forming them are closer than d units for more than l units

distance < ddistance < dlength > llength > l

Two wires couple if distance < d AND length > l

Otherwise, they do not couple

Two wires couple if distance < d AND length > l

Otherwise, they do not couple

Page 8: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

8

Ryan Kastner

ASIC/SOC, September 2000

Coupling-Free Routing (CFR)Coupling-Free Routing (CFR)Coupling-Free Routing (CFR)Coupling-Free Routing (CFR)

Given a set of nets S={Ni={(x1i,y1i),(x2i,y2i)} | 1 i n} S is coupling-free if there is a single bend layout for

every net such that no two routes couple

Given a set of nets S={Ni={(x1i,y1i),(x2i,y2i)} | 1 i n} S is coupling-free if there is a single bend layout for

every net such that no two routes couple

Coupled layoutCoupled layout Coupling-free layoutCoupling-free layout

Page 9: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

9

Ryan Kastner

ASIC/SOC, September 2000

Usefulness of CFRUsefulness of CFRUsefulness of CFRUsefulness of CFR

Minimum interconnect delay Single bend routing insures minimum wirelength Introduces only one via Coupling between nets is minimized

Increases predictability of routes Allows accurate prediction of wirelength, congestion, etc Predictable Routing, ICCAD 2000

Speeds up single net routing process

Minimum interconnect delay Single bend routing insures minimum wirelength Introduces only one via Coupling between nets is minimized

Increases predictability of routes Allows accurate prediction of wirelength, congestion, etc Predictable Routing, ICCAD 2000

Speeds up single net routing process

Page 10: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

10

Ryan Kastner

ASIC/SOC, September 2000

Usefulness of CFR-Detailed RoutingUsefulness of CFR-Detailed RoutingUsefulness of CFR-Detailed RoutingUsefulness of CFR-Detailed Routing

As fabrication technology progresses, routing layers become more plentiful

Reserving layers for critical nets is common Power, ground and clock are already routed on preferred layers

Use preferred layers for critical nets Layer can be used for timing critical nets Critical nets have little “slack” - need minimum delay CFR insures that nets have minimum delay

minimum wirelength minimum number of vias minimum coupling

As fabrication technology progresses, routing layers become more plentiful

Reserving layers for critical nets is common Power, ground and clock are already routed on preferred layers

Use preferred layers for critical nets Layer can be used for timing critical nets Critical nets have little “slack” - need minimum delay CFR insures that nets have minimum delay

minimum wirelength minimum number of vias minimum coupling

Page 11: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

11

Ryan Kastner

ASIC/SOC, September 2000

Usefulness of CFR-Single Layer Usefulness of CFR-Single Layer Usefulness of CFR-Single Layer Usefulness of CFR-Single Layer

Single layer routing is a important problem for routing Area routers often use single layer routing for each layer Printed Circuit Board (PCB) use single layer algorithms

Best known academic single layer router (developed by Lin and Ro) uses two step process

Find a maximum planar set of one-bend nets Use rubberband equivalent to route remaining nets

CFR can be easily be incorporated into in first step to

produce a planar set of nets with minimum coupling

Single layer routing is a important problem for routing Area routers often use single layer routing for each layer Printed Circuit Board (PCB) use single layer algorithms

Best known academic single layer router (developed by Lin and Ro) uses two step process

Find a maximum planar set of one-bend nets Use rubberband equivalent to route remaining nets

CFR can be easily be incorporated into in first step to

produce a planar set of nets with minimum coupling

Page 12: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

12

Ryan Kastner

ASIC/SOC, September 2000

Usefulness of CFR-Global routingUsefulness of CFR-Global routingUsefulness of CFR-Global routingUsefulness of CFR-Global routing

Coupling at global routing is hard to determine Routes are not exact, makes it difficult to know adjacency

relations of nets Detailed router will often make local changes

Global routing allows global changes, it is next to impossible to make global changes at the detailed stage

A coupling-free global layout will produce a coupling-free detailed layout

Coupling at global routing is hard to determine Routes are not exact, makes it difficult to know adjacency

relations of nets Detailed router will often make local changes

Global routing allows global changes, it is next to impossible to make global changes at the detailed stage

A coupling-free global layout will produce a coupling-free detailed layout

Page 13: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

13

Ryan Kastner

ASIC/SOC, September 2000

MAX-CFL DefinitionMAX-CFL DefinitionMAX-CFL DefinitionMAX-CFL Definition

Given a set of two-terminal nets S and a positive integer K |S|. Is there a single bend routing for at least K nets such that no two routings couple?

Additional routing constraints can easily be added Routed nets must be planar Routed nets must be routed on two layers

MAX-CFL for planar layouts is NP-Complete General MAX-CFL NP-Complete?

Given a set of two-terminal nets S and a positive integer K |S|. Is there a single bend routing for at least K nets such that no two routings couple?

Additional routing constraints can easily be added Routed nets must be planar Routed nets must be routed on two layers

MAX-CFL for planar layouts is NP-Complete General MAX-CFL NP-Complete?

Page 14: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

14

Ryan Kastner

ASIC/SOC, September 2000

AlgorithmsAlgorithmsAlgorithmsAlgorithms

We developed two algorithms Greedy Forcing

Algorithms try to maximize number of nets routed and/or criticality of routed nets

We developed two algorithms Greedy Forcing

Algorithms try to maximize number of nets routed and/or criticality of routed nets

Page 15: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

15

Ryan Kastner

ASIC/SOC, September 2000

CriticalityCriticalityCriticalityCriticality

Most often defined as the amount of timing slack available for the net

Slack values given gates, nets during logic synthesis stage Delay through a network of gates and wires must not exceed

clock frequency

Most often defined as the amount of timing slack available for the net

Slack values given gates, nets during logic synthesis stage Delay through a network of gates and wires must not exceed

clock frequency

Flip Flop

gate

gate

gateFlip Flop

networknetwork

DSM increases for need interconnect timing slack DSM increases for need interconnect timing slack

Page 16: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

16

Ryan Kastner

ASIC/SOC, September 2000

Results in terms of criticalityResults in terms of criticalityResults in terms of criticalityResults in terms of criticality

Benchmarks do not have criticality data

We used wire length for criticality Delay increases at rate:

O(l2) without wiresizing O(ll) with optimal wiresizing O(l) with proper buffer insertion

We ran experiments using each function as criticality

Benchmarks do not have criticality data

We used wire length for criticality Delay increases at rate:

O(l2) without wiresizing O(ll) with optimal wiresizing O(l) with proper buffer insertion

We ran experiments using each function as criticality

Criticality functions: Quadratic (l2), l-root-l (l l) and linear (l) functions

Criticality functions: Quadratic (l2), l-root-l (l l) and linear (l) functions

Page 17: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

17

Ryan Kastner

ASIC/SOC, September 2000

Greedy AlgorithmGreedy AlgorithmGreedy AlgorithmGreedy Algorithm

1 Given a set of nets N

2 Sort N by criticality (largest smallest)

3 for each net n N

4 do route n in upper-L or lower-L, if possible

Simple and fast; Running time is O(n log n)

1 Given a set of nets N

2 Sort N by criticality (largest smallest)

3 for each net n N

4 do route n in upper-L or lower-L, if possible

Simple and fast; Running time is O(n log n)

Page 18: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

18

Ryan Kastner

ASIC/SOC, September 2000

Forcing algorithmForcing algorithmForcing algorithmForcing algorithm

In order to avoid coupling, a routing of a net forces another net into a particular route

In order to avoid coupling, a routing of a net forces another net into a particular route

Net 1Net 1

Net 2Net 2 To avoid coupling

Net 2 must be lower-L

To avoid coupling

Net 2 must be lower-L

Net 1Net 1

Net 2Net 2

An lower-L routing of Net 1 forces a lower-L routing of Net 2An lower-L routing of Net 1 forces a lower-L routing of Net 2

Page 19: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

19

Ryan Kastner

ASIC/SOC, September 2000

Forcing AlgorithmForcing AlgorithmForcing AlgorithmForcing Algorithm

1 Given a set of net N2 Determine the forcing interactions between the nets N3 R NULL4 for each net n N5 do R R U n.upper-L U n.lower-L6 Sort R by number of forcings (smallest largest)7 for each routing r R8 do if net associated with r is unrouted and r is

routable9 then route r

1 Given a set of net N2 Determine the forcing interactions between the nets N3 R NULL4 for each net n N5 do R R U n.upper-L U n.lower-L6 Sort R by number of forcings (smallest largest)7 for each routing r R8 do if net associated with r is unrouted and r is

routable9 then route r

Running time is O(n2)Running time is O(n2)

Page 20: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

20

Ryan Kastner

ASIC/SOC, September 2000

EvaluationEvaluationEvaluationEvaluation

Find the x “most critical” nets in each circuit Vary x from 25 to 250 Perform algorithms on the x nets Gathered statistics from each layout

Percentage of nets laid out Criticality of nets laid out

Find the x “most critical” nets in each circuit Vary x from 25 to 250 Perform algorithms on the x nets Gathered statistics from each layout

Percentage of nets laid out Criticality of nets laid out

Page 21: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

21

Ryan Kastner

ASIC/SOC, September 2000

Circuit BenchmarksCircuit BenchmarksCircuit BenchmarksCircuit BenchmarksData file Num Cells Num Nets Num Pins MCNC Benchmarksprimary1 833 1156 3303primary2 3014 3671 12914avqs 21584 30038 84081biomed 6417 7052 22253struct 1888 1920 5407 ISPD98 Benchmarksibm01 12036 13056 45815ibm05 28146 29647 127509ibm10 68685 29647 127509ibm15 161187 186991 716206ibm18 210341 202192 819969

Page 22: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

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Ryan Kastner

ASIC/SOC, September 2000

Fraction of nets placedFraction of nets placedFraction of nets placedFraction of nets placed

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

25 50 75 100 125 150 175 200 225 250

total nets considered

fra

cti

on

ro

ute

d

greedy

forcing

Algorithm Avg. routes laid outgreedy 30.28%direct forcing 35.30%

Forcing algorithm outperforms greedy algorithmForcing algorithm outperforms greedy algorithm

Page 23: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

23

Ryan Kastner

ASIC/SOC, September 2000

Forcing vs. GreedyForcing vs. GreedyForcing vs. GreedyForcing vs. Greedy

forcing vs greedy

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

25 50 75 100 125 150 175 200 225 250

total nets considered

rela

tiv

e c

riti

ca

lity

quadratic

linear

l root l

relative criticality = (greedy criticality)/(forcing criticality)relative criticality = (greedy criticality)/(forcing criticality)

Page 24: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

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Ryan Kastner

ASIC/SOC, September 2000

Criticality resultsCriticality resultsCriticality resultsCriticality results

Greedy algorithm outperforms every other function

Using linear function: 20% better than forcing algorithm

l-root-l and quadratic functions have similar trends

Greedy algorithm outperforms every other function

Using linear function: 20% better than forcing algorithm

l-root-l and quadratic functions have similar trends

Greedy algorithm best for criticalityGreedy algorithm best for criticality

Page 25: Ryan Kastner ASIC/SOC, September 2000 1 Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer

25

Ryan Kastner

ASIC/SOC, September 2000

ConclusionConclusionConclusionConclusion

Coupling-free routing useful for many routing algorithms Detailed routing Global routing Single layer routing

Allows early prediction of routing metrics Congestion Wire length Interconnect delay

Implication algorithm maximizes routes placed Greedy algorithm maximizes criticality placed

Coupling-free routing useful for many routing algorithms Detailed routing Global routing Single layer routing

Allows early prediction of routing metrics Congestion Wire length Interconnect delay

Implication algorithm maximizes routes placed Greedy algorithm maximizes criticality placed