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Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
TWEPP-07 Topical Workshop on Electronics for Particle Physics
Prague 2007
A MAPS-based readout for Tera-Pixel electromagnetic calorimeter at
the ILC
Y. Mikami, O. Miller, V. Rajovic, N.K. Watson, J.A. WilsonUniversity of Birmingham
J.A. Ballin, P.D. Dauncey, A.-M. Magnan, M. NoyImperial College London
J.P. Crooks, M. Stanitzki, K.D. Stefanov, R. Turchetta, M. Tyndel, E.G. VillaniRutherford Appleton Laboratory
2
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
OutlineOutline
• ILC CALICE
• CALICE MAPS Concept, R&D activity
• Test plan and setup
• Conclusions
3
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
• Exact ILC beam timing parameters not yet defined:– Beams collide rapidly within a quick burst (“train”)– Long dead time between trains
• Assume nominal case timing as follows– Beam collision period 337ns– Bunch train length 1ms – Train rate = 5Hz, i.e. 199ms between trains; 0.5% duty cycle
• Rate of signals– ILC is not like LHC; rate of physics processes is small– Most collisions give nothing, but when reaction does happen, many adjacent channels will
be hit– Assume average ≈106 hits/pixel/crossing, which is ≈ 0.005 hits/pixel/train– MAPS based ECAL prototype designed to cope with double event rate and half bunch
spacing
TESLA 500GeV
ILC operation
4
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE description
• CALICE has a baseline ECAL design• Sampling calorimeter, alternating thick conversion
layers (tungsten) and thin measurement layers (silicon)
• Around 2m radius, 4m long, 30 layers tungsten and silicon, ≈2000m2 Si
• Mechanical structure• Half of tungsten sheets embedded in carbon fibre
structure• Other half of tungsten sandwiched between two
PCBs each holding one layer of silicon detector wafers
• Whole sandwich inserted into slots in carbon fibre structure
5
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Baseline ECAL design
• Silicon sensor detectors in baseline are diode pads, pad size between 1.0×1.0 and 0.5×0.5 cm2, glued to large PCB • Pad readout is analogue signal; digitized by Very Front End (VFE) ASIC mounted o the other PCB side• Si wafers ≈ 10x10cm2
• Si layers on PCB ≈ 1.5m long 30cm wide• Average dissipated power 1-5 W/mm2
• Total number of pads up to 80M
CALICE description
Embedded VFE ASIC
Silicon sensor0.3mm
Tungsten1.4 mm
PCB~0.8 mm
6
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
• Divide wafer into small pixels so as to have small probability of more than one particle going through each pixel
• Binary readout, 1bit ADC• Improved jet resolution or reduced number of layers ( thus
cost) for the same resolution
• Around 100 particles/mm2 pixel size of maximum 100 X 100μm2
• Current design with 50 x 50μm2 pixel• Total number of pixel for ECAL around 8 x 1011
pixels Terapixel system• Record collision number each time hit exceeding
threshold (timestamp stored in memory on sensor )• Information read out in between trains
CALICE MAPS design
7
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Design with MAPS without VFE
MAPS ECAL design• Baseline design with diode pads largely unaffected
by use of MAPS: easy ‘swap-in’
Potential benefits include:• Increased surface for thermal dissipation• Less sensitivity to SEU because of spread out logic• Cost saving (CMOS standard process vs. high
resistivity Si for producing 2*10^7 cm2 and/or overall more compact detector system)
• Simplified assembly ( single sides PCB, no need for grounding substrate)
CALICE MAPS design
Silicon sensor0.3mm
Tungsten1.4mm
PCB~0.8mm
8
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
SiD 16mm2 area cells
5050 μm2
MAPS pixels
ZOOM
9
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
• First prototype designed in CIS 0.18m process submitted early 2007
• Novel process (INMAPS) to increase charge collection efficiency• Different pixel architectures included in the first prototype • Target is to reduce noise to the level of physics background
(S/N>15)• Faulty pixels masking and variable threshold to reduce false hits
and crosstalk• Optimization of pixel layout and topology essential• Minimization of power consumption essential
CALICE MAPS design
10
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
• Pixel layout optimization: Maximization of signal Minimization of charge sharing (crosstalk) Collection time
Large phase space:
-
-
+
+
+
+
+
-- -
--
-
• Pixel size
• Diode size
• Diode layout
• Biasing
• Process
Simulation Specs? Design
CALICE MAPS design
substrate
epitaxial
NW
11
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Q lost in NWell
e-
Q collected by diodes
MAPS - central NW houses electronics-
CALICE MAPS design
Full 3D device simulation using TCAD Sentaurus (Synopsys) for charge
collection study
1.8x1.8m2
1.5V3.5x3.5m2
3.3V
Collected charge on the diodes and central Nwell vs. MIP
impact position
12
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Novel CMOS MAPS process: INMAPS
● Using Deep Pwell implant to shield N-well housing readout electronic: more sophisticated in-pixel electronics possible
● Remarkable improvement in charge collection
● Study of optimal diodes location and size carried out for the new process
≈ 144mV≈ 202mV
≈ 9.5μm
CALICE MAPS design – novel process -
Electric potential in epitaxial layer 12m
NWellDiode NWell
Deep-PWell
Epitaxial
Top sideSubstrate side
Substrate
13
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
• Several Deep PW layouts studied• Optimization of collecting diodes size and location given the electronic design constraints for highest S/N
1.8x1.8 m2
0V
CALICE MAPS design - pixel simulation -
Cell size: 50 x 50 m2
Deep PW
14
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Pre-sample Pixel layout (right) and device model (left)
50m
1.8x1.8m20V
CALICE MAPS design - pixel simulation -
Deep PW
15
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE MAPS design - readout
Rst
Vrst
Shaper
PreRst
Buffer
s.f
Cfb
CinBuffer
s.f
Vth+Vth-
Reset
Sample
Cstore
Preamp Shap
er
Rst
Cpre
Cfb
Rfb
RinCinVth+Vth-
Pre-Shape Pixel Analog Front End
Low gain / High Gain
Comparator
Pre-Sample Pixel Analog Front End
Low gain / High Gain
Comparator
Hit Logic
150ns
150ns
450ns
Hit Logic
Self Reset
Trim&Mask
SRAM SR
Trim&Mask
SRAM SR
Hit Output
Hit Output
Pre-Shape:Pixel reset before start of bunch trainStand by in readoutHit event generates one time hit-flag to the logicCR-RC shaper decays according to input amplitude then is ready to accept next event
Pre-Sample:Pixel reset before start of bunch train and automatically after local hit during bunch trainStand by in readoutCA output sampled afterReset and then real-time difference input to compExpected similar noise characteristics from both designs
16
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Pics of layouts
CALICE MAPS design - pixel layout -
Pre-sample layout Pre-shape layout
17
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE MAPS design - pixel architecture -
●Each digital block serves 42 pixels from one row
●Row split into 7 groups of 6 pixels
●Following a hit, for each row the logic stores in SRAM time stamp(13 bits), pattern number (3 bits), pattern (6 bits)
●22 bits/hit + 9 bits row encoding = 31bits/hit
●Register for masking out noisy pixels
18
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE MAPS design - pixel architecture -
• 1*1 cm² in total• 2 capacitor arrangements• 2 architectures6 million transistors, 28224 pixels• Estimated power:
10μW/pixel continuous
40μW/mm2 including 1% duty factor
• Dead area 250μm every 2mm
• Each sensor could be flip-chip bonded
to a PCB
4600um
42 pixels 42 pixels
2100um250um
2100um250um
84 pixels
19
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE MAPS design – pixel architecture
Sensor microphotograph
20
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE MAPS - RAL test setup -
Planned tests: basic functionality (2 weeks ago, ongoing), source, beam and Laser MIP (next 6 months)• Three wavelength laser: λ=1064, 532,355nm, focusing < 2 μm, pulse 4ns, 50Hz repetition, • Labview Control software • MIP Calibration: Si reference detector coupled to low noise CA + differentiator (no shaper) A250CF peltier cooled• Amplifier Gain measured ~ 7mV/MIP • Amount of stray light and EMP reduced within the laser test setup
21
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE MAPS - RAL test setup - A250CF cal - Qvs V -
-2
0
2
4
6
8
10
12
14
16
18
0.498 3.82 7.24 10.53 13.58 16.78
V(mV)
Q(f
C)
A250CF calibration using injected charge through
capacitor and pulse generator
Reference sensor
ND filter
CA
22
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE MAPS - RAL test setup -
• A250CF output vs. Laser intensity• Q injected vs. Laser intensity• MIP-equivalent vs. Laser intensity • Sub-MIP resolution AND accuracy capability (λ = 1064nm, spot size = 2μm)
Laser output 0%
A250CF cal -Vout (laser E)
V = 1.1429*(%/25+1)2 - 3.4731*(%/25+1) + 14.656 +/-0.0272*(%/25+1)^2-0.0088*(%/25+1)+0.41
0
5
10
15
20
25
30
0 25 50 75 100
% Laser intensity
Vo(
mV
)
Q vs % laser intensity
-2
0
2
4
6
8
10
12
14
16
0 25 50 75 100
% Laser intensity
Q(f
C)
MIP eqv vs. % Laser intensity
-0.5
0
0.5
1
1.5
2
2.5
0 25 50 75 100
% Laser intensity
MIP
eqv
MIP ‘noise’Q ref detector
Laser output 100%
23
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Conclusions
• MAPS-based ECAL can potentially offer a number of advantages in terms of performances and overall cost
• Novel INMAPS process for MAPS might have significant advantages in terms of charge collection efficiency
• Pixel design and readout electronics optimized for charge collection and S/N
• First design aims at demonstrating feasibility of the approach and to achieve significantly high S/N; choice of the best performing structure
• Also verification of simulation results with test results: ‘calibration’ of device simulator
• Power dissipation still high and needs to be addressed
• Test setup ready
• Chip testing underway now
24
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
•Crosstalk is reduced by increasing threshold
•This at the expense of S/N !
•High S/N ratio needed
•Reduce the charge lost in N-Well housing the readout electronic
Qthr 225 => S/N ~ 4 Qthr 250 => S/N ~ 4.4 Qthr 275 => S/N ~ 4.8 Qthr 300 => S/N ~ 5.2
CALICE MAPS design – backup slides -
• Δv = 52 mV @ 250 e-
• Noise =12 mV (8 fF)• S/N = 4.33 (Sg = Ng)• e-
in ~ 57 e-
Δv = 52 mV @ 250 e-
25
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Pre-sample Pixel layout
50 m
1.8x1.8 m20V
CALICE MAPS design – backup slides pixel simulation -
Deep PW
0
100
200
300
400
500
600
700
800
100
90
80
70
60
50
75
80
85
90
95
10
0
Σ diodes Q (x,y)
Pre-sample D-PW collected charge - Single pixel –Final Simulation of 3x3 pixels array ongoing tocompare with test results
26
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
CALICE MAPS - backup slides power consumption -
27
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Geant4 Einit
in 5x5 μm² cells
Sum energy in 50x50 μm² cells
Esum
Apply charge spreadEafter charge spread
Add noise to signal hitswith σ = 100 eV
(1 e- ~ 3 eV 30 e- noise)
+ noise only hits : proba 10-6 ~ 106 hits in the whole detector
BUT in a 1.5*1.5 cm² tower : ~3 hits.
%Einit
%Einit
%Einit %Einit
%Einit
%Einit %Einit
%Einit
Eini
tRegister the position and the number
of hits above threshold
Importance of the charge spread :
initneighbours EE %)80%50(~
CALICE MAPS - backup slides charge spread study -
28
Rutherford Appleton LaboratoryParticle Physics Department
G. Villani CALICE MAPS Prague TWEPP 2007
Stave structure concept
Lack of hybrids/ASIC allow less complex/thinner PCB
Thinner sensors (down to 100µm)
Bump-bond MAPSMAPS
Tungsten
Stave Controllerwith optical linkPCB
CALICE MAPS - backup slides stave -