Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with … · 2012. 4. 13. · T r a n s i t i o n T i m e 1 . 5 ♦♦ µ s pe r F i g u r e 6 , + 3 V t o -3 V I n s t a n

1

Date: 10/29/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation

FEATURES Fast 20Mbps Differential Transmission Rates Internal Transceiver Termination Resistors

for V.11 & V.35 Interface Modes:

RS-232 (V.28) EIA-530 (V.10 & V.11) X.21 (V.11) EIA-530A (V.10 & V.11) RS-449/V.36 V.35 (V.35 & V.28) (V.10 & V.11)

Protocols are Software Selectable with 3-Bit Word Eight (8) Drivers and Eight (8) Receivers Termination Network Disable Option Internal Line or Digital Loopback for Diagnostic Testing Certified conformance to NET1/NET2 and TBR-1

TBR-2 by TUV Rheinland (TBR2/30451940.001/04) Easy Flow-Through Pinout +3.3V Only Operation Individual Driver and Receiver Enable/Disable Controls Operates in either DTE or DCE Mode

SP3508

Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors

DESCRIPTION

The SP3508 is a monolithic device that supports eight (8) popular serial interface standards for Wide Area Network (WAN) connectivity. The SP3508 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex regulated charge pump allowing +3.3V only operation. Sipex's patented charge pump provides a regulated output of +5.5V, which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. The SP3508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than six capacitors used for the internal charge pump. All necessary termination is integrated within the SP3508 and is switchable when V.35 drivers and V.35 receivers, or when V.11 receivers are used. The SP3508 provides the controls and transceiver availability for operating as either a DTE or DCE.

Additional features with the SP3508 include internal loopback that can be initiated in any of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. The SP3508 also includes a latch enable pin with the driver and receiver address decoder. The internal V.11 or V.35 termination can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and receivers in the SP3508 include separate enable pins for added convenience. The SP3508 is ideal for WAN serial ports in networking equipment such as routers, access concentrators, network muxes, DSU/CSU's, networking test equipment, and other access devices.

Applicable U.S. Patents-5,306,954; and others patents pending

®

APPLICATIONS Router Frame Relay CSU DSU PBX Secure Communication Terminals

Now Available in Lead Free Packaging

Refer to page 9 for pinout

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ELECTRICAL SPECIFICATIONSTA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating

temperature range (-40°C to +85°C), unless otherwise specified.

VCC

................................................................................................ +7V Input Voltages:

Logic ................................................ -0.3V to (VCC

+0.5V) Drivers ............................................. -0.3V to (VCC+0.5V) Receivers ........................................................... ±15.5V

Output Voltages:Logic ................................................ -0.3V to (V

CC+0.5V)

Drivers ................................................................... ±12V Receivers ........................................ -0.3V to (V

CC+0.5V)

Storage Temperature ................................................ -65°C to +150°C Power Dissipation ................................................................. 1520mW

(derate 19.0mW/°C above +70°C)

Due to the relatively large package size of the 100-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within

Package Derating:øJA ................................................................................................................. 36.9 °C/W ø

JC .................................................................................................................... 6.5 °C/W

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended

periods of time may affect reliability.

ABSOLUTE MAXIMUM RATINGS

48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order to remove moisture prior to soldering. Sipex ships the 100-pin LQFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.

STORAGE CONSIDERATIONS

R E T E M A R A P .N I M .P Y T .X A M ST I N U S N O I T I D N O C

S T U P N I C I G O L

V LI 8 . 0 ♦♦♦♦♦ V

V H I 0 . 2 ♦♦♦♦♦ V

S T U P T U O C I G O L

V LO 4 . 0 ♦♦♦♦♦ V A m 2 . 3– =T U O I

V H O V CC -

6 . 0V C C -

3 . 0 ♦♦♦♦♦ V

A m 0 . 1=T U O I

) s t u p t u O ( s r e t e m a r a P C D R E V I R D 8 2 .V

s t u p t u O

e g a t l o V t i u c r i C n e p O 1 ±10 ♦♦♦♦♦ V 1 e r u g i Fr e p

e g a t l o V d e d a o L 0 . 5 ± ♦♦♦♦♦ V 2 e r u g i Fr e p

t n e r r u C t i u c r i C -t r o h S 0 0 1 ± ♦♦♦♦♦ A m 4 e r u g i Fr e p

e c n a d e p m I f f O -r e w o P 0 0 3 ♦♦♦♦♦ Ω 5 e r u g i Fr e p

) s t u p t u O ( s r e t e m a r a P C A R E V I R D 8 2 .V V CC s r e t e m a r a p C A r o f V 3 . 3 + =

e m i T n o i t i s n a r T 5 . 1 ♦♦♦♦♦ sµ V 3 -o t V 3 + , 6 e r u g i F r e p

e t a R w e l S s u o e n a t n a t s n I 0 3 sµ / V 3 e r u g i F r e p

t : y a l e D n o i t a g a p o r P L H P 5. 0 0. 1 0. 3 ♦♦♦♦♦ sµ

t : y a l e D n o i t a g a p o r P H L P 5. 0 0. 1 0. 3 ♦♦♦♦♦ sµ

e t a R n o i s s i m s n a r T . x a M 0 2 1 03 2 ♦♦♦♦♦ s p b k

3





) s t u p n I ( s r e t e m a r a P C D R E V I E C E R 8 2 .V

e c n a d e p m I t u p n I 3 7 ♦♦♦♦♦ kΩ 7 e r u g i F r e p

s a i B t i u c r i C -n e p O 0 . 2 + ♦♦♦♦♦ V 8 e r u g i Fr e p

d l o h s e r h T H G I H 7 . 1 0. 3 ♦♦♦♦♦ V

d l o h s e r h T W O L 8 . 0 2. 1 ♦♦♦♦♦ V

s r e t e m a r a P C A R E V I E C E R 8 2 .V V CC s r e t e m a r a p C A r o f V 3 . 3 + =

t : y a l e D n o i t a g a p o r P L H P 0 0 1 00 5 s n

t : y a l e D n o i t a g a p o r P H L P 0 0 1 00 5 s n

e t a R n o i s s i m s n a r T x a M 0 2 1 53 2 s p b k


e g a t l o V t i u c r i C n e p O 0 . 4 ± 0 . 6 ± ♦♦♦♦♦ V 9 e r u g i Fr e p

e g a t l o V d e t a n i m r e T -t s e T V 9 . 0 CO V 01 e r u g i F r e p

t n e r r u C t i u c r i C -t r o h S 0 5 1 ± A m 11 e r u g i F r e p

t n e r r u C f f O -r e w o P 0 0 1 ± ♦♦♦♦♦ Aµ 2 1 e r u g i F r e p


e m i T n o i t i s n a r T 0 0 2 ♦♦♦♦♦ s n % 0 9 o t % 0 1 ; 3 1 e r u g i F r e p

t : y a l e D n o i t a g a p o r P L H P 0 0 1 00 5 ♦♦♦♦♦ s n

t : y a l e D n o i t a g a p o r P H L P 0 0 1 00 5 ♦♦♦♦♦ s n

e t a R n o i s s i m s n a r T x a M 0 2 1 ♦♦♦♦♦ s p b k


t n e r r u C t u p n I 5 2 . 3 - 5 2 . 3 + A m 5 1 d n a 4 1 s e r u g i F r e p

e c n a d e p m I t u p n I 4 ♦♦♦♦♦ kΩ

y t i v i t i s n e S 3 . 0 ± ♦♦♦♦♦ V

s r e t e m a r a P C A R E V I E C E R 0 1 .V V CC s r e t e m a r a p C A r o f V 3 . 3 + =

t : y a l e D n o i t a g a p o r P L H P 0 2 1 05 2 ♦♦♦♦♦ s n

t : y a l e D n o i t a g a p o r P H L P 0 2 1 05 2 ♦♦♦♦♦ s n

e t a R n o i s s i m s n a r T x a M 0 2 1 ♦♦♦♦♦ s p b k

4






V ( e g a t l o V t i u c r i C n e p O C O ) 0 . 6 ± ♦♦♦♦♦ V 61 e r u g i F r e p

e g a t l o V d e t a n i m r e T t s e T 0 . 2 ± ♦♦♦♦♦ V 71 e r u g i F r e p

5 . 0 V( C O ) ♦♦♦♦♦ V

e c n a l a B 4 . 0 ± V 71 e r u g i F r e p

t e s f f O 0 . 3 + ♦♦♦♦♦ V 71 e r u g i F r e p

t n e r r u C t i u c r i C -t r o h S 0 5 1 ± ♦♦♦♦♦ A m 81 e r u g i F r e p

t n e r r u C f f O -r e w o P 0 0 1 ± ♦♦♦♦♦ Aµ 9 1 e r u g i F r e p


e m i T n o i t i s n a r T 01 ♦♦♦♦♦ s n o t % 0 1 ; 5 3 d n a 1 2 s e r u g i F r e p

;F p 0 5 =L C g n i s U % 0 9

t : y a l e D n o i t a g a p o r P L H P 0 3 06 ♦♦♦♦♦ s n 5 3 d n a 2 3 s e r u g i F r e p

t : y a l e D n o i t a g a p o r P H L P 0 3 06 ♦♦♦♦♦ s n 5 3 d n a 2 3 s e r u g i F r e p

w e k S l a i t n e r e f f i D 5 01 ♦♦♦♦♦ s n 5 3 d n a 2 3 s e r u g i F r e p

e t a R n o i s s i m s n a r T . x a M 0 2 ♦♦♦♦♦ s p b M


e g n a R e d o M n o m m o C 7 - 7+ ♦♦♦♦♦ V

y t i v i t i s n e S 2 . 0 ± ♦♦♦♦♦ V

t n e r r u C t u p n I 5 2 . 3 - 5 2 . 3 ± A m

r o n o r e w o p ; 2 2 d n a 0 2 e r u g i F r e p f f o

Ω0 0 1 / w t n e r r u C n o i t a n i m r e T

-7 . 0 6 ±5

A m 4 2 d n a 3 2 e r u g i F r e p

e c n a d e p m I t u p n I 4 ♦♦♦♦♦ kΩ

s r e t e m a r a P C A R E V I E C E R 1 1 .V V CC s r e t e m a r a p C A r o f V 3 . 3 + =F p 0 5 =L C g n i s U

t : y a l e D n o i t a g a p o r P L H P 0 3 06 s n 7 3 d n a 2 3 s e r u g i F r e p

t : y a l e D n o i t a g a p o r P H L P 0 3 06 s n 7 3 d n a 2 3 s e r u g i F r e p

w e k S 5 01 s n 23 e r u g i F r e p

e t a R n o i s s i m s n a r T x a M 0 2 s p b M

5






e g a t l o V t i u c r i C n e p O 0 2 . 1 ± V 61 e r u g i F r e p

e g a t l o V d e t a n i m r e T t s e T 4 4 . 0 ± 66 . 0 ± V 52 e r u g i F r e p

t e s f f O 6 . 0 ± ♦♦♦♦♦ V 52 e r u g i F r e p

t o o h s r e v O t u p t u O -V 2 . 0 -

T S

-2 . 0 +V T S

♦♦♦♦♦ V V; 5 2 e r u g i F r e p TS e t a t sy d a e t S =

e u l a v

e c n a d e p m I e c r u o S 0 5 05 1 ♦♦♦♦♦ Ω Z; 6 2 e r u g i F r e p S V= 2 V/ 1 0 5 x

e c n a d e p m I t i u c r i C -t r o h S 5 3 1 56 1 Ω 72 e r u g i F r e p


e m i T n o i t i s n a r T 0 2 ♦♦♦♦♦ s n

t : y a l e D n o i t a g a p o r P L H P 0 3 06 ♦♦♦♦♦ s n C ; 5 3 d n a 2 3 s e r u g i F r e p L F p 0 2=

t : y a l e D n o i t a g a p o r P H L P 0 3 06 ♦♦♦♦♦ s n C ; 5 3 d n a 2 3 s e r u g i F r e p L F p 0 2=

w e k S l a i t n e r e f f i D 5 ♦♦♦♦♦ s n C ; 5 3 d n a 2 3 s e r u g i F r e p L F p 0 2=

e t a R n o i s s i m s n a r T . x a M 0 2 ♦♦♦♦♦ s p b M


y t i v i t i s n e S 0 5 ± 00 2 ± ♦♦♦♦♦ V m

e c n a d e p m I e c r u o S 0 9 01 1 Ω Z; 9 2 e r u g i F r e p S V= 2 V/ 1 0 5 x Ω

e c n a d e p m I t i u c r i C -t r o h S 5 3 1 56 1 Ω 03 e r u g i F r e p

s r e t e m a r a P C A R E V I E C E R 5 3 .V V CC s r e t e m a r a p C A r o f V 5 + =

t : y a l e D n o i t a g a p o r P L H P 0 3 06 s n C ; 7 3 d n a 2 3 s e r u g i F r e p L F p 0 2=

t : y a l e D n o i t a g a p o r P H L P 0 3 06 s n C ; 7 3 d n a 2 3 s e r u g i F r e p L F p 0 2=

w e k S 5 01 s n C ; 2 3 s e r u g i F r e p L F p 0 2=

e t a R n o i s s i m s n a r T . x a M 0 2 s p b M

S T N E R R U C E G A K A E L R E V I E C S N A R T

t n e r r u C e t a t S -3 t u p t u O r e v i r D 0 02 A µ d e l b a s i d s r e v i r D ; 1 3 e r u g i F r e p

e t a t S -3 t u p t u O r e v i e c e R t n e r r u C

1 01 Aµ

DX 1 1 1 =

6





S T N E M E R I U Q E R R E W O P

V CC 5 1 . 3 3. 3 54 .3 V

I C C ) d e t c e l e S e d o M o N ( 1 ♦♦♦♦♦ Aµ I l lA CC V h t iw e r a s e u l a v CC V3 . 3 + =

) 2 3 2 -S R / 8 2 .V 5 9 ♦♦♦♦♦ A m f NI & e v i t c a s r e v i r D ; s p b k 0 3 2 =

d e d a o l

) 2 2 4 -S R / 1 1 .V ( 0 3 2 ♦♦♦♦♦ A m f NI d e d a o l & e v i t c a s r e v i r D ; s p b M 0 2 =

) 9 4 4 -S R & 0 3 5 -A I E ( 0 7 2 ♦♦♦♦♦ A m f NI d e d a o l & e v i t c a s r e v i r D ; s p b M 0 2 =

) 5 3 .V ( 0 7 1 ♦♦♦♦♦ A m I f@ 5 3 .V N @8 2 .V , s p b M 0 2 =

s p b k 0 3 2

7


OTHER AC CHARACTERISTICSTA = 0 to 70°C and VCC = +3.3V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE

RS-232/V.28tPZL; Tri-state to Output LOW 0.70 5.0 µs CL = 100pF, Fig. 33 & 39; S1 closedtPZH; Tri-state to Output HIGH 0.40 2.0 µs CL = 100pF, Fig. 33 & 39; S2 closedtPLZ; Output LOW to Tri-state 0.20 2.0 µs CL = 100pF, Fig. 33 & 39; S1 closedtPHZ; Output HIGH to Tri-state 0.40 2.0 µs CL = 100pF, Fig. 33 & 39; S2 closed

RS-423/V.10 tPZL; Tri-state to Output LOW 0.15 2.0 µs CL = 100pF, Fig. 33 & 39; S1 closedtPZH; Tri-state to Output HIGH 0.20 2.0 µs CL = 100pF, Fig. 33 & 39; S2 closedtPLZ; Output LOW to Tri-state 0.20 2.0 µs CL = 100pF, Fig. 33 & 39; S1 closedtPHZ; Output HIGH to Tri-state 0.15 2.0 µs CL = 100pF, Fig. 33 & 39; S2 closed


V.35tPZL; Tri-state to Output LOW 2.60 10.0 µs CL = 100pF, Fig. 33 & 36; S1 closedtPZH; Tri-state to Output HIGH 0.10 2.0 µs CL = 100pF, Fig. 33 & 36; S2 closedtPLZ; Output LOW to Tri-state 0.10 2.0 µs CL = 15pF, Fig. 33 & 36; S1 closedtPHZ; Output HIGH to Tri-state 0.15 2.0 µs CL = 15pF, Fig. 33 & 36; S2 closed

RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE

RS-232/V.28tPZL; Tri-state to Output LOW 0.12 2.0 µs CL = 100pF, Fig. 34 & 37; S1 closedtPZH; Tri-state to Output HIGH 0.10 2.0 µs CL = 100pF, Fig. 34 & 37; S2 closedtPLZ; Output LOW to Tri-state 0.10 2.0 µs CL = 100pF, Fig. 34 & 37; S1 closedtPHZ; Output HIGH to Tri-state 0.10 2.0 µs CL = 100pF, Fig. 34 & 37; S2 closed


8


OTHER AC CHARACTERISTICS: ContinuedTA = 0 to 70°C and VCC = +3.3V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONSRS-422/V.11 tPZL; Tri-state to Output LOW 0.10 2.0 µs CL = 100pF, Fig. 34 & 38; S1

closedtPZH; Tri-state to Output HIGH 0.10 2.0 µs CL = 100pF, Fig. 34 & 38; S2

closedtPLZ; Output LOW to Tri-state 0.10 2.0 µs CL = 15pF, Fig. 34 & 38; S1

closedtPHZ; Output HIGH to Tri-state 0.10 2.0 µs CL = 15pF, Fig. 34 & 38; S2

closedV.35tPZL; Tri-state to Output LOW 0.10 2.0 µs CL = 100pF, Fig. 34 & 38; S1

closedtPZH; Tri-state to Output HIGH 0.10 2.0 µs CL = 100pF, Fig. 34 & 38; S2

closedtPLZ; Output LOW to Tri-state 0.10 2.0 µs CL = 15pF, Fig. 34 & 38; S1

closedtPHZ; Output HIGH to Tri-state 0.10 2.0 µs CL = 15pF, Fig. 34 & 38; S2

closed

TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 32, 35, 37)

RS-232 Driver 100 ns [ (tphl )Tx1 – (tphl )Txn ]

100 ns [ (tplh )Tx1 – (tplh )Txn]

RS-232 Receiver 20 ns [ (tphl )Rx1 – (tphl )Rxn ]

20 ns [ (tphl )Rx1 – (tphl )Rxn ]


2 ns [ (tplh )Tx1 – (tplh )Txn ]

RS-422 Receiver 3 ns [ (tphl )Rx1 – (tphl )Rxn ]3 ns [ (tphl )Rx1 – (tphl )Rxn ]



RS-423 Receiver 5 ns [ (tphl )Rx2 – (tphl )Rxn ]

5 ns [ (tphl )Rx2 – (tphl )Rxn ]

V.35 Driver 4 ns [ (tphl )Tx1 – (tphl )Txn ]


V.35 Receiver 6 ns [ (tphl )Rx1 – (tphl )Rxn ] 6 ns [ (tphl )Rx1 – (tphl )Rxn]

9


PINOUT

GND 1

SDEN 2

TTEN 3

STEN 4

RSEN 5

TREN 6

RRCEN 7

RLEN 8

LLEN 9

RDEN 10

RTEN 11

TXCEN 12

CSEN13

DMEN 14

RRTEN 15

ICEN 16

TMEN 17

D0 18

D1 19

D2 20

D_LATCH 21

TERM_OFF 22

VCC 23

C3P 24

GND 25

C3N

26

VS

S2

27

AG

ND

28

AV

CC

29

LOO

PB

AC

K 3

0T

XD

31

TX

CE

32

ST

33

RT

S 3

4

DT

R 3

5

DC

D_D

CE

36

RL

37

LL 3

8

RX

D 3

9

RX

C 4

0

TX

C 4

1

CT

S 4

2

DS

R 4

3

DC

D_D

TE

44

RI

45

TM

46

GN

D 4

7

VC

C 4

8

RD

(b)

49

RD

(a)

50

75 GND

74 C1P

73 VCC

72 C2P

71 GND

70 C1N

69 C2N

68 VSS1

67 RL(a)

66 VCC

65 LL(a)

64 TM(a)

63 IC

62 RRT(a)

61 RRT(b)

60 GNDV10

59 DM(a)

58 DM(b)

57 CS(a)

56 CS(b)

55 TXC(a)

54 GND

53 TXC(b)

52 RT(a)

51 RT(b)

100

VC

C

99 S

D(b

)

98 V

CC

97 S

D(a

)

96 G

ND

95 T

T(b

)

94 V

CC

93 T

T(a

)

92 G

ND

91 S

T(b

)

90 V

CC

89 S

T(a

)

88 G

ND

87 T

R(b

)

86 V

CC

85 T

R(a

)

84 G

ND

83 R

S(b

)

82 V

CC

81 R

S(a

)

80 G

ND

79 R

RC

(a)

78 V

CC

77 R

CC

(b)

76 V

DD

SP3508

®

10


SP3508 Pin Designation

Pin Number Pin Name Description Pin Number Pin Name Description

1 GND Signal Ground 51 RT(B) RxC Non-Inverting Input

2 SDEN TxD Driver Enable Input 52 RT(A) RxC Inverting Input

3 TTEN TxCE Driver Enable Input 53 TxC(B) TxC Non-Inverting Input

4 STEN ST Driver Enable Input 54 GND Signal Ground

5 RSEN RTS Driver Enable Input 55 TxC(A) TxC Inverting Input

6 TREN DTR Driver Enable Input 56 CS(B) CTS Non-Inverting Input

7 RRCEN DCD Driver Enable Input 57 CS(A) CTS Inverting Input

8 RLEN RL Driver Enable Input 58 DM(B) DSR Non-Inverting Input

9 LLEN LL Driver Enable Input 59 DM(A) DSR Inverting Input

10 RDEN RxD Receiver Enable Input 60 GNDV10 V.10 Rx Reference Node

11 RTEN RxC Receiver Enable Input 61 RRT(B) DCDDTE Non-Inverting Input

12 TxCEN TxC Receiver Enable Input 62 RRT(A) DCDDTE Inverting Input

13 CSEN CTS Receiver Enable Input 63 IC RI Receiver Input

14 DMEN DSR Receiver Enable Input 64 TM(A) TM Receiver Input

15 RRTEN DCDDTE Receiver Enable Input 65 LL(A) LL Driver Output

16 ICEN RI Receiver Enable Input 66 VCC Power Supply Input

17 TMEN TM Receiver Enable Input 67 RL(A) RL Driver Output

18 D0 Mode Select Input 68 VSS1 -2xVCC Charge Pump Output

19 D1 Mode Select Input 69 C2N Charge Pump Capacitor

20 D2 Mode Select Input 70 C1N Charge Pump Capacitor

21 D_LATCH Decoder Latch Input 71 GND Signal Ground

22 TERM_OFF Termination Disable Input 72 C2P Charge Pump Capacitor

23 VCC Power Supply Input 73 VCC Power Supply Input

24 C3P Charge Pump Capacitor 74 C1P Charge Pump Capacitor

25 GND Signal Ground 75 GND Signal Ground

26 C3N Charge Pump Capacitor 76 VDD 2xVCC Charge Pump Output

27 VSS2 Minus VCC 77 RRC(B) DCDDCE Non-Inverting Output

28 AGND Signal Ground 78 VCC Power Supply Input

29 AVCC Power Supply Input 79 RRC(A) DCDDCE Inverting Output

30 LOOPBACK Loopback Mode Enable Input 80 GND Signal Ground

31 TxD TxD Driver TTL Input 81 RS(A) RTS Inverting Output

32 TxCE TxCE Driver TTL Input 82 VCC Power Supply Input

33 ST ST Driver TTL Input 83 RS(B) RTS Non-Inverting Output

34 RTS RTS Driver TTL Input 84 GND Signal Ground

35 DTR DTR Driver TTL Input 85 TR(A) DTR Inverting Output

36 DCD_DCE DCDDCE Driver TTL Input 86 VCC Power Supply Input

37 RL RL Driver TTL Input 87 TR(B) DTR Non-Inverting Output

38 LL LL Driver TTL Input 88 GND Signal Ground

39 RxD RxD Receiver TTL Output 89 ST(A) ST Inverting Output

40 RxC RxC Receiver TTLOutput 90 VCC Power Supply Input

41 TxC TxC Receiver TTL Output 91 ST(B) ST Non-Inverting Output

42 CTS CTS Receiver TTL Output 92 GND Signal Ground

43 DSR DSR Receiver TTL Output 93 TT(A) TxCE Inverting Output

44 DCD_DTE DCDDTE Receiver TTL Output 94 VCC Power Supply Input

45 RI RI Receiver TTL Output 95 TT(B) TxCE Non-Inverting Output

46 TM TM Receiver TTL Output 96 GND Signal Ground

47 GND Signal Ground 97 SD(A) TxD Inverting Output

48 VCC Power Supply Input 98 VCC Power Supply Input

49 RD(B) RXD Non-Inverting Input 99 SD(B) TxD Non-Inverting Output

50 RD(A) RXD Inverting Input 100 VCC Power Supply Input

11


Table 1. Driver Mode Selection

Table 2. Receiver Mode Selection

SP3508 Driver Table

SP3508 Receiver Table

t u p t u O r e v i r D n i P

e d o M 5 3 . V 03 5 -A I E

e d o M

2 3 2 -S R e d o M) 8 2 .V (

A 0 3 5 -A I E e d o M

9 4 4 -S R e d o M) 6 3 .V (

e d o M 1 2 .X ) 1 1 .V (

n w o d t u h S d e t s e g g u S

l a n g i S

E D O M )2 D , 1 D , 0 D ( 10 0 01 0 11 0 001 101 01 1 11 1

T1 ) a ( T U O 53 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( D x T

T1 ) b ( T U O 53 . V 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( D x T

T2 ) a ( T U O 53 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( E C x T

T2 ) b ( T U O 53 . V 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( E C x T

T3 ) a ( T U O 53 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( E C D _C x T

T3 ) b ( T U O 53 . V 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( E C D _C x T

T4 ) a ( T U O 82 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( S T R

T4 ) b ( T U O Z-h g i H 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( S T R

T5 ) a ( T U O 82 . V 11 . V 82 . V 01 . V 11 . V 11 . V Z-h g i H ) a ( R T D

T5 ) b ( T U O Z-h g i H 11 . V Z-h g i H Z-h g i H 11 . V 11 . V Z-h g i H ) b ( R T D

T6 ) a ( T U O 82 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( E C D _D C D

T6 ) b ( T U O Z-h g i H 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( E C D _D C D

T7 ) a ( T U O 82 . V 01 . V 82 . V 01 . V 01 . V Z-h g i H Z-h g i H LR

T8 ) a ( T U O 82 . V 01 . V 82 . V 01 . V 01 . V Z-h g i H Z-h g i H LL

t u p n I r e v i e c e R n i P

e d o M 5 3 . V 03 5 -A I E

e d o M

2 3 2 -S R e d o M) 8 2 .V (

A 0 3 5 -A I E e d o M

9 4 4 -S R e d o M) 6 3 .V (

e d o M 1 2 .X) 1 1 .V (

n w o d t u h S d e t s e g g u S

l a n g i S

E D O M )2 D , 1 D , 0 D ( 10 0 01 0 11 0 001 101 01 1 11 1

R1 ) a ( N I 53 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( D x R

R1 ) b ( N I 53 . V 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( D x R

R2 ) a ( N I 53 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( C x R

R2 ) b ( N I 53 . V 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( C x R

R3 ) a ( N I 53 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( E T D _C x T

R3 ) b ( N I 53 . V 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( E T D _C x T

R4 ) a ( N I 82 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( S T C

R4 ) b ( N I Z-h g i H 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( S T C

R5 ) a ( N I 82 . V 11 . V 82 . V 01 . V 11 . V 11 . V Z-h g i H ) a ( R S D

R5 ) b ( N I Z-h g i H 11 . V Z-h g i H Z-h g i H 11 . V 11 . V Z-h g i H ) b ( R S D

R6 ) a ( N I 82 . V 11 . V 82 . V 11 . V 11 . V 11 . V Z-h g i H ) a ( E T D _D C D

R6 ) b ( N I Z-h g i H 11 . V Z-h g i H 11 . V 11 . V 11 . V Z-h g i H ) b ( E T D _D C D

R7 ) a ( N I 82 . V 01 . V 82 . V 01 . V 01 . V Z-h g i H Z-h g i H IR

R8 ) a ( N I 82 . V 01 . V 82 . V 01 . V 01 . V Z-h g i H Z-h g i H MT

12


Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage

Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current

Figure 6. V.28 Driver Output Rise/Fall Times Figure 5. V.28 Driver Output Power-Off Impedance

TEST CIRCUITS

A

VOC

C

A

VT

C

3kΩ

A

VT

C

7kΩ Oscilloscope

Scope used for slew rate measurement.

A

Isc

C

A

C

VCC = 0V

±2V

IxA

C

3kΩ 2500pF Oscilloscope

13


Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias

Figure 9. V.10 Driver Output Open-Circuit Voltage Figure 10. V.10 Driver Output Test Terminated Voltage

Figure 12. V.10 Driver Output Power-Off Current Figure 11. V.10 Driver Output Short-Circuit Current

A

C

Iia

±15V

A

C

voc

A

VOC3.9kΩ

C

A

Vt450Ω

C

A

Isc

C

A

C

±0.25V

VCC = 0V

Ix

14


Figure 13. V.10 Driver Output Transition Time Figure 14. V.10 Receiver Input Current

Figure 15. V.10 Receiver Input IV Graph Figure 16. V.11 Driver Output Open-Circuit Voltage

Figure 17. V.11 Driver Output Test Terminated Voltage Figure 18. V.11 Driver Output Short-Circuit Current

A

450Ω

C

Oscilloscope

A

C

Iia

±10V

A

B

VOC3.9kΩ

VOCA

VOCB

C

A

B

VT

50Ω

VOS

C

50Ω

A

B

C

Isa

Isb

V.10 RECEIVER

+3.25mA

-3.25mA

+3V +10V

-3V -10V

Maximum Input Current Versus Voltage

15


Figure 19. V.11 Driver Output Power-Off Current Figure 20. V.11 Receiver Input Current

Figure 21. V.11 Driver Output Rise/Fall Time Figure 22. V.11 Receiver Input IV Graph

A

B

C

Ixa

±0.25V

A

B

C

Ixb

±0.25V

VCC = 0V

VCC = 0V

A

B

C

Iia

±10V

C

Iib

±10V

A

B

A

B

50Ω

C

50Ω

50Ω VE

Oscilloscope

V.11 RECEIVER

+3.25mA

-3.25mA

+3V +10V

-3V -10V

Maximum Input Current Versus Voltage

16


Figure 23. V.11 Receiver Input Current w/ Termination

Figure 24. V.11 Receiver Input Graph with Termination

Figure 25. V.35 Driver Output Test Terminated Voltage

Figure 26. V.35 Driver Output Source Impedance

A

B

C

Iia

±6V

C

Iib

±6V

A

B

100Ω to 150Ω

100Ω to 150Ω

A

B

V2

50Ω

C

24kHz, 550mVp-p Sine Wave

V1

A

B

50Ω

C

50Ω

VT

VOS

V.11 RECEIVER w/ Optional Cable Termination

(100Ω to 150Ω) i [mA] = V [V] / 0.1

i [mA] = V [V] - 3) / 4.0

i [mA] = V [V] / 0.1

i [mA] = V [V] - 3) / 4.0

-6V -3V

+3V +6V

Maximum Input Current

versus Voltage

Figure 27. V.35 Driver Output Short-Circuit Impedance

A

B

C

ISC

±2V

17


Figure 31. Driver Output Leakage Current Test

Figure 32. Driver/Receiver Timing Test Circuit

Figure 29. V.35 Receiver Input Source ImpedanceFigure 28. V.35 Driver Output Rise/Fall Time

Figure 30. V.35 Receiver Input Short-Circuit Impedance

A

B

C

50Ω

Oscilloscope

50Ω

50Ω

A

B

V2

50Ω

C

24kHz, 550mVp-p Sine Wave

V1

A

B

C

Isc

±2V

A

B

IZSC

Logic “1”

±10V

1 1 1

D2 D1 D0

VCC = 0V

VCC

Any one of the three conditions for disabling the driver.

IZSC ±10V

CL1

15pF

ROUT

B

A

B

A

TIN

CL2

fIN (50% Duty Cycle, 2.5VP-P

)

18


Figure 33. Driver Timing Test Load Circuit Figure 34. Receiver Timing Test Load Circuit

Figure 35. Driver Propagation Delays

Figure 36. Driver Enable and Disable Times

Figure 37. Receiver Propagation Delays

500Ω

CL

OutputUnder

Test

S1

S2

VCC1KΩ

1KΩCRL

Receiver Output S1

S2

Test PointVCC

+3V

0V

5V

VOL

A, B0V

1.5V 1.5V

tZL

tZH

VOH

A, B 2.3V

2.3V

tLZ

tHZ

0.5V

0.5V

Output normally LOW

Output normally HIGH

Mx or Tx_Enablef = 1MHz; tR ≤ 10ns; tF ≤ 10ns

VOH

VOL

RECEIVER OUT (VOH - VOL)/2 (VOH - VOL)/2

tPLH

f > 10MHz; tR < 5ns; tF < 5ns

OUTPUT

V0D2+

V0D2–A – B 0V 0V

tPHL

INPUT

tSKEW = | tPHL - tPLH |

+3V

0V

DRIVER INPUT

A

B

DRIVER OUTPUT

VO+ DIFFERENTIALOUTPUT

VB – VA

0V VO–

1.5V 1.5V

tPLH

tR tF

f > 10MHz; tR < 5ns; tF < 5ns

VO 1/2VO 1/2VO

tPHL

tDPLH tDPHL

tSKEW = | tDPLH - tDPHL |

19


Figure 38. Receiver Enable and Disable Times

Figure 39. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times

+3V

0V Tx_Enable 1.5V 1.5V

tZL

f = 60kHz; tR < 10ns; tF < 10ns

TOUT

tLZ

Output LOW

0V

+3V

0V

VOH

1.5V 1.5V

tZH

f = 60kHz; tR < 10ns; tF < 10ns

TOUT

tHZOutput HIGH

0V

Tx_Enable

VOL

0.5V VOH -

VOL 0.5V - VOL 0.5V-

+3V

0V

+3.3V

RECEIVER OUT0V

1.5V 1.5V

tZL

tZH

f = 1MHz; tR < 10ns; tF < 10ns

RECEIVER OUT 1.5V

1.5V

tLZ

tHZ

0.5V

0.5V

Output normally LOW

Output normally HIGH

VIL

VIH

DECx

RxENABLE

20


Figure 40. Typical V.10 Driver Output Waveform. Figure 41. Typical V.11 Driver Output Waveform.

Figure 42. Typical V.28 Driver Output Waveform. Figure 43. Typical V.35 Driver Output Waveform.

21


Figure 44. Functional Diagram

TxD

SD(a)

SD(b)

SDEN

VCC

VDD

C1-C1+

+3.3V (decoupling capacitor not shown)

1µF

SP3508

TxCE

TT(a)

TT(b)

TTEN

ST

ST(a)

ST(b)

STEN

RD(a)

RxD RDEN

RD(b)

RT(a)

RxC RTEN

RT(b)

TxC(a)

TxC TxCEN

TxC(b)

CS(a)

CTS CSEN

CS(b)

DM(a)

DSR DMEN

DM(b)

RRT(a)

DCD_DTE RRTEN

RRT(b)

TM(a)

TM TMEN

RTS

RS(a)

RS(b)

RSEN

DTR

TR(a)

TR(b)

TREN

DCD_DCE

RRC(a)

RRC(b)

RRCEN

LL

LL(a)

LLEN

C2-C2+

1µF

1µF

GND

D0

D1

D2

TERM-OFF

D-LATCH

V.10-GND

RL

RL(a)

RLEN

IC

RI ICEN

LOOPBACK

76

29

50

39

10

49

52

40

11

51

55

41

12

53

57

42

14

56

59

43

13

58

62

44

15

61

63

45

16

64

46

17

18

19

20

21

22

30

+3.3V

(See pinout assignments for

GND and VCC pins)

74 70 72 69

AGND

31

97

99

2

32

93

95

3

33

89

91

4

34

81

83

6

35

85

87

5

36

79

77

7

37

67

8

38

65

9

60

28

V.35 MODE

RX ENABLE

51ohms

51ohms

124ohms

RECEIVER TERMINATION NETWORK

V.11 MODE

V.35 MODE

TX ENABLE

51ohms

51ohms

124ohms

V.35 DRIVER TERMINATION NETWORK

VSS168

VSS21µF

27

1µF

1µF

24

26

AVCC

C3-

C3+

Inverter

Regulated Charge Pump

CVDD

C1 C2

C3

CVSS1

CVSS2

22


The SP3508 contains highly integrated serial transceivers that offer programmability between interface modes through software control. The SP3508 offers the hardware interface modes for RS-232 (V.28), RS-449/V.36 (V.11 and V.10), EIA-530 (V.11 and V.10), EIA-530A (V.11 andV.10), V.35 (V.35 and V.28) and X.21(V.11). The interface mode selection is done via three control pins, which can be latched via micropro-cessor control.

The SP3508 has eight drivers, eight receivers, and Sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. Other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail-safe when inputs are either open or shorted.

THEORY OF OPERATION

The SP3508 device is made up of

1) the drivers

2) the receivers

3) charge pumps

4) DTE/DCE switching algorithm

5) control logic.

Drivers

The SP3508 has eight enhanced independent drivers. Control for the mode selection is done via a three-bit control word into D0, D1, and D2. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accom-modate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the re-quired signal levels. The mode of each driver in the different interface modes that can be se-lected is shown in Table 1.

There are four basic types of driver circuits – ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423), ITU-T-V.11 (RS-422), and CCITT-V.35.

The V.28 (RS-232) drivers output single-ended signals with a minimum of +5V (with 3kΩ & 2500pF loading), and can operate over 120kbps. Since the SP3508 uses a charge pump to gener-ate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 driver archi-tecture is similar to Sipex's standard line of RS-232 transceivers.

The RS-423 (V.10) drivers are also single-ended signals which produce open circuit VOL andVOH measurements of +4.0V to +6.0V. When terminated with a 450Ω load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 (RS-423) drivers are used in RS-449/V.36, EIA-530, and EIA-530A modes as Category II signals from each of their corresponding specifications. TheV.10 driver can transmit over 120Kbps if neces-sary.

The third type of drivers are V.11 (RS-422) differential drivers. Due to the nature of differ-ential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain +2V differential out-put levels with a load of 100Ω. The strength allows the SP3508 differential driver to drive over long cable lengths with minimal signal degradation. The V.11 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data. Sipex's new driver design over its prede-cessors allow the SP3508 to operate over 20Mbps for differential transmission.

FEATURES

23


The fourth type of drivers are V.35 differential drivers. There are only three available on the SP3508 for data and clock (TxD, TxCE, and TxC in DCE mode). These drivers are current sources that drive loop current through a differential pair resulting in a 550mV differential voltage at the receiver. These drivers also incorporate fixed termination networks for each driver in order to set the V

OH and V

OL depending on load conditions.

This termination network is basically a “Y” configuration consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors to GND. Filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground.

The drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable DTE/DCE. The enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on Figure 44. The enable pins have internal pull-up and pull-down devices, depending on the active polarity of the receiver, that enable the driver upon power-on if the enable lines are left floating. During disabled conditions, the driver outputs will be at a high impedance 3-state.

The driver inputs are both TTL or CMOS compatible. All driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic LOW (“0”). Unused driver inputs can be left floating. The internal pull-up resistor value is approximately 500kΩ.

ReceiversThe SP3508 has eight enhanced independent receivers. Control for the mode selection is done via a three-bit control word that is the same as the driver control word. Therefore, the modes for the drivers and receivers are identical in the application.

Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics

will change to support the required serial interface protocols of the receivers. Table 1 shows the mode of each receiver in the different interface modes that can be selected. There are two basic types of receiver circuits—ITU-T-V .28 (RS-232) and ITU-T-V.11, (RS-422).

The RS-232 (V.28) receiver is single-ended and accepts RS-232 signals from the RS-232 driver. The RS-232 receiver has an operating input voltage range of +15V and can receive signals downs to +3V. The input sensitivity complies with RS-232 and V.28 at +3V. The input impedance is 3kΩ to 7kΩ in accordance to RS-232 and V.28. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic “1” and a +0.4V maximum for a logic “0”. The RS-232 (V.28) protocol uses these receivers for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The RS-232 receivers can operate over 120kbps.

The second type of receiver is a differential type that can be configured internally to support ITU-T-V.10 and CCITT-V.35 depending on its input conditions. This receiver has a typical input impedance of 10kΩ and a differential threshold of less than +200mV, which complies with the ITU-T-V.11 (RS-422) specifications.V.11 receivers are used in RS-449/V.36, EIA-530, EIA-530A and X.21 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential V.11 transceiver has improved architecture that allows over 20Mbps transmission rates.

Receivers dedicated for data and clock (RxD, RxC, TxC) incorporate internal termination forV.11. The termination resistor is typically 120Ωconnected between the A and B inputs. The termination is essential for minimizing crosstalk and signal reflection over the transmission line . The minimum value is guaranteed to exceed 100Ω, thus complying with the V.11 and RS-422 specifications. This resistor is invoked when the receiver is operating as a V.11 receiver, in modes EIA-530, EIA-530A, RS-449/V.36, and X.21.

FEATURES

24


The same receivers also incorporate a termination network internally for V.35 applications. ForV.35, the receiver input termination is a “Y” termination consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors and GND. The receiver itself is identical to the V.11 receiver.

The differential receivers can be configured to be ITU-T-V.10 single-ended receivers by internally connecting the non-inverting input to ground. This is internally done by default from the decoder. The non-inverting input is rerouted to V10GND and can be grounded separately. The ITU-T-V.10 receivers can operate over 120Kbps and are used in RS-449/V.36, E1A-530, E1A-530A and X.21 modes as Category II signals as indicated by their corresponding specifications. All receivers include an enable/ disable line for disabling the receiver output allowing convenient half-duplex configurations. The enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on Figure 44. The receiver’s enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. During disabled conditions, the receiver outputs will be at a high impedance state. If the receiver is disabled any associated termination is also disconnected from the inputs.

FEATURES

All receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. For single-ended V.28 and V.10 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high (“1”) at the receiver outputs. The differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic HIGH (“1”) at the receiver output.

CHARGE PUMP

SP3508 uses an internal capacitive charge pump to generate Vdd and Vss. The design is Sipex patented (5,306,954) four-phased voltage shift-ing charge pump converters that converts the input voltage of 3.3V to nominal output volt-ages of +/-6V (Vdd & Vss1). SP3508 also in-cludes an inverter block that inverts Vcc to -Vcc (Vss2). There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows.

4-phased doubler pump

Phase 1

-VSS1 charge storage -During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C1+ is then switched to ground and the charge in C1- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2xVCC.

VCC = +3V

–3V –3V

+3V

VSS1 Storage Capacitor

VDD Storage Capacitor

C1 C2

+

+

+ + –

–––

CVDD

CVSS1

Figure 45. Charge Pump - Phase 1.

25


Phase 2

-VSS1 transfer -Phase two of the clock connects the negative terminal of C2 to the VSS1 storage capacitor and the positive terminal of C2 to ground, and transfers the negative generated voltage to CVSS1. Thisgenerated voltage is regulated to -5.5V. Simultaneously, the positive side of the capacitor C1 is switched to VCC and the negative side is connected to ground.

FEATURES

Phase 3

-VDD charge storage -The third phase of the clock is identical to the first phase-the charge transferred in C1 produces -VCC in the negative terminal of C1 which is applied to the negative side of the capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2xVCC.

VCC = +3V

–6V

VSS Storage Capacitor


C1 C2

+

+

+ + –

–––

CVDD

CVSS1


VCC = +3V

–3V

+3V

–3V



C1 C2

+

+

+ + –

–––

CVSS1

CVDD

Figure 47.Charge Pump - Phase 3.

Phase 4

-VDD transfer -The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers the generated 5.5V across C2 to CVDD, the VDD storage capacitor. This voltage is regulated to +5.5V. At the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor C1 is switched to VCC and the negative side is connected to ground, and the cycle begins again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V- are separately generated from VCC; in a no-load condition V+ and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of

V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 1µF with a 16V breakdown voltage rating.

26


VCC = +3V

+6V



C1 C2

+

+

+ + –

–––

CVDD

CVSS1


2-phased inverter pump

Phase 1

Please refer to figure below: In the first phase of the clock cycle, switches S2 and S4 are opened and S1 and S3 closed. This connects the flying capacitor, C3, from Vin to ground. C3 charge up to the input voltage applied at Vcc.

Phase 2

In the second phase of the clock cycle, switches S2 and S4 are closed and S1 and S3 are opened. This connects the flying capacitor, C3, in parallel with the output capacitor, CVSS2. The Charge stored in C3 is now transferred to CVSS2. Simultaneously, the negative side of CVSS2 is connected to VSS2 and the positive side is connected to ground. With the voltage across CVSS2 smaller than the voltage across C3, the charge flows from C3 to CVSS2 until the voltage at the VSS2 equals -VCC.

C3

S2S1

S3 S4VSS2

CVSS2

+ +

VCC

VSS2 = -VCC

Figure 49. Circuit for an Ideal Voltage Inverter.

FEATURES

27


R e c o

m m

e n d

e d S

i g n

a l s a n d

P o

r t P i n

A s s i g

n m

e n t s

P i n

N u m

b e r P

i n M n e m

o n i cC

i r c u i tP

i n M n e m

o n i cP

i n N

u m b e r

S i g n a l

T y p e

M n e m

o n i c

D B

-2 5 P

i n ( F )

S i g n a l

T y p e

M n e m

o n i c

D B

-2 5 P

i n ( F )

S i g n a l

T y p e

M n e m

o n i c

D B

-3 7 P

i n ( F )

S i g n a l

T y p e

M n e m

o n i c

M 3 4

P i n ( F

)S

i g n a l T

y p eM

n e m o

n i cD

B -1 5

P i n ( F

)3 1

T x D

S D

( A )

9 7V

. 2 8 B

B

3 V

. 1 1 B

B ( A

) 3

V . 1 1

R D

( A )

6 V

. 3 5 1 0 4

R

V . 1 1

R ( A

) 4

2S

D E

NS

D ( B

)9 9

V . 1 1

B B

( B )

1 6 V

. 1 1 R

D ( B

) 2 4

V . 3 5

1 0 4T

V

. 1 1 R

( B )

1 13 2

T x C

ET

T ( A

)9 3

V . 2 8

D D

1 7

V . 1 1

D D

( A )

1 7 V

. 1 1 R

T ( A

) 8

V . 3 5

1 1 5V

V

. 1 1 B

( A )

7 * *3

T T

E N

T T

( B )

9 5V

. 1 1 D

D ( B

) 9

V . 1 1

R T

( B )

2 6 V

. 3 5 1 1 5

X

V . 1 1

B ( B

) 1 4 * *

3 3S

TS

T ( A

)89

V . 2 8

D B

1 5

V . 1 1

D B

( A )

1 5 V

. 1 1 S

T ( A

) 5

V . 3 5

1 1 4Y

V

. 1 1 S

( A )

64

S T

E N

S T

( B )

9 1V

. 1 1 D

B ( B

) 1 2

V . 1 1

S T

( B )

2 3 V

. 3 5 1 1 4

A A

V

. 1 1 S

( B )

1 334

R T

SR

S ( A

)8 1

V . 2 8

C B

5

V . 1 1

C B

( A )

5 V

. 1 1 C

S ( A

) 9

V . 2 8

1 0 6D

V

. 1 1 I ( A

) 5

5R

S E

NR

S ( B

)8 3

V . 1 1

C B

( B )

1 3 V

. 1 1 C

S ( B

) 2 7

V . 1 1

I ( B )

1 23 5

D T

RT

R ( A

)8 5

V . 2 8

C C

6

V . 1 1

C C

( A )

6 V

. 1 1 D

M ( A

) 1 1

V . 2 8

1 0 7E

6T

R E

NT

R ( B

)8 7

V . 1 1

C C

( B )

2 2 V

. 1 1 D

M ( B

) 2 9

3 6D

C D

_ D C

ER

R C

( A )

7 9V

. 2 8 C

F

8 V

. 1 1 C

F ( A

) 8

V . 1 1

R R

( A )

1 3 V

. 2 8 1 0 9

F7

R R

C E

NR

R C

( B )

7 7V

. 1 1 C

F ( B

) 1 0

V . 1 1

R R

( B )

3 13 7

R L

R L ( A

)67

V . 2 8

C E

2 2

V . 2 8

1 2 5 J

8R

L E N

3 8L L

L L ( A )

6 5V

. 2 8 T

M

2 5 V

. 1 0 T

M

2 5 V

. 1 0 T

M

1 8 V

. 2 8 1 4 2

N N

9L L E

N #

3 9R

x DR

D ( A

)5 0

V . 2 8

B A

2

V . 1 1

B A

( A )

2 V

. 1 1 S

D ( A

) 4

V . 3 5

1 0 3P

V

. 1 1 T

( A )

21 0

R D

E N

#R

D ( B

)4 9

V . 1 1

B A

( B )

14 V

. 1 1 S

D ( B

) 2 2

V . 3 5

1 0 3S

V

. 1 1 T

( B )

94 0

R x C

R T

( A )

5 2V

. 2 8 D

A

2 4 V

. 1 1 D

A ( A

) 2 4

V . 1 1

T T

( A )

1 7 V

. 3 5 1 1 3

U

V . 1 1

X ( A

) 7 * *

1 1R

T E

N #

R T

( B )

5 1V

. 1 1 D

A ( B

) 1 1

V . 1 1

T T

( B )

3 5 V

. 3 5 1 1 3

W

V . 1 1

X ( B

) 1 4 * *

4 1T

x CT

x C ( A

)5 5

12T

x C E

N #

T x C

( B )

5 34 2

C T

SC

S ( A

)5 7

V . 2 8

C A

4

V . 1 1

C A

( A )

4 V

. 1 1 R

S ( A

) 7

V . 2 8

1 0 5C

V

. 1 1 C

( A )

31 3

C S

E N

#C

S ( B

)56

V . 1 1

C A

( B )

1 9 V

. 1 1 R

S ( B

) 2 5

V . 1 1

C ( B

) 1 0

4 3D

S R

D M

( A )

5 9V

. 2 8 C

D

2 0 V

. 1 1 C

D ( A

) 2 0

V . 1 1

T R

( A )

1 2 V

. 2 8 1 0 8

H1 4

D M

E N

#D

M ( B

)5 8

V . 1 1

C D

( B )

2 3 V

. 1 1 T

R ( B

) 3 0

4 4D

C D

_ D T

ER

R T

( A )

6 21 5

R R

T E

N #

R R

T ( B

)6 1

45R

II C

6 3V

. 2 8 R

L 2 1

V . 1 0

R L

2 1 V

. 1 0 R

L 1 4

V . 2 8

1 4 0N

1 6I C

E N

#4 6

T M

T M

( A )

6 4V

. 2 8 L L

1 8 V

. 1 0 L L

1 8 V

. 1 0 L L

1 0 V

. 2 8 1 4 1

L1 7

T M

E N

S P

3 5 0 8 M u

l t i p r o

t o c o

l C o

n f i g

u r e d

a s D C

E

I n t e r f a c e t o S y s t e m

L o g i cI n t e r f a c e t o P

o r t -C

o n n e c t o r

R e c e i v e r _ 4

R e c e i v e r _ 5

R e c e i v e r _ 6

D r i v e r _ 7

D r i v e r _ 8

R S

-4 4 9V

. 3 5X

. 2 1

D r i v e r _ 1

R S

-2 3 2 o r V . 2 4

E I A

-5 3 0

R e c e i v e r _ 2

R e c e i v e r _ 3

D r i v e r _ 2

D r i v e r _ 3

D r i v e r _ 4

D r i v e r _ 5

R e c e i v e r _ 1

D r i v e r _ 6

S p a r e d r i v e r s a n d r e c e i v e r s m

a y b e u s e d f o r o p t i o n a l s i g n a l s ( S i g n a l

Q u a l i t y , R

a t e D e t e c t , S

t a n d b y ) o r m a y b e d i s a b l e d u s i n g i n d i v i d u a l

e n a b l e p i n s f o r e a c h d r i v e r a n d r e c e i v e r

* * X . 2 1 u s e e i t h e r B

( ) o r X

( ) , n o t b o t hP

i n a s s i g n m e n t s a n d s i g n a l f u n c t i o n s a r e s u b j e c t t o n a t i o n a l o r r e g i o n a l v a r i a t i o n a n d

p r o p r i e t a r y / n o n -s t a n d a r d i m p l e m

e n t a t i o n s

R e c e i v e r _ 7

R e c e i v e r _ 8

D C

E C

O N

F I G

U R

A T

I O N

S P

3 5 0 8 E n h a n c e d W

A N

M u l t i – M

o d e S e r i a l T

r a n s c e i v e r

© C

o p y r i g h t 2 0 0 4 S i p e x C

o r p o r a t i o n

2 7

28


R e c o

m m

e n d

e d S

i g n

a l s a n d

P o

r t P i n

A s s i g

n m

e n t s

P i n

N u m

b e r P

i n M n e m

o n i cC

i r c u i tP

i n M n e m

o n i cP

i n N

u m b e r

S i g n a l

T y p e

M n e m

o n i c

D B

-2 5 P

i n ( M )

S i g n a l

T y p e

M n e m

o n i c

D B

-2 5 P

i n ( M )

S i g n a l

T y p e

M n e m

o n i c

D B

- 3 7 P

i n ( M )

S i g n a l

T y p e

M n e m

o n i c

M 3 4

P i n ( M

)S

i g n a l T

y p eM

n e m o

n i cD

B -1 5

P i n ( M

)3 1

T x D

S D

( A )

9 7V

. 2 8 B

A2

V . 1 1

B A

( A )

2 V

. 1 1 S

D ( A

) 4

V . 3 5

1 0 3P

V

. 1 1 T

( A )

22

S D

E N

S D

( B )

9 9V

. 1 1 B

A ( B

) 1 4

V . 1 1

S D

( B )

2 2 V

. 3 5 1 0 3

S

V . 1 1

T ( B

) 9

3 2T

x C E

T T

( A )

9 3V

. 2 8 D

A

2 4 V

. 1 1 D

A ( A

) 2 4

V . 1 1

T T

( A )

1 7 V

. 3 5 1 1 3

U

V . 1 1

X ( A

) 7 * *

3T

T E

NT

T ( B

)9 5

V . 1 1

D A

( B )

1 1 V

. 1 1 T

T ( B

) 3 5

V . 3 5

1 1 3W

V

. 1 1 X

( B )

1 4 * *3 3

ST

S T

( A )

894

S T

E N

S T

( B )

9 134

R T

SR

S ( A

)8 1

V . 2 8

C A

4 V

. 1 1 C

A ( A

) 4

V . 1 1

R S

( A )

7 V

. 2 8 1 0 5

C

V . 1 1

C ( A

) 3

5R

S E

NR

S ( B

)8 3

V . 1 1

C A

( B )

1 9 V

. 1 1 R

S ( B

) 2 5

V . 1 1

C ( B

) 1 0

3 5D

T R

T R

( A )

8 5V

. 2 8 C

D

2 0 V

. 1 1 C

D ( A

) 2 0

V . 1 1

T R

( A )

1 2 V

. 2 8 1 0 8

H6

T R

E N

T R

( B )

8 7V

. 1 1 C

D ( B

) 2 3

V . 1 1

T R

( B )

3 03 6

D C

D _ D

C E

R R

C ( A

)7 9

7R

R C

E N

R R

C ( B

)7 7

3 7R

LR

L ( A )

67V

. 2 8 R

L 2 1

V . 1 0

R L

2 1 V

. 1 0 R

L 1 4

V . 2 8

1 4 0N

8R

L E N

3 8L L

L L ( A )

6 5V

. 2 8 L L

1 8 V

. 1 0 L L

1 8 V

. 1 0 L L

1 0 V

. 2 8 1 4 1

L9

L L E N

#3 9

R x D

R D

( A )

5 0V

. 2 8 B

B3

V . 1 1

B B

( A )

3 V

. 1 1 R

D ( A

) 6

V . 3 5

1 0 4R

V

. 1 1 R

( A )

41 0

R D

E N

#R

D ( B

)4 9

V . 1 1

B B

( B )

1 6 V

. 1 1 R

D ( B

) 2 4

V . 3 5

1 0 4T

V

. 1 1 R

( B )

1 14 0

R x C

R T

( A )

5 2V

. 2 8 D

D

1 7 V

. 1 1 D

D ( A

) 1 7

V . 1 1

R T

( A )

8 V

. 3 5 1 1 5

V

V . 1 1

B ( A

) 7 * *

1 1R

T E

N #

R T

( B )

5 1V

. 1 1 D

D ( B

) 9

V . 1 1

R T

( B )

2 6 V

. 3 5 1 1 5

X

V . 1 1

B ( B

) 1 4 * *

4 1T

x CT

x C ( A

)5 5

V . 2 8

D B

1 5

V . 1 1

D B

( A )

1 5 V

. 1 1 S

T ( A

) 5

V . 3 5

1 1 4Y

V

. 1 1 S

( A )

612

T x C

E N

#T

x C ( B

)5 3

V . 1 1

D B

( B )

1 2 V

. 1 1 S

T ( B

) 2 3

V . 3 5

1 1 4 A

A

V . 1 1

S ( B

) 1 3

4 2C

T S

C S

( A )

5 7V

. 2 8 C

B5

V . 1 1

C B

( A )

5 V

. 1 1 C

S ( A

) 9

V . 2 8

1 0 6D

V

. 1 1 I ( A

) 5

1 3C

S E

N #

C S

( B )

56V

. 1 1 C

B ( B

) 1 3

V . 1 1

C S

( B )

2 7V

. 1 1 I ( B

) 1 2

4 3D

S R

D M

( A )

5 9V

. 2 8 C

C6

V . 1 1

C C

( A )

6 V

. 1 1 D

M ( A

) 1 1

V . 2 8

1 0 7E

1 4D

M E

N #

D M

( B )

5 8V

. 1 1 C

C ( B

) 2 2

V . 1 1

D M

( B )

2 94 4

D C

D _ D

T E

R R

T ( A

)6 2

V . 2 8

C F

8 V

. 1 1 C

F ( A

) 8

V . 1 1

R R

( A )

1 3 V

. 2 8 1 0 9

F1 5

R R

T E

N #

R R

T ( B

)6 1

V . 1 1

C F

( B )

1 0 V

. 1 1 R

R ( B

) 3 1

45R

II C

6 3V

. 2 8 C

E

2 2V

. 2 8 1 2 5

J1 6

I C E

N #

4 6T

MT

M ( A

)6 4

V . 2 8

T M

2 5

V . 1 0

T M

2 5

V . 1 0

T M

1 8

V . 2 8

1 4 2 N

N1 7

T M

E N

R S

- 4 4 9V

. 3 5X

. 2 1

R e c e i v e r _ 7

R e c e i v e r _ 8

R S

-2 3 2 o r V . 2 4

E I A

-5 3 0

R e c e i v e r _ 4

R e c e i v e r _ 5

R e c e i v e r _ 6

D r i v e r _ 7

D r i v e r _ 8

D r i v e r _ 6

D r i v e r _ 2

D r i v e r _ 3

D r i v e r _ 4

D r i v e r _ 5

S p a r e d r i v e r s a n d r e c e i v e r s m

a y b e u s e d f o r o p t i o n a l s i g n a l s ( S i g n a l

Q u a l i t y , R

a t e D e t e c t , S

t a n d b y ) o r m a y b e d i s a b l e d u s i n g i n d i v i d u a l

e n a b l e p i n s f o r e a c h d r i v e r a n d r e c e i v e r

* * X . 2 1 u s e e i t h e r B

( ) o r X

( ) , n o t b o t hP

i n a s s i g n m e n t s a n d s i g n a l f u n c t i o n s a r e s u b j e c t t o n a t i o n a l o r r e g i o n a l v a r i a t i o n a n d

p r o p r i e t a r y / n o n -s t a n d a r d i m p l e m

e n t a t i o n s

S P

3 5 0 8 M u

l t i p r o

t o c o

l C o

n f i g

u r e d

a s D T

E

I n t e r f a c e t o S y s t e m

L o g i cI n t e r f a c e t o P

o r t -C

o n n e c t o r

D r i v e r _ 1

R e c e i v e r _ 1

R e c e i v e r _ 2

R e c e i v e r _ 3

S P

3 5 0 8 E n h a n c e d W

A N

M u l t i – M

o d e S e r i a l T

r a n s ceiver v ©

C o p y r i g h t 2 0 0 4 S

i p e x C o r p o r a t i o n

2 8

D T

E C

O N

F I G

U R

A T

I O N

29


TERM_OFF FUNCTION

The SP3508 contains a TERM_OFF pin that dis-ables all three receiver input termination networksregardless of mode. This allows the device to beused in monitor mode applications typically foundin networking test equipment.

The TERM_OFF pin internally contains a pull-down device with an impedance of over 500kΩ,which will default in a "ON" condition duringpower-up if V.35 receivers enable line and theSHUTDOWN mode from the decoder will disablethe termination regardless of TERM_OFF.

LOOPBACK FUNCTION

The SP3508 contains a LOOPBACK pin thatinvokes a loopback path. This loopback path isillustrated in Figure 50. LOOPBACK has an inter-nal pull-up resistor that defaults to normal modeduring power up or if the pin is left floating. Duringloopback, the driver output and receiver inputcharacteristics will still adhere to its appropriatespecifications.

DECODER AND D_LATCH FUNCTION

The SP3508 contains a D_LATCH pin that latchesthe data into the D0, D1 and D2 decoder inputs. Iftied to a logic LOW ("0"), the latch is transparent,allowing the data at the decoder inputs to propa-gate through and program the SP3508 accord-ingly. If tied to a logic HIGH ("1"), the latch locksout the data and prevents the mode from changinguntil this pin is brought to a logic LOW.

FEATURES

There are internal pull-up devices on D0, D1 and

D2, which allow the device to be in SHUTDOWNmode ("111") upon power up. However, if thedevice is powered-up with the D_LATCH at alogic HIGH, the decoder state of the SP3508 willbe undefined.

CTR1/CTR2 EUROPEAN COMPLIANCY

As with all of Sipex's previous multi-protocolserial transceiver IC's the drivers and receivershave been designed to meet all the requirements toNET1/NET2 and TBR2 in order to meet CTR1/CTR2 compliancy. The SP3508 is also tested in-house at Sipex and adheres to all the NET1/2physical layer testing and the ITU Series V speci-fications before shipment. Please note that al-though the SP3508, as with its predecessors, ad-here to CRT1/CTR2 compliancy testing, any com-plex or usual configuration should be double-checked to ensure CTR1/CTR2 compliance. Con-sult the factory for details.

30


Figure 50. Loopback Path

SD(a)

SD(b)

RD(a)

RD(b)

TT(a)

TT(b)

RT(a)

RT(b)

TxD

RxD

TxCE

RxC

ST(a)

ST(b)

TxC(a)

TxC(b)

ST

TxC

RS(a)

RS(b)

CS(a)

CS(b)

TR(a)

TR(b)

DM(a)

DM(b)

RTS

CTS

DTR

DSR

RRC(a)

RRC(b)

RRT(a)

RRT(b)

DCD_DCE

DCD_DTE

RL(a)

IC

RL

RI

LL(a)

TM(a)

LL

TM

31

39

32

40

33

41

34

42

35

43

36

44

37

45

38

46

97

99

50

49

93

95

52

51

89

91

55

53

81

83

57

56

85

87

59

58

79

77

62

61

67

63

65

64

31


Figure 51. SP3508 Typical Operating Configuration to Serial Port Connector with DCE/DTE programmability

20 (V.11, V.28) DTR_DSR_A 23 (V.11) DTR_DSR_B

1µF 1µF

CVDD

VCC

VDD C1- C2-C1+ C2+1µF

SP3508CF

TxD

TxCE

ST

RTS

DTR

DCD_DCE

RL

RxC

TxC

CTS

DSR

DCD_DTE

RI

TM

10µF

µDB-26 Serial Port Connector Pins Signal (DTE_DCE)

2 (V.11, V.35, V.28) TXD_RXD_A 14 (V.11, V.35) TXD_RXD_B

11 (V.11, V.35) TXCE_TXC_B

25 (V.10, V.28) LL_TM

15 (V.11, V.35, V.28) *TXC_RXC_A 12 (V.11, V.35) *TXC_RXC_B

SDEN

24 (V.11, V.35, V.28) TXCE_TXC_A

3 (V.11, V.35, V.28) RXD_TXD_A 16 (V.11, V.35) RXD_TXD_B

8 (V.11, V.28) DCD_DCD_A 10 (V.11) DCD_DCD_B

9 (V.11, V.35) RXC_TXCE_B 17 (V.11, V.35, V.28) RXC_TXCE_A

LLEN

STEN

GND

* - Driver applies for DCE only on pins 15 and 12. Receiver applies for DTE only on pins 15 and 12.

+3.3V

I/O Lines represented by double arrowhead signifies a bi-directional bus.

Input Line Output Line

LL

RxD

TTEN

RSEN TREN RRCENRLEN

RDEN

TMEN

TxCENRTEN

CSEN DMEN RRTENICEN

TERM_OFF

D_LATCH

D0

D1

D2

Charge Pump Section

Transceiver Section

Logic Section+3.3V

21 (V.10, V.28) RL_RI

22 (V.10, V.28) RI_RL

18 (V.10, V.28) LL_TM

DCE/DTE

Driver applies for DCE only on pins 8 and 10. Receiver applies for DTE only on pins 8 and 10.

LOOPBACK +3.3V

19 (V.11) RTS_CTS_B 4 (V.11, V.28) RTS_CTS_A

6 (V.11, V.28) DSR_DTR_A 22 (V.11) DSR_DTR_B

13 (V.11) CTS_RTS_B 5 (V.11, V.28) CTS_RTS_A

31SD(a)

35

34

38

39

40

42

43

44

41

32

36

45

37

46

AGND

SD(b)

TT(a)

TT(b)

ST(a) ST(b)

RS(a)

RS(b)

TR(a)

TR(b)

RRC(a)

RRC(b)

RL(a)

RD(a)

LL(a)

RD(b)

RT(a)

RT(b)

TxC(a) TxC(b)

CS(a)

CS(b)

DM(a)

DM(b)

RRT(a)

RRT(b)

IC

TM(a)

18

19

20

97

99

93

95

89 91

81

83

85

87

79

77

67

50

65

49

51

55

53

57

56

59

58

62

61

63

64

52

21

22

30

28

+3.3V

AVCC

24

26 68

27VSS2

VSS1

C3+C3-

69 72 70 74 76

29

1µF

C1 C2

C3

CVSS1

CVSS2

23456789

10

11

12 13

14 15 16 17

33

32


PACKAGE: 100 PIN LQFP

100 PIN LQFP

PIN 1

E1

D1

D

CL

b e

Seating Plane

A1

CL E

A

L

11°-13°

0°MIN

0°–7°

0.2 RAD MAX.

0.08 RAD MIN.

DIMENSIONS Minimum/Maximum

(mm)

SYMBOL

A

A1

A2

b

D

D1

e

E

E1

N

100–PIN LQFP JEDEC MS-026 (BED) Variation

MIN NOM MAX

1.60

0.05 0.15

1.35 1.40 1.45

0.17 0.22 0.27

16.00 BSC

14.00 BSC

0.50 BSC

16.00 BSC

14.00 BSC

100

A

c

L1

A2

11°-13°

COMMON DIMENSIONS

SYMBL MIN NOM MAX

c 0.09 0.20

L 0.45 0.60 0.75

L1 1.00 REF

33


ORDERING INFORMATION

Part Number Temperature Range Package TypesSP3508CF ............................................. 0°C to +70°C ................................................. 100–pin JEDEC LQFP SP3508EF ......................................... -40°C to +85°C ................................................. 100–pin JEDEC LQFP

Corporation

ANALOG EXCELLENCE

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Sipex Corporation

Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

REVISION HISTORY

Available in lead free packaging. To order add “-L” suffix to part number.

Example: SP3508EF = standard; SP3508EF-L = lead free

DATE REVISION DESCRIPTION1/12/04 A Implemented tracking revision.2/27/04 B Included Diamond column in spec table indicating which specs apply

over full operating temp. range. In figure 51, fixed typo on pin 61 and 62 from an input line to a bidirectional bus.

3/31/04 C Corrected max dimension for symbol c on LQFP package. 6/3/04 D Added tables to page 27 and 28.

10/12/04 E Certified conformance to NET1/NET2 and TBR-1 TBR-2 BY TUV

Rheinland (Test Report # TBR2/30451940.001/04)

10/29/04 F Corrected V.28 Driver Open Circuit values, pages 27 and 28 -- both for DCE and DTE that BA(B) should go to pin 14.

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Documents

Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with … · 2012. 4. 13. · T r a n s i t i o n T i m e 1 . 5 ♦♦ µ s pe r F i g u r e 6 , + 3 V t o -3 V I n s t a n