RTU Paper Solution - Global Institute of Technology, Jaipur · Solution VI and VIII sem University Examination 2019 Subject: Microcontroller &Embedded System Code: 8EC4.3A Semester:

Global Institute of Technology, Jaipur ITS-1, IT Park, EPIP, Sitapura Jaipur 302022 (Rajasthan)

Solution VI and VIII sem University Examination 2019

Subject: Microcontroller &Embedded System Code: 8EC4.3A Semester: VIII/Year: IV

RTU Paper Solution

Branch – Electronics & Communication Engineering

Subject Name –Microcontroller and Embedded System

Paper Code –8E8026

Date of Exam –20/4/2019










UNIT –I

Ans 1(a)

The programming model of 8051 contain 8 or 16 bit registers and memory locations. Each registers

has an internal 1 byte address with exception of program counter. Some registers has byte as well as

bit addressable.The assembly language is a low-level programming language used to write program

code in terms of mnemonics. Even though there are many high-level languages that are currently in

demand, assembly programming language is popularly used in many applications.It can be used for

direct hardware manipulations. It is also used to write the 8051 Code efficiently with less number of

clock cycles by consuming less memory compared to the other high-level languages.

Programming model and Architecture of 8051 Microcontroller




Registers are mainly used while programming microcontrollers in assembly language. But for c

programming, we still need to know about some registers. Registers are used to perform MOV and

ADD instructions.

Registers

As you know in microprocessors registers are used to store temporary instructions and data.

Instructions are used to processed addresses to fetch data. 8051 microcontrollers have 8 bit

registers. 8 bit registers have 8 bit start from D0-D7. D0 is least significant bit and D7 is least

significant bit. To process data larger than 8 bit, it should be broken into 8 bit pieces. It has many

registers but general purpose registers are mostly accessible to programmers. There are two types of

registers 1) General purpose registers 2) Special purpose registers. List of mostly used general

purpose registers is given below:

A accumulator ( It is used to perform arithmetic and logic instructions)

B, R0, R1, R2, R3, R4, R5, R6, R7 registers ( They are used to store instruction address and

data)

DPTR ( Data pointers is used to access and process data in different addressing modes) It

consists of high byte ( DPH) and a low byte (DPL) . It is used to hold 16 bit address. It is

used as a base register in indirect jumps, external data transfer and lookup table instructions.

PC (Program counter is 16 bit register. It is used to store the address of next instruction to be

executed )

All these registers are of 8-bits other than data pointer and program counter registers.

8051 data type

8051 microcontroller has only one data type of 8 bit. The size of each register is also 8 bit. If data is

larger than 8 bit, it is programmer responsibility to divide data into 8 bit pieces before processing.

DB directive is most widely used data directive in assembly language for assemblers.

Program status word register




8051 microcontroller has program status register also know as flag register. Flag register is used to

show status of arithmetic logic instructions like carry bit, zero carry bit etc. PSW is an 8 bit register.

Only 6 bits are used. PSW register is also called flag register. Flag register has 8 flags. Four flags are

called conditional flags which execute instruction only if condition is fulfilled. These conditional

flags are OV (overflow), P (parity), AC (auxiliary carry) and CY (carry). Bit number 3 and 4 of

PSW register is used to change the bank registers. Bit number 1 and 5 of program status register are

unused and it can be used by programmer for any specific purpose.

Register banks

32 Bytes of RAM are dedicated for register banks and stacks. These 32 bytes are broken in four

banks. Each back has 8 registers from R0-R7. R0 is RAM location zero and so R7 is RAM location

seven. The second bank register is started from location 8 and end 05H. The third bank starts from

10H and finished on location 17H. The last bank is located between the 18H-1FH.

8051 microcontroller stack

Stack is a part of RAM which is used by the processor to store data or an address temporarily. Stack

is very important part of microprocessor because there are very limited numbers of registers to store

data and addresses. Stack pointer is 8051 is 8 bit wide. It means it can hold data from 00 to FFH.

Stack pointer is used by CPU to access the stack. 8051 have 8 bit stack pointer. It means it can

access values from 00H-FFH. When it is turned on, the stack pointer contains value of 07.

Memory in 8051

It have complex memory organization. Because 8051 microcontroller have separate adress bus for

program memory, Data memory and exteranl RAM. It is based on Harvard architecture developed

by Harvard in 1944. It may consists of internal or external program memory. It can support upto 64k

bytes of external memory. I have 128 bytes of internal data memory.




Ans 1 (b)

ALE (Pin 31) − This is ALE pin which stands for Address Latch Enable. It is used to

demultiplex the address-data signal of port.

RST (Pin 9) − It is a RESET pin, which is used to reset the microcontroller to its initial

values.

EA (Pin 30) − This is EA pin which stands for External Access input. It is used to

enable/disable the external memory interfacing.

PSEN (Pin 29) − This is PSEN pin which stands for Program Store Enable. It is used to read

a signal from the external program memory.

OR

Ans 1 (a)

8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or output.

Hence, total 32 input/output pins allow the microcontroller to be connected with the peripheral

devices.

Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per the

logic state.

o Input/Output (I/O) pin − All the circuits within the microcontroller must be

connected to one of its pins except P0 port because it does not have pull-up resistors

built-in.

o Input pin − Logic 1 is applied to a bit of the P register. The output FE transistor is

turned off and the other pin remains connected to the power supply voltage over a

pull-up resistor of high resistance.

Port 0 − The P0 (zero) port is characterized by two functions −

o When the external memory is used then the lower address byte (addresses A0A7) is

applied on it, else all bits of this port are configured as input/output.




When P0 port is configured as an output then other ports consisting of pins with built-

in pull-up resistor connected by its end to 5V power supply, the pins of this port have

this resistor left out.

Port 1

P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can be

configured as general I/O only. It has a built-in pull-up resistor and is completely compatible with

TTL circuits.

Port 2

P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses intended

for the external memory chip. This port can be used for higher address byte with addresses A8-A15.

When no memory is added then this port can be used as a general input/output port similar to Port1.

Port 3

In this port, functions are similar to other ports except that the logic 1 must be applied to

appropriate bit of the P3 register.

Input Configuration

If any pin of this port is configured as an input, then it acts as if it “floats”, i.e. the input has

unlimited input resistance and in-determined potential.

Output Configuration

When the pin is configured as an output, then it acts as an “open drain”. By applying logic 0 to a

port bit, the appropriate pin will be connected to ground (0V), and applying logic 1, the external

output will keep on “floating”.

In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup resistor.




Ans 1 (b)

Timer Mode control (TMOD) Special Function Register:

TMOD register is not bit addressable.

TMOD

Address: 89 H

Various bits of TMOD are described as follows -

Gate: This is an OR Gate enabled bit which controls the effect of on START/STOP of Timer. It is set

to one ('1') by the program to enable the interrupt to start/stop the timer. If TR1/0 in TCON is set and signal

on pin is high then the timer starts counting using either internal clock (timer mode) or external pulses

(counter mode).

It is used for the selection of Counter/Timer mode.

Mode Select Bits:




M1 and M0 are mode select bits.

SCON (Serial Port Control Register)

Serial port control and status register is the special function register SCON.

This register contain not only the mode selection bits but also the 9th data bit for transmit and

receive (TB8 and RB8) and the serial part interrupt bits (TI and RI)

SMO – Serial port mode 0 shift register

SM1 – serial port mode 1 8 bit UAR + variable

SM2 – enable multiprocessor communication in mode 2/3

REN – set/ clear by software to enable/disable reception

TB8 – the 9th bit that will be transmitted in mode 2/3 set/clear by software.

RB8 – in mode 2/3 it is the 9th bit that was received in mode 1 if SM2 =0, RB8 is the stop bit that

was received in mode it is not used.

TI – transmit interrupt flag set by hardware at the end of 8 bit time in mode 0 at the beginning of the

stop bit in the other mode it must be cleared by software




RI – receive interrupt flag set by hardware and must be cleared by software.

SMO SM1 Mode Description Baud Rate

0 0 Mode 0 Shift register (fosc/12)

0 1 Mode 1 9 bit UART variable

1 0 Mode 2 9 bit UART (fosc/64) or

(fosc/32)

1 1 Mode 3 9 bit UART variable

UNIT II

Ans 2 (a)

Introduction to 8051 Microcontroller Instruction Set

Writing a Program for any Microcontroller consists of giving commands to the Microcontroller in a

particular order in which they must be executed in order to perform a specific task. The commands

to the Microcontroller are known as a Microcontroller’s Instruction Set.

Just as our sentences are made of words, a Microcontroller’s (for that matter, any computer) program

is made of Instructions. Instructions written in a program tell the Microcontroller which operation to

carry out.

An Instruction Set is unique to a family of computers. This tutorial introduces the 8051

Microcontroller Instruction Set also called as the MCS-51 Instruction Set.

As the 8051 family of Microcontrollers are 8-bit processors, the 8051 Microcontroller Instruction Set

is optimized for 8-bit control applications. As a typical 8-bit processor, the 8051 Microcontroller




instructions have 8-bit Opcodes. As a result, the 8051 Microcontroller instruction set can have up to

28 = 256 Instructions.

Arithmetic instructions

Arithmetic instructions perform several basic operations such as addition, subtraction, division,

multiplication etc. After execution, the result is stored in the first operand. For example: ADD A,

R1 - The result of addition (A+R1) will be stored in the accumulator.

ARITHMETIC INSTRUCTIONS

Mnemonic Description Byte Cycle

ADD A,Rn Adds the register to the

accumulator 1 1

ADD A,direct Adds the direct byte to the

accumulator 2 2

ADD A,@Ri Adds the indirect RAM to

the accumulator 1 2

ADD A,#data Adds the immediate data

to the accumulator 2 2

ADDC A,Rn

Adds the register to the

accumulator with a carry

flag

1 1

ADDC A,direct

Adds the direct byte to the

accumulator with a carry

flag

2 2




ADDC A,@Ri

Adds the indirect RAM to

the accumulator with a

carry flag

1 2

ADDC A,#data

Adds the immediate data

to the accumulator with a

carry flag

2 2

SUBB A,Rn

Subtracts the register from

the accumulator with a

borrow

1 1

SUBB A,direct

Subtracts the direct byte

from the accumulator with

a borrow

2 2

SUBB A,@Ri

Subtracts the indirect

RAM from the

accumulator with a

borrow

1 2

SUBB A,#data

Subtracts the immediate

data from the accumulator

with a borrow

2 2

INC A Increments the

accumulator by 1 1 1

INC Rn Increments the register by

1 1 2

INC Rx Increments the direct byte 2 3




by 1

INC @Ri Increments the indirect

RAM by 1 1 3

DEC A Decrements the

accumulator by 1 1 1

DEC Rn Decrements the register

by 1 1 1

DEC Rx Decrements the direct

byte by 1 1 2

DEC @Ri Decrements the indirect

RAM by 1 2 3

INC DPTR Increments the Data

Pointer by 1 1 3

MUL AB Multiplies A and B 1 5

DIV AB Divides A by B 1 5

DA A

Decimal adjustment of the

accumulator according to

BCD code

1 1




Ans 2 (b)

Byte-Level Logical Operations

The byte-level logical operations use all four addressing modes for the source of a data byte. The A

register or a direct address in internal RAM is the destination of the logical operation result.

Keep in mind that all such operations are done using each individual bit of the destination and source

bytes. These operations, called byte-level Boolean operations because tlfe entire byte is affected, are

listed in the following table:

Mnemonic Operation

ANL A,#n AND each bit of A with the same bit of immediate

number n; put the results in A

ANL. A.add AND each bit of A with the same bit of the direct RAM

address; put the results in A

ANLA,Rr AND each bit of A with the same bit of register Rr; put

the results in A AND each bit of A with the same bit of

the contents of the RAM address contained in Rp; put

the results in A

ANL A,@Rp AND each bit of A with the direct RAM address; put the

results in the direct RAM address

ANL add.A AND each bit of the RAM address with the same bit in

the number n; put the result in the RAM address

ANL add,#n OR each bit of A with the same bit of n; put the results

in A

ORL A,#n OR each bit of A with the same bit of the direct RAM





ORL A,add OR each bit of A with the same bit of register Rr; put the

results in A OR each bit of A with the same bit of the

contents of the RAM address contained in Rp; put the

results in A

ORL A,Rr OR each bit of A with the direct RAM address; put the


ORL A,@Rp OR each bit of the RAM address with the same bit in the

number n; put the result in the RAM address

ORL add.A XOR each bit of A with the same bit of n; put the results

in A

ORL add,#n XOR each bit of A with the same bit of the direct RAM


XRL A,#n XOR each bit of A with the same bit of register Rr; put

the results in A XOR each bit of A with the same bit of

the contents of the RAM address contained in Rp; put

the results in A

XRL A,add XOR each bit of A with the direct RAM address; put the


XRL A,Rr Operation

XRL A,@Rp AND each bit of A with the same bit of immediate

number n; put the results in A

XRL add.A AND each bit of A with the same bit of the direct RAM


XRL add,#n XOR each bit of the RAM address with the same bit in

the number n; put the result in the RAM address

CLRA Clear each bit of the A register to zero




CPL A Complement each bit of A; every I becomes a 0, and

each 0 becomes a 1

Bit-Level Logical Operations

Certain internal RAM and SFRs can be addressed by their byte addresses or by the address of each

bit within a byte. Bit addressing is very convenient when you wish to alter a single bit of a byte, in a

control register for instance, without having to wonder what you need to do to avoid altering some

other crucial bit of the same byte. The assembler can also equate bit addresses to labels that make the

program more readable. For example, bit 4 of TCON can become TR0, a label for the timer 0 run

bit.

The ability to operate on individual bits creates the need for an area of RAM that contains data

addresses that hold a single bit. Internal RAM byte addresses 20h to 2Fh serve this need and are both

byte and bit addressable. The bit addresses are numbered from 00h to 7Fh to represent the 12Sd bit

addresses (16d bytes x S bits) that exist from byte addresses 20h to 2Fh. Bit 0 of byte address 20h is

bit address 00h, and bit 7 of byte address 2Fh is bit address 7Fh. You must know your bits from your

bytes to take advantage of this RAM area.

The following table lists the Boolean bit-level operations.

Mnemonic Operation

ANL C,b AND C and the addressed bit; put the

result in C

ANL C,/b AND C and the complement of the

addressed bit; put the result in C; the

addressed bit is not altered

ORL C,b OR C and the addressed bit; put the result

in C

ORLC,/b OR C and the complement of the




addressed bit; put the result in C; the

addressed bit is not altered

CPLC Complement the C flag

CPL b Complement the addressed bit

CLRC Clear the C flag to zero

CLR b Clear the addressed bit to zero

MOV C,b Copy the addressed bit to the C flag

MOV b,C Copy the C flag to the addressed bit

SETB C Set the flag to one

SETB b Set the addressed bit to one

OR

Ans 2 (a)

Addressing mode is a way to address an operand. Operand means the data we are operating upon (in

most cases source data). It can be a direct address of memory, it can be register names, it can be any

numerical data etc. I will explain this with a simple data move instruction of 8051.

MOV A,#6AH

Here the data 6A is the operand, often known as source data. When this instruction is executed, the

data 6AH is moved to accumulator A.

In 8051 There are six types of addressing modes.

Immediate Addressing Mode

Register Addressing Mode

Direct Addressing Mode




Register Indirect Addressing Mode

Indexed Addressing Mode

Implied Addressing Mode

Immediate addressing mode

In this Immediate Addressing Mode, the data is provided in the instruction itself. The data is

provided immediately after the opcode. These are some examples of Immediate Addressing Mode.

MOVA, #0AFH;

MOVR3, #45H;

MOVDPTR, #FE00H;

In these instructions, the # symbol is used for immediate data. In the last instruction, there is DPTR.

The DPTR stands for Data Pointer. Using this, it points the external data memory location. In the

first instruction, the immediate data is AFH, but one 0 is added at the beginning. So when the data is

starting with A to F, the data should be preceded by 0.

Register addressing mode

In the register addressing mode the source or destination data should be present in a register (R0 to

R7). These are some examples of RegisterAddressing Mode.

MOVA, R5;

MOVR2, #45H;

MOVR0, A;

In 8051, there is no instruction like MOVR5, R7. But we can get the same result by using this

instruction MOV R5, 07H, or by using MOV 05H, R7. But this two instruction will work when the

selected register bank is RB0. To use another register bank and to get the same effect, we have to




add the starting address of that register bank with the register number. For an example, if the RB2 is

selected, and we want to access R5, then the address will be (10H + 05H = 15H), so the instruction

will look like this MOV 15H, R7. Here 10H is the starting address of Register Bank 2.

Direct Addressing Mode

In the Direct Addressing Mode, the source or destination address is specified by using 8-bit data in

the instruction. Only the internal data memory can be used in this mode. Here some of the examples

of direct Addressing Mode.

MOV80H, R6;

MOVR2, 45H;

MOVR0, 05H;

The first instruction will send the content of registerR6 to port P0 (Address of Port 0 is 80H). The

second one is forgetting content from 45H to R2. The third one is used to get data from Register R5

(When register bank RB0 is selected) to register R5.

Register indirect addressing Mode

In this mode, the source or destination address is given in the register. By using register indirect

addressing mode, the internal or external addresses can be accessed. The R0 and R1 are used for 8-

bit addresses, and DPTR is used for 16-bit addresses, no other registers can be used for addressing

purposes. Let us see some examples of this mode.

MOV0E5H, @R0;

MOV@R1, 80H

In the instructions, the @ symbol is used for register indirect addressing. In the first instruction, it is

showing that theR0 register is used. If the content of R0 is 40H, then that instruction will take the




data which is located at location 40H of the internal RAM. In the second one, if the content of R1 is

30H, then it indicates that the content of port P0 will be stored at location 30H in the internal RAM.

MOVXA, @R1;

MOV@DPTR, A;

In these two instructions, the X in MOVX indicates the external data memory. The external data

memory can only be accessed in register indirect mode. In the first instruction if the R0 is holding

40H, then A will get the content of external RAM location40H. And in the second one, the content

of A is overwritten in the location pointed by DPTR.

Indexed addressing mode

In the indexed addressing mode, the source memory can only be accessed from program memory

only. The destination operand is always the register A. These are some examples of Indexed

addressing mode.

MOVCA, @A+PC;

MOVCA, @A+DPTR;

The C in MOVC instruction refers to code byte. For the first instruction, let us consider A holds

30H. And the PC value is1125H. The contents of program memory location 1155H (30H + 1125H)

are moved to register A.

Implied Addressing Mode

In the implied addressing mode, there will be a single operand. These types of instruction can work

on specific registers only. These types of instructions are also known as register specific instruction.

Here are some examples of Implied Addressing Mode.

RLA;




SWAPA;

Ans 2(b)

ConditionalJump:

For every interesting or meaningful situation of flags, a conditional jump is there. For example JZ

and JNZ check the zero flag. If in a comparison both operands are same, the result of subtraction will

be zero and the zero flag will be set. Thus JZ and JNZ can be used to test equality. That is why there

are renamed versions JE and JNE read as jump if equal or jump if not equal.They seem more logical

in writing but mean exactly the same thing with the same opcode. Many jumps are renamed with two

or three names for the same jump, so that the appropriate logic can be conveyed in assembly

language programs. This renaming is done by Intel and is a standard for iAPX88. JC and JNC test

the carry flag. For example we may need to test whether there was an overflow in the last unsigned

addition or subtraction. Carry flag will also be set if two unsigned numbers are subtracted and the

first is smaller than the second. Therefore the renamed versions JB, JNAE, and JNB, JAE are there

standing for jump if below, jump if not above or equal, jump if not below, and jump if above or

equal respectively.

Unconditional Jump:

There is no such restriction and we can define data anywhere in the code. Taking the previous

example, if we place data at the start of code instead of at the end and we load our program in the

debugger. We can see our data placed at the start but the debugger is intending to start execution at

our data. The COM file definition said that the first executable instruction is at offset 0100 but we

have placed data there instead of code. So the debugger will try to interpret that data as code and

showed whatever it could make up out of those opcodes.

SJMP refers to short jump and LJMP refers to long jump. All the conditional jumps are short jumps.

SJMP: This instruction is of two bytes in which first one is opcode & second is the address. The

relative address of the instruction called should be in between -127 to 127 bytes from the current

program counter (PC).




LJMP: This instruction is of three bytes in which the first is the opcode and the second & third are

for address. The relative address of the instruction can be anywhere on the ROM. So it is clear from

the above examples that we can use different jump instructions with a condition or counter called

conditional loop. And when we create loop inside an existing loop it is called nested loop.

UNIT –III

Ans 3 (a)

Interrupt.:

When a Process is executed by the CPU and when a user Request for another Process then this will

create disturbance for the Running Process. This is also called as the Interrupt.

Interrupts can be generated by User, Some Error Conditions and also by Software’s and the

hardware’s. But CPU will handle all the Interrupts very carefully because when Interrupts are

generated then the CPU must handle all the Interrupts Very carefully means the CPU will also

Provides Response to the Various Interrupts those are generated. So that When an interrupt has

Occurred then the CPU will handle by using the Fetch, decode and Execute Operations.

Types of Interrupts

Generally there are three types o Interrupts those are Occurred For Example

1) InternalInterrupt

2) SoftwareInterrupt.

3) External Interrupt.

The External Interrupt occurs when any Input and Output Device request for any Operation and

the CPU will Execute that instructions first For Example When a Program is executed and when we

move the Mouse on the Screen then the CPU will handle this External interrupt first and after that he

will resume with his Operation.

The Internal Interrupts are those which are occurred due to Some Problem in the Execution For

Example When a user performing any Operation which contains any Error and which contains any




type of Error. So that Internal Interrupts are those which are occurred by the Some Operations or by

Some Instructions and the Operations those are not Possible but a user is trying for that Operation.

And The Software Interrupts are those which are made some call to the System for Example while

we are Processing Some Instructions and when we wants to Execute one more Application

Programs.

Interrupts are basically the events that temporarily suspend the main program, pass the control to the

external sources and execute their task. It then passes the control to the main program where it had

left off.

8051 has five interrupts. These interrupts are INT0, INT1,TO ,T1 , TI/RI. All of the interrupts can

be enabled or disabled by using the IE (interrupt enable) register.

The interrupt addresses of these interrupts are like below:

Interrupt Address

INT0 0003H

INT1 000BH

T0 0013H

T1 001BH

TI/RI 0023H

Interrupt Enable (IE)Register

This register can be used to enable or disable interrupts programmatically. This register is an SFR.

The address is A8H. This byte is bit addressable. So it can be programmed by the user. The bits in

this register has a different meaning. The register structure is looking like this:




BitAddress AF AE AD AC AB AA A9 A8

Bit Details EA X X ES ET1 EX1 ET0 EX0

Now, let us see the bit details and different operations when the value is low (0) and high(1).

Bit

Details

High Value(1) Low Value(0)

EA Least significant 5 bits can decide enable

or disable of these five interrupts.

Disable all five interrupts. It just ignores

the rest five bits.

ES Enable Serial Port Interrupt Disable Serial Port Interrupt

ET1 Enable Timer1 interrupt Disable Timer1 interrupt

EX1 Enable external interrupt 1 (INT1) Disable external interrupt 1 (INT1)

ET0 Enable Timer0 interrupt Disable Timer0 interrupt

EX0 Enable external interrupt 0 (INT0) Disable external interrupt 0 (INT0)

Interrupt Priority (IP) Register

All of these five interrupts can be in one or two interrupt level. The priority levels are level 1 and

level 0. Priority level 1 indicates the higher priority, and level 0 indicates lower priority. This IP

register can be used to store the priority levels for each interrupt. This is also a bit addressable SFR.

Its address is B8H.

BitAddress BF BE BD BC BB BA B9 B8

Bit Details X X X PS PT1 PX1 PT0 PX0





Bit

Details

High Value(1) Low Value(0)

PS Set 1 level priority of Serial port interrupt Set 0 level priority of Serial port

interrupt

PT1 Set 1 level priority of Timer1 interrupt Set 0 level priority of Timer1 interrupt

PX1 Set 1 level priority of external interrupt 1

(INT1)

Set 0 level priority of external interrupt 1

(INT1)

PT0 Set 1 level priority of Timer0 interrupt Set 0 level priority of Timer0 interrupt

PX0 Set 1 level priority of external interrupt 0

(INT0)

Set 0 level priority of external interrupt 0

(INT0)

When all of the five interrupts are in same priority level, and if all of the interrupts are enabled, then

the sequence of interrupts will be INT0, T0, INT1, T1, TI/R I.

Some specific priority register value can be used to maintain the priorities of the interrupts. Let the

value of Priority register is xxx00101 indicates the sequence INT0, INT1, TI/RI, T1, T0. But all of

the sequences are not feasible. Like INT0, INT1, TI/RI, T1, T0 is not valid.

External Interrupt

The external interrupts of 8051 are INT0and. INT1 These interrupts can be programmed to either

edge-triggered or level triggered. The TCON register can be used top rogram external interrupts to

edge or level triggered. The TCON isTimer Control. TCON is another bit addressable SFR. Here the

address is 88H.




BitAddress 8F 8E 8D 8C 8B 8A 89 88

Bit Details TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0


Bit Details High Value(1) Low Value(0)

IT0 Set ( INT0) as negative edge triggeredinput. Set ( INT0) as active low level

triggered input.

IT1 Set ( INT1) as negative edge triggeredinput. Set ( INT1) as active low level

triggered input.

IE0 This will be 1, when INT0is activated as level

triggered.

This will be 0, when INT0is

activated as edge triggered.

IE1 This will be 1, when INT1 is activated as level

triggered.

This will be 0, when INT1 is

activated as edge triggered.

TR0 Set Timer0 as run mode Set Timer0 as stop mode.

TR1 Set Timer1 as run mode Set Timer1 as stop mode.

TF0 High when Timer T0 overflow occurs. After resetting the timer T0

thiswill also be changed to 0

state

TF1 High when Timer T1 overflow occurs. After resetting the timer T1

this will also be changed to 0

state.




The IT0 and IT1 are stands for Interrupt Type. These bits are used to decide whether

the INT0 and INT1 will be level trigged or edge triggered.

IE0 and IE1 bits are used to indicate the status of external interrupts. These bit can be set or reset by

the microcontroller itself.

The first four bits are the status information about timers. When TR0 and TR1 are 1, it indicates the

running mode of the timers. These bits provide software control over the running of timers. Timers

can also be controlled by the hardware. The priority of hardware mode is higher than the software

mode.

The TF0 and TF1 are used to indicate the overflow of timer T0 and T1 respectively. When over flow

occurs these flags are set to 1. When the interrupt is handled by some interrupt service subroutine

(ISS), these will be 0.

Serial Port Interrupt

Bit

Details

Description

SM0 This is Serial Port Mode 0 shift register

SM1 This is Serial Port Mode 1 (8-bit UAR + variable)

SM2 Enable multiprocessor communication in the mode 2 or 3

REN Set or reset by the software to enable or disable the Reception

TB8 It indicates the 9th bit that will be transmitted in mode 2 or 3. It can be set or




The serial ports can be used either Transmitting mode or reception mode. The interrupt status for the

Transmission is provided by TI, and status for Reception is provided by RI. These are two bits of

SCON(Serial Control). This is also a bit addressable SFR. The address is98H

BitAddress 9F 9E 9D 9C 9B 9A 99 98

Bit Details SM0 SM1 SM2 REN TB8 RB8 TI RI

The interrupt Structure of 8051 is like below:

reset by the software

RB8 In mode 2 or 3, the 9th bit was received in mode 1.

TI The transmission interrupt flag. It can be set by hardware.

RI The receiver interrupt flag. It can be set by hardware but must be reset by

software.




Ans 3 (b)

Maskable Interrupt

A maskable interrupt is a one that can be suppressed by software/code. That is to say, it may be

ignored. Usually there are standard interrupt masking techniques for every processor, so that it may

not be interrupted while performing some crucial task. Maskable interrupts can be ignored

usingthesemethods.

Non-Maskable Interrupt:

Non-maskable interrupts are, likewise, those which can (and should) not be ignored. So events like

critical hardware failure and system resets are attached to non-maskable interrupts to ensure that

there's a "way out".

OR







Ans 3 (b)

Software and Hardware Timers Everything is based on time the ability to time intervals or to

generate signals with a particular interval time are common requirements

1. software delay loop „

easy to insert; requires no additional hardware „

problem if other actions are to be done in parallel „

can be accurate if code is carefully timed „

IDE may have timing option

2. hardware timer „

integrated into microcontroller or separate chip „

can be exact „

allows actions in parallel

UNIT –IV

Ans 4

SERIAL DATA COMMUNICATION IN 8051 MICROCONTROLLER

• The fastest way of transmitting data, within a microcomputer is parallel data transfer.

• For transferring data over long distances, however, parallel data transmission requires too many

wires.

• For long distance transmission, data is usually converted from parallel form to serial form so that

it can be sent on a single wire or pair of wires.

• Serial data received from a distant source is converted to parallel form and it can be easily

transferred on the microcomputer buses.

Serial data can be sent by two ways. They are,

1. Synchronous communication . 2. Asynchronous communication




In synchronous transmission, data are transmitted in block at a constant rate. The start and end of a

block are identified with specific bytes or bit patterns. In asynchronous transmission, data is

transmitted one by one. The beginning of a data character is indicated by the line going low for 1 bit

time. This bit is called a start bit. The data bits are then sent out on the line one after the other. Note

that the least significant bit is sent out first. Depending on the system, the data word may consist of

5, 6, 7 or 8 bits. Following the data bits is a parity bit, which is used to check for errors in received

data. The line is returned high for at least 1-bit time to identify the end of the character. This

always-high bit is referred to as a stop bit. Some systems may use 2 stop bits. The bit format for

asynchronous data transmission is,

• The term baud rate is used to indicate the rate at which serial data is being transferred. Baud rate =

1/ time for a bit cell

• A device such as INTEL 8251A, which can be programmed to do either asynchronous or

synchronous communication, is often called USART (Universal Synchronous Asynchronous

Receiver Transmitter).

• A device such as the National 1NS8250, which can only do asynchronous communication, is often

referred to as a Universal Asynchronous Receiver Transmitter (UART).

• For sending serial data over long distances the standard telephone system is a convenient path,

because the wiring and connections are already in place.

• Standard phone lines often referred to as switched lines because any two points can be connected

together through a series of switches and have a bandwidth of about 300 to 3000 Hz.

• But digital signals require very large bandwidth (typically 5 MHz). Therefore, digital signals

cannot be sent directly over standard phone lines. So, the digital signals are converted to audio-

frequency tones, which are in the frequency range.

• The device used to do this conversion and to convert transmitted tones back to digital information

is called a MODEM.

• Modems and other equipment used to send serial data over long distances are known as data

communication equipment or DCE. The terminals and computers that are sending or receiving the

serial data are referred to as data terminal equipment or DTE. RS-232C serial data standard.




Mode-1 (standard UART mode) :

In mode-1, the serial port functions as a standard Universal Asynchronous Receiver Transmitter (UART)

mode. 10 bits are transmitted through TXD or received through RXD. The 10 bits consist of one start bit

(which is usually '0'), 8 data bits (LSB is sent first/received first), and a stop bit (which is usually '1'). Once

received, the stop bit goes into RB8 in the special function register SCON. The baud rate is variable.

The following figure shows the way the bits are transmitted/ received.

Fig 11.2 Data transmission format in UART mode

Bit time= 1/fbaud

In receiving mode, data bits are shifted into the receiver at the programmed baud rate. The data word (8-bits)

will be loaded to SBUF if the following conditions are true.

1. RI must be zero. (i.e., the previously received byte has been cleared from SBUF)

2. Mode bit SM2 = 0 or stop bit = 1.

After the data is received and the data byte has been loaded into SBUF, RI becomes one.

Mode-1 baud rate generation:

Timer-1 is used to generate baud rate for mode-1 serial communication by using overflow flag of the timer to

determine the baud frequency. Timer-1 is used in timer mode-2 as an auto-reload 8-bit timer. The data rate is

generated by timer-1 using the following formula.

Where,




SMODis the 7th bit of PCON register

fosc is the crystal oscillator frequency of the microcontroller

It can be noted that fosc/ (12 X [256- (TH1)]) is the timer overflow frequency in timer mode-2, which is the

auto-reload mode.

If timer-1 is not run in mode-2, then the baud rate is,

Timer-1 can be run using the internal clock, fosc/12 (timer mode) or from any external source via pin T1

(P3.5) (Counter mode).

OR

Ans 4

RAM, or random access memory, is a kind of computer memory in which any byte of memory can be

accessed without needing to access the previous bytes as well. RAM is a volatile medium for storing

digital data, meaning the device needs to be powered on for the RAM to work. DRAM, or Dynamic

RAM, is the most widely used RAM that consumers deal with. DDR3 is an example of DRAM.

SRAM, or static RAM, offers better performance than DRAM because DRAM needs to be refreshed

periodically when in use, while SRAM does not. However, SRAM is more expensive and less dense

than DRAM, so SRAM sizes are orders of magnitude lower than DRAM.

Comparison Chart

BASIS FOR

COMPARISON SRAM DRAM

Speed Faster Slower

Size Small Large




BASIS FOR

COMPARISON SRAM DRAM

Cost Expensive Cheap

Used in Cache memory Main memory

Density Less dense Highly dense

Construction Complex and uses

transistors and latches.

Simple and uses capacitors and

very few transistors.

Single block of memory

requires

6 transistors Only one transistor.

Charge leakage property Not present Present hence require power

refresh circuitry

Power consumption Low High

UNIT 5



















OR

Ans 5(a)

Real Time System : There is also a Operating System which is known as Real Time Processing

System. In this Response Time is already fixed. Means time to Display the Results after Possessing

has fixed by the Processor or CPU.

Real Time System is used at those Places in which we Requires higher and Timely Response. These

Types of Systems are used in Bomb and Reservation. So When we Specify the Request , the CPU

will Perform at that Time. There are two Types of Real Time System

A Hard Real-Time System guarantees that critical tasks complete on time. This goal requires that

all delays in the system be bounded from the retrieval of the stored data to the time that it takes

the operating system to finish any request made of it.

http://ecomputernotes.com/fundamental/disk-operating-system/what-is-operating-system




A Soft Real Time System where a critical real-time task gets priority over other tasks and retains

that priority until it completes. As in hard real time systems kernel delays need to be bounded.







Ans 5 (b) Architecture of an Embedded System

Figure shows a configuration diagram of a typical embedded system consisting of two main parts:

embedded hardware and embedded software. The embedded hardware

primarily includes the processor, memory, bus, peripheral devices, I/O ports, and various

controllers. The embedded software usually contains the embedded operating system and various

applications.

Basic architecture of an embedded system

Input and output are characteristics of any open system, and the embedded system is no exception.

In the embedded system, the hardware and software often collaborate to deal with various input

signals from the outside and output the processing results through some form. The input signal may

be an ergonomic device (such as a keyboard, mouse, or touch screen) or the output of a sensor circuit

in another embedded system. The output may be in the form of sound, light, electricity, or another

analog signal, or a record or file for a database.




Typical Hardware Architecture

The basic computer system components—microprocessor, memory, and input and output

modules—are interconnected by a system bus in order for all the parts to communicate and execute a

program .

Computer architecture

In embedded systems, the microprocessor's role and function are usually the same as those of the

CPU in a general-purpose computer: control computer operation, execute instructions, and process

data. In many cases, the microprocessor in an embedded system is also called the CPU. Memory is

used to store instructions and data. I/O modules are responsible for the data exchange between the

processor, memory, and external devices. External devices include secondary storage devices (such

as flash and hard disk), communications equipment, and terminal equipment. The system bus

provides data and controls signal communication and transmission for the processor, memory, and

I/O modules.




There are basically two types of architecture that apply to embedded systems: Von Neumann

architecture and Harvard architecture.

Documents

RTU Paper Solution - Global Institute of Technology, Jaipur · Solution VI and VIII sem University Examination 2019 Subject: Microcontroller &Embedded System Code: 8EC4.3A Semester: