€¦ · RTF file · 2017-10-09LATHA MATHAVAN ENGINEERING COLLEGE S.JANARTHANAN, AP/ECE Department: ECE SUBJECT: DIGITAL ELECTRONICS QUESTION BANK UNIT – I PART -A (2 Marks) 1

LATHA MATHAVAN ENGINEERING COLLEGE

S.JANARTHANAN, AP/ECE

Department: ECE

SUBJECT: DIGITAL ELECTRONICS

QUESTION BANK

UNIT I

PART -A (2 Marks)

1. Convert binary number 11011110 into its decimal equivalent.(AUC MAY 2012)

State Demorgans theorem. (AUC MAY 2012)

Write the application of gray code. (AUC MAY 2012)

The solution of the quadratic equation X^2-11x +22=0 is x=3 and x=6. What is the base of the numbers? (AUC MAY 2012)

Map the standard SOP expression on a karnaugh map. (AUC NOV

2011) ABC + A B C +ABC +ABC

6.

Draw the logic diagram of OR gate using universal gates. (AUC NOV 2011)

7.

State De-Morgans theorem. (AUC APR 2010)

8.

Draw an active-high

tri-state buffer and write its truth table. (AUC APR 2010)

9.

Prove that the logical

sum of all minterms of a Boolean function of 2 variables is 1.(AUC NOV 2009)

10. Show that a positive

logic NAND gate is a negative logic NOR gate. (AUC NOV2009)

Convert 10002 into gray code and Excess 3 code.(AUC NOV 2008)

Simplify the given function : F=ABC +ABC+ABC+ABC+ABC. (AUC NOV 2008)

Using 2s compliment perform the given subtraction 1011012 1101002(AUC NOV 2007)

Using Boolean algebra prove xy + xy =x + y (AUC NOV 2007)

Convert the binary number 10112 to gray code.(AUC JUNE 2007)

Minimize the function using Boolean algebra f=x(y+wz)+wxz (AUC JUNE 2007)

PART B (16 Marks)

1. Convert the following decimal numbers to their hexadecimal equivalent. i)1410 ii) 8010 iii) 300010 iv) 250010 (AUC MAY 2012)

Explain the canonical and standard forms of Boolean expression with examples.

2. Elaborate the basic laws of Boolean alzebra with sample. (AUC MAY2012) Write the steps for multiplying a logic expression using a karnaugh map.3. Implement the switching function F(x,y,z) =

m(1,2,3,4,5,7) (AUC MAY 2012)

4. Minimize the expression using Quine Mccluskey(Tabulation) method (AUC MAY



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2012) Y=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD

5. Simplify the logic function using Quine McCluskey method and realize using NAND gates. (AUC NOV 2011)

f(A,B,C,D)=m(1,3,5,9,10,11)+d(6,8)

6. a) Draw a TTL circuit with totem pole output and explain its working. (AUCNOV 2011) b)With a neat diagram ,explain the operation of CMOS NAND and NOR gates.

i) Express the Boolean function as POS form (1)SOP form D = (A + B) (B + C) (4) (ii)Minimize the given terms

M (0, 1, 4, 11, 13, 15) + d (5, 7, 8) using Quine-McClusky methods and verify the results using K-map methods. (12) (AUC APR 2010)

7. i)Implement the following function using NOR gates. (8) (AUC APR 2010)

Output = 1 when the inputs are m(0,1,2,3,4) = 0 when the inputs are m(5,6,7) .

(ii) Discuss the general characteristic of TTL and CMOS logic families.(8) (AUC APR 2010) 8. (a) (i) Express the Boolean function F = XY + XZ in product of Maxterm.(6)

Reduce the following function using K-map technique ) (AUC NOV 2009)

f (A, B, C, D) = (0, 3, 4, 7, 8, 10, 12, 14) + d (2, 6) . (10) ) (AUC NOV 2009)

Simplify the following Boolean function by using Quine Mcclusky method

F(A,B,C,D)= (0, 2, 3, 6, 7, 8, 10, 12, 13)(16) (AUC NOV 2009)

12. Simplify the given function using K map F=m(1,3,4,5,9,11,12,13,14,15) (AUC NOV

2008)

List all the prime implicants and draw the logic diagram for the minimized expression using gates (4) (AUC NOV 2008)

Solve the given expression using tabular method

F=m(0,2,3,6,7,10,12,14,15) (16) (AUC NOV 2008)

For the given functions :g(w,x,y,z)=m(0,3,4,5,8,11,12,13,14,15). List all

prime implicants and find the minimum product of sum expression. (AUC NOV 2007)

16. For the given function f(a,b,c,d)=m(0,2,3,6,8,12,15)+d(1,5) (AUC NOV 2007)

Find the minimum sum of products expression using Quine McCluskey method.(AUC NOV 2007)17.

Find the minimum sum of product expression using K map for the function ,F=m(7,9,10,11,12,13,14,15) and realize the minimized function using onlyNAND gates (AUC JUNE 2007)



Department: ECE

18. Simplify using Quine Mc Clusky method F=m(0,1,2,3,10,11,12,13,14,15) (AUC JUNE 2007)

UNIT 2

PART -A (2 Marks)

1.

What is tristate logic? What are its demerits? (AUC MAY 2012)

2.

State the features

of bipolar logic families. (AUC MAY 2012)

3.

Draw the logic diagram and give the truthtable of Half subtractor. (AUC MAY 2012)

4.

What is meant by look ahead carry ? (AUC NOV 2011)

5.

Give the logical expression for sum output and carry output of a full adder.(AUC NOV 2011)

6.

Write an expression for borrow and difference in a full subtractor circuit.(AUC APR 2010)

7.

Draw the circuits

diagram for 4 bit Odd parity generator. (AUC APR 2010)

8.

Suggest a solution

to overcome the limitation on the speed of an adder.(AUC NOV 2009)

Differentiate a decoder from a demultiplexer. (AUC NOV 2009)

Design a half adder using verilog. (AUC NOV 2008)

Draw the logic diagram of a master /slave JK flip flop. (AUC NOV 2008)

Draw a 2 input CMOS NOR gate. (AUC NOV 2007)

Define fanout of a digital IC. (AUC NOV 2007)

14.What is the advantage of using schottky TTL gate. (AUC JUNE 2007)

15. Define propagation delay. (AUC JUNE 2007)

PART -B (16 Marks)

1.

Design Half and Full subtractor circuits (AUC MAY 2012)

2.

Design a circuit that converts 8421 BCD code to Excess -3 code. (AUC MAY 2012)

3.

Design a 2 bit comparator and explain its operation in detail. (AUC NOV 2011)

4. a)Draw the circuit of BCD adder and explain. (AUC NOV 2011)

b)What is priority encoder? How is it different from encoder? Draw the circuit of 4 bit priority encoder and explain. (AUC NOV 2011)

5. i)Derive the equation for a 4-bit look ahead carry adder circuit. (6)

(ii)Draw and explain the block diagram of a 4-bit serial adder to add the contents of two registers. (10)

(AUC APR 2010)

6. Multiply (1011)2 by (1101)2 using addition and shifting operation so draw block diagram of the 4-bit by 4 bit parallel multiplier. (8)

Design and implement the conversion circuits for Binary code to gray code. (8)



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Design a carry look ahead adder with necessary diagrams. (16) (AUC NOV 2009)

7.

(i) Implement full subtractor using demultiplexer. (10) (AUC NOV 2009)

(ii) Implement the given Boolean function using 8 : 1 multiplexer

F(A, B, C) = (1, 3, 5, 6) . (6) (AUC NOV 2009)

8.

Design a mod 10 synchronous counter and draw the timing diagram of it.(AUC NOV 2008)

9.

Design a 4 bit universal shift register and explain its function. (AUC NOV 2008)

10.

Design a 4:1 multiplexer using transmission

gates and explain its operation.(AUC NOV 2007)

11.

Draw a 2 input NAND gate using schotky TTL logic and explain its operation.(AUC NOV 2007)

12.

Draw the circuit diagrams of 2 input CMOS NOR gate and CMOS NAND gate using CMOS logic and

explain their

operation. (AUC JUNE 2007)

13.What are

the different types of TTL gates

available? Explain their operations taking suitable example.

(AUC JUNE 2007)

UNIT 3 : Design of Sequential Circuits

PART A (2 Marks)

1.

Draw the logic

diagram

and give the truth table of Half Subtractor.(AUC MAY 2012)

2.

State the principle of parity checker. (AUC MAY 2012)

3.

Draw the logic

diagram

of T flip flop using JK flip flop. (AUC NOV 2011)

How can a SIPO register used as a SISO register? (AUC NOV 2011)

Mention any two differences between the edge triggering and level triggering. (AUC APR 2010)

What is meant by programmable counter? Mention its application. (AUC APR 2010)

7.

Write down the characteristic equation for JK flipflop. (AUC NOV 2009)

8.

Distinguish

between synchronous and asynchronous

sequential circuits. (AUC NOV 2009)

9.

Differentiate

combinational and sequential circuits.

(AUC NOV 2008)

10.What is an essential hazard? (AUC NOV 2008)

Implement the function f=m(0,1,4,5,7) using 8:1 multiplexer. (AUC NOV 2007)

Design a half subtractor using 2 to 4 decoder. (AUC NOV 2007)

Design a 2 input NAND gate using 2:1 multiplexer. (AUC JUNE 2007)

Design a half adder. (AUC JUNE 2007)

PART B (16 Marks)



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1.

Implement

a fulladder with two 4x1 multiplexers. (AUC MAY 2012)

2.

Implement

the following function using PLA. (AUC MAY 2012)

A(x,y,z)=m(1,2,4,6) B(x,y,z)=m(0,1,6,7) C(x,y,z)=m(2,6)

3.

a i) Draw the logic diagram of master slave SR flip flop and explain its working with truth table.(10)

(AUC NOV 2011)

ii)

Design a D flip flop using JK flip flop and explain with its truth table.(6) (AUC NOV 2011)

Draw the logic diagram of 4 bit binary up /down synchronous counter and explain with truth table .Also draw the timing diagram. (AUC NOV 2011)

(a) (i) Construct a clocked JK flip flop which is triggered at the positive edge of the clock pulse from a clocked SR flip flop consisting of NOR gates. (4)

(ii) Design a synchronous up/down counter that will count up from zero to one to two to three, and will

repeat whenever an external input x is logic 0, and will count down from three to two to one to zero, and

will repeat whenever the external input x is logic 1.

Implement your circuit with one TTL SN74LS76 device and one TTLSN74LS00 device. (12) (AUC APR

2010)

(b) (i)Write down the Characteristic

table for the JK flip

flop with NOR gates. (4)

(ii)What is meant by Universal

Shift

Register? Explain the principle of Operation of

4-bit Universal

Shift Register.

(12) (AUC APR 2010)

6. i) How will

you convert a D flipflop into JK flipflop?

(8)(AUC NOV 2009)

ii)Explain

the operation of a JK master slave flipflop. (8)(AUC NOV 2009)

7. Explain

in detail the operation of a 4 bit binary ripple

counter. (16)(AUC NOV 2009)

8. An asynchronous circuit is described by the following

excitation and output

functions:

Y=x1 x2 +(x1+x2)y , z=y a) Draw the logic diagram

b) Derive

the transistion table and output map. (AUC NOV 2008)

Differentiate synchronous and asynchronous sequential circuits with examples.(6) (AUC NOV 2008) Write short notes on race conditions in asynchronous sequential circuits and explain how they can be avoided.(10) (AUC NOV 2008)

a)Design a BCD Excess 3 code converter and implement it using logic gates.(AUC NOV 2007)(8) b)Design a 4 bit ripple carry adder. (AUC NOV 2007)(12)

Design the given functions using PAL and PROM (AUC NOV 2007)



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F1=m(0,1,4,5,7,9,11,13) F2=m(1,3,5,6,9,11,14,15)

Design 4 bit comparator using logic gates. (AUC JUNE 2007)

Implement the given function using PROM and PAL (AUC JUNE 2007)

F1=m(0,1,3,5,7,9) F2=m(1,2,4,7,8,10,11)

UNIT 4 : Memory Devices

PART A (2 Marks)

1.

Mention any four applications of shift registers. (AUC MAY 2012)

2.

How does JK flip flop differ from an SR flip flop in its basic operation. (AUC MAY 2012)

What is the need for output buffer in a PLA system? (AUC NOV 2011)

Bring out the difference between fundamental mode and pulse mode sequential circuits.(AUC NOV

2011)

What is meant by memory expansion? Mention its limit. (AUC APR 2010)

6. What are the advantages of static RAM compared to Dynamic RAM? (AUC APR 2010)

Compare and contrast static RAM and dynamic RAM. (AUC NOV 2009)

What is PAL? How does it differ from PLA? (AUC NOV 2009)

How the semiconductor memories are classified? (AUC NOV 2008)

Design a D flip flop using verilog. (AUC NOV 2008)

Draw the logic diagram of 3 bit ring counter. (AUC NOV 2007)

12.Write the excitation tables of JK and D flip flops. (AUC NOV 2007)

13.Write the characteristic equation of JK FF and show how JKFF can be converted to TFF. (AUC JUNE

2007)

14. Draw the logic diagram of 4 bit universal shift register. (AUC JUNE 2007)

PART B(16 Marks)

1.

Design the sequential circuit specified

by the state diagram using JK flip flop (AUC MAY 2012)

2.

Draw a 4 bit ripple counter with D flip

flop. (AUC MAY 2012)

3.

Draw the basic block diagram of PLA device and explain each block. List out its applications. Implement

a combinational circuit using PLA by taking a suitable Boolean function. (AUC NOV 2011)

4.

a)Explain the operation of static and dynamic MOS RAM cell with necessary diagrams.(12) (AUC NOV

2011)

b)What are the advantages of FPGA. (AUC NOV 2011)



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5. (a) (i) We can expand the word size of a RAM by combining two or more RAM chips. For instance, we can use two 32 8 memory chips where the number 32 represents the number of words and 8 represents the number of bits per word, to obtain a 32 16 RAM. In this case the number of words remains the same but the length of each word will two bytes long. Draw a block diagram to show how we can use two 16 4 memory chips to

obtain a 16 8 RAM. (8) (AUC APR 2010)

(ii)

Explain the principle

of operation of Bipolar SRAM cell.

(8) (AUC APR 2010)

6. (b) (i) A combinational

circuit

is defined as the functions(AUC APR 2010)

F1

= ABC+ABC+ABC

F2

= ABC+ABC+ABC

7. i)Implement the digital

circuit

with a PLA having 3 inputs,

3 product terms, and 2

outputs. (8) (AUC APR 2010)

(ii) Write a note on SRAM based FPGA. (8) (AUC APR 2010)

8. (a) Implement the following Boolean functions with a PLA

F1(A ,B ,C ) = (0, 1, 2, 4)

F2( A,B ,C ) = (0, 5, 6, 7)

F3(A ,B , C) = (0, 3, 5, 7) . (16) (AUC NOV 2009)

Design a combinational circuit using a ROM. The circuit accepts a three bit number and outputs a binary number equal to the square of the input number. (16)(AUC NOV 2009)

Draw the logic diagram of Xilinx 4000 CLB and I/O blocks and explain their function. (AUC NOV

2008)

Implement the given functions using PROM (AUC NOV 2008)

F1=m(0,1,3,4,6,7) F2=m(1,2,3,5)

12. Design a binary to gray code converter using verilog. (AUC NOV 2008)

13. For the state diagram shown ,design a sequential circuit using JK flip flops(AUC NOV 2008)

14. Design a synchronous counter which counts in the sequence 0,2,6,1,7,5,0 using D flip flop. Draw the logic and state diagram. (AUC JUNE 2007)

15.Write short notes on semiconductor memories.(6) (AUC JUNE 2007) Reduce the given state table using implication chart.(10) (AUC JUNE 2007)



Department: ECE

UNIT 5 : Synchronous and Asynchronous Sequential Circuits

PART A (2 Marks)

Define Race condition. (AUC MAY 2012)

What is meant by essential hazards? (AUC MAY 2012)

Give the difference between RAM and ROM. (AUC NOV 2011)

What is meant by hazard and how it could be avoided? (AUC NOV 2011)

Draw the block diagram for Moore model. (AUC APR 2010)

What are hazard free digital circuits? (AUC APR 2010)

What are Hazards? (AUC NOV 2009)

8. Compare the ASM chart with a conventional flow chart. (AUC NOV 2009)

Implement 2 input XOR gate using NAND-NAND logic. (AUC NOV 2008)

List any two advantages of using CMOS logic. (AUC NOV 2008)

11.What are the different

types of races that

occur in fundamental mode circuits.(AUC NOV 2007)

12. Define cycle in asynchronous sequential

circuits. (AUC NOV 2007)

13.What is a hazard in asynchronous sequential circuit. (AUC JUNE 2007)

14.What are the different

methods of operation in asynchronous sequential circuits. (AUC JUNE 2007)

PART B (16 Marks)

1. Design an asynchronous sequential circuit that has 2 inputs X2 and X1 and one output z. When X1=0 ,the output z is O. The first change X2 that occurs while X1 is 1will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0. (AUC MAY 2012)

Find the circuit that has no static hazards and implement the Boolean function F(A,B,C,D)=m(1,3,5,7,8,9,14,15) (AUC MAY 2012)

i)Write short notes on shared row state assignment with an example.(8) (AUC NOV 2011)(8) (AUC

NOV 2011)

ii)A sequential circuit has 3 D flip flop. A,B and C and one input X. It is desired by the following flip flop functions(8) (AUC NOV 2011)

DA =(BC+BC)X +(BC+BC)X ; DB=A , DC=B

Derive the state table for the circuit and draw two state diagrams for X=0 and other for X=1

4. i)Explain the method to eliminate static hazard in an asynchronous circuit with an



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example.(10) (AUC NOV 2011)

ii)Write short notes on verilog.(6) (AUC NOV 2011)

5. (a) For the circuit shown in figure, write down the state table and draw the state diagram

and analyze the operation. (16) (AUC APR 2010)

(b) What are called as essential hazards? How does the hazard occur in sequential circuits? How can the same be eliminated using SR latches?Give an example.(16)(AUC APR 2010)

6.

(a) Design a three bit binary counter using T flipflops. (16) (AUC NOV 2009)

7.

(b) Design a negative-edge triggered T flipflop. (16)(AUC NOV 2009)

8. a) Draw a 2 input NAND gate in TTL logic and explain its operation.(12)(AUC NOV 2008) b) Write short notes on BICMOS logic. (AUC NOV 2008)

a) Design a 2 input NOR gate using CMOS logic. (AUC NOV 2008) b)Write short notes on CMOS logic and interfacing. (AUC NOV 2008)

Discuss on the different types of hazards that occur in asynchronous sequential circuits.(AUC NOV

2007)

11.Write short notes on i) race free assignments ii) pulse mode circuits. (AUC NOV 2007)

12.Write short notes on races and cycles that occur in fundamental mode circuits(10) (AUC JUNE 2007)

What is an essential hazard? Explain with example.(6) (AUC JUNE 2007)

13. Explain how hazard free realization can be obtained for a boolean function.(8) (AUC JUNE 2007)

Discuss a method used for race free assignments with example.(8) (AUC JUNE 2007)

QUESTION BANK

SUBJECT NAME: DIGITAL ELECTRONICS



Department: ECE

YEAR: II SEM: III

UNIT I

MINIMIZATION TECHNIQUES AND LOGIC GATES

PART A (2 MARKS)

1) Define binary logic?

Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT.

2) Convert (634) 8 to binary

6 3 4

110 011 100

Ans = 110011100

3) Convert (9B2 - 1A) H to its decimal equivalent.

N = 9 x 162 + B x 161 + 2 x 160 + 1 x 16-1 + A (10) x 16-2

2304 + 176 + 2 + 0.0625 + 0.039

2482.110

4) State the different classification of binary codes?

Weighted codes

Non - weighted codes



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Reflective codes

Sequential codes

Alphanumeric codes

Error Detecting and correcting codes.

Convert 0.640625 decimal numbers to its octal equivalent. 0.640625 x 8 = 5.125

0.125 x 8 = 1.0

= 0.640 625 10 = (0.51) 8

Convert 0.1289062 decimal numbers to its hex equivalent 0.1289062 x 16 = 2.0625

0.0625 x 16 = 1.0 = 0.2116

Convert 22.64 to hexadecimal number.

16 22 -6

16 1 -1

0

0.64 x 16 = 10.24

0.24 x 16 = 3.84

0.84 x 16 = 13.44



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.44 x 16 = 7.04

Ans = (16. A 3 D 7) 16

8) State the steps involved in Gray to binary conversion?

The MSB of the binary number is the same as the MSB of the gray code number. So write it down. To obtain the next binary digit, perform an exclusive OR operation between the bit just written down and the next gray code bit. Write down the result.

Convert gray code 101011 into its binary equivalent. Gray Code: 1 0 1 0 1 1

Binary Code: 1 1 0 0 1 0

Substract (0 1 0 1) 2 from (1 0 1 1) 2

1 0 1 0

0 1 0 1

Answer = 0 1 1 0

11) Add (1 0 1 0) 2 and (0 0 1 1) 2 1 0 1 0 0 0 1 1

Answer = (1 1 0 1) 2

12) Using 10s complement subtract 72532 - 3250 M = 72532



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10s complement of N = + 96750

-----------

Sum = 169282

Discard end carry

Answer = 69282

13) Find 2S complement of (1 0 1 0 0 0 1 1) 2

0 1 0 1 1 1 0 0 1

- 1s Complement

+

1

0 1 0 1 1 1 0 1 0

- 2s complement.

14) Substract 1 1 1 0 0 1 2 from 1 0 1 0 1 1 2 using 2s complement method

1 0 1 0 1 1

+ 0 0 0 1 1 1 - 2s comp. of 1 1 1 0 0 1 1 1 0 0 1 0 in 2s complement form

Answer (0 0 1 1 1 0 )2

15) Find the excess -3 code and 9s complement of the number 40310

4 0 3

0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 +

0 1 1 1 0 0 1 1 0 1 1 0 ----- excess 3 code



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9s complement 1 0 0 0 1 1 0 0 1 0 0 1

What is meant by bit? A binary digit is called bit

Define byte?

Group of 8 bits.

List the different number systems? i) Decimal Number system

ii) Binary Number system iii) Octal Number system

iv) Hexadecimal Number system

State the abbreviations of ASCII and EBCDIC code? ASCII-American Standard Code for Information Interchange. EBCDIC-Extended Binary Coded Decimal Information Code.

What are the different types of number complements?

rs Complement

(r-1)s Complement.

21) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction

(a) X -Y and (b) Y - X using 2's complements.



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a) X = 1010100

2's complement of Y = 0111101

--------------

Sum = 10010001

Discard end carry

Answer: X - Y = 0010001

b) Y = 1000011

2's complement of X = + 0101100

---------------

Sum = 1101111

There is no end carry, The MSB BIT IS 1.

Answer is Y-X = -(2's complement of 1101111) = - 0010001

22) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction

(a) X -Y and (b) Y - X using 1's complements. a) X - Y = 1010100 - 1000011

X = 1010100

1's complement of Y = + 0111100

--------------

Sum = 10010000



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End -around carry = + 1

--------------

Answer: X - Y = 0010001

b) Y - X = 1000011 - 1010100

Y = 1000011

1's complement of X = + 0101011

------------

Sum = + 1101110

There is no end carry.

Therefore the answer is Y - X = -(1's complement of 1101110) = -0010001

Write the names of basic logical operators. 1. NOT / INVERT

2. AND

3. OR

What are basic properties of Boolean algebra?

The basic properties of Boolean algebra are commutative property, associative property and distributive property.

25) State the associative property of boolean algebra.



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The associative property of Boolean algebra states that the OR ing of several variables results in the same regardless of the grouping of the variables. The associative property is stated

as follows:

A+ (B+C) = (A+B) +C

26) State the commutative property of Boolean algebra.

The commutative property states that the order in which the variables are OR ed makes no difference. The commutative property is:

A+B=B+A

27) State the distributive property of Boolean algebra.

The distributive property states that AND ing several variables and OR ing the result with a single variable is equivalent to OR ing the single variable with each of the the several variables and then AND ing the sums. The distributive property is:

A+BC= (A+B) (A+C)

28) State the absorption law of Boolean algebra.

The absorption law of Boolean algebra is given by X+XY=X, X(X+Y) =X. 29) Simplify the following using De Morgan's theorem [((AB)'C)'' D]' [((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B']

(AB)' C + D'

(A' + B' )C + D'



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30) State De Morgan's theorem.

De Morgan suggested two theorems that form important part of Boolean algebra.

They are,

The complement of a product is equal to the sum of the complements. (AB)' = A' + B'

The complement of a sum term is equal to the product of the complements. (A + B)' = A'B'

Reduce A.A'C A.A'C = 0.C [A.A' = 1] = 0

Reduce A(A + B) A(A + B) = AA + AB = A(1 + B) [1 + B = 1] = A.

Reduce A'B'C' + A'BC' + A'BC

A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C = A'C' + A'BC [A + A' = 1]

= A'(C' + BC)

= A'(C' + B) [A + A'B = A + B]



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33) Reduce AB + (AC)' + AB'C(AB + C)

AB + (AC)' + AB'C(AB + C) = AB + (AC)' + AAB'BC + AB'CC

AB + (AC)' + AB'CC [A.A' = 0]

AB + (AC)' + AB'C [A.A = 1]

AB + A' + C' =AB'C [(AB)' = A' + B']

A' + B + C' + AB'C [A + AB' = A + B]

A' + B'C + B + C' [A + A'B = A + B]

A' + B + C' + B'C

=A' + B + C' + B' =A' + C' + 1

= 1 [A + 1 =1]

Simplify the following expression Y = (A + B)(A + C' )(B' + C' ) Y = (A + B)(A + C' )(B' + C' )

= (AA' + AC +A'B +BC )(B' + C') [A.A' = 0] = (AC + A'B + BC)(B' + C' )

= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC' = AB'C + A'BC'

Show that (X + Y' + XY)( X + Y')(X'Y) = 0

(X + Y' + XY)( X + Y')(X'Y) = (X + Y' + X)(X + Y' )(X' + Y) [A + A'B = A + B]



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(X + Y' )(X + Y' )(X'Y) [A + A = 1]

(X + Y' )(X'Y) [A.A = 1]

X.X' + Y'.X'.Y

0 [A.A' = 0]

Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC ABC + ABC' + AB'C + A'BC=AB(C + C') + AB'C + A'BC =AB + AB'C + A'BC

=A(B + B'C) + A'BC =A(B + C) + A'BC =AB + AC + A'BC =B(A + C) + AC =AB + BC + AC

=AB + AC +BC ...Proved

Convert the given expression in canonical SOP form Y = AC + AB + BC Y = AC + AB + BC

=AC(B + B' ) + AB(C + C' ) + (A + A')BC

=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC =ABC + ABC' +AB'C + AB'C' [A + A =1]

Define duality property.



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Duality property states that every algebraic expression deducible from the postulates of

Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's.

39) Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x(y'z' + yz). By applying De-Morgan's theorem.

F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z') F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)'

x' + (y'z')'(yz)'

x' + (y + z)(y' + z')

Simplify the following expression Y = (A + B) (A = C) (B + C)

= (A A + A C + A B + B C) (B + C) = (A C + A B + B C) (B + C)

= A B C + A C C + A B B + A B C + B B C + B C C = A B C

What are the methods adopted to reduce Boolean function? i) Karnaug map

ii) Tabular method or Quine Mc-Cluskey method



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iii) Variable entered map technique.

42) State the limitations of karnaugh map.

Generally it is limited to six variable map (i.e) more then six variable involving expression are not reduced.

The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form.

43) What is a karnaugh map?

A karnaugh map or k map is a pictorial form of truth table, in which the map diagram is made up of squares, with each squares representing one minterm of the function. 44) Find the minterms of the logical expression Y = A'B'C' + A'B'C + A'BC + ABC'

Y = A'B'C' + A'B'C + A'BC + ABC' =m0 + m1 +m3 +m6

=_m(0, 1, 3, 6)

45) Write the maxterms corresponding to the logical expression Y = (A + B + C' )(A + B' + C')(A' + B' + C)

= (A + B + C' )(A + B' + C')(A' + B' + C) =M1.M3.M6

=_ M(1,3,6)

46) What are called dont care conditions?



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In some logic circuits certain input conditions never occur, therefore the corresponding

output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by X ord in the truth tables and are called dont care conditions or incompletely specified functions.

47) What is a prime implicant?

A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map.

48) What is an essential implicant?

If a min term is covered by only one prime implicant, the prime implicant is said to be essential

Unit II

49. What is a Logic gate?

Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function.

50. Give the classification of logic families logic families

1. Bipolar 2.Unipolar

1. Saturated 2. Non Saturated 1. PMOS



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RTL 2.1.Schottky TTL 2. NMOS

ECL 2.2. DTL 3. CMOS

I I C

TTL

What are the basic digital logic gates? The three basic logic gates are

AND gate

OR gate

NOT gate

Which gates are called as the universal gates? What are its advantages?

The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application.

53. Classify the logic family by operation? The Bipolar logic family is classified into

Saturated logic

Unsaturated logic.

The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family. The Schottky TTL, and ECL logic comes under the unsaturated logic family. 54.State the classifications of FET devices.



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FET is classified as

Junction Field Effect Transistor (JFET)

Metal oxide semiconductor family (MOS).

55.Mention the classification of saturated bipolar logic families. The bipolar logic family is classified as follows:

RTL- Resistor Transistor Logic

DTL- Diode Transistor logic

I2L- Integrated Injection Logic

TTL- Transistor Transistor Logic

ECL- Emitter Coupled Logic 56.Mention the different IC packages?

DIP- Dual in line package

LCC- Leadless Chip Carrier

PLCC- Plastic Leaded Chip carrier

PQFP- Plastic Quad Flat Pack

PGA- Pin Grid Array

57. Mention the important characteristics of digital ICs?

Fan out

Power dissipation



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Propagation Delay

Noise Margin

Fan In

Operating temperature

Power supply requirements

Define Fan-out?

Fan out specifies the number of standard loads that the output of the gate can drive without impairment of its normal operation.

Define power dissipation?

Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.

What is propagation delay?

Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns.

Define noise margin?

It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts.

Define fan in?

Fan in is the number of inputs connected to the gate without any degradation in the voltage level.

What is Operating temperature?



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All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c.

64.What is High Threshold Logic?

Some digital circuits operate in environments, which produce very high noise signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic.

What are the types of TTL logic?

Open collector output

Totem-Pole Output

Tri-state output.

What is depletion mode operation MOS?

If the channel is initially doped lightly with p-type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode.

67. What is enhancement mode operation of MOS?

If the region beneath the gate is left initially uncharged the gate field must induce a channel before current can flow. Thus the gate voltage enhances the channel current and such a

device is said to operate in the enhancement mode. 68. Mention the characteristics of MOS transistor?



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The n- channel MOS conducts when its gate- to- source voltage is positive.

The p- channel MOS conducts when its gate- to- source voltage is negative

Either type of device is turned of if its gate- to- source voltage is zero.

69. How schottky transistors are formed and state its use?

A schottky diode is formed by the combination of metal and semiconductor. The

presence of schottky diode between the base and the collector prevents the transistor from going into saturation. The resulting transistor is called as schottky transistor. The use of schottky transistor in TTL decreases the propagation delay without a sacrifice of power dissipation.

List the different versions of TTL 1.TTL (Std.TTL) 2.LTTL (Low Power TTL)

3.HTTL (High Speed TTL) 4.STTL (Schottky TTL) 5.LSTTL (Low power Schottky TTL)

Why totem pole outputs cannot be connected together.

Totem pole outputs cannot be connected together because such a connection might produce excessive current and may result in damage to the devices.

72. State advantages and disadvantages of TTL Adv:

Easily compatible with other ICs Low output impedance



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Disadv:

Wired output capability is possible only with tristate and open collector types Special circuits in Circuit layout and system design are required.

73. When does the noise margin allow digital circuits to function properly.

When noise voltages are within the limits of VNA(High State Noise Margin) and VNK for a particular logic family.

What happens to output when a tristate circuit is selected for high impedance. Output is disconnected from rest of the circuits by internal circuitry.

What is 14000 series.

It is the oldest and standard CMOS family. The devices are not pin compatible or electrically compatible with any TTL Series.

Implement the Boolean Expression for EX OR gate using NAND Gates.

Define combinational logic

When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.

78. Explain the design procedure for combinational circuits

The problem definition

Determine the number of available input variables & required O/P variables.



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Assigning letter symbols to I/O variables

Obtain simplified Boolean expression for each O/P.

Obtain the logic diagram.

79. Define Half adder and full adder

The logic circuit that performs the addition of two bits is a half adder. The circuit that performs the addition of three bits is a full adder.

90. Draw the logic Symbol and construct the truth table for the two input EX OR gate. 81. Define Decoder?

A decoder is a multiple - input multiple output logic circuit that converts coded inputs into coded outputs where the input and output codes are different.

82. What is binary decoder?

A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n out puts lines.

83. Define Encoder?

An encoder has 2n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input value.

84. What is priority Encoder?



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A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority

will take precedence. 85. Define multiplexer?

Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line.

86. What do you mean by comparator?

A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers.

87. List basic types of programmable logic devices.

Read only memory

Programmable logic Array

Programmable Array Logic

Define ROM

Read only memory is a device that includes both the decoder and the OR gates within a single IC package.

Define address and word:

In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word.



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State the types of ROM

Masked ROM.

Programmable Read only Memory

Erasable Programmable Read only memory.

Electrically Erasable Programmable Read only Memory.

What is programmable logic array? How it differs from ROM?

In some cases the number of dont care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the

minterms as in the ROM.

Which gate is equal to AND-invert Gate? NAND gate.

Which gate is equal to OR-invert Gate? NOR gate.

Bubbled OR gate is equal to--------------

NAND gate

Bubbled AND gate is equal to--------------

NOR gate Unit -III



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96. What are the classification of sequential circuits?

The sequential circuits are classified on the basis of timing of their signals into two types. They are,

1)Synchronous sequential circuit. 2)Asynchronous sequential circuit. 97. Define Flip flop.

The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.

98.What are the different types of flip-flop?

There are various types of flip flops. Some of them are mentioned below they are, RS flip-flop

SR flip-flop D flip-flop JK flip-flop T flip-flop

99.What is the operation of RS flip-flop?

When R input is low and S input is high the Q output of flip-flop is set.

When R input is high and S input is low the Q output of flip-flop is



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reset.

When both the inputs R and S are low the output does not change

When both the inputs R and S are high the output is unpredictable.

100.What is the operation of SR flip-flop?

When R input is low and S input is high the Q output of flip-flop is set.

When R input is high and S input is low the Q output of flip-flop is reset.

When both the inputs R and S are low the output does not change.

When both the inputs R and S are high the output is unpredictable.

101.What is the operation of D flip-flop?

In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.

102. What is the operation of JK flip-flop?

When K input is low and J input is high the Q output of flip-flop is set.

When K input is high and J input is low the Q output of flip-flop is reset.

When both the inputs K and J are low the output does not change



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When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.

103. What is the operation of T flip-flop?

T flip-flop is also known as Toggle flip-flop.

When T=0 there is no change in the output.

When T=1 the output switch to the complement state (ie) the output toggles.

104. Define race around condition.

In JK flip-flop output is fed back to the input. Therefore change in the output results

change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called race around condition.

105. What is edge-triggered flip-flop?

The problem of race around condition can solved by edge triggering flip flop.

The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

106. What is a master-slave flip-flop?

A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.

107.Define rise time.



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The time required to change the voltage level from 10% to 90% is known as rise time(tr).

108.Define fall time.

The time required to change the voltage level from 90% to 10% is known as fall time(tf).

109.Define skew and clock skew.

The phase shift between the rectangular clock waveforms is referred to as skew and the time delay between the two clock pulses is called clock skew. 110.Define setup time.

The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as tsetup .

111. Define hold time.

The hold time is the minimum time for which the voltage levels at the excitation

inputs must remain constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as thold.

112. Define propagation delay.

A propagation delay is the time required to change the output after the application of the input.



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113.Define registers.

A register is a group of flip-flops flip-flop can store one bit information. So an n-bit register has a group of n flip-flops and is capable of storing any binary information/number containing n-bits.

114.Define shift registers.

The binary information in a register can be moved from stage to stage within the register or into or out of the register upon application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers. 115.What are the different types of shift type?

There are five types. They are,

_ Serial In Serial Out Shift Register

_ Serial In Parallel Out Shift Register

_ Parallel In Serial Out Shift Register

_ Parallel In Parallel Out Shift Register _ Bidirectional Shift Register

116.Explain the flip-flop excitation tables for RS FF. RS flip-flop

In RS flip-flop there are four possible transitions from the present state to the



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next state. They are,

0 0 transition: This can happen either when R=S=0 or when R=1 and S=0. 0 1 transition: This can happen only when S=1 and R=0.

1 0 transition: This can happen only when S=0 and R=1.

1 1 transition: This can happen either when S=1 and R=0 or S=0 and R=0. 117.Explain the flip-flop excitation tables for JK flip-flop

In JK flip-flop also there are four possible transitions from present state to next state. They are,

0 0 transition: This can happen when J=0 and K=1 or K=0.

0 1 transition: This can happen either when J=1 and K=0 or when J=K=1. 1 0 transition: This can happen either when J=0 and K=1 or when J=K=1. 1 1 transition: This can happen when K=0 and J=0 or J=1.

118.Explain the flip-flop excitation tables for D flip-flop

In D flip-flop the next state is always equal to the D input and it is independent of the present state. Therefore D must be 0 if Q n+1 has to 0,and if Qn+1 has to be 1 regardless the value of Qn.

119. Explain the flip-flop excitation tables for T flip-flop

When input T=1 the state of the flip-flop is complemented; when T=0,the state of the flip-flop remains unchanged. Therefore, for 0 0 and 1 1 transitions T must be 0 and



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or 0 1 and 1 0 transitions must be 1. 120. Define sequential circuit?

In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables.

121.Give the comparison between combinational circuits and sequential circuits. Combinational circuits Sequential circuits

Memory unit is not required 1. Memory unity is required

Parallel adder is a combinational circuit 2. Serial adder is a sequential circuit

What do you mean by present state?

The information stored in the memory elements at any given time define.s the present state of the sequential circuit.

What do you mean by next state?

The present state and the external inputs determine the outputs and the next state of the sequential circuit.

State the types of sequential circuits?

Synchronous sequential circuits

Asynchronous sequential circuits

Define synchronous sequential circuit

In synchronous sequential circuits, signals can affect the memory elements only at



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discrete instant of time.

126. Define Asynchronous sequential circuit?

In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.

127.Give the comparison between synchronous & Asynchronous sequential circuits? Synchronous sequential circuits Asynchronous sequential circuits.

1.Memory elements are clocked flip-flops 1.Memory elements are either unlocked flip - flops or time delay elements.

2. Easier to design 2. More difficult to design 128.Define flip-flop

Flip - flop is a sequential device that normally samples its inputs and changes its outputs only at times determined by clocking signal.

Draw the logic diagram for SR latch using two NOR gates.

The following wave forms are applied to the inputs of SR latch. Determine the Q waveform Assume initially Q = 1

Here the latch input has to be pulsed momentarily to cause a change in the latch output state, and the output will remain in that new state even after the input pulse is over. 131.What is race around condition?

In the JK latch, the output is feedback to the input, and therefore changes in the output



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results change in the input. Due to this in the positive half of the clock pulse if J and K are both high then output toggles continuously. This condition is known as race around condition.

132.What are the types of shift register?

Serial in serial out shift register?

Serial in parallel out shift register

Parallel in serial out shift register

Parallel in parallel out shift register

Bidirectional shift register shift register 133.State the types of counter?

Synchronous counter

Asynchronous Counter

134.Give the comparison between synchronous & Asynchronous counters. Asynchronous counters Synchronous counters

In this type of counter flip-flops are connected in such a way that output of 1st flip-flop drives the clock for the next flipflop. In this type there is no connection between output of first flip-flop and clock input of



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the next flip - flop

All the flip-flops are Not clocked simultaneously

All the flip-flops are clocked simultaneously

135.The t pd for each flip-flop is 50 ns. Determine the maximum operating frequency for MOD - 32 ripple counter.

f max (ripple) = 5 x 50 ns = 4 MHZ Unit-IV

136. What are secondary variables?

-present state variables in asynchronous sequential circuits 137.What are excitation variables?

-next state variables in asynchronous sequential circuits

What is fundamental mode sequential circuit? -input variables changes if the circuit is stable -inputs are levels, not pulses

-only one input can change at a given time

What are pulse mode circuit?

-inputs are pulses



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-width of pulses are long for circuit to respond to the input

-pulse width must not be so long that it is still present after the new state is reached 140. What are the significance of state assignment?

In synchronous circuits-state assignments are made with the objective of circuit reduction

Asynchronous circuits-its objective is to avoid critical races 141. When do race condition occur?

-two or more binary state variables change their value in response to the change in i/p variable

142.What is non critical race?

-final stable state does not depend on the order in which the state variable changes

-race condition is not harmful 143.What is critical race?

-final stable state depends on the order in which the state variable changes -race condition is harmful

144. When does a cycle occur?

-asynchronous circuit makes a transition through a series of unstable state 145.What are the different techniques used in state assignment?



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-shared row state assignment -one hot state assignment

146.What are the steps for the design of asynchronous sequential circuit? -construction of primitive flow table

-reduction of flow table -state assignment is made

-realization of primitive flow table 147.What is hazard?

-unwanted switching transients 148.What is static 1 hazard?

-output goes momentarily 0 when it should remain at 1 149.What is static 0 hazard?

-output goes momentarily 1 when it should remain at 0 150. What is dynamic hazard?

-output changes 3 or more times when it changes from 1 to 0 or 0 to 1 151.What is the cause for essential hazards?

-unequal delays along 2 or more path from same input 151.What is flow table?

-state table of an synchronous sequential network



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152.What is SM chart?

-describes the behavior of a state machine -used in hardware design of digital systems 152.What are the advantages of SM chart? -easy to understand the operation

-east to convert to several equivalent forms 153. What is primitive flow chart?

-one stable state per row 154.What is combinational circuit?

Output depends on the given input. It has no storage element. 155.What is state equivalence theorem ?

Two states SA and SB, are equivalent if and only if for every possible input X sequence, the outputs are the same and the next states are equivalent

i.e., if SA (t + 1) = SB (t + 1) and ZA = ZB then SA = SB. 156.What do you mean by distinguishing sequences?

Two states, SA and SB of sequential machine are distinguishable if and only if their exists at least one finite input sequence. Which, when applied to sequential machine causes different output sequences depending on whether SA or SB is the initial state. 157. Prove that the equivalence partition is unique



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Consider that there are two equivalence partitions exists : PA and PB, and PA ) PB.

This states that, there exist 2 states Si & Sj which are in the same block of one partition and not in the same block of the other. If Si & Sj are in different blocks of say PB, there exists at least on input sequence which distinguishes Si & Sj and therefore, they cannot be in the same block of PA.

158.Define compatibility

States Si and Sj said to be compatible states, if and only if for every input sequence

that affects the two states, the same output sequence, occurs whenever both outputs are specified and regardless of whether Si on Sj is the initial state.

159.Define merger graph.

The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn.

160.Define incompatibility

The states are said to be incompatible if no line is drawn in between them. If implied states are incompatible, they are crossed & the corresponding line is ignored. 161.Explain the procedure for state minimization.

1. Partition the states into subsets such that all states in the same subsets are 1 - equivalent.



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Partition the states into subsets such that all states in the same subsets are 2 - equivalent.

Partition the states into subsets such that all states in the same subsets are 3 - equivalent.

162.Define closed covering

A Set of compatibles is said to be closed if, for every compatible contained in the set,

all its implied compatibles are also contained in the set. A closed set of compatibles, which contains all the states of M, is called a closed covering.

163.Define machine equivalence

Two machines, M1 and M2 are said to be equivalent if and only if, for every state in M1, there is a corresponding equivalent state in M2 & vice versa.

164.Define state table.

For the design of sequential counters we have to relate present states and next states. The table, which represents the relationship between present states and next states, is called state table.

Define total state

The combination of level signals that appear at the inputs and the outputs of the delays define what is called the total state of the circuit.

166.What are the steps for the design of asynchronous sequential circuit?



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Construction of a primitive flow table from the problem statement.

Primitive flow table is reduced by eliminating redundant states using the state reduction

State assignment is made

The primitive flow table is realized using appropriate logic elements.

167. Define primitive flow table :

It is defined as a flow table which has exactly one stable state for each row in the table. The design process begins with the construction of primitive flow table. 168.What are the types of asynchronous circuits ?

Fundamental mode circuits

Pulse mode circuits

169.Give the comparison between state Assignment Synchronous circuit and state assignment asynchronous circuit.In synchronous circuit, the state assignments are made with the objective of circuit reduction. In asynchronous circuits, the objective of state assignment is to avoid critical races.

170.What are races?

When 2 or more binary state variables change their value in response to a change in an input variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable



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manner.

171.Define non critical race.

If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race. 172.Define critical race?

If the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race.

173What is a cycle?

A cycle occurs when an asynchronous circuit makes a transition through a series

of unstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable to another, until the inputs are changed.

174.List the different techniques used for state assignment.

Shared row state assignment

One hot state assignment.

175.Write a short note on fundamental mode asynchronous circuit. Fundamental mode circuit assumes that. The input variables change only when

the circuit is stable. Only one input variable can change at a given time and inputs are levels and not pulses.

176. Write a short note on pulse mode circuit.



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Pulse mode circuit assumes that the input variables are pulses instead of level. The width of the pulses is long enough for the circuit to respond to the input and the pulse width

must not be so long that it is still present after the new state is reached. 177.Define secondary variables

The delay elements provide a short term memory for the sequential circuit. The present state and next state variables in asynchronous sequential circuits are called secondary

variables.

178. Define flow table in asynchronous sequential circuit.

In asynchronous sequential circuit state table is known as flow table because of the behaviour of

the asynchronous sequential circuit. The stage changes occur in independent of

a clock, based on the logic propagation delay, and cause the states to .flow. from one to

another.

179. A pulse mode asynchronous machine has two inputs. If produces an output

whenever two consecutive pulses occur on one input line only. The output remains at 1 until a pulse has occurred on the other input line. Write down the state table for the machine. 180.What is fundamental mode.

A transition from one stable state to another occurs only in response to a change in the input state. After a change in one input has occurred, no other change in any input

occurs until the circuit enters a stable state. Such a mode of operation is referred to as a



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fundamental mode.

181. Write short note on shared row state assignment.

Races can be avoided by making a proper binary assignment to the state

variables. Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which

transitions occur be given adjacent assignments. Two binary are said to be adjacent if they differ in only one variable.

182. Write short note on one hot state assignment.

The one hot state assignment is another method for finding a race free state assignment. In this method, only one variable is active or hot for each row in the original flow table, ie, it requires one state variable for each row of the flow table. Additional row are introduced to provide single variable changes between internal state transitions.

Unit-V

183. Explain ROM

A read only memory(ROM) is a device that includes both the decoder and the

OR gates within a single IC package. It consists of n input lines and m output lines.

Each bit combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input



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variables is 2n

What are the types of ROM? 1.PROM

2.EPROM

3.EEPROM

Explain PROM.

_ PROM (Programmable Read Only Memory)

It allows user to store data or program. PROMs use the fuses with

material like nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50 mA of current for the period 5 to 20s.The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent.

186. Explain EPROM.

_ EPROM(Erasable Programmable Read Only Memory)

EPROM use MOS circuitry. They store 1s and 0s as a packet of charge in a

buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed.

187. Explain EEPROM.



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_ EEPROM(Electrically Erasable Programmable Read Only Memory) EEPROM also use MOS circuitry. Data is stored as charge or no charge on an

insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals.

189. What is RAM?

Random Access Memory. Read and write operations can be carried out. 190. Define ROM

A read only memory is a device that includes both the decoder and the OR gates within a single IC package.

191. Define address and word:


What are the types of ROM.

Masked ROM.




What is programmable logic array? How it differs from ROM?



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In some cases the number of dont care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.

194.What is mask - programmable?

With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.

195. What is field programmable logic array?

The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA.

List the major differences between PLA and PAL

PLA:

Both AND and OR arrays are programmable and Complex Costlier than PAL

PAL

AND arrays are programmable OR arrays are fixed Cheaper and Simpler

Define PLD.

Programmable Logic Devices consist of a large array of AND gates and OR gates that



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can be programmed to achieve specific logic functions. 198. Give the classification of PLDs.

PLDs are classified as PROM(Programmable Read Only Memory), Programmable Logic Array(PLA), Programmable Array Logic (PAL), and Generic Array Logic(GAL) 199. Define PROM.

PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a programmable OR array.

200. Define PLA

PLA is Programmable Logic Array(PLA). The PLA is a PLD that consists of a programmable AND array and a programmable OR array.

201. Define PAL

PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.

202. Why was PAL developed ?

It is a PLD that was developed to overcome certain disadvantages of PLA, such

as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.

203. Define GAL



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GAL is Generic Array Logic. GAL consists of a programmable AND array and a fixed OR array with output logic.

204. Why the input variables to a PAL are buffered

The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.

What does PAL 10L8 specify ? PAL - Programmable Logic Array

- Ten inputs

L - Active LOW Ouput

- Eight Outputs

What is CPLD ?

CPLDs are Complex Programmable Logic Devices. They are larger versions of PLDs with a centralized internal interconnect matrix used to connect the device macro cells together.

207.Define bit, byte and word.

The smallest unit of binary data is bit. Data are handled in a 8 bit unit called byte. A complete unit of information is called a word which consists of one or more bytes. 208. How many words can a 16x8 memory can store ?

A 16x8 memory can store 16,384 words of eight bits each



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209. Define address of a memory.

The location of a unit of data in a memory is called address. 210. Define Capacity of a memory.

It is the total number of data units that can be stored. 211. What is Read and Write operation ?

The Write operation stores data into a specified address into the memory and the Read operation takes data out of a specified address in the memory.

212. Why RAMs are called as Volatile ?

RAMs are called as Volatile memories because RAMs lose stored data when the power is turned OFF.

212.Define ROM.

ROM is a type of memory in which data are stored permanently or semi permanently. Data can be read from a ROM, but there is no write operation

213. Define RAM.

RAM is Random Access Memory. It is a random access read/write memory. The data can be read or written into from any selected address in any sequence.

214. List the two categories of RAMs.

The two categories of RAMs are static RAM(SRAM) and dynamic RAM (DRAM).



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215. Define Static RAM and dynamic RAM

Static RAM uses flip flops as storage elements and therefore store data indefinitely as

long as dc power is applied. Dynamic RAMs use capacitors as storage elements and cannot retain data very long without capacitors being recharged by a process called refreshing. 216. List the two types of SRAM

Asynchronous SRAMs

Synhronous Burst SRAMs 217.List the basic types of DRAMs

Fast Page Mode DRAM,Extended Data Out DRAM(EDO DRAM),Burst EDO DRAM and Synchronous DRAM.

Define a bus

A bus is a set of conductive paths that serve to interconnect two or more functional components of a system or several diverse systems.

219. Define Cache memory

It is a relatively small, high-speed memory that can store the most recently used instructions or data from larger but slower main memory.

220. What is the technique adopted by DRAMs.

DRAMs use a technique called address multiplexing to reduce the number of address



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lines.

221.Give the feature of UV EPROM

UV EPROM is electrically programmable by the user, but the store data must be erased by exposure to ultra violet light over a period of several minutes. 222.Give the feature of flash memory.

The ideal memory has high storage capacity, non-volatility; in-system read and write capability, comparatively fast operation. The traditional memory technologies such as ROM,

PROM, EEPROM individually exhibits one of these characteristics, but no single technology has all of them except the flash memory.

223.What are Flash memories ?

They are high density read/write memories that are non-volatile, which means data can be stored indefinitely with out power.

List the three major operations in a flash memory. Programming, Read and Erase operation

What is a FIFO memory ?

The term FIFO refers to the basic operation of this type of memory in which the first data bit written into the memory is to first to be read out.

226.List basic types of programmable logic devices. 1. Read only memory



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Programmable logic Array

Programmable Array Logic

Define ROM

A read only memory is a device that includes both the decoder and the OR gates within a single IC package.

228.Define address and word:


229. What are the types of ROM ?

Masked ROM.




300. What is programmable logic array? How it differs from ROM?

In some cases the number of dont care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.



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301.What is mask - programmable?

With a mask programmable PLA, the user must submit a PLA PLA program table to the manufacturer.

302.Give the comparison between PROM and PLA. PROM PLA

And array is fixed and OR array is programmable.

Both AND and OR arrays are Programmable.

Cheaper and simple to use. Costliest and complex than PROMS.

Part B

Unit-I

1) Simplify the boolean function using tabulation method. F = (0,1,2,8,10,11,14,15)

List all the min terms

Arrange them as per the number of ones based on binary equivalent

Compare one group with another for difference in one and replace the bit with dash. Continue this until no further grouping possible.

The unchecked terms represent the prime implicants.



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F = W'X'Y' + X'Z' + WY

Determine the prime implicants of the function F (W,X,Y,Z) = (1,4,6,7,8,9,10,11,15)

List all the min terms

Arrange them as per the number of ones based on binary equivalent

Compare one group with another for difference in one and replace the bit with dash. Continue this until no further grouping possible.

The unchecked terms represent the prime implicants. F = X'Y'Z + W'XZ' + W'XY + XYZ + WYZ + WX'

Minimum Set of prime implicants F = X'Y'Z + W'XZ' + XYZ + WX'

Simplify the Boolean function using K-map.

F(A,B,C,D,E) = (0,2,4,6,9,13,21,23,25,29,31)

Five variables hence two variable k maps one for A = 0 and the other for A = 1.

F = A'B'E' + BD'E + ACE

Obtain the canonical sum of products of the function Y = AB + ACD Y = AB (C + C')(D + D') + ACD (B + B')

Y = ABCD + ABCD' + ABC'D + ABC'D' + AB'CD

State the postulates and theorems of Boolean algebra.

X + 0 = X X 1 = X



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X + X' = 1 X X' = 0

X + X = X X X = X

X + 1 = 1 X 0 = 0 (X')' = X

X + Y = Y + X XY = YX

X + (Y + Z) = (X + Y) + Z X(YZ) = (XY)Z

X(Y + Z) = XY + XZ X + YX = (X + Y) (X + Z) (X + Y)' = X'Y' (XY)' = X' + Y'

X + XY = X X(X + Y) = X

Unit-II

Explain with neat diagrams TTL. Disadvantages of other families Diagram of TTL

Theory

Working principle

Discuss all the characteristics of digital ICs.

Fan out

Power dissipation

Propagation Delay



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Noise Margin

Fan In

Operating temperature

Power supply requirements

Explain with neat diagram how an open collector TTL operates. Disadvantages of other families

Diagram of open collector gate TTL Theory

Working principle

Explain the different applications of open collector TTL.

Wired logic

Common bus system

Drive a lamp or relay

10. Explain in detail about schottky TTL. Disadvantages of other families Diagram of schottky TTL

Theory

Working principle

Advantages



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11.Explain in detail about three state gate. Disadvantages of other families Explanation about three state gate Theory

Working principle

12.Explain with necessary diagrams MOS & CMOS. PMOS

NMOS

CMOS

Diagrams

13.Design a 4-bit binary adder/subtractor circuit. Basic equations

Comparison of equations Design using twos complement Circuit diagram

Unit-III

14.Explain the working of BCD Ripple Counter with the help of state diagram and logic diagram.

BCD Ripple Counter Count sequence



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Truth Table

State diagram representing the Truth Table Truth Table for the J-K Flip Flop

Logic Diagram

15.Design a logic circuit to convert the BCD code to Excess 3 code. Truth Table for BCD to Excess 3 conversion.

K-map simplification

Logic circuit implementing the Boolean Expression

16.Design and explain a comparator to compare two identical words. Two numbers represented by A = A3A2A1A0 & B = B3B2B1B0

If two numbers equal P = Ai Bi

Obtain the logic Expression . Obtain the logic diagram.

17.Design a sequential detector which produces an output 1 every time the input sequence 1011 is detected.

Construct state diagram Obtain the flow table

Obtain the flow table & output table Transition table



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Select flip flop Excitation table Logic diagram

18.. Explain in detail about serial in serial out shift register. Block diagram

Theoretical explanation Logic diagram Working

Unit-IV

19.Explain with neat diagram the different hazards and the way to eliminate them. Classification of hazards

Static hazard & Dynamic hazard definitions K map for selected functions

Method of elimination Essential hazards

20.State with a neat example the method for the minimization of primitive flow table. Consider a state diagram

Obtain the flow table

Using implication table reduce the flow table



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Using merger graph obtain maximal compatibles Verify closed & covered conditions

Plot the reduced flow table

21.Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0.

Obtain the state diagram Obtain the flow table

Using implication table reduce the flow table Using merger graph obtain maximal compatibles Verify closed & covered conditions

Plot the reduced flow table Obtain transition table Excitation table

Logic diagram

22.. Explain in detail about Races. Basics of races

Problem created due to races Classification of races Remedy for races



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cycles

23.. Explain the different methods of state assignment Three row state assignment

Shared row state assignment Four row flow table

Multiple row state assignment Prevention of races.

Unit-V

24Explain in detail about PLA with a specific example. Explanation about ROM

Classifications of ROM

Architecture of ROM

Specification of PLA

Specific Example

Related Diagram

Related Table.

25. Implement the following using a mux. F(a,b,c,d) = (0,1,3,4,8,9,15) Obtain the truth table

From the truth table realize the expressions for the outputs and inputs



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Realize the logic diagram.

26. Explain with neat diagrams a RAM architecture. Different Memories

Classification of memories

RAM architecture diagram

Timing waveforms

Coincident Decoding

Read write operations

27.Explain in detail about PLA and PAL. Basic ROM

Classification of PROM

Logic difference between Prom & PLA

Logic diagram implementing a function

Logic difference between Prom & PAL

Logic diagram implementing a function

28. Explain with neat diagrams a ROM architecture. Different Memories

Classification of memories

ROM architecture diagram



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Timing waveforms

Coincident Decoding

Read write operations

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