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ESSCIRC'85

RTB: A Full-Duplex ECL Transceiver For Wideband DigitalSystems.

Piero Belforte - Vanni Poletto - Mario Sartori

CSELT (Centro Studi e Laboratori Telecomunicazioni)1014B Torino (Italy), via G. Reiss Romoli 274, Tel. 39-11-21691

Summary

This paper deals with the design of a low cost ECL bipolar compatible I.C

performing the function of four balanced full-duplex transceivers particularlysuitable for interconnections long up to several tens of meters in digitalsystems.

One of the most interesting applications of this circuit is in the field of

wideband digital switching (up to 100 Mbit/sec) where the amount of two-wayinternal connections can be very high, [l] More precisely when bidirectional

video communications are concerned (as in the case of the digital switching of

video telephony signals) the use of this component virtually halves the wiringcost. Other applications include narrow band (up to 2 Mbit/sec) digital switchingsystems where it is possible to achieve great saving in cabling cost or to allow

the designers to implement interesting diagnosis and signalling schemes inside

the exchange.[2] Obviously his application range is not bounded to these fields

but covers all the situations where two-way communication implying the use of

standard receiver/transmitter pairs is needed.

The functional behaviour of RTB is shown in fig. 1:

Ct is an ECL driver with a low output inpedance, Ip is a common mode

current source, Ro is the line characteristic resistance, A1(A2) are linear

amplifiers, Cr is a differential to single ended ECL translator.

(.) Patents pending

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When two transceivers are sending data through the same line, the signal at

both end of the line is a superposition of the one transmitted from the local

terminal and the one received from the remote terminal. The line signal swing is

a bit larger than the standard ECL but down-shifted about .8 V. The circuit

subtracts from the line signal the contribution due to trasmitter, taking into

account the 6 dB attenuation caused by the line impedance matching. In ideal

conditions (lossless cable and negligible output impedance of the driver), it is

easy to show that, if the gain of Al is a half of the gain of A2, a completecancellation of the transmitted signal occurs. In such a way the outputtranslator Cr has the function of restoring the ECL level compatibility.

As the circuit recovers the incoming signal wave, it is easy to gaininformation about an abnormal state of the link (cut or shorted). This feature

also supplies a very simple method for testing the circuit; in fact, when the line

is open, the signal decoded at the receiving side of the tranceiver is equal to the

transmitted one, while when it is shorted the complement of the transmitted

signal can be found at the output. Therefore, connecting both open and shorted

the four tranceivers' line outputs, allows to check the correct behaviour of the

device.

In the chip four different functions are present, each one working in a fullyindependent mode, so attention must be paid to avoid crosstalk among them.

For this reason a careful design was made of the common bias circuit to obtain

an efficient decoupling.

The main goal of the design was to achieve the best trade-off between speedand power dissipation. For this reason a new low dissipation switched-load line

driver (*) suitable for ECL circuitry was developed, [fig. 2] The power

consumption of the drivers is externally programmable according to bit-rate

requirements and length of the cable interconnection; this is obtained throughan internally built voltage reference and an external programming resistor. In

the chip's architecture the bias circuit is shared by the four transceivers and a

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power saving is gained in it owing to the availability of complementary current

mirrors and amplifiers. (*)The I.C. was designed following both traditional and new methodological

approaches. In particular the optimization of the circuit from the point of view

of speed was carried out using advanced characterization and simulation

techniques. The choice of the sizes and geometries of transistors making up the

main circuit blocks (current switches, buffers, etc.) was the consequence of

their time-domain reflectometer (TDR) characterization. The TDR responses

have been obtained from a set of standard kit-parts available on SGS LLV

process. From these TDR responses very accurate macromodels of circuit blocks

are obtained using fitting programs. The very close integration between

computerized measurements and simulation tools allows the designer to obtain

very quickly and easily the optimized parameters of macromodels. [fig. 3] These

macromodels and their related parameters are then used to simulate the

internal behaviour, mainly concerning critical paths, in the integrated circuit. A

similar technique was also utilized for pin level electrical characterization of

the whole circuit.

The real world operation where two similar tranceivers are interconnected

through an external lossy cable was then analyzed. In this case the actual cable

is directly modeled by its time-domain scattering parameters. Suitable

simulation programs [3] utilize both I.C. and cable models for the analysis of

situations which are not covered by standard simulation aids. The results of

these evaluations for various bit-rates and cable lengths are shown in the paper

[fig. 4]. Chip's photograph and sizes are shown in Fig. 5.

Finally the main features of the implemented chip are given includingelectrical performances [fig. 6] and actual measurements in real operatingconditions, [fig. 7]

The RTB is now inserted as standard component among telecom I.Cs byS.G.S ATES.

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Acknowledgments

The authors wish to thank particularly Dr. Siligoni and Dr. Garue of S.G.S

ATES for their useful advices during the developement of the circuit.

Bibliography

[l] Enzo Garetti Piero Belforte Luciano Gabrieili

"New switching techniques for wideband and ISDN environments"

International Switching Symposium'84 (ISS '84) Florence

[2] Piero Belforte Enzo Garetti

"A new generation of LSI switching networks"

FORUM 'B3 - Geneva.

[3] Piero Belforte Bruno Bostica Giancarlo Guaschino

'Time domain simulation of lossy interconnections usingwave digital networks"International Symposium on Circuits and Systems (ISCAS '82)Roma, May 10-12, 1982

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equivalentcircuitresponse

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Fig.3 - Fitting of the emitter follower T.D.R. responseusing a macromodel.

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Fig. 4 - Time jitter computer evaluation for differentinterconnection lengths (100 balanced ribboncable).

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- Main electrical characteristics.

- Voltage supply 5V +_ lou- Power consumption 660mW- Input and output levels ECL 10K canpatibile- Typical Input-output delay

time (transmitter + receiver) 7 ns

IÎ&L _7 . Receivers ' output Eye patterns in real operating ccnditlans.(TVo functions connected through 8 meter ribbon cable)Upper : 50 M bit/sec.Lower : 100 Kbit/sec uncorrelated.

Fig. 5 - Chip's photograph (device area 3.2 mm2 pad area = 25%)