Routing Guide - Molex

I‐Trac™ Routing Guide: Backplane and Daughter card Connectors

I‐Trac Backplane and Daughter Card Connector

I‐Trac Routing Guide

SERIES: 76015, 76029, 75705, 75991, 76035 – Backplane Header Signal Module 76020, 75710, 76274, 76040 – Daughtercard Receptacle Signal Module

76011, 75910 – Right Angle Receptacle Signal Module (RAM)

Date: April 18, 2008 Revision: 2.0

By Dave Dunham Signal Integrity Manager [email protected]

Phone: (630) 718‐5817

Disclaimer: Molex does not guarantee the performance of the final product to the information provided in this document. All information in this report is considered Molex proprietary and confidential

MOLEX INCORPORATED 2222 WELLINGTON COURT, LISLE, IL 60532‐1682

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mailto:[email protected]


TABLE OF CONTENTS I. Overview...................................................................................................................................................3 II. Pad Stack..................................................................................................................................................4 Circular Pad Stack...................................................................................................................................4 Dumbbell Antipads.................................................................................................................................4 Diamond Antipads..................................................................................................................................5

III. Transmission Line Interface................................................................................................................6 Differential Flag Transmission Line Interface.....................................................................................6

IV. Escape Examples ..................................................................................................................................7 Escape Routing Discussion ....................................................................................................................7 Crosstalk ...................................................................................................................................................8 Four Track Escape, Six Pairs Per Wafer using the 11 row example.................................................9 Backplane (75705)................................................................................................................................9

Six Track Escape, Eight Pairs Per Wafer using the 11 row example..............................................10 Daughter card (75710) ......................................................................................................................10

Six Track Escape, Eight Pairs Per Wafer using the 11 row example..............................................11 Backplane (75705)..............................................................................................................................11

Atypical Escape Example using the 11 row example ......................................................................12 Backplane (75705)..............................................................................................................................12

V. Appendix ..............................................................................................................................................13 Glossary ..................................................................................................................................................13


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I. Overview

The I‐Trac connector system offers many options for PCB routing. Because the wafer pitch is 3.7mm, multi‐track routing between the press‐fit pins is possible. Because any pin can be assigned to conduct a signal, or return currents, many signal and ground patterns are possible. The intention of this document is to describe some common configurations and give examples. Two types of examples are offered. A standard technology that offers two or four track routing between the wafers and easily manufactured trace widths and spaces. The standard technology lends itself to high speed interconnect design by delivering a higher signal to noise ratio, but lower signal density per routing layer. An advanced technology that offers as much as six track routing between the wafers with an attendant, smaller feature size and a reduced signal to noise ratio. The advanced technology lends itself to higher density, slower speed, signals. Because most PCB design takes place using English units, this guide uses English units (inches). If there is a conflict, use the metric dimensions listed on the mechanical drawings. This guide is not intended as a substitute for engineering analysis.


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II. Pad Stack

Circular Pad Stack To conduct single ended signals and for many other purposes, a simple circular pad stack may be preferred. This is the highest density option. Any pin can be assigned to conduct signals using the circular pad stack.

Feature Diameter (mils) Finished hole 18 Drill 22 Pad 32 Antipad 46 or 44*

*Use 44mil antipads for the high density daughter card.

Dumbbell Antipads Higher speed differential pairs may benefit from the reduced capacitance of a dumbbell antipad. This antipad is recommended for I‐Trac™ routing using grouped pairs (TX/RX grouping used in many SerDes designs).

Figure 1.1 Dumbbell antipads around backplane pads.

An 8‐pair escape, 6mil trace and 8mil space shown using I‐Trac™ 11 row.


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Figure 1.2 Dumbbell antipads around daughter card pads.

A 6‐pair escape, 6mil trace shown using the I‐Trac™ 11 row. Note, the high density daughter card examples require 0.0440” antipads, instead of 0.0460”. This is due to a closer transmission line to via pad spacing (6mil

transmission line to pad spacing for the high density daughter card versus 7mil transmission line to via spacing for the high density backplane).

Diamond Antipads Diamond antipads offer the highest speed option. However, they are more complex and limit signal density in some applications. This is a superior choice for an I‐Trac™ routing using a pair‐ground escape pattern.

Figure 1.3 Diamond antipads around backplane pads.

Backplane vias are on a 45º angle.


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Figure 1.4 Diamond antipads around daughter card pads. Daughter card vias are not on a 45º angle, thus partial symmetry.

III. Transmission Line Interface Differential Flag Transmission Line Interface An opportunity for deskew and improved return loss is present at the pin escape via. To reduce intra‐pair skew the example escape has a symmetric design and the transmission line pair exits perpendicular to the via pair. To improve return loss the length of transmission line in the antipad region of the via has been increased to offer an inductive compensation to the capacitive via. This is done, in part, by attaching the transmission line to the via pad tangent to the pad. This feature also helps to prevent drill breakout like a tear drop, without the extra capacitance of a full tear drop. See figure 3.1. If a normal‐to‐the‐drill, transmission line to via interface is preferred, it is recommended that tear drops be added to the interface to prevent drill breakout. See figure 3.2.


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Figure 3.1 Flag Escape Detail. Backplane, 4mil track and 5mil gap shown.

Figure 3.2 Tear drop example for, normal‐to‐the‐drill escapes.

IV. Escape Examples Escape Routing Discussion I‐Trac offers opportunities for very high speed signal transmission and for high density signal transmission. This makes I‐Trac a good candidate for systems with high to very high speed, differential signaling with the inclusion of slower speed signals. Antipad size and crosstalk are important factors to consider when developing a PCB design to interface with I‐Trac. Smaller antipads allow for higher density routing, however they also lead to excess capacitance and limit the bandwidth available by making the system resonant at a lower frequency. Larger antipads offer more bandwidth, but limit the size of the routing channel. A similar trade off occurs with crosstalk. Lower density escapes often see less crosstalk because there is more space between conductors and often there are additional returns between the signal conductors as well. Both of these things help to limit crosstalk. Both of these things also limit signal density. Because digital systems have a variety of requirements, examples of both high density and high speed escapes are offered. The available space between the vias is a fundamental factor in escape design. An important consideration is the size of the antipad. It must be large enough to prevent the formation of high resistance shorts and conductive anodic filament growth, CAF. Thus, Molex recommends that the antipad diameter be no smaller than 42mil. If the design will support a larger antipad, take advantage of it. Examples shown here take advantage of a 46mil antipad (backplane) and a 44mil antipad (high density daughter card). The two and four track routing examples can be made in ½ oz and 1oz copper without difficulty. The six track examples should be constrained to ½ oz copper only.


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It is possible to escape from an I‐Trac connector at right angles to the preferred direction. See Figure 4.4 (Atypical Escape Example). In the example shown, there is 11mil between the drilled hole for an I‐Trac pin and the closest approach of a trace. This is far enough to meet many PCB fabricators recommendations. Crosstalk Crosstalk presents a problem for any signaling design. It is almost always a good idea to take steps to minimize it. Most digital systems use unidirectional signaling and the advice below assumes that send and receive data use different wires. This assumption simplifies the discussion because backwards, or near end (NEXT), crosstalk is easier to avoid. There are some simple things to do to reduce crosstalk in many systems. These include:

1. Separate transmit and receive transmission lines. If transmit and receive transmission lines need to be placed on the same layer, separate them with extra space. If they can be placed on separate routing layers, do so.

2. Separate transmit and receive vias. For I‐Trac, ideally the transmit and receive signals will be separated by a ground via in the same wafer. For differential signaling, we have seen about 3X less crosstalk by separating transmit and receive pairs by vias instead of separating the transmit and receive pairs by wafer. The examples below capitalize on this by grouping like transmission lines across wafers. Do not overlap transmit and receive via antipads.

3. Separate transmit or receive vias from each other. Far end crosstalk is still a concern, even if it isn’t as much of a concern as near end crosstalk. If a ground via can be placed between signals, a crosstalk reduction will result. The 6‐pair examples below capitalize on this by placing a ground via between every pair.

4. Separate transmit or receive transmission lines from each other. In a perfect stripline system, far end crosstalk is negligible. Unfortunately practical systems can not use perfect striplines and imperfections result in far end crosstalk.


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Four track escape, six pairs per wafer using the 11 row example Backplane (75705)

Figure 4.1 Four track, six pair, 11 row backplane (75705) escape example.

A 6mil trace and 8mil space illustrated. Using this pattern, it is possible to escape in three signal layers.

Figure 4.2, Four track, six pair per wafer, 11 row backplane (75705) example.


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Six track escape, eight pairs per wafer using the 11 row example Daughter card (75710)

Figure 4.3 Six track, eight pair per wafer, 11 row daughter card (75710) escape example. 4mil trace and 5mil space illustrated. Using this pattern, it is possible to escape in three signal layers.

Figure 4.4 Six and four track, eight pair per wafer, 11 row escape example.


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Six track escape, eight pairs per wafer using the 11 row example Backplane (75705)

Figure 4.3 Six track, eight pair per wafer, 11 row backplane (75705) card escape example. 4mil trace and 5mil space illustrated. Using this pattern, it is possible to escape in three signal layers.


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Atypical escape example using the 11 row example Backplane (75705)

Figure 4.4 Atypical escape, six pair per wafer, 11 row backplane (75705) card example. 6mil trace illustrated. It is possible to escape at right angles to the preferred direction. Using 58mil antipads and

6mil traces leaves 11mil between the drilled hole and the trace.


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V. Appendix

Glossary ANNULAR RING: The ring from the inside surface of the finished hole to the outside surface of the pad. ANTIPAD: That area around the pad, from which copper has been excluded. Can be conceived of as a cylinder of exclusion centered on the intended path of the drill. BACKPLANE: That PCB associated with the male connectors. COPPER WEIGHT: Copper thickness on a PCB laminate can be measured by observing its thickness, or by observing the weight of a one foot square piece of solid copper foil. Because the density of copper does not change, the measures are equivalent. To convert finished copper weight to copper thickness use the following relationship; 0.0012” < 1oz < 0.0014” The density of copper doesn’t change, but the thickness of the copper after processing does change, thus the range. DAUGHTER CARD: That PCB associated with female connectors. FINISHED HOLE: A hole after processing is complete. If a plated hole is requested, the finished hole diameter is the distance from inner plated wall to inner plated wall. PAD: The copper cylinder that was penetrated by a drill. Often serves as an attach point for transmission lines. TEAR DROP: An extra fillet of copper to reduce the chances of drill breakout in the pad. The fillet makes the pad look like a drop of water, a tear drop.


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