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Home » Source Code » rouiter design using
verilog » router_reg.v
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From： rouiter design using verilog
Description：design router using verilog.design a 1x3 router
using verilog.
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/************************************************************************
MAVEN SILICON CONFIDENTIAL ‐ This is an unpublished,
proprietary work
of Maven Silicon Softech Pvt. Ltd., Bangalore, and is fully
protected
under copyright and trade secret laws. You may not view, use,
disclose,
copy, or distribute this file or any information contained
herein except
pursuant to a valid written license from Maven Silicon
Softech Pvt. Ltd.,
Bangalore
Design Name : router_1X3
Module Name : router_reg
Date : 19/09/2009
Description : This module contains all the status,
data
parity registers required by router_1x3 Author : P R
SIVAKUMAR
Email : [email protected]
Company : Maven Silicon, Bangalore
www.vlsitraining.com
Version : 1.0 revision 0.0
*************************************************************************/
module router_reg ( clock,
resetn,
packet_valid,
data_in,
fifo_full,
detect_add,
lfd_state,
ld_state,
lp_state,
laf_state, full_state,
reset_int_reg,
parity_done,
low_packet_valid,
dout,
err
);
input clock;
input resetn;
input packet_valid;
input [7:0] data_in;
input fifo_full;
input reset_int_reg;
input detect_add; input ld_state;
input lp_state;
input lfd_state;
input laf_state;
input full_state;
output parity_done;
output low_packet_valid;
output [7:0] dout;
output err;
reg parity_done;
reg low_packet_valid;
reg [7:0] dout;
reg err;
//Internal signals
reg [7:0] first_byte;
reg [7:0] full_state_byte;
reg [7:0] data_parity;
reg [7:0] parity;
reg check_error;
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