Robert Mroczyński - Kyungpook National Universitybkict-ocw.knu.ac.kr/include/download.html?fn=55C4687838A... · Quirk M., Serda J.: Semiconductor Manufacturing Technology, Prentice

2. Fabrication techniques

KNU Seminar Course 2015

Robert Mroczyński

KNU Seminar Course 2015 – College of IT Engineering

Technological layers used in the course of

the IC fabrication

2

Semiconductors

Fundamental part of each IC, active material of

semiconductor device – channel of the MOS transistor

(also as the amorphous semiconductor layer in TFTs)

Dielectrics

Isolation between metallization levels, passivation of

semiconductor devices, implantation/diffusion masks,

gate dielectrics !

Conductive materials

Pads, contacts, conductive paths


The division of fabrication techniques

3

Two fundamental techniques for layers fabrication

Direct chemical reaction between semiconductor

substrate and reactive gases e.g., thermal oxidation,

thermal nitridation, plasma oxidation; the fabricated layer

is a derivative of the semiconductor substrate e.g.,

silicon oxynitride; only few materials can be obtained on

the particular substrate

Semiconductor substrate acts only as the passive

component during particular layer fabrication e.g.,

chemical vapor deposition, physical vapor deposition; the

freedom of choice of the obtained layer and

semiconductor substrate


Fundamental techniques

4

Direct chemical reaction

Thermal oxidation

RTP (Rapid Thermal Processing)

The layer is deposited on the substrate

CVD – Chemical Vapor Deposition (APCVD, LPCVD,

PECVD, MOCVD)

ALD – Atomic Layer Deposition

PVD – Physical Vapor Deposition (Thermal Evaporation,

Ion Sputtering, Magnetron Reactive Sputtering)


Silicon dioxide (SiO2) fabrication

5

Si

SiO2

Silicon dioxide

Silicon substrate

h1

h2

h1 ≠ h2

Silicon is consumed

44 % !!


Thermal oxidation of silicon

6

Gas distribution

system

O2

Ar

N2

‘furnace zone’

900 – 1100°C

Quartz furnace with heating system Si

SiO2


Process’ parameters

7

Temperature

Time

Pressure

Reactive gases composition and flows

Semiconductor substrate’s orientation

Type of the process (‘wet’ <-> ‘dry’)

Doering R., Nishi Y.: Handbook of

semiconductor technology

Huff H.R., Gilmer D.C.: High dielectric constant materials

0,0

0,1

1,0

10,0

10 100 1000

Ox

ide

th

ick

ne

ss

[m

m]

Oxidation time[min]

20 atm

10 atm

5 atm

1 atm


Dry <-> wet oxidation

8

‘DRY’

Fabricated in pure oxygen

(sometimes with HCl addition in

order to improve electro-

physical properties and kinetics

control

Very slow growth

Low amount of defects on the

silicon/silicon dioxide interface

(Qit)

‘WET’

Fabricated in the mixture of

oxygen and water vapors

Fast growth

Bigger amount of defects on the

silicon/silicon dioxide interface

(Qit), as well as the dielectric

layer bulk in comparison to ‘dry’

oxide

A. Javey, Berkeley Univ., EECS143


Vertical furnaces

9

Lower amount of semiconductor wafers

batch -> higher process’ versatility

Lower area occupation by the equipment,

i.e., ‘foot-print’

The better control of reactive gases flow

around the semiconductor wafers -> the

better homogeneity of silicon dioxide

thickness across the each wafer

The possibility for introduction of additional

rotation of silicon wafers during the process

-> better homogeneity

Smaller temperature gradient onto the

wafer

Higher automation of processing

The easier change of quartz furnace


Ultra-thin oxide layers formation

10

In ultra-thin regime the oxidation time is very short – from several

minutes down to few seconds – it is hard to control the thermal

process -> lack of process’ repeatability !


… and thus RTP reactors have been designed

11

Rapid Thermal Processing

The huge of thermal power is

focused onto a very small

area -> the possibility to

obtain a very rapid and

precise temperature changes

Small volume of the reactive

chamber -> the full change of

the reactive gases in few

seconds


Typical RTP process’ flow

12

Time

Temp. Temp.

Time 25 s – 1 min

Heating

Neutr

al gases

Pro

cess

Reactive g

ases

Coolin

g

Neautr

al gases

Sta

ge 1

Sta

ge 2

Oth

er

reactive g

ases

Heating

Neutr

al gases

Coolin

g

Neautr

al gases


Applications of RTP

13

Fabrication of ultra-thin dielectric layer (RTO – Rapid

Thermal Oxidation, RTN – Rapid Thermal Nitridation)

The densification of layers

The annealing of layers: dielectric (fabricated by different

methods) in order to improve electro-physical properties,

conductive in order to improve contact properties

Post implantation annealing in order to electrical

activation of dopants

Reflow of Phospho-Silicate- and Phospho-Boron-Silicate

Glass (PSG and BPSG)

Silicide formation (TiSi2)


Thermal oxidation <-> RTP

14

Thermal Oxidation RTP


Silicon oxide applications – Field Oxide

15

Serves as an isolation barrier between individual transistors to

isolate them from each other

Common field oxide thickness range from 2.500 Å to 15.000 Å

Wet oxidation is the preferred method

Quirk M., Serda J.:

Semiconductor

Manufacturing

Technology,

Prentice Hall 2001

Field oxide

Transistor site

p+ Silicon substrate


Silicon oxide applications – Gate Dielectric

16

Serves as a dielectric between the gate and source-drain parts of

MOS transistor

Growth rate at room temperature is 15 Å per hour up to about 40 Å

Common gate oxide film thickness range from about 30 Å to 500 Å

Dry oxidation is the preferred method Quirk M., Serda J.:

Semiconductor Manufacturing Technology, Prentice

Hall 2001

Gate oxide

Transistor site


Source Drain

Gate


Silicon oxide applications – masking material

17

Masking material when implanting dopant into wafer

Dopants diffuse into unmasked areas of silicon by

selective diffusion Quirk M., Serda J.:

Semiconductor

Manufacturing

Technology,

Prentice Hall 2001

Dopant barrier

spacer oxide

Ion implantation

Gate

Spacer oxide protects narrow

channel from high-energy implant


Silicon oxide applications – Pad Oxide

18

Provides stress reduction for Si3N4

Thermally grown and very thin Quirk M., Serda J.:

Semiconductor

Manufacturing

Technology,

Prentice Hall 2001

Silicon oxynitride

Nitride oxidation mask Bird’s beak region

Selective oxidation

Pad oxide

Silicon substrate

Silicon dioxide


LOCOS – Local Oxidtion of Silicon

19

The decrease of field oxide height and window shape in

comparison to ‘classical’ isolation

The possibility of further easier processing steps, e.g.

dielectric and conductive layers deposition

Better isolation of adjacent devices

KNU Seminar Course 2015 – College of IT Engineering 20

Plummer J.D., Deal M.D., Griffin P.B.:

Silicon VLSI technology


Step coverage

21

The layer growth kinetics depends on the angle which

allows to access of deposited materials

The profile is a very important, but not independent

parameter

The homogeneity of step coverage is temperature

dependent – the higher temperature, the better particles

allocation – more convenient places from the energetic

point of view

φ


Examples of covering failures

22




Shallow Trench Isolation (STI)

23

Much better isolation of adjacent devices in

comparison to LOCOS


STI with CMP

24

CMP – Chemical-Mechanical Polishing

‘modified’ version of STI which is commonly used in

nowadays ICs technologies

24


How it is in the reality ?

25

Doering R., Nishi Y.:

Handbook of

semiconductor

technology


Silicon oxide applications – Screen Oxide

26

Quirk M., Serda J.:

Semiconductor

Manufacturing

Technology,

Prentice Hall 2001

Sometimes referred to as “sacrificial oxide”, screen oxide, is

used to reduce implant channeling and damage

Assists creation of shallow junctions

Dry oxide

Ion implantation Screen oxide

High damage to upper Si surface + more channeling

Low damage to upper Si surface + less channeling



Silicon oxide applications – Intermetal Oxide

27

Serves as protective/isolation layer between metal lines

This oxide is not thermally grown, but is deposited (see

further part of this lecture !) Quirk M., Serda J.:

Semiconductor

Manufacturing

Technology,

Prentice Hall 2001

Passivation layer

ILD-4

ILD-5

M-3

M-4

Interlayer oxide

Bonding pad metal


Chemical Vapor Deposition (CVD) processes

28

Atmospheric Pressure CVD (APCVD)

Low Pressure CVD (LPCVD)

Plasma Enhanced CVD (PECVD)

Metalo-Organic CVD (MOCVD)

Atomic Layer Deposition (ALD)

Doering R., Nishi Y.:

Handbook of semiconductor technology


APCVD

29

Process’ parameters:

Reactive gases composition

Wafer transportation speed

Temperature

To pumps

Nitrogen

courtain

Gases inlet

Transport

belt Heater




LPCVD


Reactive gases

composition

Temperature

Pressure

Time

Gas distribution system

Quartz furnace with heaters

Loadlock

To pumps

Pressure meter

SiH4

SiCl2H2

N2


PECVD


Reactive gases composition

Temperature

Pressure

Power

Time

Electrode geometry

Gas inlet

PLASMA

~

Heated table

R.F. generator

To pumps

Electrodes


The comparison of CVD reactors

32

PROCESS

ADVANTAGES

DISADVANTAGES

APPLICATION

APCVD

(300-500°C)

• simplicity of reactor

• fast deposition rate

• low temperature

processing

• poor step coverage

• impurities

• passivation and isolation oxides

(doped, as well as un-doped)

LPCVD

(600-850°C)

• cleanliness of deposited

materials

• homogeneity

• conformal step coverage

• a large batch processing

• high temperature

processing

• low deposition rate

• gate and tunneling dielectrics

• isolation oxides (doped, as well

as un-doped)

• silicon nitrides

• poly-silicon

PECVD

(200-400°C)

• low temperature

processing

• fast deposition rate

• good step coverage

• impurities • passivation and isolation oxides

• M(O)EMS !


Atomic Layer Deposition (ALD)

33

ALD is a self-limiting, sequential surface

chemistry that deposits conformal thin-films of

materials onto substrates of varying

compositions

ALD is similar in chemistry to CVD, except that

the ALD reaction breaks the CVD reaction into

two half-reactions, keeping the precursor

materials separate during the reaction

ALD film growth is self-limited and based on

surface reactions, which makes achieving

atomic scale deposition control possible

By keeping the precursors separate throughout

the coating process, atomic layer control of film

grown can be obtained as fine as ~0.1

angstroms per monolayer


Exemplary ALD process scheme – hafnium

dioxide (HfO2) deposition

34

M. Godlewski:

Technologia Osadzania Warstw Atomowych –

zastosowania w elektronice, fotowoltaice i optoelektronice Si Si Si Si

Si Si Si Si

O O O O

H H H H

Hf Cl

Cl

Cl

Cl

Hf Cl

Cl

Cl

Cl




35

Si Si Si Si

Si Si Si Si

O O O O

H H H H

Hf Cl

Cl

Cl

Cl

Hf Cl

Cl

Cl

Cl

M. Godlewski:


zastosowania w elektronice, fotowoltaice i optoelektronice




36

Si Si Si Si

Si Si Si Si

Hf Cl

Cl

Cl

O O O O

Hf Cl

Cl

Cl

O

O

O H H

H

H

H H

M. Godlewski:






37

Si Si Si Si

Si Si Si Si

O O O O

Hf Hf Hf Hf O O O

O O O O

H H H H

Hf Cl

Cl

Cl

Cl

Hf Cl

Cl

Cl

Cl

M. Godlewski:






38

Si Si Si Si

Si Si Si Si

O O O O

Hf Hf Hf Hf O O O

O O O O

Hf Hf Hf Hf O O O

M. Godlewski:




ALD applications

39

High-k dielectric materials – HfO2, Al2O3, TiO2, ZrO2

Barrier layers or metal gates: TiN, TaN

Huff H.R., Gilmer D.C.:

High dielectric constant

materials


Physical Vapor Deposition (PVD) processes

40

Thermal evaporation

Ion sputtering

Radio Frequency (R.F) magnetron sputtering


Thermal evaporation

41

Material

evaporated

Support wih

wafers

To pumps

Vacuum chamber Thermal evaporation -> only selected

materials, such as: Al, Au, Ag…

Very high vacuum -> mean particles

free path

Resistor and evaporated material can

react with each other -> impurities

Cheap and easy technology !


Conductive materials

42

Material

Melting

temperature

[°C]

Resistivity

[µΩcm]

Silicon 1412 ~ 109

Polysilicon (poly-Si) 1412 500 – 525

Aluminum (Al) 660 2.65

Copper (Cu) 1083 1.678

Tungsten (W) 3417 8

Titanium (Ti) 1670 60

Tantalum (Ta) 2996 13 – 16

Molibdenum (Mo) 2620 5

Platinum (Pt) 1772 10


Thermal evaporation with e-gun

43

Focused high energy electron beam (>4 kW)

High magnetic field which deflects the electron flux -> mass separation and control

Cooling system -> no impurities from crucible material

BUT

Problems with the evaporation of compound materials – different vapor pressure

X-Rays

Porosity of layers due to the high energy ions which introduce clusters deposition on the surface

Magnets

E-gun (hot filament) Cooling system

Target


Evaporation failures

44

The problem with the ensure of

homogeneity of evaporated

materials on the large surface

simultaneously with high layer

growth rate

Shadow zones

The only option -> to increase the

source-substrate lenght BUT reactor

geometry/size, as well as high vacuum

necessity issues

Thickness

Wafers rotation

Increase the area of

evaporated material


Sputtering process

45

In order to glow discharge (plasma ignition)

the vacuum cannot be as high as in the

case of thermal evaporation

Low vacuum -> impurities + low mean free

path

Small differences of compound materials in

comparison to target composition

Better process’ control -> more controllable

process’ parameters BUT optimization

Very high equipment cost

Increase of ion density -> magnetic field

use (magnetron sputtering process)

Radio frequency (R.F.) sputtering -> in

order to dielectric layers fabrication

PLASMA

+ -

cathode anode

electrons

ions

Si wafer Target


Magnetron sputtering

46

Magnetic field can trap the electrons

in the vapor phase

Electrons more effectively ionize the

gas particles -> ion bombardment of

target is increased

Lower process’ temperatures

Higher sputtered area

PLAZMA

N S

Target

N

Magnets

Si wafers


The most common problem

47

Electromigration effect

Characteristic for ALL materials

Electrons transfer theirs momentum to material’s atom - > atoms flow

Critical condition – current density

At the negative potential – possible open

At the positive potential – possible shortage

Sze S.M.: Semiconductor devices – physics and technology Javey A.: EE143


Aluminum and copper – materials

commonly used for conductive patterns

48

Al Cu

Resistivity [µΩcm] 2.65 1.678

Electromigration

resistance

Low High

Corrosion

resistance

Low Medium

CVD fabrication Yes No

CMP processing Yes Yes


Copper metallization

49

There are no effective methods for

patterns definition by using classical

lithography methods (no possibility

for dry etching)

Damascene technology is the only

option

Necessity for using barrier layers

which eliminate the migration of

copper atoms into adjacent

semiconductor and dielectric layers

There are also needed layers which

improve the adhesion level and

special layers for copper electro-

plating (copper fabrication)





Thank you for attention !

51

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Robert Mroczyński - Kyungpook National Universitybkict-ocw.knu.ac.kr/include/download.html?fn=55C4687838A... · Quirk M., Serda J.: Semiconductor Manufacturing Technology, Prentice