RN - 1 03/08/05 National Aeronautics and Space Administration Jet Propulsion Laboratory California Institute of Technology Implementation of an Antenna

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National Aeronautics and Space AdministrationJet Propulsion LaboratoryCalifornia Institute of Technology Implementation of an Antenna Array Signal Processing

Breadboard for the Deep Space Network

RadioNet Engineering Forum Workshop:

Next Generation Correlators for Radio Astronomy and Geodesy

Robert Navarro

Jet Propulsion Laboratory,

California Institute of Technology.

June 27, 2006

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DSN Large Array Background

• The DSN is currently evaluating the use of a Large Array to replace or augment the current 34 and 70 meter antenna assets.

• Will mainly be used to support telemetry of deep space missions but will also support navigation and some science requirements.

• The current Large Array strawman design calls for

– Three Complexes (Western US, Australia, European Longitude), each with:

• 100 to 400 downlink antennas nominally sized at 12m each.

• Remotely conduct all real-time monitor and control for the network

• Number of Antennas in a cluster scaleable up to 400.

– Design needs to accommodate growth but is not infinitely scalable

• Number of IF inputs per antenna ~2.

– RCP & LCP or X and Ka

• IF signal bandwidth ~500 MHz 1dB

– Main driver for sample rate of 1280 Ms/sec.

• Signals of interest can come from anywhere in input passband

• Provide up to 16 simultaneous phased array outputs

• Provide a wideband correlator (~500 MHz) which can process a significant number of the antenna signals

– Required to support the array for phase and antenna position calibration and searching for lost spacecraft

Large Array Overview Proposed Signal Processing Req.

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Breadboard Array Signal Processing Objectives

• Provide a means to evaluate the performance of the Breadboard Array’s antenna subsystem (the antenna, feed and RF-IF downconversion) for one 12 meter and two 6 meter antennas.

• Design and build prototype signal processing hardware – High density IF digitizer, current design supports 6 Antennas (12 IF inputs) in one

chassis– High speed FPGA digital signal processing board for AdvancedTCA chassis

• Demonstrate and evaluate proposed signal processing techniques – Implement an architecture similar to an FX correlator but includes synthesis processing at

the output to reconstruct a time domain signal for beamforming applications – Provide both beamformer and wideband correlation functions– Support Order N and Order N2 complexity combining algorithms– Polyphase FIR filter and FFT for Analysis filterbank – Synthesis filterbank for reconstruction of beamformer output

• Gain experience with various technologies that may be used in the Large Array– High speed serial digital signal interconnects (3 to 10 Gbit/s links)– High speed analog to digital converters (1280 Ms/s, 8 bit) – AdvancedTCA Chassis with high speed serial backplane– Field Programmable Gate Arrays for digital signal processing– Linux OS for use in embedded processors

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Breadboard Hardware

IF Digitizer (IFD)

Array Sampler Module (ASM)

IFA

IFB


IFA

IFB


IFA

IFB

CommonModule (CMM)

100 MHZ

1PPS

Realtime Signal Proc (RSP)

Array Processing Element (APE)


Data Processor &Controller PC (DPC)

GigabitEtherswitch

12x DigitalFiber Optic

700-1200 MHzAnalog Fiber Optic

From Antenna

Timing Reference

Breadboard Array Signal Processing


Bac

kpla

ne

Bac

kpla

ne

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Breadboard Signal Processing Flow

• Functional Blocks in green are implemented.

• Functional Blocks in blue are in development

ADC DelayAnalysis

FilterbankPhase

RotationCorr

ADC DelayAnalysis

FilterbankPhase

RotationCombine

SynthFilterbank

Receiver

N

N

IF signal from Antenna

IF signal from Antenna

Cross Correlation

Data

Breadboard Array Correlator and Combiner Signal FlowSimplified Two Antenna Case

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Detail – Analysis Filterbank

• Block Diagram of Analysis Filterbank in Antenna FPGA

• This structure allows for oversampling of the DFT to obtain overlap in the bandwidth of the frequency channels.

• The extra bandwidth in each frequency channel allows for fringe rate (frequency) corrections to be made to each channel.

• Also, it allows for the analysis/synthesis filterbank combination to give near perfect reconstruction with a simple square root raised cosine prototype filter.

Short Time Transform)(~ mX k

)( rh Analysis Window

Time aliasing (Overlap-Add) in

blocks of K samples.

Windowed Sequence

Sequence of Operations for weighted overlap-add spectral analyzer

DFT

+

+

+

Implemented with FFT

Time Aliased sequence

Input x(n) in Blocksof M samples

N – Sample Shift Register(Direction of Shift)

r=0 r=K-1

(From Multirate Digital Signal Processing, Crochiere and Rabiner, page 318)

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APE Board in Real-time Signal Processor

4

4

4

4

4

Demux

Demux

PPC

GigabitEthernet

DSPFPGA

DSPFPGA

DSPFPGA

DSPFPGA

PPCInterface

FPGA

Fanout &IF Select

FPGA

CrossbarSwitch

Digital IFData From Sampler

1280 Ms/sec

HS Serial IO to/fromATCA Fullmesh

Backplane

Digital IFData From Sampler

1280 Ms/sec

Ethernetto/from DPC


PPC Bus

High-speed(HS) serial IO

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APE Board Picture

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BBA Signal Processing Results Summary

• Built and Tested Hardware: 3 Array Sampler Modules (ASM) for the IF Digitizer (IFD) and 3 Array Processing Element (APE) boards for the Real Time Signal Processor (RSP).

• Software and Signal Processing Firmware (FPGA code) for the wideband correlator completed and tested.

• Successfully demonstrated these technologies for BBA:– High Speed A/D (1280 Ms/sec, 10 bit digitizer)– Analog Fiber link from Antenna to IFD.– Optical Fiber link from IFD to RSP.– High Speed Serial links (3.2 Gb/sec) between Filterbanks and

Correlator blocks.– Real-time Linux OS for Embedded PowerPC processors.– Wideband (640 MHz) Discrete Fourier Transform Analysis Filterbank

implemented in FPGA.

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Experimental Results

• Successfully detected interferometric fringes from two 6 meter antennas using Venus as the source in Dec 2005.

• Successfully stopped interferometric fringes using Geometric models while viewing Venus, Cygnus A, and Cassiopeia A with the two 6 meter antennas on the mesa in January 2006.

• Signal Processing Monitor plots give visibility to confirm correlation and measure delay offsets but not to do detailed analysis of data.

• Correlation Data is archived for later processing using AIPS software to determine more accurate antenna position.

• Continued observations with other sources such as 3C84, 3C273, and 3C48.

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Experiment Results: Phase and Amplitude

Results from two 6 meter antennas looking at Cygnus A:

• Amplitude and Phase shown over 640 MHz complex sampling band.

• Large spikes in Amplitude and Phase from RF interference at X-band

•Geometric models and offsets for path delay applied to bring delay to zero.

• For zero delay, the plot of phase versus frequency should have a slope of zero across the band.

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Experiment Results: Lag and Time Delay Plots

Results from two 6 meter antennas looking at Cygnus A:

• Plot of Lag Amplitude made by taking inverse FFT of frequency channel data.

•Main Lobe of lag plot centered at delay of Antenna2 to Antenna1.

• Frequency channels with RF interference excluded in calculating these plots.

• Delay Time History plot tracks peak of Lag Amplitude plot.

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Experimental Results: Visibility Phase and Amp

3C84 at X-band - day 06/159Lag(0) data for 160 channels (9100 to 9300 MHz)

Running Boresight Script to go on and off source.

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

19:00:00 20:00:00 21:00:00 22:00:00 23:00:00 0:00:00

Time UT Hours

Vis

ibil

ity

Am

pli

tud

e (d

B)

-4

-3

-2

-1

0

1

2

3

4

Vis

ibil

ity

Ph

ase

(rad

ian

s)

Peak_Amp

Peak_Phase

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Scaling to Larger Arrays

• Revise current ATCA APE board into 3 or 4 ATCA boards optimized to the various functions of the Array Signal Processing using latest FPGA technology available.

– Input analysis filterbank (Frequency Channelizer) Board– Data Routing/Corner Turner Board – Correlate/Combine Board– Synthesis Board

• Research interconnect strategies for Advanced TCA to Advanced TCA chassis interconnection.

• Architecture must provide features to increase system reliability– Redundant power supplies & hard drives to avoid the most common failures– Hot swap capability to allow hardware repair without shutting down systems – Avoid single points of failure by distributing functions across multiple boards and

chassis– Automatic diagnostics to identify hardware to be swapped – Many of these features are provided by attributes of Advanced TCA shelf

technology.

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Large Array Signal Processing Architecture

FX Beamformer & Correlator

• Digitize entire antenna IF bandwidth• Apply course delay and phase

corrections in time domain • Analysis filterbank uses polyphase

FIR filter and a FFT to break the time domain signal up into evenly spaced frequency channels

• Apply fine delay and phase corrections in the frequency domain

• Multiple correction profiles required to support multiple beams per antenna

• Multiple resolutions required to support wideband correlation and spacecraft signals

• Pre-Router receives frequency channel data from multiple antennas and rearranges the data so that each output carries data for all input antennas over a subset of the frequency channels

• Failure of one block does not cause failure of entire signal processing system

Ant IFAnalysis

FilterbankIF Digitizer

AnalysisFilterbank

Ant IF IF DigitizerAnalysis

Filterbank

AnalysisFilterbank

AnalysisFilterbank

AnalysisFilterbank

IF DigitizerAnt IFPre

Router

PreRouter

Ant IF IF Digitizer

Ant IF IF Digitizer

IF DigitizerAnt IF

PreRouter

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FX Beamformer & Correlator

• Post-Router receives input from each Pre-Router and completes the corner turning process

• Beamformers receive data from Post-Routers and process data from all antennas for a subset of the frequency channels

• Beamformers provides both a wideband correlation function and narrower band spacecraft processing

• Synthesis filterbanks receive data from multiple beamformers and transforms them into a wider bandwidth time-domain signal

• Multiple Synthesis filterbanks provide multiple phased array outputs

• Output rate of Synthesis filterbanks can be scaled to meet required output bandwidth

Synthesis Filterbank

Beam 2

Beam 1

Beam K

PostRouter

PostRouter

PostRouter

BeamformerCorrelator





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Signal Processing Hardware for strawman 400 Antenna Array

23 Digitizer Racks

1 Antenna (2 bands) per Sampler module

6 Sampler & 1 Common module per chassis

67 Dig chassis per 400 Antenna Cluster

Each Dig chassis requires 100MHz, 1PPS, & 10Base-T

2 Antenna (2 bands) per Ant board

10 Ant & 4 Pre-Rtr boards per chassis

20 Ant chassis per 400 Antenna Cluster

Each Ant chassis requires 100MHz, & 1000Base-T

10 Antenna

Signal Proc Racks

8 Beam Former

Signal Proc Racks

1 Beam per Beam Former chassis

5 Post-Rtr, 8 Beam Former & 1 Synthesis board per BF chassis

16 Beamformer chassis per 400 Antenna Cluster

Each BF chassis requires 100MHz, & 1000Base-T


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BBA Correlator Summary

• Type: Connected Element• Output: Spectral Line, Continuum, and Combiner• Input BW and Digitization: Digitize at 1280 Msamples/sec with 8 bit samples. 500 MHz

effective bandwidth.• Special Processing: Feedback for Combiner processing. Manual RFI Signal processing to

identify RFI at X-Band (~8100 MHZ)• Spectral Channels: 512 Spectral Channels. Each channel is has 1.25 MHz bandwidth. Each

channel is sampled at 1.5625 MHz.• Integration time: Range of 10 millisecond to 50 seconds.• Dynamic Range: Input A/D has 8 bits dynamic range. Correlation of spectral channels for

phasing and radio astronomy uses 2 bit complex data for each channel. Combiner output is 6 bits complex per spectral channel and 8 bits real output for synthesized time domain signal.

• Scale of Construction: Pushing technology limits• Technology approach: Custom Hardware in ATCA chassis. FPGA’s with 2.5 Gigasample/sec

serial links, Embedded Real-time Linux• Current hardware scalable up to 16 antennas per ATCA chassis. Future enhancements to

architecture should enable scaling to 100’s of antennas.• The architecture is very flexible. The signal processing board contains 4 signal processing

FPGA’s with over 50000 logic cells, 232 18bit by 18 bit multipliers and 16 high speed serial I/O’s each. All FPGA’s interconnected to each other and across the ATCA backplane. Currently, the main limiting factor is the amount of data transported over the 2.5 Gs/sec serial IO links.

• Correlator uses an FX architecture with polyphase filtering and independent fringe phase correction for each channel.

Documents

RN - 1 03/08/05 National Aeronautics and Space Administration Jet Propulsion Laboratory California Institute of Technology Implementation of an Antenna