RISC

By Ryan Aldana

Agenda

• Brief Overview of RISC and CISC

• Features of RISC

• Instruction Pipeline

• Register Windowing and renaming

• Data Conflicts

• Branch Conflicts

Overview

• The world of microprocessors is divided into 2 parts– RISC– CISC

RISC

• Reduced Instruction Set Computer– Instruction set is reduced

• Excludes the instruction set that corresponds to higher level languages

– Instruction set is simpler– RISC has under 100 instructions– Examples of RISC:

• MIPS, SPARC, ARM

Applications of RISC (MIPS)

• “Sony Computer Entertainment Inc. (SCEI) has long relied on the MIPS® architecture, most notably for its PlayStation® family of products, including the 128-bit Emotion Engine® multimedia processor in the PlayStation® 2 computer entertainment system. In 2002, SCEI acquired a license for the MIPS64™ architecture.”text from http://www.mips.com/content/Ecosystem/Licensees/ProductCatalog/licensees

Other companies that use MIPS

• ATI• Motorola• NEC• Phillips• Sharp• Sony• Texas Instruments• Toshiba

– Info taken from http://www.mips.com/content/Ecosystem/Licensees/ProductCatalog/licensees

Side Note

• The first microprocessors had very simple instruction sets

CISC

• Complex Instruction Set Computers

• Instruction set is larger– Usually corresponds to statements in higher

level languages

• Instruction set is more complex

• Example of CISC– Pentium

Example of CISC

• Pentium

– Info and pics taken from http://www.intel.com/products/desktop/processors/pentium4HTXE/index.htm?iid=ipp_desk+proc_p4htxe&

Special note on Intel P4 HT+X

• Cache– “L3: 2MB, L2: 512KB, L1: 8KB”

– Info and pics taken from http://www.intel.com/products/desktop/processors/pentium4HTXE/index.htm?iid=ipp_desk+proc_p4htxe&

Overview and Side note

• RISC and CISC have opposite approaches– Each approach offers some advantage

• RISC and CISC differ in complexities of their instruction sets

CISC

• CISC has over 300 instructions– Some are used a lot

• Like the register move instructions

– Some are rarely used

In General

• The more instructions it has, the larger the propagation delay gets

Propagation Delay

• “The time it takes to transmit a signal from one place to another. Propagation delay is dependent solely on distance and two thirds the speed of light. Signals going through a wire or fiber generally travel at two thirds the speed of light. Contrast with nodal processing delay.”

• Info taken from http://www.techweb.com/encyclopedia/defineterm?term=PROPAGATIONDELAY&exact=1

Example

• CPU with 16 instructions– Uses a 4-16 decoder

• CPU with 32 instructions– Uses a 5-32 decoder

• This decoder needs more time to generate its outputs than the smaller one

• So why not use two 4-16 decoders?• Because two 4-16 decoders actually increase

propagation delay

Increase CPU speed

• Some designers wanted to make the CPU faster– To do that, they believed that they should

reduce the propagation delay• To do that, they eliminated the rarely used

instructions

Tradeoff

• Eliminating the instructions that corresponds to higher level language will force the processor to use more statements.– This will cause the processor to take more time

to process.

Common Features of RISC (10 of them)

• 1) Fixed length instructions– Every instruction has the same size bits

• 2) Limited Loading and Storing Instructions Access Memory – CISC can interact with the values in memory– RISC limits the interaction by placing the

values into a register first before interaction

Common Features of RISC

• 3)Fewer Addressing Modes– Certain modes degrade performance

• Indirect address mode– RISC has quicker addressing modes

• Register Direct addressing mode• Relative addressing mode

Common Features of RISC

• 4)Instruction Pipeline– RISC processors can execute one instruction

while fetching and decoding the next instruction

– The instruction pipeline breaks up the execution into stages

Common Features of RISC

• 5) Large Number of Registers– CISC uses their chip space for the control logic– RISC uses their chip space for more registers

• 6) Hardwired Control Unit– CISC is too complicated to implement a

hardwired control unit– RISC has a hardwired control unit for higher

clock rates

Common Features of RISC

• 7) Delayed loads and branches– This is used to avoid wasting time

• The RISC instruction pipeline encounters hazards during instructions that use a common operand

– Delayed loads and branches can avoid these hazards

Common Features of RISC

• 8) Speculative Execution of Instructions– The processor will execute the instruction

ahead of time but not save the value• If the processor was suppose to execute the

instruction, it will save the value• If not, it will discard the value• The Pentium Itanium Processor uses this

method

Common Features of RISC

• 9) Optimizing Compiler– An optimizing compiler can optimize the

instructions to facilitate delayed loads and branches

– It optimizes by rearranging the instructions to be executed

Common Features of RISC

• 10) Separate Instruction and Data Streams– This helps to avoid memory access conflicts

Instruction Pipeline

• Pipelined instructions break down the fetch-decode-execute and processes several instructions in parallel

• Instruction pipeline allows RISC processors to execute one instruction per clock cycle

Instruction Pipeline

• The pipeline is broken down into stages– For example:

• Stage 1 – fetch• Stage 2 – decode• Stage 3 – execute• Stage 4 – store value

• There is latency due to initialization

Instruction Pipeline

• The first RISC computer uses a four stage instruction pipeline

• The RISC II uses a three stage instruction pipeline

• The MIPS uses a five-stage instruction pipeline

• The fewer number of stages, the faster it is

Instruction Pipeline

• The breakdown of the instruction execution into stages reduces hardware– The fetch stage does not require the hardware

needed to decode the instruction– The decode stage does not access memory

because the fetch stage already accesses

Instruction Pipeline

• If a pipeline has four stages and each had a delay of 10ns, 10ns, 100ns, 40ns – The clock period must be a maximum of100ns

to account for the slowest stage – The designers would then have to split up stage

3 into two 50ns so that the clock cycle would go down to 50ns

Register Windowing and Renaming

• The RISC processor cannot access the registers all the time– Global Registers

• These registers are available to most RISC processors all the time

– Windowed• These registers are available at specific times

Register Windowing and Renaming

• A processor could have 4 frames of 8 registers each

• The Processor would have to keep track of which window is active and contains valid data– Window pointer register

• This keeps track of which window is active– Window mask register

• This keeps track of the window that contains valid data

Register Windowing and Renaming

• Most RISC processors have eight windows

• Register renaming allows the CPU to activate A group of windows at any given time

• Register windowing only allows SPECIFIC groups to be active at any given time

Data Conflicts

• Data conflicts occurs within a RISC pipeline when one instruction stores a result in a register and another instruction uses that value as an operand – In other words, the Instruction Pipeline

processes the instruction before it is supposed to

Data Conflicts Example

• Instruction:

• Incorrect:

• Correct:

Data Conflicts Example

• Possible Method:

• This reduces overall system performance

Data Conflicts Example

• Optimizing Compiler will reorder the instructions:

• But some don’t work:

Branch Conflicts Example

• Here, the code should jump to 10 after the third instruction, but instructions 4 and 5 are now already in the pipeline

Branch Conflicts Example

Conclusion

• RISC vs CISC, which is better?– There is no right or wrong answer– Each has some feature that is better than the

other