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Doctoral Thesis

Multi-Standard CMOS Baseband Filters for WirelessCommunication Receiver

Author(s): Blattmann, René M.

Publication Date: 2016

Permanent Link: https://doi.org/10.3929/ethz-a-010794506

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Multi-Standard CMOS Baseband Filters for WirelessCommunication Receiver

Diss. ETH No. 23706

Multi-Standard CMOSBaseband Filters for Wireless

Communication Receiver

A dissertation submitted toETH ZURICH

for the degree ofDoctor of Sciences

presented byRENE MATTHIAS BLATTMANN

MSc ETHborn March 18th, 1983

citizen of Oberrieden ZH, Switzerland

accepted on the recommendation ofProf. Dr. Qiuting Huang, examiner

Prof. Dr. Hans-Andrea Loeliger, co-examiner

2016

Abstract

Mobile broadband internet access has become widely accessible in thelast years and has pushed the popularity of smart phones, tablets andother mobile devices. Third generation (3G) networks are commonlyavailable and also fourth generation (4G) systems are growing. Secondgeneration (2G) networks are still used as fall-back technology or forwide area coverage. Therefore, radio handsets are required to supporta multitude of wireless communication standards.

The dynamic range requirements of cellular communication is toochallenging for direct A/D conversion at the antenna. Consequently,programmable analog receiver circuits are needed for the wide range ofcarrier frequencies and signal bandwidths to be covered. The design ofmulti-standard baseband filters for such wireless receivers is describedin this thesis.

Frequency and gain programmability, as well as power efficiencyand silicon area are key aspects for the baseband filter. A 6th orderactive-RC lowpass filter is found most suitable for the challengig re-quirements. The wide range of bandwiths is covered by an elaboratescaling scheme. Active-RC circuits are known to be power hungry,therefore a technique to compensate for reduced amplifier speed andgain during the filter design is presented.

Two multi-standard baseband filters have been implemented in a130 nm CMOS technology. The first design supports all 2G, 3G andLTE bandwidths with 8 discrete cutoff frequency settings and a lim-ited fine-tuning range. The cutoff frequency of the second design canbe tuned quasi-continuously between 156 kHz and 40 MHz. Therefore,this circuit can handle any signal bandwidth in the provided range,including 4G and WLAN standards.

v

Kurzfassung

Die Verfugbarkeit von mobilem Breitband-Internet hat in den letztenJahren stark zugenommen und hat die Popularitat von Smart Phones,Tablets und anderen mobilen Geraten gefordert. Mobilfunknetze derdritten Generation (3G) sind weit verbreitet und auch Systeme dervierten Generation (4G) werden ausgebaut. Netzwerke der zweitenGeneration (2G) werden jedoch immer noch als Absicherung oderzur Abdeckung von grossen Gebieten verwendet. Deshalb muss einMobilfunkgerat heutzutage verschiedenste Standards erfullen.

Die Anforderungen von Mobilfunkstandards an den Dynamikbe-reich des Empfangers sind zu hoch fur eine direkte A/D Wandlung ander Antenne. Folglich werden programmierbare analoge Empfanger-schaltungen benotigt um den grossen Bereich von Tragerfrequenzenund Signalbandbreiten abzudecken. Das Design von Multi-StandardBasisband-Filtern fur solche Empfanger ist Thema dieser Arbeit.

Programmierbarkeit, Stromverbrauch und Chipflache sind Schlus-selaspekte fur das Basisband-Filter. Es wurde festgestellt, dass einActive-RC Filter die hohen Anforderungen am besten erfullt. DerFrequenzbereich wird mit einer durchdachten Skalierung abgedeckt.Active-RC Schaltungen weisen generell einen hohen Stromverbrauchauf, deshalb wird eine Technik vorgestellt um den Einfluss von redu-zierter Verstarker-Bandbreite beim Filter-Design zu kompensieren.

Zwei Multi-Standard Basisband-Filter wurden in einer 130 nmCMOS Technologie implementiert. Das erste Design verfugt uber alle2G, 3G und LTE Bandbreiten durch 8 diskrete Frequenzschritte. DieGrenzfrequenz des zweiten Designs kann von 156 kHz bis 40 MHzeingestellt werden. Dadurch unterstutzt es eine beliebige Signalband-breite im verfugbaren Bereich, inklusive 4G und WLAN Standards.

vii

Acknowledgments

First of all, I would like to thank my supervisor Prof. Qiuting Huangfor giving me the opportunity to pursue my Ph.D. with the Analogand Mixed-Signal Group and for the experience I have gained duringthe years at IIS. I am also grateful to Prof. Hans-Andrea Loeliger forthe co-examination of my thesis.

I thank all the colleagues from IIS and ACP for the support duringmy Ph.D and the nice institute events. I will also keep good memoriesof the technical and non-technical discussions in the office with LucaBettini, Benjamin Sporrer, Schekeb Fateh, Philipp Schonle and XuHan.

I want to express my gratitude to all the people working in thebackground, especially the Microelectronics Design Center (DZ) andthe computer administration. Many thanks go to Thomas Kleier forthe support in the lab and Martin Lanz for packaging the chips.

Last but foremost, my deepest thanks go to my parents and tomy girlfriend Erika, the most important person in my life, who havealways supported and encouraged me.

Zurich, July 2016 Rene Blattmann

ix

Contents

Abstract v

Kurzfassung vii

Acknowledgments ix

1 Introduction 11.1 Mobile Communication Trends . . . . . . . . . . . . . 21.2 Wireless Channel . . . . . . . . . . . . . . . . . . . . . 41.3 Cellular Communication . . . . . . . . . . . . . . . . . 5

1.3.1 1G - Analog Cellular Communication . . . . . 61.3.2 2G - Digital Cellular Communication . . . . . . 71.3.3 3G - High-Speed Cellular Communication . . . 91.3.4 3.9G/4G - Broadband Cellular Communication 11

1.4 Wireless LAN . . . . . . . . . . . . . . . . . . . . . . . 141.5 Wireless Standards Overview . . . . . . . . . . . . . . 151.6 Scope of the Thesis . . . . . . . . . . . . . . . . . . . . 161.7 Organization of the Thesis . . . . . . . . . . . . . . . . 16

2 Wireless Communication Technology 192.1 The Road towards Software-Defined Radio . . . . . . . 20

2.1.1 Superheterodyne Architecture . . . . . . . . . . 202.1.2 Software Radio Vision . . . . . . . . . . . . . . 222.1.3 Direct Conversion Architecture . . . . . . . . . 232.1.4 Alternative Architectures . . . . . . . . . . . . 25

2.2 Receiver Requirements . . . . . . . . . . . . . . . . . . 27

xi

xii CONTENTS

2.2.1 Test Cases . . . . . . . . . . . . . . . . . . . . . 282.2.2 Block Level Requirements . . . . . . . . . . . . 352.2.3 LNA and Mixer . . . . . . . . . . . . . . . . . . 372.2.4 Baseband . . . . . . . . . . . . . . . . . . . . . 38

3 Filter Design 493.1 Prototype Filter . . . . . . . . . . . . . . . . . . . . . 50

3.1.1 Filter Order and Gain Strategy . . . . . . . . . 513.2 Circuit Technique . . . . . . . . . . . . . . . . . . . . . 523.3 Filter Architecture . . . . . . . . . . . . . . . . . . . . 54

3.3.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . 543.4 Gain Scaling . . . . . . . . . . . . . . . . . . . . . . . 613.5 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.6 Frequency Scaling . . . . . . . . . . . . . . . . . . . . 653.7 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.7.1 Programmable Resistor Array . . . . . . . . . . 673.7.2 Precision and Matching . . . . . . . . . . . . . 69

3.8 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . 733.8.1 Monotonicity . . . . . . . . . . . . . . . . . . . 743.8.2 Switch Sizing . . . . . . . . . . . . . . . . . . . 76

3.9 Process Variation . . . . . . . . . . . . . . . . . . . . . 783.9.1 RC Tuning . . . . . . . . . . . . . . . . . . . . 783.9.2 Offset Compensation . . . . . . . . . . . . . . . 79

4 Predistortion 814.1 Circuit non-Idealities . . . . . . . . . . . . . . . . . . . 82

4.1.1 Finite Amplifier Speed and Gain . . . . . . . . 824.1.2 Parasitic Capacitance . . . . . . . . . . . . . . 83

4.2 Compensation . . . . . . . . . . . . . . . . . . . . . . . 844.2.1 Integrator Phase Lag Compensation . . . . . . 844.2.2 Zero Compensation . . . . . . . . . . . . . . . . 85

4.3 Filter Predistortion . . . . . . . . . . . . . . . . . . . . 864.3.1 Predistortion Principle . . . . . . . . . . . . . . 864.3.2 Predistortion Algorithm . . . . . . . . . . . . . 91

4.4 Frequency Scaling with Predistortion . . . . . . . . . . 944.5 Gain Scaling with Predistortion . . . . . . . . . . . . . 954.6 Filter Architecture with Predistortion . . . . . . . . . 96

4.6.1 Sensitivity with non-ideal Amplifiers . . . . . . 96

CONTENTS xiii

4.6.2 Stability in Saturation . . . . . . . . . . . . . . 994.7 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.7.1 Architecture . . . . . . . . . . . . . . . . . . . 1014.7.2 Amplifier Programmability . . . . . . . . . . . 1074.7.3 Noise and DC Offset . . . . . . . . . . . . . . . 109

4.8 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . 1104.8.1 Differential Pair Non-Linearity . . . . . . . . . 1114.8.2 Second Stage Non-Linearity . . . . . . . . . . . 1124.8.3 Lossy Integrator Non-Linearity . . . . . . . . . 113

5 Implemented Multi-Standard Baseband Filters 1195.1 Multi-Standard 2G/3G/LTE BBF . . . . . . . . . . . 120

5.1.1 Architecture and Design . . . . . . . . . . . . . 1205.1.2 Characterization Results . . . . . . . . . . . . . 1215.1.3 Version with Non-Unit Resistors . . . . . . . . 1285.1.4 Characterization Summary . . . . . . . . . . . 130

5.2 Tunable BBF for 2G to 4G SDR . . . . . . . . . . . . 1325.2.1 Architecture and Design . . . . . . . . . . . . . 1325.2.2 Characterization Results . . . . . . . . . . . . . 1335.2.3 Characterization Summary . . . . . . . . . . . 137

6 Summary and Conclusion 139

A Receiver Requirements 145A.1 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . 145A.2 Intercept Points . . . . . . . . . . . . . . . . . . . . . . 146A.3 Reference Sensitivity with Transmitter Leakage . . . . 147A.4 Blocker Tolerance . . . . . . . . . . . . . . . . . . . . . 149A.5 Intermodulation . . . . . . . . . . . . . . . . . . . . . . 149A.6 Cascaded Blocks . . . . . . . . . . . . . . . . . . . . . 151

B Filter Sensitivity 153B.1 Leapfrog Filter Sensitivity . . . . . . . . . . . . . . . . 153B.2 Predistortion Sensitivity . . . . . . . . . . . . . . . . . 157

C Predistortion and Transistor Model 161C.1 Minimum GBP for Predistortion . . . . . . . . . . . . 161C.2 Practical GBP for Predistortion . . . . . . . . . . . . . 163

xiv CONTENTS

C.3 Predistortion with Combined Model . . . . . . . . . . 163C.4 Single Transistor Non-Linearity . . . . . . . . . . . . . 165C.5 MOSFET Hand Calculation Model . . . . . . . . . . . 166

Acronyms 169Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Bibliography 173

Curriculum Vitae 187

Chapter 1

Introduction

Wireless internet access has become very important in the modernsociety. Nowadays, it is completely normal to have high-speed internetconnection on the go. People can browse the web, read news, exchangein social media, play games and watch TV with their smart phonesand tablet computers everywhere. This shows that mobile phoneshave changed from a voice communication device to multi-functionallifestyle devices, connecting the user to the whole world. The ca-pabilities of modern smart phones are even comparable to personalcomputers just some years ago.

The immense growth in cellular data rates has been realized bydevelopments in various fields. Since the wireless spectrum for cellularcommunication is a scarce resource, it is very important to improvespectral efficiency. Code Division Multiplexing (CDM) or Orthogo-nal Frequency-Division Multiplexing (OFDM) is used in the 3rd and4th generation communication standards. Further increase in trans-mission rates can be achieved by larger channel bandwidth, higherorder modulation schemes like 64 Quadrature Amplitude Modulation(QAM) and Multiple-Input Multiple-Output (MIMO) operation. Im-proved process technology allows to implement the required digitalsignal processing circuits energy efficient for portable devices. Thegrowing number of subscribers are served with an increasing, thoughlimited number of frequency bands. This is nice from a user point ofview and fundamental from a service provider point of view, but very

1

2 CHAPTER 1. INTRODUCTION

demanding for the device manufacturer. Integrating various opera-tion bands and communication standards into a single device, whilekeeping cost and power consumption low, is an ongoing challenge.

Advanced process technology plays a major role in the history ofcellular communication since the mobile devices not only need to betechnically feasible, but also cost-efficient. The mobile communicationmarket has become a highly competitive multi-billion business. Highvolume fabrication of more and more integrated systems has loweredthe price of devices and accelerated the spread of mobile communica-tion all over the world. In 2013, the number of mobile subscriptionswas estimated to have reached more than 6.8 billions, corresponding toan average of 96.2 mobile-cellular subscriptions per 100 inhabitants [1].

1.1 Mobile Communication TrendsThe success story of cellular communication started slowly in the1980s, when the first analog systems where introduced. Ten yearslater, GSM was born as an international digital communication stan-dard that allowed roaming across different countries. It took anotherten years for the Third Generation (3G) networks to show up andstarting to focus on higher data-rates. Concurrent to the increasingpopularity of the internet, mobile communication systems began toshift from voice- to data-oriented systems. The recently introducedLong Term Evolution (LTE) standard consequently has a flat, IP-based network architecture.

Today, mobile cellular signal coverage reaches almost everyone onearth. However, only a part of the networks support broadband3G technology. Fig. 1.1 shows the strong growth of cellular com-munication, which has reached 96 subscriptions per 100 inhabitantsworld-wide, one third of them being broadband. The number ofwired internet connections is also steadily growing, but with muchlower slope and on a lower level. The number of fixed telephonesubscriptions in contrast is decreasing since more than 5 years. By theend of 2012, around 50% of the people on earth have been within reachof a 3G network [1]. But there is a significant difference in mobile-broadband subscriptions between developed countries with 74.8 anddeveloping countries with 19.8 subscriptions per 100 inhabitants at the

1.1. MOBILE COMMUNICATION TRENDS 3

2000 2002 2004 2006 2008 2010 2012 20140

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of subscriptions p

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100 inhabitants

Mobile−cellular telephone

Mobile−broadband

Fixed−telephone

Fixed−broadband

Figure 1.1: Development of world-wide telephone and internet sub-scriptions in the last ten years (estimate for 2012, 2013) [1].

end of 2013. Nevertheless, developing countries form a fast growingmarket, because mobile-broadband internet access is rather a substi-tution than a complement to fixed (wired) broadband connections.In these countries, Worldwide Interoperability for Microwave Access(WiMAX) is a significant competitor to cellular systems like UniversalMobile Telecommunications System (UMTS) and LTE. WiMAX wasspecifically developed for internet connectivity at places where nowired broadband internet is available. The global market share ofWiMAX is still small and not included in Fig. 1.1. Nevertheless,in some developing countries, about half of the wireless broadbandsubscriptions are WiMAX subscriptions.

Mobile data traffic is expected to grow by 66% per year in thenext 4 years, mostly driven by smartphones. By 2017, 4G technologyis predicted to account for 10% of mobile connections and 45% ofmobile data traffic [1].


1.2 Wireless ChannelReliable communication over a wireless channel is subject to physicalrestrictions. According to the Shannon-Hartley theorem, the channelcapacity C of a channel with Additive White Gaussian Noise (AWGN)is given by

C = B · log2

(1 + S

N

)(1.1)

where B is the bandwidth of the channel, S and N are the averagereceived signal and noise power over the bandwidth. For large Signal-to-Noise Ratio (SNR), the capacity is bandwidth-limited, i.e. propor-tional to the signal bandwidth and the logarithm of the SNR. If theSNR is small, the capacity is power-limited and becomes independentof the bandwidth.

The average received signal strength Pr decays as a power law ofthe distance d between the sender and the receiver [2]

Pr (d) = P0 ·(d0

d

)n(1.2)

where P0 is the average received power at a reference distance d0.The path loss exponent n depends on the obstacles between senderand receiver. In free space, the exponent is n=2. In urban areas, theattenuation is much stronger, the path loss exponent is typically in therange between 2 and 4 [2]. The maximum transmit power and cellularcommunication bandwidth are limited by the national exposure limitsand spectrum licensing. This fundamentally limits the achievable datarate of cellular communication systems.

Beside the slow fading effect of exponentially decreasing signalstrength, the wireless channel exhibits fast fading, also known assmall scale fading [2]. Fast fading is caused by interference of multipleversions of the same signal, arriving at different times at the receiverdue to reflections, scattering and diffraction. This can cause rapidfluctuations in signal strength over a small travel distance or shorttime interval. Multipath propagation also leads to Inter-Symbol Inter-ference (ISI) due to echoes. Random frequency modulation is anotherissue caused by varying Doppler shifts of the multipath signals

1.3. CELLULAR COMMUNICATION 5

1.3 Cellular CommunicationThe concept of cellular communication was introduced by AT&T BellLaboratories in the 1970s [3]. The geographical area to be covered isdivided into hexagonal cells, each served by one Base Station (BS).The Mobile Station (MS) can move freely and will automaticallyconnect to the BS with best signal quality. The available frequencyspectrum is limited, therefore several cells in a given coverage areawill use the same set of frequencies. This frequency reuse results inco-channel interference. In a regular hexagonal cell grid, the numberof cells per cluster, i.e. the number of frequency sets can be N=1, 3, 4,7, 9, ... [3]. The co-channel reuse ratio Q is the ratio of the distance Dbetween the nearest co-channel cells to the cell radius R and is relatedto the number of cells per cluster:

Q = D

R=√

3N (1.3)

In a hexagonal grid, there are six nearest co-channel cells. The result-ing Signal-to-Interference Ratio (SIR) for a MS at the cell edge canbe approximated as

SIR = R−n

6D−n = 16 (3N)

n2 (1.4)

Assuming a path loss exponent of n = 4 results in SIR ≈ 11 dBfor N = 3 and SIR ≈ 19 dB for N = 7, severely limiting the linkperformance. A larger cluster size would increase the SIR, but this isnot suitable, because it would entail a reduction of capacity and leadto a lower overall system performance. The worst case of six nearestco-channel cells transmitting at full power on the same frequency canbe avoided by cell sectoring and smart power control.

Interferences are not only created by neighboring cells, adjacentchannel interference within one cell can also be very harmful. If notsufficiently attenuated, frequencies close to the wanted channel cansaturate the receiver just as any other blocking signal. Even if theadjacent channel does not saturate the receiver, imperfections maycause the adjacent channels to leak into the wanted channel. This isespecially critical in near-far situations, where a weak signal should bereceived while a strong adjacent signal is present. This is for example


the case when a MS at the cell edge receives the weak signal fromthe BS while another MS nearby transmits at high power on theadjacent channel to the same BS. Adjacent channel interference can bemitigated by proper channel allocation schemes and transmit powercontrol. The frequency clusters can be defined such that the minimumspacing between two adjacent channels within one cell is equal to thecluster size N. RF-filtering can only be used in Frequency DivisionMultiple Access (FDMA) systems to suppress the transmit signal ofa nearby device. In Code Division Multiple Access (CDMA) systems,all MSs use the same channel frequency which can be very challengingfor the BS on the uplink, if the signals from a near MS and a far MSshould be received concurrently.

1.3.1 1G - Analog Cellular Communication

The first cellular system was launched 1979 in Japan for the Tokyometropolitan region. It was the first cellular network supportingautomatic connection setup and handover and consisted of 88 cellsites. The system operated at frequencies of 400 MHz and 800 MHz.In the 1980s, cellular systems emerged all over the world. The NordicMobile Telephony (NMT) opened for service in 1981 in Sweden andNorway. The system started in the 450 MHz band and was laterextended to the 900 MHz band. The NMT network was used invarious countries in northern Europe and even supported internationalroaming. In the USA the Advanced Mobile Phone System (AMPS)was commercially launched in 1983 and operated in the 850 MHzband.

All First Generation (1G) systems were based on analog frequencymodulation and very weak in terms of security. The lack of en-cryption made the services vulnerable to eavesdropping and cloning(the identity of a registered MS was imitated to make calls withoutpaying). FDMA was used to separate the different users, leading tovery inefficient use of the available spectrum. Due to their heavyweight and low battery lifetime, 1G systems were mainly used ascarphones.


1.3.2 2G - Digital Cellular Communication

The Second Generation (2G) cellular networks fixed the most impor-tant drawbacks of 1G systems. Cellular communication was globallystandardized, digital encryption allowed secure communication andthe available spectrum was used more efficiently to offer service toa larger number of customers concurrently. Additionally, first basicdata services were introduced.

Global System for Mobile Communication (GSM) is the most pop-ular communication technology of the last 20 years and was originallyinitiated by the European Conference of Postal and Telecommunica-tions administration (CEPT) which formed the Groupe Special Mobile(GSM) to develop a new European digital cellular voice telephonystandard. In 1991, GSM was launched in Finland, operating in the900 MHz band with channels of 200 kHz bandwidth. A few yearslater GSM was widely used across Europe and became the dominant2G cellular technology all over the world. GSM is also operated inother frequency bands as DCS (Digital Cellular System, 1800 MHz)and PCS (Personal Communication System, 1900 MHz). In the USA,Digital AMPS (also known as D-AMPS, IS-54 or US-TDMA) waslaunched in 1991 and prevalent during the 1990s. D-AMPS used thesame carrier frequencies as AMPS, allowing a smooth transition todigital systems. Like GSM, D-AMPS used a Time Division MultipleAccess (TDMA) technique to increase spectral efficiency. In 1995,cdmaOne (also called IS-95) was introduced in the USA. cdmaOne isa CDMA technology operating in the 1900 MHz band with 1.25 MHzchannel bandwidth and directly competing with D-AMPS. Due tothe higher capacity of the CDMA based system, cdmaOne slowlyreplaced D-AMPS, which was gradually deactivated by the operatorsin the years after 2000. Personal Digital Cellular (PDC) was anotherTDMA system exclusively used in Japan since 1993. PDC operatedin the 800 MHz and 1500 MHz bands and was slowly replaced by 3Gtechnologies and finally shut down in 2012.

The primary objective of 2G systems was to provide voice tele-phony. While the GSM standard contained Short Messaging Service(SMS) from the beginning, most early GSM mobile phones were notable to send SMS text messages. In the first years, the use of SMS in-creased only slowly due to billing issues and restrictions by operators.


After 2000, SMS message volume has shown an immense growth as itoffered a cost effective communication alternative to phone calls. Onlyin recent years, SMS volume growth has slowed down because of thecheaper, IP-based instant messaging service applications for modernsmartphones. Fig. 1.2 illustrates the development of text messagessent world-wide per day. The number of SMS text messages stagnateswhile instant messaging has already surpassed SMS and is predictedto grow further rapidly.

2002 2004 2006 2008 2010 2012 2014 2016 20180

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s]

SMS

Instant Messaging

Figure 1.2: Number of SMS and instant text messages sent world-wideper day and forecast for 2015 and 2017 [4].

The emerging demand for data-services could not be handled bythe slow circuit switched connections of GSM. Therefore General PacketRadio Service (GPRS) was introduced in 2000 to improve the datarates of GSM. The packet switched data service offers a theoreticalmaximum data rate of 86 kbps if 4 time slots are used. In practice avalue of up to 40 kbps is achievable under normal conditions. SinceGPRS significantly increases the data rate of GSM, it is often referredas a 2.5G technology. Further improvement was introduced by thelaunch of Enhanced Data rates for GSM Evolution (EDGE) in 2003.Using 8 PSK instead of Gaussian Minimum Shift Keying (GMSK)as modulation scheme, allowed a theoretical maximum throughput of237 kbps, which is almost a three-fold increase compared to GPRS.


With the success of 3G systems, EDGE was mainly used as a fallbacktechnology in areas without 3G coverage. Evolved EDGE (E-EDGE)was developed around 2006 to reduce the gap of increasing 3G datarates and the 2G fallback system. The most important new featuresto increase the speed are 32 QAM modulation scheme and DownlinkDual Carrier (DLDC) to receive two carriers concurrently. E-EDGEsupports data rates up to 1.18 Mbps when 6 time slots are usedwith DLDC. Receiver diversity improves the signal quality in low-SNR scenarios and the possibility of simultaneous transmission andreception avoids sacrificing time slots for switching between the twomodes. Despite the great improvement of E-EDGE compared toEDGE, operators have only poorly adopted this technology. Invest-ments are preferably made to improve 3G infrastructure and roll outFourth Generation (4G) networks.

1.3.3 3G - High-Speed Cellular CommunicationWhile GSM was developed and deployed, the International Telecom-munication Union (ITU) was already thinking of the next genera-tion of cellular communication. The IMT-2000 (International MobileTelecommunications-2000) standard defines the requirements for a 3Gwireless communication system. It aims to provide internationallycompatible wireless voice telephony and data services with up to2 Mbps. New frequency bands increase capacity and target globaloperation. The minimum required data rate for 3G system is 144 kbps,therefore even EDGE, which is often referred as a 2.75G technologyfulfills the IMT-2000 requirements.

The ITU defines requirements but does not develop the actualstandards. The 3rd Generation Partnership Project (3GPP) [5] wasformed to develop a cellular system for IMT-2000, based on GSMspecifications. 3GPP is a collaboration of standard-developing orga-nizations from all over the world. In 2000, 3GPP has also adopted thestandardization of GSM and its enhancements. The Universal MobileTelecommunications System (UMTS or Universal Terrestrial RadioAccess, UTRA) is the third generation successor of GSM. WidebandCDMA (WCDMA), the FDD variant of UMTS, was commerciallylaunched in 2001 and uses the same carrier frequencies as GSM andan additional band at 2.1 GHz. It employs 5 MHz channels with


QPSK modulation and supports a data rate of 384 kbps in pedestrianenvironment and up to 2 Mbps in low range distance. WCDMA cancarry over 100 simultaneous voice calls per channel. Time DivisionSynchronous CDMA (TD-SCDMA) is the TDD variant of UMTS. Itis operated at 1.9 GHz/2.0 GHz with a channel bandwidth of 1.6 MHzand therefore supports a lower number of simultaneous voice calls perchannel than WCDMA. TD-SCDMA offers similar maximum datarates as WCDMA thanks to smaller spreading factors. TD-SCDMA isfavorably used in China while WCDMA is the 3G technology of choicein Europe. 3GPP has continuously improved the UMTS standardintroducing High Speed Downlink/ Uplink Packet Access (HSDPA/HSUPA), together named HSPA and generally classified as a 3.5Gtechnology. First commercial WCDMA networks supporting HSDPAand HSUPA have been launched in 2005 and 2007 respectively. HS-DPA enables data rates up to 14.4 Mbps. HSPA+, launched in 2009,boosts the speed of the WCDMA networks to 28 Mbps using 2x2MIMO with 16 QAM modulation. Dual carrier operation provideseven 84 Mbps with 64 QAM modulation. The rapid growth of globalcellular data traffic is shown in Fig. 1.3 in comparison with onlyslightly increasing voice traffic in the last 4 years.

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q30

10

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Glo

bal daily

tra

ffic

[P

eta

Byte

s]

2010 2011 2012 2013

Voice

Data

Figure 1.3: Global daily data and voice traffic (uplink + downlink) [6].


In the USA, where GSM was not predominant, the developmentof 3G networks was based on the cdmaOne technology. 3GPP2 [7] isa collaboration of organizations from North America, Japan, Chinaand Korea, similar to the 3GPP and specified the CDMA2000 (alsoCDMA2k) standard as a competitor to the UMTS technology. SinceCDMA2000 is based on cdmaOne, it uses the same channel band-width of 1.25 MHz. Supporting up to 35 simultaneous phone calls,it doubles the capacity compared to its predecessor. It also enablesdata rates up to 153 kbps in both directions, uplink and downlink.CDMA2000 has evolved as Evolution Data Optimized (EV-DO), sup-porting downlink data rates up to 3.1 Mbps in Revision A and hasbeen commercially launched in 2002 in Korea. Because CDMA2000EV-DO is a data only standard, IP-based telephony or a fall-back toCDMA2000 has to be used for phone calls. The channel bandwidthof 1.25 MHz fundamentally limits achievable data rates. Thereforemulticarrier operation was introduced 2006 in Revision B, enablingup to 14.7 Mbps with three carriers and higher order modulationschemes. A further software upgrade called EV-DO Advanced bringsa number of improvements for the user as well as the operator andsupports data rates up to 19.6 Mbps using four aggregated carriers.

1.3.4 3.9G/4G - Broadband Cellular Communica-tion

In 2010, the ITU has specified the requirements for 4G communicationsystems, called IMT-Advanced, similar to the IMT-2000 definition.Key requirements for 4G systems are peak data rates of 1 Gbps forlow mobility (10 km/h) and 100 Mbps for high mobility (350 km/h)scenarios. The increasing data rates will be required for the immensegrowth forecast in mobile data traffic as shown in Fig. 1.4.

3GPP has developed Evolved UTRA (E-UTRA), known as LTEas successor of the UMTS technology in 2007. LTE does not reachthe needed data rate to be qualified as a 4G network and is thereforereferred to as a 3.9G system. Nevertheless, LTE is often marketed asa 4G technology to emphasize the improvements compared to basic3G standards. LTE uses OFDM and is designed very flexible. Itsupports Frequency-Division Duplex (FDD) and Time-Division Du-plex (TDD) operation and channel bandwidths between 1.4 MHz and


2013 2014 2015 2016 2017 20180

2

4

6

8

10

12

14

16

18

Exabyte

per

Month

Mobile Video

Mobile Web/Data

Mobile M2M

Mobile File Sharing

Figure 1.4: Global monthly data traffic forecast by application [8].

20 MHz. A large variety of operation bands between 450 MHz and3.8 GHz have been defined. Operation bands of primary interest arethe ones already used for 2G/3G systems and the 2.6 GHz band. LTEuses a packet switched data network and does not only offer higherthroughput, but also lower latency, which is gaining in importance formany services. Downlink data rates up to 100 Mbps (no MIMO) and300 Mbps (4x4 MIMO) can be achieved with 64 QAM modulation and20 MHz channel bandwidth. The first commercial LTE networks werelaunched 2009 in Scandinavia. For voice calls, early implementationsfall back to a circuit switched 2G or 3G technology. Voice over LTE(VoLTE) is an approach under development to include voice service inthe LTE data flow and to ensure seamless handover to circuit switchednetworks in case of poor LTE signal quality. Alternatively, IP-basedtelephony can be used on a software level.

LTE Advanced, which basically aggregates several LTE channels,was defined in 2011 and is a true 4G technology. With same mobilityrequirements as for LTE, the LTE Advanced system should supportpeak data rates up to 1 Gbps in downlink direction and 500 Mbpsin uplink direction. Several scenarios for aggregated LTE carriers(not necessarily of the same channel bandwidth) will be defined. The


aggregation can be intra-band (contiguous or non-contiguous) or inter-band, in different operation bands. A maximum signal bandwidth of100 MHz will be achieved using 5 aggregated LTE signals of 20 MHz.Further modifications on system level will improve spectral efficiencyand latency.

The only strong competitor to LTE in the race towards 4G commu-nication is Mobile WiMAX, an OFDM system with TDD operation.Basic WiMAX as defined 2004 by the WiMAX Forum [9] is basedon the IEEE 802.16d (also referred to as 802.16-2004) standard andwas designed as an all-IP network to provide last mile wireless broad-band internet access as an alternative to wired broadband internet.Connection can be brought to several devices by Wireless Local AreaNetwork (WLAN) functionality of the WiMAX device. Basic WiMAXis not a cellular technology because all stations are fixed in locationand no handover procedure is specified. In 2005, Mobile WiMAX(based on 802.16e) introduced mobility and handover to WiMAX.Offering cheap broadband wireless internet access for mobile devices,Mobile WiMAX became a direct competitor to 3G systems. Thisactually triggered the 3GPP to develop LTE. The 802.16 standardsare very flexible with carrier frequencies between 2 GHz and 11 GHzand channel bandwidths ranging from 1.25 MHz to 20 MHz. Butonly a limited set thereof was defined to be used for WiMAX. MobileWiMAX supports channel bandwidth up to 10 MHz and is operatedat licensed frequencies of 2.3 GHz, 2.5 GHz and 3.5 GHz. A peakdownlink data rate of 37 Mbps can be achieved with 64 QAM mod-ulation, 2x2 MIMO and assuming a DL/UL ratio of 5:3. Due to itslower coverage and speed (up to 120 km/h) requirements compared toLTE, Mobile WiMAX is rather classified as a Wireless MetropolitanArea Network (WMAN) than a cellular network.

WiMAX Advanced (also called Mobile WiMAX 2) is based onthe 802.16m standard specified in 2011 and targets to fulfill the 4Grequirements. The measures to reach this goal are very similar as forLTE Advanced. WiMAX Advanced makes use of 64 QAM, 8x8 MIMOand aggregation of carriers with bandwidth of 20 MHz and more.Commercial availability of networks supporting 4G peak data ratesdoes not only depend on the availability of devices, but also on theavailability of frequency spectrum owned by the operator. This holdsfor WiMAX Advanced as well as for LTE Advanced and first real


networks are likely to use intra-band aggregated spectrum of up to40 MHz.

Ultra Mobile Broadband (UMB) was intended to become the 4Gsuccessor of CDMA2000. The standard is not expected to be deployedin large scale, because UMB’s lead sponsor Qualcomm has stoppedUMB development in 2008 in favor of the LTE technology.

1.4 Wireless LAN

WLAN has become a popular alternative to wired Local Area Network(LAN) for internet connectivity at home and at public places. Easeof installation and high data rates offer a good user experience forinternet access in a low mobility environment. The first release of theIEEE 802.11 family (also marketed under the brand name Wi-Fi) in1997, specified a wireless link using spread spectrum modulation with20 MHz channel bandwidth and data rates up to 2 Mbps in the unli-censed 2.4 GHz Industrial, Scientific and Medical (ISM) radio band.Version 802.11b (1999) improved the data rate to 11 Mbps and 802.11gintroduced OFDM based transmission in 2003 with throughput up to54 Mbps and full backwards compatibility. Due to the high data rateand fast availability of commercial products, 802.11g became the mostpopular standard in wireless networks.

WLAN in the 2.4 GHz band is experiencing interference of otherdevices operating in the same ISM band as Bluetooth devices, mi-crowave ovens or cordless phones. Already 1999, the 5 GHz band(operating at 5.8 GHz) was specified for WLAN operation with datarates up to 54 Mbps (802.11a). This was a welcome extension ofwireless spectrum as the 2.4 GHz band got heavily crowded withincreasing popularity of WLAN. The major drawback of the highercarrier frequency is the reduced coverage due to lower penetrationof the signal through walls. 2009, support of MIMO for furtherthroughput enhancement was introduced in 802.11n. So far, channelbandwidth was fixed to 20 MHz, setting a basic limit to achievabledata rates. 802.11ac was approved in January 2014 and providesseveral measures for high-speed data transmission in the 5 GHz band.

1.5. WIRELESS STANDARDS OVERVIEW 15

Channel bandwidth up to 80 MHz (mandatory) or 160 MHz (op-tional), up to 256 QAM modulation and more spatial streams forMIMO allow for data-rates up to 867 Mbps.

1.5 Wireless Standards OverviewThe carrier frequencies and channel bandwidths of the previouslypresented wireless cellular and non-cellular standards are summarizedin Fig. 1.5. A wide range of carrier frequencies between 450 MHzand 5.8 GHz are used. The operation bands around 800 MHz areparticularly interesting for long-range communication due to lowerattenuation compared to higher carrier frequencies. But more cus-tomers can be served with high data rates in operation bands near2 GHz or 3.5 GHz, because wider spectrum is available. WLAN at5.8 GHz falls a bit apart, but offers the potential of using very highchannel bandwidths for high-speed data transfer.

Figure 1.5: Wireless communication standards overview.


1.6 Scope of the ThesisThe aim of this thesis is the design of a multi-standard basebandfilter for a wireless communication receiver. The focus is on thearea and power efficient implementation of a highly flexible filter tosupport all wireless 2G, 3G and 4G communication standards. Filterrequirements are derived from the standard specifications and thecircuit architecture is chosen accordingly. A major part of the thesisis dedicated to the impact of amplifier non-idealities and the measuresto compensate for them. Two prototype circuits have been fabricatedin a 130 nm CMOS technology to demonstrate the proposed concepts.

1.7 Organization of the ThesisChapter 2: Wireless Communication Technology presents theevolution of wireless communication towards the software defined ra-dio concept. Different approaches for receiver architectures are shown.Further, receiver requirements are derived from standard documentsand broken down into block-level specifications. Obviously the maininterest lies on the requirements for the baseband filter.

Chapter 3: Filter Design discusses the basic design of the filterimplementation. It is shown why an active-RC implementation isbest suited for cellular applications and the architecture is discussedin detail. A sensitivity analysis highlights that the superior immunityto component variation of the leapfrog architecture fades away withreduced amplifier speed. Dominant noise sources are identified todefine the maximum impedance level. The frequency scaling scheme ispresented to implement the required 267-fold cutoff frequency tuningrange from 150 kHz to 40 MHz.

Chapter 4: Predistortion examines the impact of circuit non-idealities on the filter transfer function. Main contributors are finiteamplifier gain and speed as well as parasitic capacitances. Thesenon-idealities can be compensated on amplifier or filter level. Filtertransfer function predistortion is considered the best approach becauseit does not introduce additional components and it is suitable for

1.7. ORGANIZATION OF THE THESIS 17

gain and frequency scaling. The implementation of an appropriateprogrammable amplifier and the associated non-linearity is discussedat the end of the chapter.

Chapter 5: Implemented Multi-Standard Baseband Filterspresents two design examples implemented in a 130 nm CMOS tech-nology. A first implementation supports 2G, 3G and LTE wirelesscommunication standards by 8 discrete frequency settings and a lim-ited fine-tuning range. A second implementation offers a quasi-continuouslycutoff frequency tuning between 156 kHz and 40 MHz with a resolu-tions below 3%.Chapter 6: Summary and Conclusion summarizes the thesis andgives concluding comments on the presented concept.

Chapter 2

WirelessCommunicationTechnology

The evolution of cellular devices has gone hand in hand with thecommunication standards. Some of the innovations could even only berealized because of the availability of new technologies and increaseddigital signal processing power. The growing number of differentstandards is a challenge for device manufacturers because the devicesshould still be small, light-weight as well as power and cost efficient.Older standards like GSM can not simply be shut down because theyare still used as fallback technology and provide excellent coverage forphone calls. For mobile data transmission in contrast, the throughputof 2G systems is hardly sufficient nowadays. This shows that thedifferent communication standards are tailored to specific needs andnot only compete, but also complement one another. In the firstsection of this chapter, it is shown how the challenge of supportingmany standards can be addressed in the receiver circuit.

The presence of strong interferers while receiving a weak signalleads to large dynamic range requirements for cellular communication.The resulting demands in terms of sensitivity, linearity and selectivityare derived from standard documents and broken down into block level

19

20 CHAPTER 2. WIRELESS COMM. TECHNOLOGY

specifications. The detailed requirements for the baseband filter to bedesigned in this thesis are presented at the end of the chapter.

2.1 The Road towards Software-DefinedRadio

All wireless communication standards share the same basic principle,given by the physics of radio transmission. The transmitter modulatesthe information on a carrier signal and the receiver gets back theinformation from the distorted Radio Frequency (RF) signal. Thereare four basic operations the receiver has to accomplish: filteringof undesired signals collected by the antenna, amplification of thewanted signal, down-conversion from carrier frequency to basebandand analog-to-digital conversion. The order of these operations ispart or the receiver circuit design and depends on the communicationstandard to be supported and the available technology.

2.1.1 Superheterodyne Architecture1G and 2G mobile communication was focused on phone calls withnarrow signal bandwidth and a small set of operation bands. Thissetup is well suited to a two step down-conversion approach with afixed intermediate frequency – the superheterodyne architecture. Thesuperheterodyne transceiver architecture was invented already duringWorld War I by Edwin Armstrong. It became the dominant architec-ture for mobile phones for many decades, because mobile devices hadto support only one communication standard at the beginning of thecellular era. Fixed carrier frequency and channel bandwidth allowedthe transceiver to be built by a large set of discrete componentssoldered on the Printed Circuit Board (PCB).

Fig. 2.1 shows the block diagram of a modern superheterodynereceiver. The incoming signal from the antenna is (optionally) filteredby an off-chip RF filter, amplified by a RF Low-Noise Amplifier (LNA)and subsequently down-converted to a fixed intermediate frequency(IF). The local oscillator frequency is adjusted to the carrier frequencyof the input signal such that the mixer output signal is always at theIF frequency. Signal filtering and amplification is mainly done at IF

2.1. THE ROAD TOWARDS SDR 21

Figure 2.1: Superheterodyne receiver block diagram.

before demodulation. Demodulation can be implemented as shownby a second mixer that converts the signal to baseband for furtherprocessing by the Base Band Filter (BBF) or directly in the digitaldomain if the Analog-to-Digital Converter (ADC) is operating at IF.The main advantage of the superheterodyne receiver is the fixed andrelatively low frequency of the IF signal. This enables efficient im-plementation of high-performance (off-chip) filters and amplificationcircuits at IF.

The success story of the superheterodyne architecture was notbased on a lack of alternatives, there was just no reason to use anotherarchitecture as long as the number of frequency bands and commu-nication standards was low. But in the last years, the number ofcellular standards steadily increased and customers ask for mobiledevices seamlessly working all over the globe. Each standard wasdefined to fit the needs at that time, so there is not a single “best”standard to be used exclusively. It is rather desirable to have differentcommunication standards that can be used depending on the needs.Serving many users with phone calls over large distances is completelydifferent from bandwidth hungry high-speed internet connections in ashort range. Therefore, a modern cellular device needs to support amultitude of communication standards. The straight-forward methodfor multi-band and/or multi-mode operation is to place several analogfront-ends on the device, either within one chip or even several chips onthe PCB. While this strategy works fine for a few front-ends in parallel,it is obvious that it will lead to unacceptable cost for an increasingnumber of standards. And fabrication cost is particularly importantin the highly competitive market of mobile communication devices.Therefore device manufacturers continuously try to reduce the numberof components to be soldered on the PCB. As a consequence, the


superheterodyne architecture has been questioned because it requiresexternal IF filters. In the meantime, reconfigurable RF transceiversare widely used for cellular devices [10–13].

2.1.2 Software Radio VisionAlready in 1993, shortly after the commercial launch of GSM, Mi-tola [14] presented his vision of Software Radio (SR). The idea is toperform the analog-to-digital conversion first, in order to shift all thesignal processing from dedicated hardware components to softwarecomputation algorithms. The intention of the concept was to reducethe time to incorporate new communication services into a product.The ideal SR is shown in Fig. 2.2(a), the signal is converted into thedigital domain at RF frequency, directly after the antenna. This leadsto extremely high requirements on the ADC and the Digital-to-AnalogConverter (DAC), rendering the realization of the concept impossible.

ADC

DAC

(a) Ideal software radio

ADC

DAC

(b) Modified variant of the ideal SR

Figure 2.2: Software radio block diagrams

The dynamic range of the ADC and the DAC can be reduced toa more reasonable order of magnitude if a LNA and an anti-aliasingfilter is placed in front of the ADC and the output signal of the DAC isprocessed by a reconstruction filter and a Power Amplifier (PA) (seeFig. 2.2(b)). With this modified setup, circuits can be realized forservices with rather low carrier frequencies like FM broadcast radio[15]. Also Cognitive Radio (CR) applications [16, 17] may be feasiblein some unlicensed frequency bands. CR are intelligent radio devices,selecting the communication parameters of the wireless interface inan opportunistic way, according to the users needs. Like this, theoccupancy of the available spectrum can be maximized.


The sampling of the input signal at RF frequency still is an issue forcarrier frequencies of several GHz, as used in cellular communicationand WLANs. In the case of the ideal SR, the required Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC is in the order of135 dB [18]. With the modified setup, including a minimal set ofanalog RF circuits, assuming a LNA gain of 15 dB and that in-bandblockers are limiting, still 100 dB of ADC dynamic range is required.The power consumption of the ADC should be in the order of 100 mWfor compact and light-weight handheld devices. Recently publishedADCs [19] reach a SNDR of 33.8 dB with an input signal bandwidthof 5 GHz and power consumption of 32 mW [20] or 69 dB SNDR witha signal bandwidth of 500 MHz and power consumption of 1.2 W [21].Obviously, the performance of the presented circuits falls short of therequirements by several orders of magnitude.

Consequently, the conversion of the signal into the digital domainsets a fundamental limit to the concept of SR. The ideal SR pro-cesses the full RF spectrum in the digital domain for maximal systemflexibility, even if the actual information is transmitted with limitedbandwidth on a specific carrier frequency. The same information canbe gathered if the system can receive a signal of arbitrary bandwidthat any carrier frequency. This is the concept of Software DefinedRadio (SDR) [22], where it is not a priori specified which part of thesignal processing is realized in hardware or software. To cover all thewireless standards presented in Sec. 1.5, a SDR needs to be able toreceive a signal of any bandwidth between 200 kHz and 160 MHz inany band from 400 MHz to 6 GHz.

2.1.3 Direct Conversion ArchitectureThe major drawback of the superheterodyne architecture is the costrelated to the off-chip filters required at IF. Using only one frequencyconversion operation directly to baseband yields the direct conversionarchitecture shown in Fig. 2.3, which is the most popular approach torealize a SDR because of its flexibility [23–28].

The Antenna Switch Module (ASM) connects the antenna portto the selected duplexer module for FDD operation. In the case ofTDD operation, a RF Surface Acoustic Wave (SAW) filter replacesthe duplexer. The RF IC may even be directly connected to the


0°

-90°

0°

-90°

Figure 2.3: Direct conversion transceiver block diagram.

ASM. For frequency agility, the LNA has to be wideband or tunableand the Local Oscillator (LO) always needs to track the carrier fre-quency. Usually a bank of duplexers is used to support simultaneousreceive and transmit operation in different bands. Ideally, the bank ofduplexers would be replace by a wideband circulator that passes thesignal of antenna, receive path and transmit path in a circular orderonly from one port to the next [29, 30]. Mixer-first receivers directlyconnect the input of the RF IC to the mixer input. This enablesblocker filtering at the receiver input at the cost of increased NoiseFigure (NF) due to the lack of LNA gain [26, 31, 32]. The PA can beimplemented as a reconfigurable circuit or a bank of fixed-frequencydevices. The receive BBF cutoff frequency and gain are adjusted tothe signal bandwidth and power level. The ADC is preferably includedin the Digital Front-End (DFE) of the RF IC and not in the digitalBase-Band (BB) IC. This allows the BB IC with purely digital signalprocessing to be implemented in the most recent CMOS technology.Overall system design also benefits if the performance of the ADC iswell known and a standardized interface such as DigRF [33] is usedbetween the RF IC and the BB IC. Furthermore, imperfections of theanalog circuits like DC offset, I/Q imbalance and magnitude or groupdelay ripple may be compensated by the DFE.


2.1.4 Alternative Architectures

The superheterodyne and direct conversion architectures are domi-nating the cellular receiver circuits. Implementations of these two ar-chitectures show slight variation in the order of filtering, amplificationand down-conversion, but the analog-to-digital conversion is always atthe end of the chain. Moving the ADC towards the front strongly in-creases the demands on the ADC performance. Therefore, alternativearchitectures struggle with the challenging requirements of cellularcommunication. Additionally, circuits for commercial products needto be low-cost and power efficient, but support high dynamic range,carrier frequency agility and increasing signal bandwidth for moderncommunication standards.

Discrete-Time Filtering

Discrete-Time (DT) analog filtering is the most promising approachto bring digital signal processing closer to the antenna. DT filteringis well suited for SDRs due to clock frequency programmability androbustness against Process-Voltage-Temperature (PVT) variations.Charge sampling is realized by integration of the input current duringa repeating time window [34]. The resulting transfer function is asinc filter and provides inherent anti-aliasing. If the signal is sam-pled at baseband frequency after the mixer, additional Continuous-Time (CT) filtering is required to attenuate blocking signals, be-cause of the flat roll-off of the sinc filter [35]. But this is undesiredsince the purpuse of DT filtering is to replace CT circuits. Ad-ditional CT filters can only avoided if the sampling is performedat RF, before or simultaneously with the down-conversion. Thisneeds a very high clock frequency, consequently DT architecturesdirectly benefit from technology scaling. Because of noise folding, DTreceivers often suffer from high NF [36, 37] or support only narrow-band signals [38]. Best reported NFs between 5 dB and 6 dB areachieved in [34] and may be just sufficient for the targeted TDDcommunication standards GSM and WiMAX, but not for WCDMA,where transmitter leakage degrades the NF. Fig. 2.4 shows a blockdiagram of the receiver architecture. The LNA with variable gainis required for signal amplification before sampling the RF signal


at Nyquist rate. A bandpass FIR (Finite Impulse Response) filterreduces aliasing and noise folding and decimates the signal by a factorof 6 by means of subsampling. The signal is further processed by aseries of IIR (Infinite Impulse Response) filters and FIR decimationfilters with programmable gain. Finally, the sampling frequency atthe input of the ADC is 20 MHz for the case of a 5 MHz LTEsignal at 1.8 GHz. A drawback of this DT architecture is that theexact sampling frequency depends on the carrier frequency of theobserved channel, complicating the interfacing to the digital basebandIC. Despite the improvement compared to previous publications, theresulting performance is still not competitive to CT direct conversionarchitectures [28] and will fail the reference sensitivity test in FDDoperation due to transmitter leakage. It is also questionable whetherDT systems in general will pass spurious response testing which isabsolutely necessary for commercial applications.

Figure 2.4: Discrete-Time receiver architecture for cellular communi-cation [34].

Direct ∆Σ

The direct delta-sigma receiver is based on a direct conversion archi-tecture [39, 40]. A low-noise transconductance amplifier (LNTA) isused in front of a passive mixer, which is implemented as a samplingswitch, followed by a switched-capacitor filter. Up-converted delta-sigma feedback provides narrow band RF filtering. This is a promisingtechnique to improve the linearity and blocker tolerance of the system,but the dynamic range is still insufficient for cellular SDR.

2.2. RECEIVER REQUIREMENTS 27

Continuous-Time Bandpass ∆Σ ADC

Sampling at RF frequency is also used in continuous-time bandpassdelta-sigma ADCs [41–44]. A high-speed low-resolution flash con-verter is operated in a loop with a RF bandpass filter that extractsthe complete RF band. Down-conversion and further filtering is thenperformed in the digital domain. Despite the remarkable advancesusing deep submicron CMOS technologies, requirements of cellularcommunications are not met yet.

Subsampling

Another approach is taken by subsampling receivers: The band-limitedRF signal is sampled at twice the signal bandwidth [45]. With acareful choice of the sampling rate and the RF signal bandwidth,aliasing can be avoided [46]. The major drawbacks of the subsamplingarchitecture are the requirement for a high quality RF bandpass anti-aliasing filter and the issue of noise folding, which depends on theundersampling ratio. Therefore this architecture is not well suited forsignals with a low ratio of signal bandwidth to carrier frequency as itis commonly the case in cellular standards.

Analog FFT

The concept of analog Fast Fourier Transform (FFT) systems is an in-teresting alternative to the commonly used digitization in the time do-main. For OFDM based communication standards as LTE, WiMAXand WLAN, digital Inverse Fast Fourier Transform (IFFT) to re-construct time domain signals may even be obsolete. Analog FFTcircuits have been implemented in the current domain [47, 48] andcharge domain [49]. Despite the feasibility of the concept has beenproven, presented circuits lack in spectrum resolution and dynamicrange to process cellular signals.

2.2 Receiver RequirementsThe direct conversion receiver architecture as shown in Fig. 2.3 of-fers good flexibility and performance with few external components.


Therefore this architecture fits best the requirements for a cellularmulti-mode and multi-band receiver, where a large range of carrierfrequencies and signal bandwidths have to be supported with lownoise and high linearity. For practical use in the near future, therequirements of a SDR receiver include signal bandwidths between200 kHz and 80 MHz in any band from 700 MHz to 6 GHz. This cir-cuit would support all major cellular, WiMAX and WLAN operationbands illustrated in Fig. 1.5.

The signal quality at the output of the receiver is affected by thenoise of the receive circuit and distortion due to non-linearity. InFDD systems, distortion is not only created by signals collected atthe antenna, but also by leakage of the transmit signal of the mobiledevice itself.

2.2.1 Test Cases

For every Radio Access Technology (RAT), there is a large bundleof specification documents, where from the physical layer definitionsare of importance for the receiver circuit (GSM [50], WCDMA [51],LTE [52], WiMAX [53], WLAN [54–56]). The test cases target toverify the ability of the circuit to receive the wanted signal in differentchallenging environments. Each test case imitates a specific scenarioas for example a device with poor signal strength at the cell edgeor communication with strong interfering signals at crowded places.System level requirements can be derived from the specifications inthe test cases of the individual standards. The most important char-acteristics of the receiver circuit are sensitivity (NF), linearity (inputcompression, second- and third-order linearity) and blocker tolerance.The definitions of NF and intercept points are presented in App. A.1and App. A.2.

Reference Sensitivity

The circuit needs to be able to successfully receive a signal at a verylow reference sensitivity power level Prs. No other signals are presentat the antenna input, therefore the performance is noise limited. The


tolerable system noise figure NF sys of the whole receiver can be cal-culated in decibel according to

NF sys = Prs − SNRreq − Pn,th (2.1)

where Pn,th = kT · BW = −174 + 10 · log10(BW ) is the thermalnoise from the source at the antenna port, integrated over the signalbandwidth BW , and SNRreq is the RAT dependent SNR requirementfor successful decoding. SNRreq can be negative as in the case ofWCDMA because of the processing gain after de-spreading. The totaltolerable noise and distortion power Pnd,tot of the receiver, referred tothe antenna port, is simply

Pnd,tot = Prs − SNRreq = Pn,th + NF sys. (2.2)

In the case of FDD systems, the transmitter is operated at maxi-mum output power level and can cause significant degradation due tothe finite Tx-to-Rx isolation and circuit non-linearity. Therefore thenoise figure NF sys of the whole receiver system has to be distinguishedfrom the noise figure NF rx of the receiver IC (not including the ASMand the duplexer). The corresponding calculation to take transmitleakage into account is shown in App. A.3. As expected, high linearityalleviates the noise requirement and vice versa.

Tbl. 2.1 gives an overview of the required NF and linearity fora selection of different wireless standards, assuming a minimum Tx-to-Rx isolation of STx2Rx = −55 dB [57, 58] and an insertion loss ofthe RF Front-End (RFFE) of ILrx = ILtx = 3 dB, where the ASMaccounts for 1 dB and the duplexer or RF SAW filter for 2 dB.

For GSM, the SNRreq is 9 dB, leading to a tolerable system NF of10 dB. Accounting for 3 dB insertion loss, this results in NF rx = 7 dB.The SNRreq for WCDMA is -18 dB [60], which is calculated froma processing gain of 10 · log10(3.84 MHz/12.2 kHz) = 25 dB and arequired SNR of 7 dB after de-spreading. The resulting system NFfor WCDMA is 9 dB. In the case of LTE, the SNRreq to decode theQuadrature Phase-Shift Keying (QPSK) modulated signal at refer-ence sensitivity is -4 dB because the specifications are with respectto a two-antenna diversity receiver [61]. The resulting NF would be11 dB, but as suggested by [62], an implementation margin of 2 dB issubtracted.


Table 2.1: Reference sensitivity test requirements.GSM WCDMA LTE WiMAX WLAN

BW [MHz] 0.2 3.84 5 20 10 20Prs [dBm] -102 -117 -100 -94 ≥ −97a ≥ −82b

NF sys [dB] 10 9 9 9 8 10NF rx [dB] 7 4 4 4 5 7IIP2UL[dBm] -c 45 53 47 -c -c

ICPUL[dBm] -c -25 -20 -20 -c -c

aSensitivity level is specified depending on modulation and coding under theassumption of 8 dB NF and additional 5 dB implementation margin [53,59]

bSensitivity level is specified depending on modulation and coding under theassumption of 10 dB NF and additional 5 dB implementation margin [54]

cNo FDD operation

The influence of transmitter leakage is lower for wide channelbandwidths in LTE because the noise power is higher while the totalpower leaked from the transmitter is constant, but spread over a largerbandwidth. As a consequence, the 1.4 MHz LTE channel requiresan IIP2UL of 56.9 dBm with NF rx = 4 dB. Already 1 dB higherduplexer isolation relaxes the IIP2 requirement by 2 dB. Since typicalduplexer isolation is 60 dB, setting a requirement of IIP2UL = 55 dBmis considered appropriate.

The values in Tbl. 2.1 are listed for the worst case requirements ofthe respective standards. Especially in LTE, the reference sensitivitypower of several operation bands is relaxed by up to 3 dB, leading tolower IIP2 requirements. The calculated noise figures show that FDDoperation has a strong impact on the requirements of the receiver cir-cuit, because the weakest signal has to be sensed while the transmitteris operating at maximum output power. Distortion due to transmitterleakage can be significantly reduced by increased Tx-to-Rx isolationor higher IIP2UL. The target receiver noise figure should be in theorder of 3 dB to include some implementation margin.

Transmitter leakage defines also the Input Compression Point (ICP)of the receiver in the reference sensitivity test at uplink frequencies.


The ICPUL listed in Tbl. 2.1 is required at maximum gain setting andcalculated as

ICPUL = PTx2Rx + PAPRUL (2.3)where PAPRUL is the Peak-to-Average Power Ratio (PAPR) of theuplink signal, which is 3.5 dB and 9 dB for WCDMA and LTE re-spectively [63,64].

Blocker Tolerance

Figure 2.5: Blocker template for a 5 MHz LTE channel [52].

Blocking tests verify the receivers ability to detect a wanted sig-nal with slightly higher power than Prs in presence of one stronginterfering signal, called blocker. Out-of-band blockers are usuallyspecified as Continuous Wave (CW) signals and therefore second orderdistortion creates only a DC-term and is not harmful in terms of NFdegradation. In-band blockers are usually real modulated signals sincethey represent other users communicating in the same operation band.Second order distortion of modulated signals leads to degradation ofthe wanted signal. The required SNR for correct decoding can stillbe maintained because the wanted signal power is higher than in thereference sensitivity test. The calculation of the IIP2DL requirementat downlink frequencies is similar as for transmitter leakage in thereference sensitivity test (see App. A.4).


The blocker template for a 5 MHz LTE channel is shown in Fig. 2.5as a representative example. This graph illustrates the large differencein power levels of the wanted signal and the blocking signals. Blockerslocated further away in terms of frequency are specified with higherpower, because they can be filtered easier than the ones close tothe wanted signal. The gap between the wanted signal and the firstblocker is left blank intentionally since this is the adjacent channel,which is described in a separate test case.

The required IIP2DL of the receiver IC is listed in Tbl. 2.2. Theresulting requirement is limiting only for GSM. For the other RATs,IIP2DL is below 15 dBm.

Table 2.2: Blocker test requirements.GSM WCDMA LTE

BW [MHz] 0.2 3.84 1.4 5 20∆Prs [dB] 3 3 6 6 9Pintf [dBm] -31 -44 -44 -44 -44IIP2DL[dBm] 40 13 14 9 0ICPDL[dBm] -23 -37 -36 -36 -36

Beside the linearity requirements, detecting a weak signal in pres-ence of a strong interferer asks for a large dynamic range. The receiverneeds to amplify the wanted signal and attenuate the interferers to anacceptable level such that the dynamic range can be handled by theADC.

The receiver circuit’s ICP is defined by the in-band blockers, be-cause out-of-band blockers are reduced at RF frequency, while in-band blockers usually experience only slight attenuation before down-conversion to baseband. For the modulated in-band blockers, theirPAPR needs to be taken into account when calculating the ICP. ForGSM, the strongest in-band blocker is a CW signal of -23 dBm at3 MHz offset, having a PAPRDL of 3 dB. For WCDMA and LTE,PAPRDL is significantly higher with 10 dB and 11 dB respectively [65,66]. The input compression points listed in Tbl. 2.2 have to be achievedat maximum receiver gain.


The WLAN and WiMAX standards do not specify blocker re-quirements like the cellular standards, but alternate (or non-adjacent)channel rejection. The wanted signal is 3 dB above Prs and alternatechannel rejection has to be better than 29 dB or 32 dB for WiMAXand WLAN respectively. Compared to the cellular standards, wherein-band blockers are ∼ 50 dB stronger than the wanted signal, thisis not as challenging for the receiver circuit in terms of linearity andinput compression.

Adjacent Channel Selectivity

The adjacent channel test can be seen as a special case of blockertest. The blocker is located next to the wanted signal, but in returnthe wanted signal power level is significantly higher than Prs in thecellular standards. Therefore second order distortion is not an issue.In the case of WiMAX and WLAN, the wanted signal is only 3 dBabove Prs, but the required adjacent channel rejection is just 10 dBand 16 dB and thus less stringent than other tests in terms of linearity.

As a consequence, for TDD systems the adjacent channel test isonly important for dynamic range issues of the ADC input. In FDDsystems, third order crossmodulation of the transmitter leakage withthe adjacent channel has to be taken into account, but is usually lessdemanding than the intermodulation test.

Intermodulation

Third order distortion is tested by two strong interfering signals with afrequency separation such that the third order intermodulation prod-uct falls at the frequency of the weak desired signal to be received.The intermodulation test is defined for the cellular RATs only.

In FDD systems, third order distortion at the wanted signal fre-quency also results from intermodulation of the leaked transmittersignal with a CW out-of-band blocker at half duplex distance. Thisdistortion power adds to the second order distortion directly createdby the leaked transmitter signal. Therefore, the required IIP3ULdepends on the achieved IIP2UL of the circuit. Second order distortionof the blocker itself does not contribute since it is a CW signal.


The calculation of the third order non-linearity is shown in App. A.5.Tbl. 2.3 lists the required IIP3DL to pass the intermodulation test.The needed IIP3UL for third order distortion during blocking test isgiven in Tbl. 2.4, assuming an IIP2UL of 55 dBm.

Table 2.3: Intermodulation test requirements.GSM WCDMA LTE

BW [MHz] 0.2 3.84 1.4 5 20∆Prs [dB] 3 3 12 6 9Pintf [dBm] -46 -43 -43 -43 -43IIP3DL[dBm] -16 -18 -22 -21 -26

Table 2.4: Blocker test requirements due to intermodulation withleaked transmitter signal.

WCDMA LTEBW [MHz] 3.84 1.4 5 20∆Prs [dB] 3 6 6 9PTx2Rx [dBm] -31 -32 -32 -32IIP3UL[dBm] -5 -6 -9 -14

Maximum Input Level

The ICPDL,ws at low gain is given by the maximum specified wantedsignal level and the associated PAPR. Tbl. 2.5 shows the specificationsresulting from the maximum input level test.

Summary

The most stringent requirements for each test case are summarized inTbl. 2.6. It should be noted, that not all of these specifications need tobe achieved at the same time in all operation bands. A more efficientimplementation can be realized if the specifications are tailored to theRATs that are really used in a specific operation band.


Table 2.5: Maximum input level test requirements.GSM WCDMA LTE WiMAX WLAN

Pws,max [dBm] -15 -25 -25 -30 -20PAPRDL [dB] 0 10 11 11a 11a

ICPDL,ws [dB] -15 -15 -14 -19 -9aSee [66]

Table 2.6: Direct conversion receiver requirement summary.Specification Comment

NF rx 4 dB Relaxed for TDD systemsIIP2UL 55 dBm In uplink band, max. gainIIP2DL 40 dBm In downlink band, max. gainIIP3UL -5 dBm Tx and CW at half duplex, max. gainIIP3DL -16 dBm In downlink band, max. gainICPUL -20 dBm In uplink band, max. gainICPDL -23 dBm In downlink band, max. gainICPDL,ws -9 dBm Wanted signal, min. gain

2.2.2 Block Level Requirements

The receiver circuit requirements derived from the RAT specificationsin the previous section have to be mapped into block level specifica-tions for the chosen direct conversion architecture. Fig. 2.6 illustrates,which blocks have a significant influence on the different receiverspecifications.

The receiver targets to operate in various operation bands withseveral RATs. Therefore the characteristics of the different blockshave to be specified in a general way that takes also their flexibilityinto account. The most stringent requirements are linked to transmit-ter leakage in LTE. From the operation bands without relaxations,frequency separation between the uplink and downlink channel canbe as low as five times the allowed channel bandwidth.


0°

-90°

Figure 2.6: Direct conversion receiver architecture with indicatedrelevance of each block on system level requirements.

For the receiver plan, it is assumed that the LNA has a widebandcharacteristic, with a frequency selectivity of 2 dB attenuation at theuplink frequency and 1 dB at half duplex distance. The mixer outputis assumed to provide first order filtering at the output with a 3 dBfrequency of 2.5 times the RF signal bandwidth, which correspondsto five times the signal bandwidth at baseband. For the input com-pression, the strong GSM in-band blocker gives the most stringentrequirements because this interferer is not attenuated by the LNAand the mixer. The input compression of the LNA is relaxed by theinsertion loss of the ASM and the duplexer, but the subsequent blocksneed to tolerate the interferer with full amplification of the previousblocks.

The calculation of the noise figure and the intercept points ofcascaded blocks is shown in App. A.6. Generally, high gain in the firststage improves the noise characteristic at the cost of worse linearity.This conflict can be somewhat relaxed because selectivity in the frontreduces the impact of non-linearity of subsequent blocks.

With the block level specifications in Tbl. 2.7, the receiver circuitfulfills the requirements derived in the previous section. It has tobe mentioned that the chosen architectures of the RF circuits havea great impact on the achievable performance and may result indifferent distribution of gain, noise and linearity requirements amongthe blocks. Especially the frequency selectivity of the LNA is assumed


conservative and increased selectivity would relax the requirements ofthe other blocks.

Table 2.7: Block level specifications for the direct conversion receiver.LNA Mixer Baseband Cascade

Gain [dB] 20 10 65 95NF [dB] 1.5 15 25 3.1IIP2 [dBm] -a 80 75 IIP2UL = 57.5IIP3 [dBm] 0 16 25 IIP3UL = −4.8ICP [dBm] -20 -2 7

aSecond order distortion of the LNA is irrelevant because the distortion productis not at the frequency of the wanted signal.

2.2.3 LNA and MixerOne fundamental property of a SDR is the carrier frequency agility. Asdefined in Sec. 2.2, the frequencies to cover range from 700 MHz up to6 GHz. The inevitable duplexer, which is required in FDD systems,severely limits the usability of one single wideband or tunable RFinput at the receiver IC. Currently available SAW duplexers are fixedin frequency, therefore a bank of these devices is required to supportdifferent operation bands. Tunable RF filters may once be availableas tunable RF Micro-Electro-Mechanical-System (MEMS) [67], butthere is still a long way until commercial products with competitivesize and cost will be available. In the future, MEMS devices couldeven offer the possibility for high quality narrow band filtering forchannel selection at RF [68].

The consequence of using a bank of duplexers is the need formultiple input pins for the RF IC, because combining the outputsof the duplexers directly is not feasible. From this argumentation [18]concluded that currently a set of narrow band LNAs is the bestsolution for a multi-standard receiver. Because most of the operationbands are used for FDD and TDD systems concurrently, the duplexersrequired for FDD RATs can be used as SAW filters for the TDD


RATs in the same band without additional cost. Frequency bandsexclusively used by TDD RATs are excluded from this rule, becausethe commonly used SAW filers to reject out-of-band blockers can beavoided if the receiver is designed appropriate [12, 25, 69–71]. If noSAW filters are required, the pin count of the RF IC can be reduceddramatically by using a low number of tunable or wideband LNAs.The increasing popularity of MIMO operation for diversity receptionor spatial multiplexing requires several independent receiver chains. IfMIMO is only used on the receive side, SAW-less operation is desirablefor the second receive chain because no duplexer is required there.

The linearity requirement of the mixer is challenging, but can behandled with a passive mixer architecture. Very high input referredIIP2 can be realized by calibration of threshold mismatch and IQ-imbalance [28] or frequency selectivity in front of the mixer [25, 69].Blocker detection schemes can change the circuit performance depend-ing on the blocker level to save power if no blocker is present [13]. Ac-tive feedback [72, 73] and feedforward [74] architectures also improvethe linearity of the receiver, but degrade the NF to an unacceptablelevel.

2.2.4 BasebandThe dynamic range of the down-converted signal is too large to behandled by the ADC. Therefore a BBF is required to reduce thedynamic range by means of blocker filtering and signal amplification.It is assumed that the out-of-band blockers are attenuated by theduplexer, the LNA and the mixer at least to the same power level asthe in-band blockers. Consequently the baseband filter can be definedaccording to the requirements given by the in-band blockers, whichare assumed to see no attenuation before the BBF.

It is further assumed that a ∆Σ ADC is used for digitization of thesignal. The ∆Σ architecture has the advantage of high sampling rateat the input, several times larger than the wanted signal Bandwidth(BW), which means that residual blocking signals can be tolerated andare removed in the subsequent filtering and decimation in the ADC.The sampling rate of a Nyquist converter would have to be chosenlarger than the BW of the wanted signal, because it is impossible toremove all blockers completely by analog filtering. Even with strong


analog filtering, a sampling rate 1.5 to 2 times larger than the wantedsignal BW is required [75].

Filter Order

Figure 2.7: Signal power levels and dynamic range requirements forthe ADC.

Fig. 2.7 shows how the dynamic range at the ADC input is com-posed. The power Pws,ADC of of the wanted signal is regulated to aconstant level. As discussed in the previous sections, strong interferingsignals are present in cellular systems. Therefore, the dynamic rangeof the ADC needs to tolerate these blocking signals, including theirPAPR. However, if the blocking signals are strongly attenuated ornot present, the PAPR of the wanted signal still adds to the requireddynamic range. An ADC noise margin of 12 dB is chosen, resultingin a 0.25 dB degradation of the overall noise figure. The requireddynamic range of the ADC is then calculated in decibel by


DRADC = HRADC + AGC + SNRreq + NM ADC

+ max (P∗res.bl.,PAPRws) (2.4)

where P∗res.bl. = Pres.bl. + PAPRbl is the residual blocker power in-cluding its PAPR. A headroom of HRADC = 6 dB and an AutomaticGain Control (AGC) step of AGC = 6 dB are used in the followingcalculations.

The required SNR depends on the RAT and the chosen data rate.A selection of SNR values is listed in Tbl. 2.8.

Table 2.8: SNR requirements for selected RATs.RAT Data rate SNRGSMa 270 kbps 9 dBEDGEb 810 kbps 30 dBWCDMAc 21.6 Mbps 23 dBLTEd 23 Mbps 16 dBLTEe 35 Mbps 21 dBWiMAXf 28.5 Mbps 21 dBWLANg 65 Mbps 21 dB

afull-rate speech [76]b8-PSK, PAPR=3 dB [76]c64 QAM, spreading factor 16 [77]d10 MHz BW, 16 QAM, coding rate 3/4 [78]e10 MHz BW, 64 QAM, coding rate 3/4 [78]f10 MHz BW, 64 QAM, coding rate 3/4 [53,79]g20 MHz BW, 64 QAM, coding rate 5/6 [80]

The optimal order of the baseband filter can be estimated byminimizing the total power consumption of the ADC and the BBF.The BBF power consumption is approximated by

PBBF = FOM BBF · fc · n (2.5)

where FOM BBF is a figure of merit of the BBF, fc is the cutofffrequency of the filter and n is the filter order. The power of theADC is estimated from the well known formula

PADC = FOM ADC · 2fc · 2ENOB(n) (2.6)


where the required Effective Number Of Bits (ENOB) is calculatedfrom the dynamic range requirement, depending on the filter order nby

ENOB (n) = DRADC (n)− 1.766.02 (2.7)

Because PADC is exponentially decreasing and PBBF is linearlyincreasing with n, there is an optimum filter order minimizing the totalpower consumption Ptot. Fig. 2.8 shows the power consumption of theADC and the BBF and the corresponding dynamic range requirementof the ADC on the example of the 20 MHz LTE adjacent channeltest and the 1.4 MHz LTE narrow band blocking test [52]. Forthe calculations, FOM ADC = 0.5 pJ/conv, FOM BBF = 0.5 nJ andSNR = 21 dB have been used and the BBF is modeled by a Chebyshevfilter with a 0.3 dB pass-band ripple and a cutoff frequency at half theRF channel bandwidth. The 20 MHz test case specifies the adjacentchannel signal as a LTE signal with only 5 MHz bandwidth and25.5 dB higher power than the wanted signal, thus concentratingthe power close to the wanted signal. The narrow band blocker for1.4 MHz channel bandwidth is specified as a CW signal only 200 kHzoffset from channel bandwidth and is 29.2 dB stronger than Pws. Theresulting optimal filter order for these two specific scenarios is 7 and6 respectively.

2 4 6 850

55

60

65

70

75

80

Rela

tive p

ow

er

level [d

B]

Filter order

0

20

40

60

80

100

120

Pow

er

[mW

]

P

ADC

PBBF

Ptot

DRADC

(a) 20 MHz BW, adjacent channel

2 4 6 850

55

60

65

70

75

80

Re

lative

po

we

r le

ve

l [d

B]

Filter order

0

1

2

3

4

5

6

Po

we

r [m

W]

P

ADC

PBBF

Ptot

DRADC

(b) 1.4 MHz BW, narrow band blocker

Figure 2.8: Estimated power consumption of the ADC and the BBFdepending on filter order for two selected LTE test cases.


If the filter cutoff frequency is placed at channel bandwidth as inthe example above, the narrow band blocker just 200 kHz apart isbarely attenuated in the case of 20 MHz channel bandwidth. Thisfundamentally limits the minimum dynamic range requirement forthe ADC. As a consequence, the total power consumption has to beoptimized under the condition, that a higher filter order is useless ifP∗res.bl. of the analyzed test case is lower than P∗res.bl. of the narrowband blocker test. With this constraint, the optimal filter order forlarge channel bandwidths corresponds to the minimum filter order,which is required to attenuate all blockers to a level, such that thedynamic range requirement is defined by the narrow band blocker test.The narrow band blocker can be attenuated by some decibel, if thefilter cutoff frequency is reduced. This is possible because the actualLTE signal occupies only 90% of the 20 MHz channel bandwidth.Indeed, the frequency dependent gain and group delay characteristicof the filter is more pronounced if the cutoff frequency is close to thesignal, but thanks to the OFDM system with it’s subcarrier basedequalization, this is not significantly affecting the signal decoding.Fig. 2.9 shows the residual blocker power (including PAPRbl) for20 MHz LTE RF channel bandwidth, when the BBF cutoff frequencyis set 5% above the actual signal baseband bandwidth of 9 MHz.

0 5 10 15 20 25−10

0

10

20

30

40

50

60

70

Blocker offset (center frequency) [MHz]

Resid

ual blo

cker

pow

er

incl. P

AP

R [dB

c]

No BBF

Order = 4

Order = 5

Order = 6

Figure 2.9: Residual blocker power P∗res.bl. including PAPRbl after thebaseband filter for different baseband filter orders on the example ofthe 20 MHz LTE channel.


It follows that the optimal filter order for LTE ranges from fourthto sixth order, depending on the signal bandwidth. In the case ofintra-band contiguous carrier aggregation as used in LTE advanced, asixth order filter is required to attenuate the 5 MHz adjacent channelof two aggregated 20 MHz carriers to the same level as the narrowband blocker. 3rd and 7nth order BBFs are optimal for GSM andWCDMA respectively. The modest power levels of the blockers in theadjacent channel and alternate channel tests for WiMAX and WLANcan be handled by a third order filter.

It has been decided to implement a sixth order BBF, this suits verywell the RATs to be served. The power saving of a programmable filterorder would not justify the excess effort. Additional attenuation onthe narrow band blocker is also welcome and power consumption isexpected to be lower than the estimated FOM BBF of 0.5 nJ in anoptimized design. The maximum residual blocker powers relative tothe wanted signal, using a sixth order Chebyshev filter, are listed inTbl. 2.9 for different RATs. In some cases, the power of the residualblocker is below the power of the wanted signal because the filter orderis higher than actually required by the specific RAT. For these stan-dards, the dynamic range requirement is not influenced by blockingsignals, but by the PAPR of the wanted signal.

Programmable Gain

Knowing the maximum residual blocker power, the wanted signalpower level Pws,ADC at the ADC input, the ADC dynamic range andthe required gain range of the analog receiver circuit can be calcu-lated. The resulting values for different RATs are listed in Tbl. 2.10,assuming a value of 4 dBm for the ADC full-scale power.

A programmable gain range between -13 dB and 94 dB is requiredto support all of the presented RATs. From Tbl. 2.10 it is also obviousthat cellular communication standards are much more demandingthan WiMAX and WLAN, as has already been observed in the systemlevel requirements. For the LNA and mixer, a total programmablegain range between 0 dB and +30 dB in steps of 6 dB can be assumed.This would lead to a required minimum BBF gain of -13 dB. Sincethe strong residual blockers are not present at high signal levels, the


Table 2.9: Maximum residual blocker powers P∗res.bl. for selected RATs(with 6th order Chebyshev filter, including PAPRbl and expressedrelative to the wanted signal power).

fbl Pbl/Pws fc P∗res.bl.RAT and test case [MHz] [dB] [MHz] [dBc]GSM alt. channela 0.4 41 0.15 < 0EDGE alt. channela 0.4 19.5 0.15 < 0WCDMA narrow band bl.a 3.5 52.7 2.15 20.6DC-HSPA n.b. intermod.b 6 48.7 4.65 30.3LTE 1.4 narrow band bl.b 0.9 29.2 0.7 11.1LTE 3 narrow band bl.b 1.7 29.2 1.42 17.2LTE 5 narrow band bl.b 2.7 29 2.36 21.5LTE 10 narrow band bl.b 5.2 29 4.73 25.2LTE 15 narrow band bl.b 7.7 26.2 7.09 23.7LTE 20 narrow band bl.b 10.2 25.5 9.45 21.1LTE adv. narrow band bl.c 20.2 23 20 25.4WiMAX adj. channeld 10 10 5 < 0WLAN adj. channeld 20 16 10 < 0

aGMSK modulated, PAPRbl = 0 dBbCW signal, PAPRbl = 3 dBcIntra-band contiguous carrier aggregation of two 20 MHz carriers, CW

blocking signal, PAPRbl = 3 dBdModulated signal, PAPRbl = 11 dB

minimum gain requirement can be relaxed. Thus a required gain rangefrom 0 dB to +65 dB is specified for the baseband filter.

The dynamic range requirement could generally be relaxed if thetotal signal power at the ADC input would be regulated to a constantlevel instead of the wanted signal power only. Higher order modulationis only used in good channel condition, this means that high SNRrequirements and high blocker power are not present at the same timeand a more elaborate fragmentation of the ADC dynamic range couldbe applied. This is suggested for the wide signal bandwidths in DC-HSPA, LTE and LTE advanced, where the BBF can not provide higherattenuation on the narrow band blockers. If sufficient dynamic range isavailable, the ADC noise margin could be increased to 16 dB, thereby


Table 2.10: Wanted signal power level at the ADC input and analogreceiver gain range for selected RATs.

Pws,ADC Gmin Gmax DRADCRAT [dBm] [dB] [dB] [dB]GSM -8 7 94 33EDGE -9 7 82.5 57WCDMA -28.6 -3.6 78.1 67.6DC-HSPA -38.3 -13.3 64.4 77.3LTE 1.4 -19.1 5.9 87.1 56.1LTE 3 -25.2 -0.2 77 62.2LTE 5 -29.5 -4.5 70.5 66.5LTE 10 -33.2 -8.2 63.8 70.2LTE 15 -31.7 -6.7 63.5 68.7LTE 20 -29.1 -4.1 64.9 66.1LTE adv. -33.4 -8.4 57.6 70.4a

WiMAX -19 11 72 56WLAN -19 11 63 56

a65.4 dB if only 16 QAM modulation is used.

lowering the degradation of the noise figure to 0.1 dB. Excess dynamicrange could also be used to reduce the maximum gain requirement e.g.in the case of GSM.

Carrier Aggregation

In LTE advanced, several LTE signals, called Component Carriers(CCs), can be aggregated in the same operation band (intra-band)or in different operation bands (inter-band) to increase the achievabledata rate. In the case of contiguous intra-band Carrier Aggregation(CA), the CCs are located next to each other in frequency and can bereceived concurrently by one receiver circuit. If two CCs of the samebandwidth are processed, a BBF with appropriate cutoff frequencycan provide adjacent channel and blocker filtering. But the specifica-tions allow also CA of CCs with different bandwidth, e.g. 10 MHz and20 MHz. Placing the LO frequency of the direct conversion receiverin between the two CCs, results in an asymmetric signal at baseband.Thus the adjacent channel and the in-band blockers of the CC with


smaller bandwidth experience only limited or no attenuation at allfrom the BBF, since the cutoff frequency has to be chosen to fit thebandwidth of the wider CC. As a consequence, the receiver has tohandle significantly higher residual blocker powers, demanding forhigher dynamic range of the ADC. Alternatively, the LO frequencycould be placed such that the baseband signal is symmetric. Withthis approach, there is a subcarrier of the wider CC falling at DCand being strongly affected by DC-offset. Also decoding in the digitaldomain is more complex if the LO frequency is not placed in betweenthe two CCs.

Baseband Structure

As shown in Sec. 2.2.2, selectivity in an early stage reduces the lin-earity requirements on the following stages. Therefore, it is beneficialto use a baseband section as shown in Fig. 2.10.

Figure 2.10: Structure of the baseband section with the BBFsurrounded by a pole and a zero, forming an allpass, and the outputbuffer to drive off-chip loads.

The pole in front of the lowpass BBF provides first order attenu-ation on the strong blocking signals. The cutoff frequency of the polecan be set withing the actual signal bandwidth, because the pole formsan allpass together with the zero at the end of the baseband section. Ifthe zero is placed as a positive zero in the right half-plane, the allpasscan be used for group-delay correction of the BBF transfer function.Group delay correction may be necessary because the wideband signalof WCDMA requires a flat filter pass-band characteristic. System-level simulations have shown, that WCDMA signals must not bedistorted by more than 0.8 dB of amplitude ripple and 120 ns ofgroup delay ripple by the BBF [65]. For GSM, the channel flatnessis unproblematic because the cutoff frequency of the filter can be setreasonably far outside the signal bandwidth. OFDM based RATs like


LTE, WLAN and WiMAX are more tolerant to gain and group delayvariation because equalization is performed on a subcarrier basis.

Mismatch between the I-path and the Q-path also degrades the sig-nal quality. Unlike in low-IF architectures, where I/Q imbalance cancause strong blockers at image frequency to fall into the wanted signal,the direct conversion architecture suffers only from SNR degradationby image components of the wanted signal itself. I/Q imbalance ismeasured by relative gain error ε = (GI/GQ − 1) and radian phasedifference ∆ϕ = ϕI−ϕQ between the two paths. The resulting ImageRejection Ratio (IRR) can be calculated as [81]

IRR ' 4ε2 + ∆ϕ2 (2.8)

High modulation order of 64 QAM require low distortion, thereforeI/Q imbalance should not exceed ε = 5% and ∆ϕ = 2, correspondingto an IRR of 30 dB [82]. The I/Q imbalance of the BBF should belower than these values, because the mixer also contributes signifi-cantly to the mismatch. If the achieved IRR is too low, compensationtechniques have to be applied [83–85].

In the target application, the allpass pole is linked with the de-modulator and therefore not part of the designed circuits in thisthesis. The BBF requirements are summarized in Tbl. 2.11, assumingthe pole in front of the BBF has an input referred noise density of4.5 nV/

√Hz (equivalent noise figure of 20 dB), a programmable gain

between 2 dB and 20 dB in 6 dB steps and a linearity of IIP2 = 77 dBmand IIP3 = 30 dBm. The noise and linearity of the positive zero andthe output buffer are not crucial due to the large gain and strong filter-ing in front. The buffer is needed to drive large off-chip capacitances.For accurate gain control, gain steps of 1 dB have to be implementedin the baseband section.


Table 2.11: Requirements for the multi-standard baseband filter.Specification Comment

Order 6th Fixed for all modesCutoff freq. 150 kHz to 40 MHz Support all RATsa

Gain -2 dB to 45 dB In steps of 1 dBNoise 81 nV/

√Hzb Max. gain

IIP2 75 dBm Max. gainIIP3 20 dBm Max. gainICP 7 dBm 3 MHz GSM blockerIRR > 30 dB ε < 5%, ∆ϕ < 2

aRF channel BW from GSM up to 80 MHz WLAN/ LTE adv./ WiMAX adv.bInput referred noise, NFeq = 45 dB

Chapter 3

Filter Design

As shown in the previous chapter, the baseband filter for a software-defined radio needs to fulfill a variety of requirements. In the following,it is shown what kind of filter is best suited for the challenging taskand how it can be realized.

Basic characteristics of the filter as the transfer function prototypeand the circuit technique to be used for implementation are discussedfirst. The resulting decision for an active RC circuit is mainly moti-vated by its superior linearity and noise properties. The sensitivityto variations in component values due to the fabrication process isanalyzed for biquad and leapfrog circuit architectures.

Filter programmability is a key property for operation in SDRs.Therefore, the implementation of programmable gain and frequency isinvestigated. A method to realize a wide range of 256-fold frequencyprogrammability, with frequency step increase below 3%, is presented.Naturally, programmable active RC circuits require programmableresistors and capacitors. The implementation of these elements isdiscussed, focusing on area efficiency and matching. The influenceof switch parasitics on the programmable capacitance and resultinglimitations are highlighted. Finally, it is shown, what measures canbe taken to deal with non-idealities due to process variations, likeinaccurate RC time constant and DC offset.

49

50 CHAPTER 3. FILTER DESIGN

3.1 Prototype FilterCommonly, Chebyshev and Butterworth filters are used as filter proto-type [86–89]. The most important characteristics of the prototype arepass-band flatness, stop-band attenuation and group delay variation.Fig. 3.1 shows the transfer functions of the two different types on theexample of a sixth order filter. Butterworth filters have flat pass-bandcharacteristic and low group delay variation, but the transition to thestop-band is rather smooth. The transfer function of Chebyshev filtersshows a tolerable pass-band gain ripple with sharp transition to thestop-band. However, the group delay variation is larger comparedto a Butterworth filter of the same order. The amount of pass-bandripple for Chebyshev filters is a design variable influencing also thetransition sharpness. A Bessel filter would provide maximally flatpass-band group delay, but it has insufficient attenuation of blockingsignals. Elliptic filters have the sharpest transition from pass-band tostop-band, but show poor asymptotic behavior since they consist ofpoles and zeros. The inverse Chebyshev filter has flat pass-band gainand transition sharpness comparable to the normal Chebyshev filter.However an inverse Chebyshev filter is not of all-pole type and suffersfrom poor asymptotic behavior as the elliptic filter.

A sharp stop-band transition is realized by special arrangement ofthe pole and zero locations. As a consequence the transfer function ofChebyshev filters is more sensitive to variation in the pole locationscompared to Butterworth filters. In terms of implementation com-plexity and power consumption, not the type of filter, but the numberof poles is essential. The amount of tolerable gain and group delayripple in the filter pass-band defines how close the cutoff frequencycan be placed to the signal bandwidth. With group delay correctionby a first order allpass, the cutoff frequency of the Chebyshev filtercan be placed as close as 14% higher than the signal bandwidth ofWCDMA [65]. The cutoff frequency of the Butterworth filter can beplaced roughly at the same frequency without violating the ampli-tude ripple requirement, but provides significantly less attenuation onblocking signals than the Chebyshev type of the same filter order.

Because of the better attenuation of blocking signals, it has beendecided to use a Chebyshev prototype for the baseband filter. Es-pecially in RATs that are more tolerant to group delay and gain

3.1. PROTOTYPE FILTER 51

Figure 3.1: Prototype filter magnitude response.

ripple than WCDMA, the advantage of the Chebyshev type of filteris obvious.

3.1.1 Filter Order and Gain StrategyThe optimal filter order for minimum total power consumption ofthe BBF and the ADC has been derived in Sec. 2.2.4. It has beenconcluded that a sixth order filter should be used to support alltargeted communication standards.

The filter gain has to be programmable in a range of 47 dB. Theimplementation of the baseband filter will consist of several stages,therefore the overall gain can be distributed among these stages. Highgain is preferably used in the front to reduce the noise contributionof the following stages. But the attenuation of blocking signals has tobe taken into account in order to avoid saturation within the circuit.Furthermore, high gain in the first stage will lead to lower linearityin the stop-band. The gain strategy is the sequential order of gainswitching across the stages, while changing the gain, such that the


blockers are not saturating the circuit. Gain change leads to transientsettling effects because the signal stored in the feedback capacitors ofthe filter depends on the gain setting. The settling after gain switchingcauses increased Error Vector Magnitude (EVM) and originates fromthe circuit offset voltage as well as the processed signal itself [63]. Theeffect can be minimized if the gain is step-wise increased starting inthe first stage. This way, the initial error voltage is never amplifiedby large gain of following stages.

3.2 Circuit TechniqueAs stated in section Sec. 2.2 the direct conversion receiver architec-ture with a CT baseband filter has been chosen. A DT switched-capacitor filter would offer straight-forward frequency scaling by clock-programmability and good robustness against PVT variations. Buta CT filter would be required anyway to avoid aliasing of noise andblocking signals. Therefore a CT BBF is implemented in this work.

(a) Active-RC (b) gm-C

Figure 3.2: Integrator circuits for active-RC and gm-C techniques.

CT filters are typically implemented as active-RC or gm-C circuits.The corresponding integrators are shown in Fig. 3.2. As the name ofthe circuits suggests, the angular cutoff frequency of the two circuittechniques is given by ωRC = (R · C)−1 and ωgmC = gm · C−1. Forthe active-RC circuit, the Gain-Bandwidth Product (GBP) of the am-plifier needs to be significantly larger than the filter cutoff frequency.This demands for a high power, but in return, the system is feedbacklinearized, insensitive to parasitic capacitances at the input as well asthe output and can process signals with large swing. The gm-C circuiton the other hand consumes less power because the cutoff frequency is

3.2. CIRCUIT TECHNIQUE 53

only limited by the transit frequency of the respective transistor. Thiscomes at the cost of low linearity due to the open-loop characteristic,higher sensitivity to parasitic capacitances at the output and limitedsignal swing. In terms of area and frequency agility, the gm-C circuitis favored because it does not require a resistor array and the cutofffrequency can be scaled by the transistor bias current. Discrete stepcutoff scaling can be implemented on the integration capacitance,the gm and the resistor. The noise contribution of the two circuitsis dominated by the resistance and the gm with advantage for theactive-RC circuit. For frequency accuracy, both circuit techniquesneed some kind of tuning setup to compensate for PVT variations.

A slightly modified version of the active-RC circuit targets toimprove the frequency agility without sacrificing too much of thebenefits. In the MOSFET-C circuit, the resistance of the active-RCcircuit is replaced by a transistor in triode region. The advantages arecontinuous tuning of the transistor resistance by the gate bias voltageand reduced area because no resistor array is required. The draw-backs include lower linearity and low signal swing due to the activeresistance. The other characteristic properties as power consumption,noise and sensitivity to parasitics are inherited from the active-RCcircuit. An additional problem of the MOSFET-C technique is theaccurate and reliable generation of the bias voltage for the triodetransistor, especially under PVT variations.

High linearity and low noise are key requirements for the BBFto be implemented, therefore an active-RC circuit is chosen to berealized, despite the related drawbacks in frequency agility and powerefficiency.

The active-Gm-RC biquad cell is an interesting approach to com-bine the low power properties of gm-C filters with the high swing andlinearity characteristic of active-RC circuits [90]. The basic idea is toinclude the pole of the Miller compensated amplifier into the transferfunction of the cell. The resulting circuit is of second order and canbe seen as biquad cell. In this thesis a different approach (presentedin Sec. 4) is taken to reduce the power consumption of the amplifier,which is generally applicable to active-RC circuits and not limited tobiquad implementations.


3.3 Filter Architecture

High-order active-RC filters are favorably realized by leapfrog filtersor cascaded biquads and in case of odd order, a first order section.The two architectures are shown in Fig. 3.3, where Tow-Thomas cellsare used in the biquad implementation. The calculation of resistorand capacitor values from a prototype filter is shown in [63]. Theadvantage of the biquad version is the direct mapping of biquad cellsand pole pairs. This allows to place the lowest pole pair in front toincrease selectivity in the first stage.

3.3.1 Sensitivity

The transfer function of the BBF depends on the exact values of thecomponents that build the circuit. Therefore it is important to knowthe influence of component inaccuracy on the overall transfer function.Leapfrog filters simulate passive LC ladder filters, therefore they in-herit the property of low sensitivity to component variation. However,the equivalence of leapfrog filters to their passive counterparts is onlyvalid if the amplifiers can be considered ideal. For a first analysis,the amplifiers are assumed ideal and only variations in the passivecomponents are evaluated.

The sensitivity Syx of y (x) with respect to x is defined as the

relative change in y (x) that results from a relative change in x [91]

Syx =

∂yy

∂xx

= ∂y

∂x· xy

(3.1)

For small variations ∆x, the resulting error in y (x) can then becalculated by

∆yy

= Syx ·

∆xx

(3.2)

δy = Syx · δx (3.3)

3.3. FILTER ARCHITECTURE 55

(a)

Leap

frog

arch

itec

ture

(b)

Tow

-Tho

mas

biqu

adar

chit

ectu

re

Figu

re3.

3:A

ctiv

e-RC

arch

itect

ures

ofa

6th

orde

rlo

wpa

ssfil

ter.


Some basic rules, directly following from the definition, are of impor-tance for intuitive understanding

y = k · xα ⇒ Syx = α (3.4)

y = y1 · y2 · y−13 ⇒ Sy

x = Sy1x + Sy2

x − Sy3x (3.5)

y = y1 + y2 + y3 ⇒ Syx = (y1Sy1

x + y2Sy2x + y3Sy3

x )y1 + y2 + y3

(3.6)

y = y (x (t)) ⇒ Syt = Sy

x · Sxt (3.7)

For a non-zero sensitivity, the relation can also be reversed to calculatethe sensitivity of x with respect to y as Sx

y = (Syx )−1.

Equation (3.7) is of particular interest for filter transfer functionsensitivity, because it is more comfortable to calculate the sensitivityof the transfer function with respect to its poles and then the sensitiv-ity of the poles with respect to component values than going straightfrom transfer function to component values. The transfer functionH (s) of a sixth order all-pole lowpass filter is given by

H (s) =∏3i=1 ω

2pi∏3

i=1

(s2 + ωpi

Qpis+ ω2

pi

) (3.8)

where ωpi and Qpi are the pole frequency and quality factor of polepair i. The sensitivity of the transfer function magnitude with respectto pole frequency and quality factor can then be calculated as

S |H|ωpi= −

2(1− γ2

i

)γ2i −

γ2i

Q2pi

(1− γ2i ) + γ2

i

Q2pi

(3.9)

S |H|Qpi = −γ2

i

Q2pi

(1− γ2i ) + γ2

i

Q2pi

(3.10)

where γi = ω/ωpi is the normalized frequency. The sensitivity onquality factor variation is bound to an upper limit of 1, while thesensitivity on pole frequency can be higher. Fig. 3.4 shows the transferfunction magnitude sensitivity with respect to pole frequency andquality factor for a sixth order Chebyshev filter with 0.3 dB pass-band


ripple and 10 MHz cutoff frequency. This filter will also be used infurther examples in this section. The figures confirm that the trans-fer function is more sensitive on variation in cutoff frequency. Themost important pole is pair 3, which is the pair of highest frequencyand quality factor. The highest sensitivity occurs close to the polefrequency of the respective pair.

105

106

107

108

−6

−4

−2

0

2

4

6

8

Frequency [Hz]

Se

nsitiv

ity

Pair 1

Pair 2

Pair 3

(a) Pole frequency sensitivity

105

106

107

108

0

0.2

0.4

0.6

0.8

1

Frequency [Hz]

Sensitiv

ity

Pair 1

Pair 2

Pair 3

(b) Pole quality factor sensitivity

Figure 3.4: Sensitivity of the transfer function magnitude for a sixthorder Chebyshev filter with 0.3 dB pass-band ripple and 10 MHz cutofffrequency.

The sensitivity of the first Tow-Thomas biquad shown in Fig. 3.3(b)on component variation can be calculated from the design equations

ωp1 =√

1Rf2Rb2C1C2

Qp1 = Rb1√Rf2Rb2

√C1

C2


The resulting sensitivity of the biquad poles with respect to the com-ponents can be expressed in a sensitivity matrix Sbq1

x as

[δωp1δQp1

]= Sbq1

x · δ−→x

=[

Sωp1C1

Sωp1C2

Sωp1Rf1

Sωp1Rf2

Sωp1Rb1

Sωp1Rb2

SQp1C1

SQp1C2

SQp1Rf1

SQp1Rf2

SQp1Rb1

SQp1Rb2

]· δ−→x

=[−0.5 −0.5 0 −0.5 0 −0.50.5 −0.5 0 −0.5 1 −0.5

]·

δC1δC2δRf1δRf2δRb1δRb2

The absolute value of the sensitivity for most of the components is 0.5,except for Rb1 which has no influence on ωp1, but higher influence onQ. The resistor Rf1 does not affect the poles at all. The sensitivityS |H|x of the transfer function on the components can be calculatedusing (3.7)

S |H|x =

S |H|ωp1,Qp1· Sbq1

x 0 00 S |H|ωp2,Qp2

· Sbq2x 0

0 0 S |H|ωp3,Qp3· Sbq3

x

(3.11)

where the diagonal structure of S |H|x confirms the independence of theseparate biquad filter stages.

Leapfrog filters have better sensitivity properties than biquad im-plementations, because they simulate passive LC ladder filters. Sincepassive filters can not generate energy, the filter gain can not exceedunity. The pole frequencies and quality factors of the leapfrog filtercan not be calculated in a closed form because of the interleavedarchitecture. However, a numerical calculation of the pole sensitivityon component values can be performed in the case of ideal amplifiers.


The transfer function in (3.8) can be rewritten with a denominatorpolynomial as

H (s) =∏3i=1 ω

2pi

s6 + a5s5 + a4s4 + a3s3 + a2s2 + a1s+ a0(3.12)

The sensitivity Safp of the denominator coefficients ai on the filter pole

frequencies and quality factors can directly be calculated from theexpansion of the denominator of (3.8). The matrix Sa

fp is invertible,therefore the sensitivity of the filter poles on the denominator coeffi-cients can be numerically evaluated as S fp

a =(Sa

fp)−1. The sensitivity

Sax of the denominator coefficients ai on the component values of the

circuit can be derived in a lengthy calculation using a Signal FlowGraph (SFG) (see App. B.1). The two sensitivity matrices are thencombined to calculate the sensitivity S lf

x of the leapfrog filter polefrequencies and quality factors on component value variations as

S lfx =

(Sa

fp)−1 · Sa

x (3.13)

The resulting sensitivity matrix for the example sixth order, 10 MHzChebyshev filter is shown in (B.11). As expected, all pole frequenciesand quality factors are affected by variations of all circuit componentsexcept the resistance Rf1. But the absolute value of the pole frequencysensitivity never exceeds 0.3. A lower sensitivity on more componentsis advantageous because component variations are caused by randomeffects and constructive superposition is less likely the more compo-nents are involved. The transfer function sensitivity is then calculatedequivalent to (3.11) as

S |H|x =[S |H|ωp1,Qp1

S |H|ωp2,Qp2S |H|ωp3,Qp3

]· S lf

x (3.14)

The accuracy of the transfer function in the pass-band is veryimportant for the designed filter. The deviation D (ω) from the idealshape due to component variation, expressed in decibel, can be cal-culated as [92]

D (ω) = 20 · log(

1 + ∆ |H (s)||H (s)|

)(3.15)


= 8.68 · ln(

1 + ∆ |H (s)||H (s)|

)(3.16)

' 8.68 · ∆ |H (s)||H (s)| = 8.68 · S |H|x · δ−→x (3.17)

where the approximation in (3.17) is valid for small variations inH (s). Taking the absolute values of all elements of the sensitivitymatrix in (3.17), a worst case estimation of the deviation can becalculated. Assuming a realistic value of δx = 1% for all components,the deviation of the resulting transfer function is shown in Fig. 3.5.The graph illustrates the advantage of the leapfrog filter architectureover its biquad counterpart with moderate variation in the pass-bandeven in this unrealistic scenario of constructive superposition of allcomponent variations.

105

106

107

−1

0

1

2

3

Frequency [Hz]

De

via

tio

n [

dB

]

Biquad

Leapfrog

Figure 3.5: Worst case approximation of the filter transfer functiondeviation for 1% component variation.

The decision, which filter architecture should be used, dependson more properties of the realization than just component sensitivity.With high amplifier speed and moderate programmability require-ments, a leapfrog filter should be implemented, due to its superiorsensitivity. With lower amplifier speed, the advantage of the leapfrogarchitecture fades away and a biquad filter can be used for its lowercomplexity and better amenability to programmability. For these

3.4. GAIN SCALING 61

reasons, both filter architectures are further analyzed and the choicefor an architecture is made during the design of the specific filtercircuits.

3.4 Gain ScalingIt is well known that the gain of a Tow-Thomas biquad is given by theresistor ratio Rb2/Rf1. Nevertheless, more insight into the circuit canbe gained by the corresponding SFG shown in Fig. 3.6. The graphconsists of one forward path P0 and two loops M1 and M2

Figure 3.6: Signal flow graph of the biquad filter stage.

P0 =(s2C1C2Rf1Rf2

)−1 (3.18)M1 = (−sC1Rb1)−1 (3.19)

M2 =(−s2C1C2Rf2Rb2

)−1 (3.20)

According to Mason’s formula, the signal transfer function can becalculated by [93]

Hsig (s) = P0

∆ =1

C1C2Rf1Rf2

s2 + s 1C1Rb1

+ 1C1C2Rf2Rb2

(3.21)

where ∆ = 1−M1−M2 is the determinant of the SFG. Programmablegain can be introduced on the resistors in the forward path. Scalingthe resistors Rf1 and Rf2 by the factors k−1

1 and k−12 respectively will

increase the DC-gain by a factor k1 · k2. In order to keep the pole


frequency and quality factor unchanged, the loop transfer functionshould stay the same, i.e. Rb2 has to be scaled by a factor k2.

A possible design approach for the biquad is to choose all resistorsto have the same value R0, and then calculate the capacitances in or-der to get the correct pole frequency and quality factor. Starting fromthis unity gain configuration, programmable gain can be introducedin the resistor values. The resistor Rf1 is particularly well suitedfor programmable gain because it does not affect the biquad poles.If a single, fixed gain, fixed frequency filter has to be designed, theimpedance values can be optimized for Spurious Free Dynamic Range(SFDR) [94]. But for a highly flexible circuit, constraints like amplifierdriving capabilities and silicon area strongly limit the possibilitiesfor optimization due to the large scaling range of the resistor andcapacitor values.

The SFG of the leapfrog filter architecture is derived in [63]. Theresults are very similar to the ones of the biquad architecture. Pro-grammable gain can also be realized in the first resistor Rf1 alone orby pairwise scaling resistor Rfi inverse to Rbi.

3.5 Noise

Figure 3.7: Noise source modeling in the biquad filter stage.

The calculation of the input referred noise of the BBF can beperformed using a SFG. Fig. 3.7 illustrates the single-ended schematicof the first biquad filter stage with all contributions from the noisycircuit elements. Resistor noise contributions are modeled as currentsources and amplifier noise contributions are modeled by equivalent

3.5. NOISE 63

Figure 3.8: Signal flow graph of the biquad filter stage with noisesources.

noise voltages. For the noise analysis, infinite amplifier gain is as-sumed. The SFG corresponding to the circuit in Fig. 3.7 is shown inFig. 3.8. The graph has the same loops M1 and M2 as the SFG inFig. 3.6. In the SFG, all noise sources have been lumped into a singlenoise current source, injected at the amplifier virtual ground node.The corresponding noise currents are calculated as

IN1 = IN,f1 + IN,b1 + IN,b2 −VN1

(1

Rf1+ 1

Rb1+ 1

Rb2+ sC1

)IN2 = IN,f2 −VN2

(1

Rf2+ sC2

)The transfer function for the noise sources differs from the signaltransfer function in (3.21), due to different forward paths. The noisetransfer function is divided by the signal transfer function to calculatethe input referred noise.

VN1,in = IN1 ·HN1 (s)Hsig (s) = PN1

P0

= −IN1 · Rf1

VN2,in = IN2 ·HN2 (s)Hsig (s) = PN2 ·∆∗N2

P0

= IN2 ·Rf1Rf2

Rb1· (1 + sC1Rb1)


where ∆∗N2 = 1−M1 is the cofactor for the noise transfer function ofIN2, because the forward path does not touch the first loop.

With this derivation, the total input referred noise power spectraldensity can be calculated. It has to be taken into account, that in thedifferential circuit, the resistor noise power is doubled. Expressing theresistors by R0 and the gain factors k1 and k2 as introduced in theprevious section, the power of the equivalent noise currents is givenby

IN12

∆f = 8kTR0

(k1 + 1 + 1

k2

)

+ VN12

∆f ·

(k1 + 1 + 1

k2

)2

R20

·

∣∣∣∣∣∣1 + sC1R0(k1 + 1 + 1

k2

)∣∣∣∣∣∣2

(3.22)

IN22

∆f = 8kTR0

k2 + VN22

∆f ·(k2

R0

)2·∣∣∣∣1 + sC2R0

k2

∣∣∣∣2 (3.23)

Neglecting the frequency dependent parts, which have a minor influ-ence below the cutoff frequency, the input referred noise power densityin the pass-band can be expressed with Rf1 = R0k

−11 as

VN1,in2

∆f ' 8kTRf1

(1 + 1

k1+ 1k1k2

)+ VN1

2

∆f

(1 + 1

k1+ 1k1k2

)≈ 8kTRf1 + VN1

2

∆f (3.24)

VN2,in2

∆f ' 8kTRf1 ·1

k1k2+ VN2

2

∆f1k2

1(3.25)

where the approximation in (3.24) is valid for high gains k1 and k2.The resistor ratios and gain factors are linked to each other by

1k1

= Rf1

Rb1(3.26)

1k1k2

= Rf1

Rb2(3.27)

3.6. FREQUENCY SCALING 65

It follows, that in the case of high BBF gain, where the noisecontribution is essential, the input referred noise of the filter is dom-inated by the resistor Rf1 and the first amplifier. In Sec. 2.2.4, themaximum BBF noise has been specified as 81 nV/

√Hz. Taking a gen-

erous margin for the noise contribution of the neglected components,50 nV/

√Hz are targeted. The value of the input resistor Rf1 should

not be larger than 60 kΩ for any cutoff frequency at maximum gain,if 80% of the noise budget is assigned to it. The remaining 20% noisepower budget limits the noise of the first amplifier to 22 nV/

√Hz.

3.6 Frequency ScalingThe cutoff frequency of an active RC filter is simply modified bychanging the R · C time constant. In the biquad SFG in Fig. 3.6,this means that either all resistors, that are involved in any loop, orall capacitors are scaled by the same factor. Scaling the capacitancehas the advantage, that the noise spectral density stays constant aswell as the maximum load current to be delivered by the amplifier.The peak current, required to charge the capacitors is equal to

ICi,max = Vm · jωCi (3.28)

where Vm is the voltage amplitude of the signal with frequency ω.Obviously, the signal frequency will scale proportional to the BBFcutoff frequency and ICi,max stays constant if Ci is scaled inversely tothe cutoff frequency.

The BBF specifications, derived in Sec. 2.2.4, require a program-mable cutoff from 150 kHz to 40 MHz. This means that the highestcutoff frequency is a factor of 267 times larger than the lowest cutofffrequency. This large range can not be covered by only scaling thecapacitance, because it would require excess silicon area for the largecapacitors on the lower frequency end and may not even be feasible onthe higher frequency end due to very small capacitance values. Therange of resistor scaling is also limited, because the noise requirementsset an upper limit on the resistance value and resistive load currentincreases for decreasing resistance as

IRf,bi,max = Vm

Rf,bi(3.29)


The cutoff frequency is not only required to be scalable in a very largerange, it also needs to be fairly accurate. A cutoff frequency resolutionof about 2% is considered appropriate.

The frequency scaling challenge can be managed by a two-foldstrategy. Coarse Frequency Selection (CFS) sets the cutoff frequencywith an exponential scaling, by doubling the capacitor or resistor val-ues. Fine Frequency Selection (FFS) tunes the filter cutoff frequencyto an accurate value, close the the frequency chosen by the CFS.Scaling the frequency in steps of factor two has the advantage, thatresistor programmability for frequency tuning partly overlaps withresistor programmability for 6 dB gain steps. This reduces the size ofthe resistor array. FFS is preferably implemented in the capacitors,because it is easier and more area efficient to scale accurately a capac-itance over a wide range by switching in and out separate capacitors,than in the case of a resistance.

A multi-mode BBF with a finite number of discrete cutoff fre-quency steps requires only a limited range of FFS for fine-tuningand compensation of process variations. In the case of a freely pro-grammable BBF for a SDR on the other hand, the FFS needs tocover the whole range between two exponential modes with sufficientresolution. For the near future, operation of LTE networks with twocomponent carriers are realistic. Omitting also the 80 MHz WLANchannel for the moment, the required BBF cutoff frequency is relaxedby a factor of two to 20 MHz maximum frequency. CFS can then beimplemented with a combination of resistor and capacitor scaling ofa factor 26 = 64. The FFS tuning range provides also up to two-foldprogrammability, therefore frequencies from 20 MHz down to 156 kHzcan be realized.

A concrete realization example is summarized in Tbl. 3.1. Fiveresistor settings and three capacitor settings are used for CFS, wheremultiple unit capacitor elements are combined in parallel. Each ofthese unit capacitors provides FFS for frequency fine tuning andadditional over-range for process compensation. The unit capacitor isprogrammable in 8 bits, from 0 · CLSB to 255 · CLSB, with a nominalvalue of Cnom,min = 90 · CLSB. This allows to double the nominalcapacitance to Cnom,max = 180 ·CLSB, while still providing 30% over-range for compensation of RC-product process variation. At the lowerbound of the RC-tuning range, where Ctun = 69·CLSB, the capacitance

3.7. RESISTORS 67

Table 3.1: Realization of 256-fold cutoff frequency programmability.Element ProgrammabilityResistor CFS 5 settings: 1x, 2x, 4x, 8x, 16xCapacitor CFSa 3 settings: 1x, 2x, 4xCapacitor FFSb 8 bitc: Cnom = 90 · CLSB to 180 · CLSB

Overall 256x (CFS: 64x, FFS: 4xd)aMultiple unit capacitors in parallel.bProgrammable unit capacitor.cProvides over-range for compensation of process variation.dFor the highest cutoff frequency, Cnom = 45 · CLSB is used.

resolution CLSB/Ctun is still as good as 1.45%. The frequency rangeof the realization can further be expanded, if the nominal capacitancevalue is reduced to 45·CLSB. This allows to boost the cutoff frequencyup to 40 MHz. Thereby, the capacitance resolution suffers, but is stillbelow 3%, even with 30% RC-tuning. The lower resolution is notan issue because the frequency accuracy of the BBF for operation inWLAN is anyway not as demanding as for the cellular standards.

3.7 ResistorsIn active-RC circuits, the virtual ground node of the amplifier iswell suited to switch in and out separate resistor elements. Areaefficiency, low parasitics, low complexity and good matching are keyrequirements for the implementation of the programmable resistor.

3.7.1 Programmable Resistor ArrayBasically, resistor elements can be combined in a serial or parallelmanner by CMOS switches. In all structures, there may be a resistorRfix, which is present in all settings. The switch size should be scaledwith the resistance value, because the switch on-resistance has tobe either negligible or proportional to the switched resistor. Thenon-linearity of the triode transistor switch can only be neglected ifthe contribution to the overall resistance is small. Low on-resistance


directly conflicts with the requirements of low parasitics, i.e. lowtransistor area. Therefore NMOS switches should be used for theirbetter conductivity.

(a) Parallel resistorarray

(b) R-2R ladder resistor

Figure 3.9: Programmable resistor array structures.

The most simple resistor array approach is a bank of parallelresistors as shown in Fig. 3.9(a). Thereby, each setting can be re-alized as a single resistor Ri, or as a combination of a subset of theparallel resistor elements. The advantages of this setup are the lowcomplexity and the wide range of resistor value programmability. Theparallel resistor bank is generally not very area efficient and consumesextraordinary large area if several resistors of almost identical valuehave to be realized.

With a R-2R ladder resistor array, exceptionally high resistancescan be realized with low area consumption (see Fig. 3.9(b)). Thisscheme allows to implement a wide range of resistances with goodresolution for low resistance values and low resolution for high effectiveresistances. The operation principle requires a good virtual groundat the amplifier input node, which conflicts with the requirement oflow amplifier power consumption. The input resistance of the ladderstructure is given by the resolution of the programmable resistanceand may cause severe loading issues for the preceding stage if Rfix issmall. The ladder structure should also be carefully used due to itshigher noise compared to a single resistor element of the same valueas the transresistance of the ladder.

The resistor array with binary weighted series resistors, illustratedin Fig. 3.10(a), offers a good area efficiency, low complexity and widetuning range with fine resolution. However it suffers from two severe

3.7. RESISTORS 69

(a) Binary weighted series array (b) One-hot series array

Figure 3.10: Programmable series resistor array structures.

drawbacks. First, most of the switches are not located at the virtualground of the amplifier and can therefore experience significant signalswing, leading to non-linearity. And second, the parasitic capacitanceof the switches results in poor frequency characteristic of the effectiveprogrammable resistor [95], also because the switches need to be quitelarge for negligible on-resistance. Better frequency response can beachieved with the one-hot series resistor array shown in Fig. 3.10(b).It has somewhat higher complexity than the binary weighted seriesversion, because of the higher number of switches. In return, allswitches are connected to the virtual ground of the amplifier.

Due to its excellent frequency characteristic and low complexity,a parallel resistor array has been chosen for the filter to be realized.Only for the very large resistor values, required for GSM, a one-hotseries structure is used.

3.7.2 Precision and MatchingThe stringent requirements on frequency and gain accuracy can onlybe met with precise resistor values and good matching. Precision inthis context means precise resistor ratios, which in turn is also givenby the matching of single resistor elements. The absolute value of thephysically fabricated resistors is subject to process variations, whichare compensated within the unit capacitance to get an accurate RCproduct.

Unit Resistor

A well known method to realize different resistor values Ri withgood matching is to implement them as a combination of a basic


Figure 3.11: Series/parallel ladder resistance structure to realize anarbitrary resistance by combination of unit resistors.

unit resistance Ru. Arranging the units in the layout in a regulararray structure will minimize the mismatch between the differentresistors. However, the set of resistance values, which is requiredto realize the desired filter transfer function, has to be considered asa set of wide range, arbitrarily distributed values. Therefore it is notstraight-forward to implement these values as a combination of Ru.For a small set, a hand crafted combination may be feasible, but fora highly programmable BBF, this is not an option.

The series/parallel ladder resistance structure shown in Fig. 3.11allows to approximate any resistance value Ri with arbitrary accuracyas a combination of units Ru. Each ladder stage Ria,b consists ofmultiple unit resistors Ru. A series combination is used in the resistorsRia and a parallel combination in Rib. The number of unit resistorsin Ria,b is computed in a sequential order from top left to bottomright and further stages are added until the total resistance Rladderhas reached the desired accuracy. For every stage, the number of Ruin series is equal to the largest number such that Rladder ≤ Ri, whilethe number of parallel Ru is equal to the largest number such thatRladder ≥ Ri. The total number of required unit resistors depends onthe exact values of Ri and Ru as well as the desired accuracy.

Non-Unit Resistor

Even if the series/parallel ladder resistance structure can realize anarbitrary resistance value, the strict use of unit resistors causes stillsignificant overhead of silicon area. The motivation for using unit

3.7. RESISTORS 71

elements is the matching requirement under strong process variationsduring chip fabrication. Resistors for analog circuits are usually fab-ricated as non-silicided polysilicon resistors, due to their excellentlinearity and relatively high sheet resistance. The cross section ofan integrated polysilicon resistor is shown in Fig. 3.12. The highlydoped polysilicon is deposited on top of a Shallow Trench Isolation(STI) oxide. The body of the resistor is protected from silicidationby an oxide layer. Only the area of the metal contacts is silicided forbetter conductivity.

Figure 3.12: Cross section of an integrated polysilicon resistor.

The total resistance Rtot of this structure is given by [96]

Rtot = Rbody + 2 · Rint + 2 · Rsilicide + 2 · Rc (3.30)

where Rbody is the resistance of the polysilicon body with lengthL, Rint is the resistance of the interface between silicided and non-silicided polysilicon, Rsilicide is the resistance of the silicided part withlength ∆L and Rc is the metal contact resistance. Usually the widthW of the resistor body is chosen small or even as the minimum allowedby the available process technology, because rather large resistors haveto be implemented with L > 10 ·W . The contact resistance is in theorder of 10 Ω and can be neglected because it accounts for less than0.1% of a resistance larger than 10 kΩ. The contribution of Rsilicide isalso very small, because L ∆L and the sheet resistance of silicideis much lower than the sheet resistance of non-silicided polysilicon.


The interface between silicide and the highly doped non-silicidedpolysilicon is similar to an ohmic metal-silicon contact. The interfaceresistance of a n-type resistor is proportional to [97].

Rint ∝ exp(

2√εSm∗n~

· ΦBn√Nd

)(3.31)

where εS is the permitivity of silicon, m∗n is the effective electron mass,~ is the Planck’s constant, ΦBn is the Schottky barrier height and Ndis the donor atom doping density. The interface resistance can beexpressed as

Rint = ρint

W(3.32)

where ρint is the resistivity of the interface with unit width.The polysilicon body resistance consists of grain boundary resis-

tivity and intragrain resistivity, which is similar to the resistivityof single crystal silicon. Thus the sheet resistance depends, amongother parameters, on grain size and doping concentration. The totalresistance can be approximated by

Rtot ' Rs ·L

W+ 2 · ρint

W(3.33)

where Rs is the sheet resistance of non-silicided polysilicon.The mismatch δR between two nominally identical resistors RA

and RB is defined asδR = RA − RB

12 (RA + RB)

(3.34)

With careful and regular layout, mismatch due to doping concen-tration can be minimized. Random variation in resistor length isnegligible, since L W . Therefore, variation in resistor width isconsidered as the main source of Rbody mismatch. Integrated cir-cuit manufacturers usually provide a mismatch coefficient for thepolysilicon body resistance in terms of standard deviation σ, which isinversely proportional to the square root of the body area A = L ·W .The interface resistance depends also on W and will therefore alsobe subject to random variation of the width. The matching of twoidentical resistors can be improved by increasing the width, whichincreases the body area and reduces the interface resistance value and

3.8. CAPACITORS 73

its sensitivity to variations in W . A larger nominal resistance is alsobeneficial, because this reduces the relative contribution of Rint to thetotal resistance.

The resistors of the BBF have a wide range of different values andaccurate resistor ratios are required. This means that resistors RAand RB of different values have to be matched. The resistance perlength depends on the exact width of the resistors after fabrication.Variations of the etching process affect narrow resistors much morethan resistors with a large width. If the width of the two resistors isnot equal, this will cause a systematic mismatch in the ratio RA/RB.The ratio of the interface resistance to the body resistance is not thesame for RA and RB, because they have different Rtot, while Rintis constant for a fixed width. The variation in body resistance andinterface resistance are not proportional, therefore causing an errorin the resistor ratio RA/RB. This error can be avoided if RA andRB are implemented as multiples of a unit resistance Ru as describedpreviously. If no unit resistor should be used, the ratio Rint/Rbodyhas to be minimized by increasing Rtot or W . A low ratio Rint/Rbodyfurther improves the linearity of the implemented resistance, becausethe interface resistance is the main contributor to non-linearity [98].

As a conclusion, three requirements have to be fulfilled for goodmatching without using a unit resistor element. First, the widthof all resistors needs to be equal. Second, the contribution of theinterface resistance to the total resistance has to be small. And third,a regular layout is required to provide a homogeneous environmentfor all resistors, even if they can not be arranged in a perfect arrayas it would be possible for unit resistors. With these restrictions,non-unit resistors provide the advantage of high area efficiency andlow parasitic capacitances.

3.8 Capacitors

In the chosen scheme for frequency agility, a programmable unit ca-pacitor cell is used for FFS. Multiple units can be activated in parallelfor CFS. Within the unit cell, accurate matching of the separate capac-itor elements is required for precise and strictly monotonic frequency


programmability. A parallel combination of switchable capacitor el-ements is the most area efficient implementation of a programmablelinear capacitance for active RC circuits.

If only a small range of FFS is required, the unit capacitor can becomposed by a constant capacitance Cfix and a binary programmablepart. In this case, matching is only critical for the binary programma-ble capacitor elements Ci, which may be implemented with a moderateresolution of about 5 bit.

In the case of a fully programmable unit capacitor as requiredfor a BBF to be operated in a SDR, 8 bit resolution is required.The accuracy of the capacitors is somewhat relaxed, because a fre-quency resolution of 2% is sufficient, corresponding to about 6 bitaccuracy. Nevertheless, the programmable capacitance value needs tobe monotonically increasing for proper operation of the RC calibrationalgorithm.

3.8.1 Monotonicity

Figure 3.13: Implementation of the 8 bit programmable unit capaci-tor, C5 to C7 are scaled thermometer coded to ensure monotonicity.

The programmable capacitance shown in Fig. 3.13 is implementedas a combination of a 5 bit binary programmable capacitor arrayand a set of thermometer coded basic capacitance elements Cb. Thestandard deviation of the basic capacitance is given as σb = αb · Cb,where αb is the standard deviation coefficient, which is inversely

3.8. CAPACITORS 75

proportional to the capacitor area. If C4 is implemented as a seriescombination of two Cb capacitors, then α4 is equal to αb√

2 , becauseit combines the random processes of the two separate capacitors.Realizing C1 to C3 with capacitor plates of shrinking area, leads toproportional increase in the respective αi. Very small capacitor area isavoided by implementing C0 as a series combination of four capacitors.The most critical situation in terms of monotonicity is, when C0 to C4are switched off and C5 is switched on. The sum of the variations inthe binary scaled capacitances and one basic capacitance needs to besmaller than the value of C0. Since the variation is a random process,standard deviations are summed up in powers

σtot =

√√√√ 5∑i=0

σ2i (3.35)

The standard deviations of the capacitor elements are summarized inTbl. 3.2. The total standard deviation is equal to σtot = 1.23 · σb.For a 4-σ design, with a yield of 99.99%, the smallest capacitance C0needs to be larger than 4σtot = 4.9 · σb.

Table 3.2: Standard deviation σi of the binary scaled capacitors andcorresponding standard deviation factor αi.

αi Ci σi

C5 αb Cb σb = αb · Cb

C4αb√

2Cb2

αbCb2√

2C3

√2αb

Cb4

αb·Cb2√

2C2 2

√2αb

Cb8

αb·Cb2√

2C1 4

√2αb

Cb16

αb·Cb2√

2C0 4αb

Cb32

αb·Cb8

σtot = 1.23 · σb


3.8.2 Switch Sizing

The switches in the programmable capacitance introduce parasiticresistances and capacitances. As in the case of the resistor array, theswitch is placed at the virtual ground of the amplifier.

(a) Switchable ca-pacitor

(b) Circuit model (c) Simplified model

Figure 3.14: Programmable capacitor modeling.

The on-resistance of the switch defines a lower limit for the sizeof the switch shown in Fig. 3.14(a). The switchable capacitor can bemodeled by the circuit in Fig. 3.14(b), if the switch is turned on. Theparasitic capacitances of the triode transistor switch are calculatedas [99]

Cp1 = Cp2 '12WLCox +WCov (3.36)

where W and L are the width and the length of the transistor channel,Cox is the gate-channel capacitance per area and Cov is the overlapcapacitance of the gate and the drain/source region per width. Sincethe resistance Ron is small, the model can be simplified as shownin Fig. 3.14(c) with a total parasitic capacitance Cp = Cp1 + Cp2.The purpose of the programmable capacitance is to integrate thecurrent, which is injected into terminal a in Fig. 3.14(c). Therefore,the relevant effective capacitance is defined by

Cab =imag

(iavb

)ω

= C0

1 + (ωC0Ron)2 (3.37)

3.8. CAPACITORS 77

where it has been assumed, that terminal a is at ground voltage. Anaccurate effective capacitance value is important within the pass-bandof the BBF. The error in the capacitance value is equal to

δCab = Cab − C0

C0= (ωC0Ron)2

1 + (ωC0Ron)2 (3.38)

Since the effect of the switch resistance needs to be negligible, thecutoff frequency should not be shifted by more than about 0.1%. Thislimits the resistance to

Ron ≤√

δCab

1− δCab· 1ωcC0

= 0.032ωcC0

(3.39)

where ωc is the angular filter cutoff frequency. (3.39) can also be seenas a limitation for the pole generated by the RonC0 product, whichneeds to be at least 32 times larger than the filter cutoff frequency.Designing the pole for 50·ωc, leaves some margin for process variation.

The parasitic capacitance at the amplifier input is an issue inwidely programmable designs. The ratio γi between parasitic capac-itance Cpar,on,i of an activated capacitor element to it’s value Ci isconstant if all switches are designed for minimum size at a specifiedcutoff frequency according to (3.39)

γon = Cpar,on,i

Ci(3.40)

If the switch is turned off, only Cp1,off is loading the amplifier inputnode. Since there is no charge accumulated in the channel, Cp1,off canbe approximated by the overlap capacitance

Cp1,off 'WCov (3.41)

For short channel devices, the parasitic capacitance of the turned-offswitch is about one third of the turned-on switch, leading to

γoff = Cpar,off,i

Ci' 1

3γon (3.42)

If the programmable capacitance is operated at its maximum valueCmax, the parasitic capacitance is not an issue, since

Cpar

Cmax= γon (3.43)


But if the capacitance value is scaled to its minimum nominal valueCnom,min, which is more than 16 times smaller than Cmax (see Tbl. 3.1),then the parasitic capacitance is as large as

Cpar

Cnom,min= γon + γoff (Cmax − Cnom,min)

Cnom,min> 6 · γon (3.44)

This effect is particularly severe because the ratio of parasitic ca-pacitance to integrator capacitance increases for high frequencies.With an ideal amplifier, parasitics at the amplifier virtual groundwould not have an impact. But the real amplifier is limited in speedand therefore the parasitics at the amplifier input will degrade theperformance of the circuit. The situation is further tightened becausethe switches in the programmable resistor array also contribute par-asitic capacitances to the virtual ground node of the amplifier. As aconsequence, the switch parasitics fundamentally limit the range offrequency selectability by programmable capacitance. The design canbe slightly improved, if the switch size is reduced for the capacitorsthat are only activated in case of low cutoff frequency.

3.9 Process VariationIt has been shown in the previous sections, that resistor and capacitorratios can be realized very accurate in integrated circuits. The abso-lute value of resistors and capacitors on the other hand is not verywell controlled.

Process variations also lead to mismatch in nominally identicaltransistors. This leads to DC offset in active RC circuits and willcause saturation in high gain settings if not treated properly.

3.9.1 RC TuningA calibration algorithm for the RC time constant of the filter isneeded to reach the required cutoff frequency accuracy [100]. Asecond order reference filter is very well suited for frequency tuning.This lowpass filter has to be made of the same components as theBBF and provides a phase shift of exactly 90 at resonance. Adigital tuning circuit adjusts the resonance frequency to an externally

3.9. PROCESS VARIATION 79

provided reference frequency by tuning the programmable capacitor.The resulting tuning code is then sent to all programmable capacitorsfor an accurate BBF cutoff frequency.

The tuning code can be modified with a look-up table for a smallrange of FFS. In a highly programmable BBF, where the FFS rangesover more than a factor of two, the tuning code can be multiplieddigitally with the nominal capacitor value for the desired frequencysetting. In the case of a 8 bit programmable unit capacitor, the refer-ence filter should be designed for a nominal tuning code of 128. Thisallows straight-forward implementation of the digital multiplicationfor the compensation of the RC time constant variation.

3.9.2 Offset CompensationDirect conversion receivers are very vulnerable to DC offset, becausethe signal is directly converted from RF frequency to baseband. Dif-ferent sources contribute to the DC offset. Basically static DC offsethas to be distinguished from dynamic DC offset. While the formeris caused by process variations like mismatch, the latter is signaldependent and due to circuit non-idealities. The most importantcontributors to static DC offset are the mixer and the BBF, the effectis usually dominated by transistor threshold mismatch. Dynamic DCoffset is mainly created by second order distortion in the mixer. ACW in-band blocker creates a DC signal which can be calculated indecibel by

PDC = PIM2,in + GFE = (2Pbl − IIP2) + GFE (3.45)

where PIM2,in is the input referred distortion power due to a blockerof power Pbl and GFE is the gain of the front-end up to the point,where the DC offset is calculated.

The DC offset of the BBF can be modeled with the same schematicas the noise contribution of the amplifiers in Fig. 3.7, where the am-plifier noise sources have to be replaced by the input referred DCoffset of the amplifiers. The calculation can then also be performedequivalent to the case of noise contribution. As can be expected, theconclusion is, that the DC offset is dominated by the contribution ofthe first amplifier.


DC offset can be removed between different blocks or also withindifferent stages of a block. Capacitive AC-coupling can theoreticallybe used to remove the DC component, but this requires extremelylarge capacitors to process narrow band signals like GSM. ThereforeAC-coupling is not practical for baseband processing in integratedcircuits. Static DC offset can be compensated by a digital start-upcalibration [101]. For dynamic DC offset, CT compensation can beimplemented by means of a high-pass filter. In wideband RATs, a firstorder high-pass with a cutoff frequency of a few kHz can be toleratedand efficiently removes dynamic DC offset.

Chapter 4

Predistortion

The design of active-RC filters is usually based on the assumptionof ideal amplifiers. This approach is suitable if the gain and thespeed of the amplifier are sufficiently high, such that the amplifiernon-idealities can be neglected in the frequency range of interest.Using an amplifier with limited gain and speed results in a distortedtransfer function. If the filter has to process wideband signals, thepower consumption of the amplifier rises due to the increased speedrequirement. The dependency between power and speed is strongerthan linearly proportional and becomes very steep when approachingtechnology limits. In the first part of this chapter, it is shown howa proper transfer function can be achieved when taking the charac-teristic of the amplifier into account during the design of the filter.The finite amplifier speed can either be compensated with additionalcircuit elements or the filter can be designed to absorb the distortion.

The design of the amplifiers with respect to the specific require-ments for a predistorted filter is discussed in detail. The chosen archi-tecture and the approach to implement power efficient programmabil-ity are presented.

The last section of this chapter treats the linearity requirements ofthe filter. As can be expected, the amplifier is the main contributorto non-linearity in the BBF. Therefore, the required linearity sets alower limit to the amplifier speed.

81

82 CHAPTER 4. PREDISTORTION

4.1 Circuit non-IdealitiesThe most important non-idealities in active-RC circuits are linked tothe amplifier. The amplifier characteristic is far from ideal, especiallywhen power consumption is restricted and signal bandwidth is high.Integrated polysilicon resistors and Metal-Insulator-Metal (MIM) ca-pacitors have very good linearity and matching characteristics. Butundesired parasitic capacitances like gate-source and wiring capaci-tances have an impact on sensitive nodes. The quality of the virtualground at the amplifier input is given by the gain in the feedback loop.If the loop gain is low, the parasitic capacitance at the amplifier inputinfluences the circuit transfer function because it dumps current toground.

In the following, the effect of the circuit non-idealities is shown onthe example of a simple integrator.

4.1.1 Finite Amplifier Speed and GainThe amplifier can be modeled by a one pole system with finite DC-gain. The gain A (s) of the amplifier can thus be expressed as

A (s) = ADC

1 + sωp

= ωGBP

ωp + s=(

1ADC

+ s

ωGBP

)−1

Taking the gain of the amplifier into account, the transfer functionof the integrator shown in Fig. 4.1 evaluates to

H (s) = −11

A(s) + sRC(

1 + 1A(s)

) (4.1)

= −11

ADC+ sRC

(1 + 1

ADC+ s

ωGBP+ 1

ωGBP·RC

) (4.2)

HωGBP (s) ' −1sRC

(1 + s

ωGBP

) (4.3)

HADC (s) ' −11

ADC+ sRC

(4.4)

4.1. CIRCUIT NON-IDEALITIES 83

Figure 4.1: Active-RC integrator.

The effect of finite amplifier speed and DC gain are evaluated sepa-rately. The approximations in (4.3) and (4.4) assume 1 (ωGBP ·RC)−1

and ADC 1 respectively.The finite amplifier GBP introduces a second pole at ωGBP and

the finite amplifier DC gain shifts the integrator pole from the originto ωint = − (RCADC)−1. The DC gain of the amplifier is usuallylarger than 40 dB and therefore the influence of the limited GBPof the amplifier is predominant, especially when signals with largebandwidth are processed.

4.1.2 Parasitic CapacitanceParasitic capacitances at the virtual ground on the amplifier inputnode have a negligible impact as long as the loop gain is large. Equa-tion (4.7) shows the effect of a parasitic capacitance Cp at the inputnode of a amplifier with finite GBP on the integrator transfer function.For the approximation, 1 (ωGBP ·RC)−1 has been assumed.

H (s) = −1sRC + 1

A(s) (1 + sR (C + Cp))(4.5)

HωGBP (s) = −1sRC

(1 + 1

ωGBPRC+ s

ωGBP

(1 + Cp

C

)) (4.6)

' −1sRC

(1 + s

ωGBP

(1 + Cp

C

)) (4.7)

As a result, the pole introduced by the finite GBP of the amplifieris shifted to lower frequencies by the parasitic capacitance at the


amplifier input node. The influence of the parasitic capacitance mightgenerally be negligible because Cp is significantly smaller than theintegrating capacitor. But for a widely programmable filter, wherethe capacitance C and the resistance R are implemented by banks ofswitchable elements, Cp can be comparable to C for small nominalintegrating capacitances. In this case, Cp is the sum of the parasiticcapacitances of the switches at the virtual ground, the amplifier inputtransistors Cgs and the wiring capacitances.

4.2 CompensationThe amplifier is the predominant source of non-idealities in activeRC-filters. With appropriate measures, the resulting effect on thefilter transfer function can be compensated.

4.2.1 Integrator Phase Lag Compensation

(a) Inverting integrator (b) Inverting lossy integrator

Figure 4.2: Single-ended integrators with phase lag compensation

The additional pole introduced by the finite GBP of the am-plifier can be seen as a phase lag term in the integrator transferfunction [102]. The derivation in [102] is shown for a single-ended5th order leapfrog filter and also takes the second pole of the amplifierinto account. The influence of the non-dominant amplifier pole isactually negligible since this pole needs to be at least

√3 times larger

than the GBP for a reasonable phase margin of more than 60.

4.2. COMPENSATION 85

The idea of the phase lag compensation is to trim all integratorslocally to have the same phase lag as the integrating stage withthe highest phase lag. For the inverting integrator in Fig. 4.2(a),this is achieved with a properly sized additional capacitance Ca atthe amplifier input. The additional capacitance shifts the secondintegrator pole to the wanted frequency. In the case of inverting lossyintegrators as shown in Fig. 4.2(b), the components R’ and C’ can bemodified to adjust the phase lag. Phase lag compensation also worksfor the differential equivalents of the circuits in Fig. 4.2.

4.2.2 Zero Compensation

(a) Equivalent integrator circuitwith ideal amplifier, modeling thepole of the finite amplifier GBP.

(b) Compensation of the inductorby additional resistor Rc

Figure 4.3: Equivalent integrator circuits for zero compensation.

Another approach for compensation is to introduce a zero to cancelthe undesired pole [95]. The pole originating from the finite amplifierGBP can be modeled by an inductor in a circuit with ideal amplifieras shown in Fig. 4.3(a). The transfer function of this circuit is

Hind (s) = −1sRC

(1 + sLR

) (4.8)

where L = RωGBP

models the undesired pole.The compensation zero is created by an additional resistor Rc,

placed in series with the integrating capacitance as shown in Fig. 4.3(b).The transfer function then becomes

Hind,Rc (s) = − (1 + sRcC)sRC

(1 + sLR

) (4.9)


This means that the pole created by the finite amplifier GBP iscompensated if the resistance Rc is equal to

Rc = 1ωGBPC

(4.10)

4.3 Filter PredistortionInstead of compensating the effect of a non-ideal amplifier, the circuitcan also be predistorted, such that the poles shift to the desiredlocation when an amplifier with finite speed is used. This approach isadvantageous, because no additional components are required. Thisis especially important for a widely tunable circuit.

4.3.1 Predistortion PrincipleAlready in 1981, Davis [103] presented a method to predistort circuitsfor finite amplifier speed. A complex algorithm is used to describethe circuit in terms of desired pole frequencies and quality factors andamplifier transfer function. Finally a set of simultaneous nonlinearequations has to be solved for the predistorted pole locations. Fromthese poles, the circuit components to be realized can be calculated.In leapfrog filters, there is no closed form equation to calculate thedifferent poles from the circuit components, therefore the method isnot applicable to leapfrog architectures.

More insight into the mechanics of predistortion can be gained byinvestigation of the basic integrator circuit. As shown in Sec. 4.1.1,the integrator with a non-ideal amplifier, having a limited GBP, canbe modeled by a two-pole system. Since active-RC circuits are builtwith integrators, the effect of a non-ideal amplifier can be estimatedfrom the shifted integrator pole [104]. The exact transfer functionof the lossy integrator shown in Fig. 4.4(a) can be calculated withthe corresponding SFG in Fig. 4.4(b). With an ideal amplifier, thecurrent to voltage conversion transfer function Tid (s) is simply givenby

Tid (s) = Vout

IC= Rb

1 + sCRb(4.11)

4.3. FILTER PREDISTORTION 87

(a) Lossy integrator circuit (b) SFG of the lossy integrator

Figure 4.4: Schematic and signal flow graph of the lossy integrator.

Taking the finite gain A (s) of the amplifier into account, T (s) can becalculated from the SFG with forward path P0 and two loops M1 andM2 as

P0 = 1sC· A

A+ 1 (4.12)

M1 = −1sCRb

(4.13)

M2 = 1sC· −1A+ 1 ·

1Rx

(4.14)

T (s) = Rb

1 + CRb ·(s ·(1 + 1

A

)+ 1

A·C ·(

1Rb

+ 1Rx

)) (4.15)

where Rx = Rf‖Rb is the parallel combination of all resistors con-nected to the amplifier input node. Rx would also include furtherfeedback resistors if the integrator is used in a filter architecture.

In a loss-less integrator, where Rb → ∞, the transfer functionbecomes

T (s) = 1C ·(s ·(1 + 1

A

)+ 1

A·CRx

) (4.16)

Limited Amplifier GBP

Considering an amplifier with limited GBP and neglecting the finiteDC gain, the gain of the amplifier can be approximated by

A (s) ' ωGBP

s(4.17)


Inserting this approximation into (4.15) leads to

T (s) = Rb

1 + CRb ·(s+ s2

ωGBP+ K1·s

ωGBPCRb

) (4.18)

where K1Rb

= (Rb‖Rx)−1, with K1 ≈ 3 because Rb and Rf can beassumed to be approximately equal. Comparing (4.11) and (4.18)yields

s = s+ s2

ωGBP+ K1 · sωGBPCRb

(4.19)

where s denotes the frequency variable of the integrator with ideal am-plifier. The same observation can be made for the loss-less integrator,where a factor K1 ≈ 1 results. For a filter with non-ideal amplifiers,this means that each pole p will be split into a pair of dependent poles

p1,2 = −ωGBP

2 − |p|K1

2 ±

√(−ωGBP

2 − |p|K1

2

)2+ p · ωGBP

(4.20)where |p| ' (CRb)−1 is the pole frequency of the prototype filter withideal amplifiers. The dominant pole is a shifted version of p towardsthe imaginary axis and the other pole is located in the far Left HalfPlane (LHP). The trace of the poles is illustrated in Fig. 4.5 on theexample of a unity frequency pole with a quality factor of 7. Theamplifier GBP is indicated relative to the prototype pole frequency|p|. For very low GBP values, the shifted dominant pole even becomesunstable.

The predistortion of a filter is performed by calculating p as afunction of the desired pole location p and the amplifier GBP. There-fore, the GBP rather needs to be expressed relative to the desired polefrequency than relative to the predistorted prototype pole frequency.It follows

ωGBP = α · |p| (4.21)

p = p+ p2

α · |p|+ K1 · p · |p|

α · |p|(4.22)

Equation (4.22) can be solved for p if α > K1 as shown in App. C.1.Even if a solution exists for very low GBP values, it is obvious, that


−14 −12 −10 −8 −6 −4 −2 0 2−4

−2

0

2

4

10 5 3

Real

Imag

Ideal poles

Distorted

Dist. compl. conj.

(a) Pole splitting due to limited amplifier GBP

−0.2 0 0.20.4

0.6

0.8

1

1.2

100 50

25

10

5

3

(b) Trace of thedominant pole

Figure 4.5: Splitting of a pole with Q=7 for different amplifier GBP(the numbers indicate the ratio of GBP to prototype pole frequency).

the pole location should be dominated by the passive componentsand not by the amplifier GBP. Therefore the GBP should be at least15-20 times larger than the desired pole frequency (see App. C.2).This will result in a design, which is reasonably sensitive to variationsin the amplifier GBP.

The presented predistortion principle is based on the assumption,that all integrators are equal. But this is not always the case becausein a high order filter, there are lossy and loss-less integrators andresistors with different impedance levels. This effect is illustratedin Fig. 4.6, where the predistortion of a sixth order Chebyshev filteris shown. The amplifier GBP in this plot is indicated as a numberrelative to the desired pole frequency. For reasonably high GBP, thepredistortion is working fine, but if the GBP is below ten times thedesired pole frequency, then the resulting poles deviate from the ideallocations.

Parasitic Capacitance

The parasitic capacitance at the amplifier input node is degrading thetransfer function, if the amplifier has a limited GBP. The parasitic


−1 −0.5 00

0.2

0.4

0.6

0.8

1

1.2

50

25 10

5

Real

Ima

g

Ideal

Predistorted

Resulting

Figure 4.6: Predistorted poles and resulting poles of a 6th orderChebyshev filter for different amplifier GBP (the numbers indicatethe ratio of GBP to desired pole frequency).

capacitance can be included in the SFG shown in Fig. 4.4(b), byreplacing Rx by Zx with

Zx = Rx‖1sCp

(4.23)

where Cp is the total parasitic capacitance connected to the virtualground of the amplifier. The resulting transfer function of the inte-grator, using the GBP model for the amplifier, is given by

T (s) = Rb

1 + CRb ·(s+ s2

ωGBP· (1 +K2) + s · K1

ωGBPCRb

) (4.24)

where K2 = CpC is the ratio of parasitic capacitance to integrator

capacitance. The quality factor of the pole, resulting from the non-idealities, is further increased by the parasitic capacitance. This effectis getting stronger for low GBP. Therefore, the influence of the par-asitic capacitance needs to be taken into account when predistortingthe filter prototype.


Limited Amplifier DC gain

The influence of finite DC gain can be included if the amplifier ismodeled by

A (s) = ωGBP

s+ ωGBPADC

=(

s

ωGBP+ 1

ADC

)−1(4.25)

Calculating the integrator transfer function results in

T (s) = Rb

1 + CRb ·(s+ s2

ωGBP+ s ·

(K1

ωGBPCRb+ 1

ADC

)+ K1

ADCCRb

)(4.26)

A low DC gain reduces the magnitude and quality factor of the pole,thereby partly compensating the impact of limited GBP and parasiticcapacitance. But the DC gain needs to be very low, in the order of40 dB, such that this effect becomes noticeable. Generally, limitedDC gain affects the filter poles much less than limited amplifier speedand parasitic capacitance.

Combined Model

The effects of the three non-idealities presented in the previous sec-tions can be described in one combined model. The relation betweenthe predistorted prototype pole p and the desired pole p is given by

p = p2

ωGBP· (1 +K2) + p ·

(1 + K1 |p|

ωGBP+ 1

ADC

)+ K1 |p|

ADC(4.27)

where K1 ≈ 3 and K2 = CpC . The solution of this equation to calculate

the prototype pole p is shown in App. C.3.

4.3.2 Predistortion AlgorithmIn the previous section, it has been shown how the prototype filterpoles can be predistorted to compensate for the non-idealities of theamplifier. If a biquad architecture is chosen, the calculation of theactive RC circuit components is straight-forward. In the case of aleapfrog architecture, the process is more complex. If the values of


the inductors and capacitors of the prototype passive LC ladder filterare known, then the component values of stage i (see Fig. 3.3(a)) canbe calculated by [63]

Rfi = Rlf,i

ki(4.28)

Rbi = Rlf,i · ki (4.29)Rb1 = Rlf,1 (4.30)

RbN+1 = Rlf,N ·RS

RLor Rlf,N ·

RL

RS(4.31)

Ci = LLC,i

RS ·Rlf,ior CLC,i · RS

Rlf,i(4.32)

where the resistor values Rlf,i can be chosen freely, ki is the specifiedgain of stage i and the formula for RbN+1 and Ci depends on whetherthe last, respectively the i-th ladder element is an inductor or acapacitor.

If the filter is not predistorted, the required inductor and capacitorvalues for the passive prototype can be taken from filter tables. Thepredistortion modifies the pole locations and therefore the componentsof the LC ladder filter are changed. Starting with the filter transferfunction given in (3.8), the squared magnitude of the reflection coef-ficient ρ (s) can be calculated as

|ρ (s)|2 = 1− |H (s)|2 (4.33)

The reflection coefficient is then calculated by a specific proceduredescribed in [105]. The input impedance Z11 of the passive LC ladderfilter can be expressed as

Z11 = RS ·1± ρ (s)1∓ ρ (s) (4.34)

Finally the component values of the passive LC filter can be calculatedby successive long division of Z11. This process is based on Foster’sexpansion and continually removes poles at infinity [105].

The resulting transfer function of a predistorted sixth order Cheby-shev filter with 0.3 dB pass-band ripple and 10 MHz cutoff frequency


is shown in Fig. 4.7(a). The GBP of the amplifiers is 25 times higherthan the filter cutoff frequency and a ratio Cp/C = 0.3 has beenused. The transfer function of the non-predistorted filter shows a highpeaking of almost 8 dB close to the cutoff frequency. The predistortedfilter on the other hand slightly droops close to the cutoff frequency.The accuracy of the predistorted transfer function can be furtherimproved if the prototype poles are adjusted in an iterative process.After a few iterations, the resulting transfer function almost perfectlyaligns with the ideal one (see Fig. 4.7(b)).

104

105

106

107

108

0

2

4

6

8

Frequency [Hz]

Ga

in [

dB

]

Ideal

Predistorted

Not predistorted

(a) Comparison of simulated transfer functions with andwithout predistortion

104

105

106

107

108

−0.5

0

0.5

1

Frequency [Hz]

Ga

in [

dB

]

Ideal

Iterative predistorted

(b) Simulated transfer function of the filter after iterativepredistortion

Figure 4.7: Simulated filter transfer function of a sixth orderChebyshev filter with amplifier GBP of 25 times the cutoff frequency.


4.4 Frequency Scaling with Predistortion

The active RC filter with ideal amplifiers can be scaled for frequencyand gain tuning simply by modifying the capacitor and resistor values.It is desirable that scaling the predistorted prototype filter cutofffrequency by a certain factor β leads to a resulting cutoff frequency,which is scaled by the same factor. Expressed in terms of the modelin (4.27), this means p′ = β ·p should result from p′ = β · p. Exploring(4.27) gives

p′ = β ·[

p2

ωGBP· (1 +K2) + p ·

(1 + K1 |p|

ωGBP+ 1

ADC

)+ K1 |p|

ADC

]= (βp)2

βωGBP· (1 +K2) + βp ·

(1 + K1 |βp|

βωGBP+ 1

ADC

)+ K1 |βp|

ADC

For proper frequency scaling of the predistorted filter transfer func-tion, the GBP of the amplifier needs to be scaled with the cutofffrequency. This is actually highly appreciated, since it allows toscale the amplifier power consumption with the filter cutoff frequency.Additionally the DC gain of the amplifier needs to stay constant aswell as the ratio K2 = Cp/C of the parasitic capacitance to theintegration capacitance. The former is not very critical, because theamplifier DC gain has a minor impact on the transfer function. Thelatter on the other hand will affect the transfer function, because theparasitics do not scale proportional to the integration capacitance.This issue can be avoided if a constant-C scaling scheme is applied,where the frequency is modified by changing only the resistors [89].Due to the wide range of frequency tuning, this is not applicable to thedesigned BBF. It is also possible to add artificial parasitics to forcethe factor K2 to be constant, but this consumes excess area and isdifficult to be implemented reliably. It has been decided to predistorteach exponential CFS setting separately and to tolerate the moderatedistortion on the transfer function, which results from FFS frequencytuning.

4.5. GAIN SCALING WITH PREDISTORTION 95

4.5 Gain Scaling with PredistortionProgrammable gain is implemented with programmable resistors. Thegain of each stage i of the leapfrog filter can be scaled by a factorki, if the corresponding feedforward and feedback resistors are scaledby Rfi/ki and Rbi · ki respectively. This modifies the RC product,which has been assumed to be equal to the pole frequency in thepredistortion derivation. The gain of each stage can be modifiedindependently, conflicting the assumption that all integrators havethe same environment. Therefore scaling the filter gain will affect thepredistortion of the transfer function. For a moderately high amplifierGBP, the variation due to gain scaling may be tolerable and can bereduced if the predistortion is performed on a medium gain setting.This has the advantage, that 6 dB gain scaling can still be performedby strict factor 2 resistor scaling and is compatible to CFS frequencyscaling.

If the amplifier GBP is low and an accurate filter transfer functionis required, then each gain setting needs to be predistorted sepa-rately for every CFS frequency setting. This will result in a largeset of resistor values that is composed of several groups, separatedby roughly a factor of two. In each group, there are several resistorvalues to be realized and their values differ only by some percent. Thisleads to a challenging resistor array implementation since even moredifferent values need to be realized accurately. A possible approachis shown in Fig. 4.8, where a parallel resistor array for coarse resistorprogramming is combined with a R-2R ladder resistor, providing awidely tunable large parallel resistance for resistor fine tuning. Theresistors RL,fix,i are required to increase the input impedance of theR-2R ladder, which loads the preceding amplifier. But this methodsuffers from several drawbacks. The switches in front of the R-2Rladder are not at virtual ground and the large number of switchesleads to high complexity. And since an amplifier with low GBP isused, the virtual ground is not very well defined, leading to inaccurateR-2R ladder transresistance.

Due to these drawbacks, another approach has been taken. First,all required values have been calculated for every resistor Rf,bi.For each of these resistors, the values are represented by the setof the lowest number of resistors, such that each required resistor


Figure 4.8: Combination of a parallel resistor array and a R-2R ladderresistance to implement a large range of resistor values with limitedfine-tuning provided by the R-2R ladder.

can be approximated with a maximum chosen percental error. Thisset is implemented by a parallel resistor array and a digital controlcircuit selects the correct resistor element for every gain and frequencysetting. The area overhead of this method is moderate, because theimplemented resistor programmability is very specific and can notgenerally be modified to any value as in the case of a R-2R ladder.The complexity can also be handled, since the parallel resistor arrayis a very regular structure.

4.6 Filter Architecture with Predistortion

It has already been shown in Sec. 3.3, that leapfrog filters have lowersensitivity to component variations than biquad filters if ideal ampli-fiers are assumed. In the following, the effect of amplifier non-idealitiesis investigated.

4.6.1 Sensitivity with non-ideal Amplifiers

The sensitivity of the filter poles with respect to the amplifier GBP canbe calculated by solving (4.27) for p. The derivation for all sensitivities

4.6. FILTER ARCHITECTURE WITH PREDISTORTION 97

is shown in App. B.2. For poles with high quality factors, ωp ' Im pcan be assumed and the sensitivity results as

SωpωGBP

≈ K1 |p|ωGBP

(4.35)

SQpωGBP

≈ −2Qp |p|ωGBP

(4.36)

The sensitivity for poles with low quality factor can be approximatedas

SωpωGBP

≈ (K1 − 1) |p|ωGBP

(4.37)

SQpωGBP

1 (4.38)

The equations above show that the sensitivity generally is propor-tional to the ratio of prototype pole frequency to amplifier GBP.Further, poles with high quality factor are more sensitive to variationsin GBP than poles with low quality factor. Sensitivity of the polefrequencies and quality factors with respect to the ratio K2 = Cp/Cis roughly K2 times the sensitivity to GBP variations. The sensitivitywith respect to amplifier DC gain ADC is proportional to 1/ADC andtherefore very small.

The effect of component variations with limited amplifier GBPhas been investigated by Matlab simulations. The circuit transferfunction has been calculated for a predistorted filter, modeling theamplifier with a finite GBP assumption. Fig. 4.9(a) and Fig. 4.9(b)show the resulting transfer functions, if all resistor and capacitorvalues as well as the amplifier GBP is subject to random variation.The ideal transfer function is highlighted in red. The filter exampleis a sixth order Chebyshev filter with 0.3 dB pass-band ripple and10 MHz cutoff frequency. The amplifier GBP is 250 MHz, whichis only 25 times higher than the cutoff frequency. The standarddeviations used for the 10’000 samples are σR = σC = 0.5% for theresistors and capacitors and σGBP = 5% for the amplifier GBP. Thedeviation of the resulting transfer function from the ideal one is shownin Fig. 4.9(c) and Fig. 4.9(d).

Generally, the leapfrog architecture still has lower variation intransfer function magnitude, but the maximum pass-band deviation,


(a)Leapfrog

filtertransfer

function(b)

Biquad

filtertransfer

function

(c)Leapfrog

filterdeviation

fromidealT

F(d)

Biquad

filterdeviation

fromidealT

F

Figure4.9:

Simulated

filtertransfer

functionsofa

6thorder

Chebyshev

leapfrogand

biquadfilter

with

lowam

plifierG

BPand

randomvariation

inthe

valuesofpassive

components

andG

BP(N

=10’000).

4.6. FILTER ARCHITECTURE WITH PREDISTORTION 99

which is highlighted in red, is very similar to the biquad architecture.This illustrates that the low sensitivity property of the leapfrog filteris diminishing, because it loses the equivalence to the passive LC filtercounterpart due to low amplifier speed.

4.6.2 Stability in Saturation

Transistor mismatch in the amplifiers causes DC offset and will satu-rate the filter output, if it is not compensated. During the DC offsetcompensation process, the correct calibration code is found in a linearor binary search. For a proper operation, the filter needs to recoverfrom saturation and to settle within a reasonable time, usually limitedby the filter low-pass characteristic.

Saturation in a biquad filter architecture is not an issue, because itwill shut down separate independent stages. In the case of the leapfrogarchitecture, saturation of separate stages will modify the overalltransfer function, because all stages have an influence on all poles.The resulting filter order depends on the number of saturated stagesand the locations of the poles is defined by the remaining unsaturatedpart of the circuit. Fig. 4.10 shows the pole locations of a sixth orderChebyshev leapfrog filter, where the amplifiers have a GBP of 25 timesthe filter cutoff frequency. The poles of the predistorted filter matchwith the ideal locations, while the poles of the non-predistorted filterdeviate. If the last stage is saturated, the remaining circuit representsa fifth order filter. The poles of the remaining filter are stable in thecase of the non-predistorted filter. The predistorted filter in contrastresults in an unstable circuit if the last stage is saturated.

This effect severely degrades the functionality of the DC offsetcompensation algorithm, because the resulting calibration code maybe wrong and the circuit may even not recover from instability. Asa consequence, the leapfrog architecture should only be used withmoderately high speed amplifiers or non-predistorted filters, wherestability is guaranteed. For predistorted circuits with low amplifierGBP, the biquad architecture is favorable.


−10 −8 −6 −4 −2 0 2−2

0

2

4

6

8

10

12

14

Real [MHz]

Imag [M

Hz]

Ideal

Predist.

Predist. 1 stage sat.

Not predist.

Not predist. 1 stage sat.

Figure 4.10: Pole locations of a sixth order Chebyshev leapfrog filter,predistorted and non-predistorted. If the last stage is saturated,a 5th order filter remains, which turns unstable in the case of thepredistorted filter.

4.7 AmplifierThe design of the amplifiers to be used in the active RC circuitdepends on the required speed, gain, load, programmability and powerconsumption. As shown in the previous section, the amplifier GBPshould be about 50 times the cutoff frequency for a leapfrog circuitand can be lowered to about 25 times the cutoff frequency for biquadarchitectures. The GBP needs to be scalable proportional to the cutofffrequency to maintain predistortion, thereby saving power for lowerGBP values is desirable. A moderate DC gain in the order of 60 dBis sufficient to avoid effects on the filter poles.

The resistive and capacitive load defines the required driving ca-pabilities of the amplifier and has also an influence on power con-sumption. Resistor and capacitor values are calculated during thefilter design process. Noise and area requirements limit the maximum

4.7. AMPLIFIER 101

resistor and capacitor values to be used. The largest capacitance canbe estimated from the lowest cutoff frequency of 150 kHz and themaximum resistance value of 60 kΩ. Taking a gain scaling factor of4 into account, results in a maximum capacitance in the order of4.4 pF. The lowest resistor value is approximated from a 40 MHzcutoff frequency with 16-fold capacitor scaling and a gain scalingfactor of 4, which gives a resistance of 0.9 kΩ. While the exact drivingrequirements depend on the exact filter implementation and gain dis-tribution among the stages, the approximation gives a good startingpoint.

The power consumption of the filter should be low, because thetarget application is a mobile device with limited battery capacity.The power efficiency of the amplifier is especially important for RATswith large bandwidth, where a high GBP is required. For narrowband standards like GSM, there is no point in optimizing the designfor the lowest possible power consumption, because the BBF is onlyone part of a transceiver circuit. Once the power consumption of theBBF is in the order of a few milliwatt, a further reduction does notlead to significant gain for the overall system, because the total powerbudget for the transceiver circuit is about 370 mW [18]. For largesignal bandwidths, the power consumption of the BBF can still besignificant, because two filters are required for I- and Q-path, or evenmore in the case of a diversity receiver.

4.7.1 ArchitectureA single stage amplifier is not suitable for the BBF, because the lowresistive load would annihilate the amplifier gain. Therefore, at leasttwo stages are required in the architecture, where the main purposeof the output stage is to provide the current to drive the resistive andcapacitive loads.

Miller Amplifier

The popular Miller architecture is well suited to drive resistive loads,but suffers from reduced speed, compared to other architectures. Theschematic of a fully differential two stage Miller amplifier with class-AB output stage is shown in Fig. 4.11. Setting RAB = 0 Ω, CAB = 0 F


Figure 4.11: Schematic of a two stage Miller Amplifier with class-ABoutput stage.

Figure 4.12: Small signal equivalent of the two stage Miller Amplifier.

4.7. AMPLIFIER 103

and modeling the transistor M6 by a resistor Rz, reveals the classicMiller compensated architecture.

The small-signal equivalent circuit of the classic Miller amplifieris shown in Fig. 4.12. The resistive and capacitive load are includedin the components R2 and C2 respectively. The small-signal transferfunction can be approximated by three poles and one zero as [106]

A (s) = vout

vin'

ADC ·(

1 + sωz

)(

1 + sωp1

)(1 + s

ωp2

)(1 + s

ωp3

) (4.39)

where a large separation of the poles has been assumed. The DC gainand the pole and zero frequencies can be calculated by

ADC ' gm1R1gm2R2 ωz '1

Cc

(Rz − 1

gm2

) (4.40)

ωp1 '1

CcR1gm2R2ωp2 '

gm2

C2ωp3 '

1C1Rz

(4.41)

assuming gm2R2 1, C1 Cc, C1 C2, R1 Rz and R1 R2.The gain-bandwidth product of the Miller amplifier is given by

ωGBP = ADCωp1 'gm1

Cc(4.42)

and thus depends only on the transconductance of the input differ-ential pair and the compensation capacitor. Implementing program-mable speed is particularly simple for a Miller amplifier, because thiscan be achieved by a tunable Miller compensation capacitance or bya programmable transconductance of the first stage. The zero can beused to cancel the second pole of the amplifier. From ωz = ωp2, itfollows for Rz and ωp3

Rz 'Cc + C2

Ccgm2ωp3 '

Ccgm2

C1 (Cc + C2) (4.43)

The resistance Rz is implemented by transistor M6, which is biasedin the triode region, since no DC current is flowing through thetransistor. Therefore Rz can be written as [106]

Rz = ∂vds6

∂id6

vds6=0

= 1K ′nW6

L6(Vgs6 −Vth)

(4.44)


where the MOSFET hand calculation model in App. C.5 has beenused. Transistor M12 is designed to emulate M2, therefore Vgs6 = Vgs11.If M6 and M11 are matched and of the same type as M2, the followingcondition must be met for pole-zero cancellation, assuming a squarelaw transistor approximation

W6

L6= Cc

Cc + C2·√W11W2I2L11L2IRz

(4.45)

The advantage of this scheme is, that pole-zero cancellation is main-tained under PVT variations and also for different bias currents I2,as long as IRz is scaled proportional to I2.

The stability of the amplifier in an integrator configuration canbe analyzed by the Phase Margin (PM) of the return ratio [107].Assuming Cfb Cin and Cfb C2, the PM can be approximated as

PM (RR) ≈ 90 − arctan(ωGBP

ωp3

)(4.46)

≈ 90 − arctan(ωGBPC1

gm2·(

1 + Ctot

Cc

))(4.47)

where Ctot = C2 + Cin.

Class-AB Output Stage

The classic Miller amplifier has a class-A output stage, which meansthat the bias current of the output stage needs to be larger than themaximum current required to drive the loads. If the bias current is toosmall, slewing will introduce significant distortion and the amplifiermay need additional time to recover afterwards. In a class-AB archi-tecture, the output stage delivers large current only when it is requiredto drive the load. If no signal is present, only a small quiescent biascurrent is flowing in the output stage. Usually, additional circuitry isrequired to control the quiescent current of the output stage [108,109]This results in increased area and reduced power efficiency if onlymoderate loads are driven and can also cause stability issues. Anelegant solution to add class-AB functionality to a Miller amplifier isshown in Fig. 4.11. The output signal of the first stage is capacitivelycoupled to the current source transistor M7 by the coupling capacitor

4.7. AMPLIFIER 105

CAB [110]. The bias point of M7 is defined by the current mirroredfrom M9 as in the classic Miller amplifier. Class-AB operation isworking for frequencies above

ωAB = 1RABCAB

(4.48)

and the transconductance of the output stage is improved to

Gout = gm2 + gm7 ·Cc

Cc + Cgs7(4.49)

therefore Cc Cgs7 should be used. For very large signals, oneof the two output transistors M2 and M7 will be shut down, whilethe other can provide significantly larger current than in quiescentstate. The frequency dependent class-AB operation is well suited forapplication in cellular radios, because the strong blocking signals arelocated at higher frequencies. This allows to choose ωAB moderatelylarge for an acceptable startup behavior of the amplifier, while thefirst strong GSM blocker is handled with class-AB operation. TheOFDM signal rarely reaches the maximum voltage level due to itshigh PAPR ratio, therefore significant power saving can be achievedwith class-AB operation for OFDM based RATs.

Alternative Architectures

The major drawback of the Miller compensated amplifier is that speedis sacrificed for stability. The pole splitting due to the Miller effectreduces the dominant pole frequency and thereby also the amplifierGBP. This leads to high power consumption for large GBP require-ments. The two-stage feedforward compensation scheme uses a differ-ent approach to ensure stability [89,111,112]. The corresponding blockdiagram is shown in Fig. 4.13. A feedforward path is introduced inparallel to the two-stage path and creates a LHP zero, which is placedto cancel the second pole. No Miller capacitance is added, thereforethe achievable GBP can be very large and is defined by the first poleωp1 = (ro1C1)−1 as

ωGBP = gm1

C1gm2ro2 (4.50)

The location of the zero can be approximated by [111]


Figure 4.13: Block diagram of the two-stage feedforward compensatedamplifier.

ωz1 ' −gm1gm2

C1gm3(4.51)

Theoretically, this circuit can achieve very high GBP values with 90phase margin, assuming perfect pole-zero canceling and neglectinghigher order poles. In practice, a robust cancellation of the poleωp2 = (ro2C2)−1 with the LHP zero is difficult. The second poledepends on resistive and capacitive load, or even worse, on the tran-sistor properties in the case of low loading. The zero on the otherhand depends on the GBP and the transconductance ratio of thesecond stage and the feedforward stage. Therefore, maintaining anaccurate cancellation for PVT variation is a challenging task. If theloading condition is largely varying, as in the case of a BBF withwide frequency and gain programmability, this task becomes hardlymanageable. In the specific case of predistortion, a well controlledGBP is also required and this is not possible as long as C1 is given bycircuit parasitics.

Multi-stage architectures can offer increased DC gain, but sufferusually from reduced GBP. Most architectures are based on the nestedMiller principle, where repetitive pole splitting is applied to guaranteestability [113–115]. Even with the employed methods to improve thespeed of multi-stage architectures, they are not competitive comparedto the two-stage Miller architecture, as long as DC gain is not an issue.

Consequently, the two-stage Miller compensated architecture hasbeen chosen for the amplifier, because it offers the best robustness andprogrammability for the varying loading conditions and reasonablepower consumption for the required speed.

4.7. AMPLIFIER 107

4.7.2 Amplifier ProgrammabilityThe speed of the amplifier has to be programmable proportional to thefilter cutoff frequency for a proper filter predistortion. The accuracyof the GBP needs to be better if the ratio of GBP to filter cutofffrequency is low.

Programmable GBP

The GBP of the Miller compensated amplifier is given by

ωGBP = gm1

CC=

√2K ′W1

L1Id1

CC(4.52)

where the square-law approximation has been used for gm1. Theamplifier is preferably designed for the largest required speed, becausekeeping sufficient PM is much easier while scaling the GBP down,than if the GBP needs to be increased. Different scaling strategieswith constant PM can be worked out. From (4.47), it follows that thetransconductance of the second stage needs to scale proportional to

gm2 =√

2K ′W2

L2Id2 ∝ ωGBP (4.53)

for a constant PM. If the GBP is scaled down, this allows to savepower in the second stage by reducing the bias current. But gm2 canalso be kept constant, since this will increase the PM if the GBP isreduced. The bias current in the second stage may not be scaled tovery low levels, because of load driving requirements.

The available parameters for programmability are the width andthe bias current of the transistors as well as the compensation capac-itance. It has to be taken into account, that the gate-source voltageof a transistor will change, if the product Wi ·Idi is not kept constant.This will change the operation point and can cause headroom issues.The width of transistor M1 and M2 should be scaled proportional,because this can be implemented by switching the current mirrortransistors M3 and M7 on several parallel sections of M1,2. If thesetwo transistors are not scaled proportional, a switch needs to be placedin the signal path, which should be avoided.


The amplifiers for the BBF designed in this thesis are programma-ble by means of bias current scaling and programmable compensationcapacitance. Avoiding to scale the transistor size eases the layout ofthe circuit and reduces the number of switches in the design.

Accurate GBP

Figure 4.14: Constant-gm biasing circuit.

If the ratio of GBP to filter cutoff frequency is large, a moderatelyaccurate transconductance is sufficient and a constant reference cur-rent can be used to bias the amplifiers. The lower the ratio is, the moreaccurate should the value of the GBP be, and a constant-gm biasingscheme is required [116, 117]. Fig. 4.14 shows a simple constant-gmbiasing circuit based on the square-law approximation model. Thewidth of transistor Mb2 is four times as large as the width of transistorMb1 and the NMOS current mirror forces the same current Id in bothbranches. Assuming square-law behavior for the transistors Mb1,2,it follows

Vgs2 = 12 (Vgs1 + Vth) (4.54)

Id · Rb = Vgs1 −Vgs2 = 12 (Vgs1 −Vth) (4.55)

2Id

Vgs1 −Vth= gmb1 = 1

Rb(4.56)

If transistor Mb1 is designed to match the amplifier input differentialpair M1, then the transconductance gm1 is proportional to the inverseof the resistance Rb. This bias scheme needs a startup circuitry, that

4.7. AMPLIFIER 109

avoids the undesired state, where no current is flowing in the twobranches of Fig. 4.14.

The accuracy of the absolute value of integrated polysilicon resis-tors is very poor. This can be avoided, if Rb is implemented as anoff-chip component, but adding an extra off-chip element is undesir-able. The exact value of gm1 is not crucial, because the importantcharacteristic is the GBP, i.e. the ratio gm1/CC. An accurate GBPcan be achieved, if Rb is matched to the resistor element used in thefilter resistor array, and the compensation capacitor is tuned with thecalibration code from the RC-tuning circuit. The tuning resolution ofthe compensation capacitor is not required to be as accurate as for theintegration capacitance, a resolution in the order of 5% is sufficient.Bias current programmability can be implemented in the resistor Rbby a binary scaled array of parallel resistor elements.

4.7.3 Noise and DC OffsetThe amplifier of the first filter stage dominates the noise and DC offsetcontributed by the amplifiers. Therefore it is worth to optimize thefirst amplifier for lower noise and DC offset, while the amplifiers of thesubsequent stages should be optimized for low power consumption.

Noise

The input referred noise of the two-stage amplifier shown in Fig. 4.11is dominated by the first amplifier stage and can be expressed as

VN1,in2

∆f = VN1,th2

∆f + VN1,f2

∆f (4.57)

VN1,th2

∆f = 8kTγgm1

·(

1 + gm5

gm1

)(4.58)

VN1,f2

∆f = Kf

2fCoxK ′·(

1W1L1

+ 1W5L5

· gm5

gm1

)(4.59)

where VN1,th2 and VN1,f

2 represent the thermal noise and the flickernoise respectively. The thermal noise can be reduced by increasing gm1and low flicker noise is achieved with large transistor area. Generally,


the contribution of the active load M5 can be reduced by increasingthe ratio gm1/gm5. This is also the reason, why a cascode transistorhas been avoided on top of M5 and a large channel length L5 is usedinstead. In Sec. 3.5, 22 nV/

√Hz has been defined as the maximum

allowed noise contribution for the first amplifier.

DC Offset

Equivalent to the noise contribution, the DC offset is also dominatedby the transistors M1 and M5 of the amplifier of the first filter stage.The standard deviation of the input referred DC offset is given by

σ2Vof,in

= σ2Vof,M1

+ σ2Vof,M5

·(

gm5

gm1

)2(4.60)

where the DC offset standard deviation of a transistor pair is domi-nated by threshold mismatch and can be approximated as

σVof,Mi' Avt

WiLi(4.61)

where Avt is a technology dependent threshold voltage mismatch co-efficient. The inverse proportionality to the transistor area can leadto a significant DC offset contribution by the active load M5. The DCoffset compensation range of the digital DC offset calibration needsto be larger than 4 · σVof,in for a 4-σ design.

4.8 LinearityActive RC circuits combine linear feedback elements and high loopgain TL (s). Therefore, the distortion signals due to the non-linearamplifier characteristic are attenuated by a factor (1 + TL (s)) at theoutput and very high linearity can be achieved. Using an amplifierwith low GBP leads to reduced loop gain, which is especially promi-nent at the filter cutoff frequency. If the GBP is 25 times larger thanthe cutoff frequency, 28 dB of amplifier gain is available at the signaledge. This gain is further reduced if the signal is amplified, as it isthe case in the BBF. Only 16 dB excess gain is left, for a 12 dB signalamplification.

4.8. LINEARITY 111

In fully differential circuits, second order distortion is very low andmainly depends on the matching of the circuit elements. Thereforethird order distortion due to transistor non-linearity is more critical.

A general non-linear system can be modeled by the polynomial

Vout = α0 + α1Vin + α2V 2in + α3V 3

in (4.62)

where the coefficients α0 and α2 are not of interest for third orderdistortion. In a two-tone test, the input signal is given by

Vin = Vm1 cos (ω1t) + Vm2 cos (ω2t) (4.63)

which results in a third order intermodulation product of

VIM3 = 34α3V 2

m1Vm2 · cos ((2ω1 − ω2) t) (4.64)

and for Vm1 = Vm2 = Vm/√

2, this simplifies to

VIM3 = 34α3

(Vm√

2

)3· cos ((2ω1 − ω2) t) (4.65)

The corresponding IIP3 is found by setting the amplitude of theintermodulation product equal to the amplitude of the fundamentalVf = α1Vm cos (ωft) and solving for V 2

m

IIP3 = 10 · log10

(8√

23 · α1

α3

)+ 10 dB [dBm] (4.66)

4.8.1 Differential Pair Non-LinearityThe differential pair of the amplifier is often operated in moderateinversion for its better transconductance efficiency compared to thestrong inversion operation region. Nevertheless, the strong inversionsquare law approximation is used in the following to estimate the thirdorder non-linearity of the differential pair shown in Fig. 4.15 [99]. Thedifferential input voltage can be expressed as

Vin = Vgs1 −Vgs2 =√

2β

(√Id1 −

√Id1

)(4.67)


Figure 4.15: Differential pair schematic.

where β = µCoxW/L. (4.67) can be reformulated to calculate thedifferential output current as

∆Id = Id1 − Id2 = β

2 Vin

√4ISS

β−V 2

in (4.68)

with V 2ov = (Vgs −Vth)2 = ISS/β, this results in

∆Id = βVinVov

√1− V 2

in4V 2

ov' gmVin −

gm

8V 2ov

V 3in = αI,1Vin + αI,3V 3

in

(4.69)where the square root has been approximated by the second orderTailor series. Using (4.66), the IIP3 of the differential pair can directlybe calculated as

IIP3 = 10 · log10

(64√

23 V 2

ov

)+ 10 dB [dBm] (4.70)

4.8.2 Second Stage Non-LinearityThe second stage of the Miller amplifier also contributes to the non-linearity. Third order distortion by a single transistor is not modeledby the simple square-law approximation. Taking mobility degradation

4.8. LINEARITY 113

into account (see App. C.5), the drain current of a NMOS transistorin the saturation region can be expressed as

Id = β

2 ·(Vgs,0 + vg (t)−Vth)2

1 + θ · (Vgs,0 + vg (t)−Vth) (4.71)

where Vgs,0 is the gate-source voltage in the operating point, vg (t) isthe small signal gate-source voltage and θ is the mobility degradationcoefficient. The coefficients for the polynomial representation can thenbe derived from the Taylor series as

αII,1 = dId

dvgαII,3 = d3Id

dv3g· 1

3! (4.72)

The corresponding calculation is shown in App. C.4 and results in

αII,1 = gm αII,3 ' −gm · θ2Vov

(4.73)

The resulting IIP3 is calculated as

IIP3 = 10 · log10

(16√

23 · Vov

θ

)+ 10 dB [dBm] (4.74)

4.8.3 Lossy Integrator Non-LinearityThe first filter stage of the BBF attenuates the strong blocking signalsbefore they are fed into the subsequent stages. Therefore, the linearityis dominated by the first amplifier, which is configured as a lossyintegrator as shown in Fig. 4.16.

Differential Pair

An intuitive approach to calculate the harmonic distortion in feedbackamplifiers has been presented in [118]. The method can be used tooptimize a filers dynamic range and power consumption [94]. Whileit can be useful for a fixed gain, fixed frequency filter, this optimiza-tion approach is not well suited for widely tunable filters, becauseexcessively large capacitors can result from the optimization process.


Figure 4.16: Lossy integrator schematic.

The amplitude of the blocking signals from a two-tone test can beapproximated at the amplifier input as

Vx,bl1 = Vm√2· |H (jωbl1)||A (jωbl1)| (4.75)

Vx,bl2 = Vm√2· |H (jωbl2)||A (jωbl2)| (4.76)

where A (s) is the frequency dependent amplifier gain and H (s) is thetransfer function of the lossy integrator, which can be approximatedas

H (s) ' −Rb

Rf· 1

1 + sRbC(4.77)

if the influence of the finite amplifier gain is neglected. The amplitudeof the distortion product created by the amplifier differential pair,referred to the amplifier input node, can be expressed as

Vx,IM3,I = 34 ·

αI,3

αI,1V 2

x,bl1Vx,bl2 (4.78)

This signal can be seen as an injected spurious signal, which is pro-cessed by the integrator circuit. The amplitude at the output of theintegrator is then calculated by

Vout,IM3,I = Vx,IM3,I ·|A (jωIM3)||1 + T (jωIM3)| (4.79)

where T (s) is the loop gain, which is equal to

T (s) = A (s) · Rf · (1 + sRbC)Rf · (1 + sRbC) + Rb

(4.80)

4.8. LINEARITY 115

and can be approximated as T (s) ≈ A (s) for frequencies far abovethe filter cutoff (s (RbC)−1) or as T (s) ≈ A (s) ·Rf/ (Rf + Rb) forfrequencies well below the filter cutoff (s (RbC)−1). The IIP3 of theintegrator circuit can be calculated by equating the distortion productwith the fundamental Vout,f = Vm · |H (jωIM3)| at the integratoroutput and solving for Vm. The frequency ωIM3 of the intermodulationproduct is equal to the frequency of the wanted signal and lies in thefilter pass-band. The resulting IIP3 is

V 2m,IIP3 = 64

√2

3 V 2ov ·|A (jωbl1)|2 · |A (jωbl2)||H (jωbl1)|2 · |H (jωbl2)|

· Rb

Rf + Rb(4.81)

where T (s) 1 has been assumed and the pass-band transfer func-tion has been approximated by |H (jωIM3)| ≈ Rb/Rf .

For the filter pass-band linearity, where ωbl1 and ωbl2 are smallerthan the filter cutoff frequency, (4.81) can be simplified to

V 2m,IIP3 = 64

√2

3 V 2ov ·|A (jωbl1)|2 · |A (jωbl2)|

(Rb/Rf)3 · Rb

Rf + Rb(4.82)

resulting in a high linearity, which scales with the ratio of amplifiergain to transfer function gain.

In the filter stop-band, the IIP3 still depends on the ratio ofamplifier gain to transfer function gain, but will have a lower value andis frequency independent if A (s) and H (s) both show a single-polecharacteristic, as it is the case for a Miller compensated amplifier anda simple integrator.

Output Stage

The linearity due to the amplifier output stage can be calculated witha similar reasoning as in the case of the differential pair. First, the two-tone signal amplitude is calculated at the gate of the output transistorsby dividing the signal at the output by the gain of the second stage

Vg,bl1 = Vm√2· |H (jωbl1)|αII,1RL,eff

(4.83)

Vg,bl2 = Vm√2· |H (jωbl2)|αII,1RL,eff

(4.84)


where αII,1 = gm2 and RL,eff is the effective load resistance at theoutput of the amplifier. The distortion product resulting from non-linearity of the second stage can be seen as a spurious signal injectedat the gate of the output transistor with amplitude

Vg,IM3,II = 34 ·

αII,3

αII,1V 2

g,bl1Vg,bl2 (4.85)

The amplitude of the corresponding distortion at the amplifier outputis then calculated as

Vout,IM3,II = Vg,IM3,II ·αII,1

|1 + T (jωIM3)| (4.86)

Which results in an IIP3 of

V 2m,IIP3 = 16

√2

3 · Vov

θ· |A (jωIM3)| (gm2RL,eff)2

|H (jωbl1)|2 · |H (jωbl2)|· Rb

Rf + Rb(4.87)

In the filter pass-band, this equation can be simplified to

V 2m,IIP3 = 16

√2

3 · Vov

θ· |A (jωIM3)| (gm2RL,eff)2

(Rb/Rf)3 · Rb

Rf + Rb(4.88)

Comparing the pass-band linearity of the differential pair in (4.82)with the linearity of the output stage in (4.88), it is obvious thatthe output stage has lower IIP3, because of the missing gain of thefirst amplifier stage. In the stop-band, the output stage has higherlinearity, because the gain of the output stage falls off at much largerfrequencies than the overall gain of the amplifier.

Fig. 4.17 shows the IIP3 of the two amplifier stages according to(4.81) and (4.87), plotted against the frequency of the first blocker.The lossy integrator has a pass-band gain of 12 dB and a 3 dBfrequency of fc = 10 MHz. The frequency of the second blockeris chosen as fbl2 ≈ 2 · fbl1, such that the intermodulation productfrequency is near DC. The parameters for the calculation are listed inTbl. 4.1.

As derived in the filter specifications, the IIP3 of the BBF needs tobe larger than 20 dBm (see Tbl. 2.11, p. 48). Therefore an amplifierGBP in the order of at least 25 times the cutoff frequency is targetedin the design, which is also consistent with the requirements of thefilter predistortion.

4.8. LINEARITY 117

104

105

106

107

108

109

0

10

20

30

40

50

60

70

80

90

100

GBP = 500 MHz

GBP = 500 MHz

GBP = 250 MHz

GBP = 250 MHz

First blocker frequency [Hz]

IIP

3 [dB

m]

Differential pair

Second stage

Figure 4.17: IIP3 of a lossy integrator with 12 dB gain and 10 MHzcutoff frequency due to non-linearity in the amplifier differential pairand second stage.

Table 4.1: Parameters for the calculation of the lossy integratorlinearity.

GBP 500 MHz 250 MHzVov1 150 mV 75 mVVov2 400 mV 200 mVgm2 10 mS 5 mSθ2 1.8 V−1

R1 1 kΩR2 4 kΩRL,eff 2 kΩ

Chapter 5

ImplementedMulti-StandardBaseband Filters

Two multi-standard baseband filters for cellular communication havebeen implemented in a 130 nm CMOS technology. The design con-cepts described in the previous chapters have been used to realize sixthorder analog lowpass filtering with a wide range of gain and frequencyprogrammability and low power consumption.

The first design offers 8 discrete cutoff frequency settings withlimited fine-tuning range to support 2G, 3G and LTE cellular commu-nication. This design has been successfully fabricated in two versions,one with strict use of a unit resistor element and the other withnon-unit resistors.

The cutoff frequency of the second design can be tuned quasi-continuously between 156 kHz and 40 MHz. Therefore, this BBFis suitable for a SDR with any signal bandwidth in the providedrange, including 4G and WLAN standards. The application of thefilter predistortion, as presented in the previous chapter, significantlyimproves the power efficiency of the circuit.

119

120 CHAPTER 5. IMPLEMENTED MULTI-STANDARD BBF

5.1 Multi-Standard 2G/3G/LTE BBF

The implemented multi-standard BBF provides cutoff frequencies be-tween 170 kHz and 9.1 MHz and supports all LTE signal bandwidthsas well as WCDMA, TD-SCDMA and two settings for GSM. Fig. 5.1shows the filter topology, consisting of the 6th order, 0.3 dB pass-bandripple Chebyshev leapfrog filter with DC offset compensation, thepositive zero and the output buffer. The pole, which forms the allpasstogether with the positive zero, is implemented in the accompanyingmixer circuit to assure layout symmetry.

SAR

Figure 5.1: Multi-standard baseband filter topology.

5.1.1 Architecture and Design

The frequency programmability is realized as a discrete number ofCFS steps by programmable resistors and capacitors and additional±6% FFS fine-tuning range in the feedback capacitance. RC tuningand DC offset calibration algorithms compensate fabrication processvariations in the active RC circuit implementation.

5.1. MULTI-STANDARD 2G/3G/LTE BBF 121

Moderate predistortion has been applied to the Chebyshev filtertransfer function, using amplifiers with a GBP 50 times higher thanthe filter cutoff frequency. A leapfrog circuit architecture has beenchosen because of its low sensitivity to component variations. Theprogrammable resistor array is realized by a combination of parallelswitchable resistors and one-hot series resistors. All resistors of theleapfrog filter are implemented as a series/parallel ladder resistancestructure with a unit resistor element (see Sec. 3.7.2). The feedbackcapacitor consists of a fixed capacitance and a binary programmablearray to compensate RC product process variations and to providesome frequency fine tuning range. Programmable gain between 3 dBand 45 dB in 6 dB steps is implemented in the leapfrog filter structure.Additional gain programmability in 1 dB steps from -5 dB to 0 dBis available in the positive zero. The 3-V output buffer is required todrive off-chip loads.

Two-stage Miller compensated amplifiers are used in all subcir-cuits. The GBP of the amplifiers in the leapfrog filter and the positivezero is programmable by means of bias current scaling. An accuratevalue for the GBP is provided by a constant-gm biasing scheme asdescribed in Sec. 4.7.2.

5.1.2 Characterization Results

The measured filter transfer functions in Fig. 5.2 show all supportedmodes with 6 dB gain steps. The BBF offers 8 basic modes, which areseparated by roughly a factor of two in cutoff frequency. Fine tuningof the cutoff frequency allows to adjust the filter transfer functionto support also WCDMA and TD-SCDMA. Two modes for GSMare available, whereby the lower cutoff frequency is better suitedto suppress the strong blocking signals. Because the allpass poleis not implemented in the BBF circuit, the positive zero has beendeactivated by switching off the corresponding capacitance for thesemeasurements. As can be seen in Fig. 5.3, the transfer functions arevery flat with pass-band ripple in the order of 0.5 dB, which is veryclose to the 0.3 dB pass-band ripple of the ideal prototype filter.Only the transfer function of the lowest cutoff frequency peaks athigh gain settings. This is because the associated resistors for low


103

104

105

106

107

108

−60

−50

−40

−30

−20

−10

0

10

20

30

40

50

Frequency [Hz]

Gain

[dB

]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

WCDMA

TD−SCDMA

(a) All BBF modes and 6 dB gain settings

104

105

106

107

32

33

34

35

Frequency [Hz]

Ga

in [

dB

]

(b) Detail view of the 33 dB gain setting

Figure 5.2: Measured filter transfer functions.

cutoff frequency and high gain are very large and introduce excessiveparasitics.

The cutoff frequencies and the current of one filter, drawn froma 1.2 V external power supply, is listed in Tbl. 5.1 for the differentmodes. The listed current does not include the power consumptionof the 3.3 V on-chip output buffer, which requires about 700 µA to


drive a 10 pF external load. The Single-Sideband (SSB) bandwidthof the actual signal is usually smaller than half of the correspondingchannel spacing to provide some guard band. The cutoff frequencyof the 15 MHz LTE mode is realized by a parallel combination of theresistors for LTE 5 MHz and LTE 10 MHz. This results in largerparasitics and therefore requires a higher GBP/fc ratio, leading to thesame power consumption as in the LTE 20 MHz mode.

Table 5.1: BBF cutoff frequencies and current from 1.2 V powersupply.

Mode SSB BW [MHz] fc [MHz] Current [mA]LTE 20 MHz 9 9.12 8.3LTE 15 MHz 6.75 6.84 8.3LTE 10 MHz 4.5 4.56 3.7LTE 5 MHz 2.25 2.28 2.7WCDMA 1.92 2.15 2.7LTE 3 MHz 1.35 1.38 2.2TD-SCDMA 0.64 0.72 2.2LTE 1.4 MHz 0.54 0.65 2.2GSM wide 0.1 0.32 2.2GSM narrow 0.1 0.17 2.2

The measured input referred noise density of the BBF is shownin Fig. 5.3 for different gain settings. The noise density is smallerthan the required 81 nV/

√Hz in all modes with a maximum value of

68 nV/√

Hz for the lowest cutoff frequency in GSM and a minimumvalue of 12 nV/

√Hz for the highest cutoff frequency. The noise is still

low for moderate filter gain settings and increases when the gain ofthe first stage is decreased. This confirms that the noise contributionof the filter is dominated by the first stage.

The filter DC gain accuracy depends on the local random variationof the fabricated resistor elements, which are nominally identical. Ascan be seen from Fig. 5.4(a), the accuracy of all 1 dB gain steps is wellbelow ±0.15 dB. Also the integrated gain error is fairly small with anabsolute value smaller than 0.3 dB for all modes (seeFig. 5.4(b)).


0 10 20 30 40 500

50

100

150

200

250

300

350

Gain [dB]

Nois

e d

ensity [nV

/sqrt

(Hz)]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

Figure 5.3: Measured average pass-band noise (input referred).

0 10 20 30 40 50

−0.1

−0.05

0

0.05

0.1

Gain setting

Gain

err

or

[dB

]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

(a) Differential gain error vs. gain setting

0 10 20 30 40 50

−0.2

−0.1

0

0.1

0.2

Gain setting

Gain

err

or

[dB

]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

(b) Integral gain error vs. gain setting

Figure 5.4: Measured DC gain accuracy of the BBF.


0 10 20 30 40 50−0.1

−0.05

0

0.05

0.1

Gain setting

Gain

mis

matc

h [dB

]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

(a) IQ gain mismatch vs. gain setting

0 10 20 30 40 50

0

0.2

0.4

0.6

Gain setting

Ph

ase

mis

ma

tch

[d

eg

]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

(b) IQ phase mismatch vs. gain setting

Figure 5.5: Measured IQ matching at half cutoff frequency.

Matching between the I-path and the Q-path of the BBF is againdominated by random mismatch, but may also be influence by processgradients because of the increased distance between two correspondingelements. The gain and phase mismatch shown in Fig. 5.5 has beenmeasured at half cutoff frequency. The resulting IQ imbalance is wellbelow the requirements of 0.43 dB gain matching and 2 phase error.This leaves sufficient margin for IQ mismatch in other receiver blocksas for example the mixer, where phase matching is more difficult dueto stringent timing requirements at carrier frequency. Despite themeasurements are taken from a single sample, the results providestatistical relevance because the resistor array consists of more than100 independent resistances to realize all gain and cutoff frequencysettings.


The residual DC offset in Fig. 5.6 has been measured after auto-matic DC offset calibration. The offset increases with the filter gain,but it stays below one LSB of the calibration algorithm for all modeand gain settings.

0 10 20 30 40 50−20

−10

0

10

20

Gain [dB]

DC

offset [m

V]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

Figure 5.6: Residual DC offset at the BBF output.

The linearity of the filter has been measured in terms of IIP3.Fig. 5.7(a) shows the pass-band linearity of all modes, where thefrequencies of the two-tone signal have been placed at fc/2 and fc.As can be expected, the linearity decreases proportional to the BBFgain, because the interferers are amplified with the full filter gain. Thestop-band linearity on the other hand only scales with the gain of thefirst stage as shown in Fig. 5.7(b), where the two-tone frequencies areat 4 · fc and 8 · fc. The non-linearity of the succeeding stages is notcontributing, because the first stage attenuates the interferers.

The 1 dB input compression point in the filter pass-band has beenmeasured for a 100 kHz CW signal and is above 10 dBm for all modesat 0 dB gain setting. The stop-band input compression point canbe expected even a few decibel higher, because the first stage is notlimiting.

The complete BBF with 6th order lowpass filter, positive zero,output buffer and supporting circuits for offset compensation, RCcalibration and biasing occupies 0.67 mm2 of silicon area in a 130 nmCMOS technology.


0 10 20 30 40 50−10

0

10

20

30

40

50

Gain [dB]

IIP

3 [dB

m]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

(a) Pass-band IIP3

0 10 20 30 40 5032

34

36

38

40

42

44

46

48

50

Gain [dB]

IIP

3 [

dB

m]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

(b) Stop-band IIP3

Figure 5.7: Measured linearity as a function of filter gain.


5.1.3 Version with Non-Unit Resistors

The resistor array of the implemented multi-standard baseband filteroccupies about 25% of the overall chip area. Improving the areaefficiency of the resistor area can therefore result in significant loweringof the overall area consumption and the related cost. It has beenshown in Sec. 3.7.2, that it is not strictly required to use a resistorunit element to achieve precise matching. If the width of all resistorsin the layout is equal and the length of each resistor is sufficientlylarge, matching can be achieved without a unit element. But realizingall the different resistances in a regular structure in the layout thenbecomes a challenge. Very large resistances, as required for the GSMmode, have to be implemented as series connection of several parts,where each part needs to be sufficiently large. Very small resistancescan not be implemented by a single element, because it would be tooshort. Therefore several resistors need to be connected in parallelto realize small resistances. While this causes some additional area,the overhead is significantly lower compared to a realization withunit elements and every resistance anyway needs to have a certainminimum area for sufficient matching accuracy.

The resistor array consists of more than 100 individual resistances,therefore a Cadence SKILL script has been written that calculates thevalues of the resistor parts and places them into a regular structure inthe layout. The resulting resistor array occupies 40% less silicon areathan the version with unit elements, reducing the overall chip area by10%. All components of the multi-standard baseband filter versionwith non-unit resistors except the resistor array are identical as in theunit resistor version. This ensures meaningful measurement results.

The measured transfer functions of the BBF with non-unit resis-tors are shown in Fig. 5.8 and look very similar to the version witha unit resistor elements. The peaking of the lowest cutoff frequencyis even significantly reduced, because the parasitics related to localinterconnections of single resistor elements is much lower.

Power consumption, noise and linearity of the baseband filter havenot changed, because only the structure of the resistor array has beenmodified. Also the residual DC offset is still below one LSB of thecalibration algorithm.


103

104

105

106

107

108

−60

−50

−40

−30

−20

−10

0

10

20

30

40

50

Frequency [Hz]

Gain

[dB

]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

WCDMA

TD−SCDMA

(a) All BBF modes and 6 dB gain settings

103

104

105

106

107

32

33

34

Freq [Hz]

Ga

in [

dB

]


Figure 5.8: Measured transfer functions with non-unit resistor array.

The gain accuracy of the baseband filter depends on resistor ele-ment matching and therefore is of particular interest to evaluate themodified resistor array structure. Fig. 5.9(a) shows the differentialgain error of the BBF, which is smaller than ±0.15 dB for all modeand gain settings. The absolute value of the integral gain error shownin Fig. 5.9(b) is below 0.3 dB for all modes. These values agree with


the results of the unit resistor implementation and confirm, that therequirements derived in Sec. 3.7.2 are sufficient to realize accurateresistor matching.

0 10 20 30 40 50

−0.1

−0.05

0

0.05

0.1

Gain setting

Gain

err

or

[dB

]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

(a) Differential gain error vs. gain setting

0 10 20 30 40 50

−0.2

−0.1

0

0.1

0.2

Gain setting

Gain

err

or

[dB

]

LTE 20

LTE 15

LTE 10

LTE 5

LTE 3

LTE 1.4

GSM wide

GSM narrow

(b) Integral gain error vs. gain setting

Figure 5.9: Measured DC gain accuracy of the BBF.

The good matching of the modified resistor array is also under-pinned by the measured IQ imbalance. The gain and phase mismatchbetween the I-path and the Q-path of the BBF is smaller than ±0.1 dBand ±0.4 respectively.

5.1.4 Characterization SummaryThe measurement results of the 2G/3G/LTE multi-standard basebandfilter are summarized in Tbl. 5.2. The chip has been fabricated in a130 nm CMOS technology and the core occupies 0.67 mm2 of silicon


area, featuring two baseband filters for the I-path and Q-path respec-tively, including biasing and calibration circuits. The micrograph ofthe chip is shown in Fig. 5.10.

Table 5.2: 2G/3G/LTE multi-standard BBF characterization sum-mary (both versions).

Supported RATs GSM, TD-SCDMA, WCDMA, all LTE BWsCutoff frequency 170 kHz to 9.1 MHz in 8 discrete stepsa

Gain -2 dB to +45 dB in 1 dB stepsPower 2.2 mA to 8.3 mA from 1.2 V supplyb

Noise 12 nV/√

Hz to 68 nV/√

HzIIP3 > 33 dBm in stop-band for all gain settingsICP > 10 dBm in pass-band at 0 dB gain settingIQ mismatch < 0.1 dB gain and < 0.6 phase mismatchGain accuracy < 0.15 dB diff. and < 0.3 dB int. gain erroraAdditional ±6% fine-tuning rangebFor one BBF, incl. biasing, w/o output buffer.

Figure 5.10: Chip micrograph of the multi-standard baseband filter(version with non-unit resistor elements).


5.2 Tunable BBF for 2G to 4G SDRThe multi-standard baseband filter presented in the previous sectionsupports a discrete set of specific signal bandwidths. The targetedsoftware defined radio receiver needs to be able to receive a signalwith arbitrary bandwidth within a given range, therefore the cutofffrequency of the BBF needs to be more flexible. This also allows thereceiver to be used for RATs that have not been specified at the timeof device fabrication. The general filter topology of the tunable 2G to4G BBF for SDR is the same as for the multi-standard BBF shownin Fig. 5.1.

5.2.1 Architecture and DesignThe power efficiency of the design has been improved by setting theamplifier GBP to 25 times the filter cutoff frequency. This needsrather strong predistortion and therefore a biquad architecture hasbeen chosen for the lowpass filter. The prototype is again a 6th orderChebyshev filter with 0.3 dB pass-band ripple.

Frequency programmability has been implemented by the schemepresented in Tbl. 3.1 (p. 67). CFS is realized as exponential factor 2frequency scaling by programmable resistors and multiple unit capaci-tors in parallel. The unit capacitor is binary programmable with 8 bitresolution, providing additional ±30% over-range to compensate RCproduct variations. This method allows to tune the cutoff frequencyquasi-continuously from 156 kHz to 40 MHz with a resolution below3%. The RC calibration is implemented as on-chip multiplicationof the nominal capacitance code with the calibration code from thereference filter.

Programmable gain between 3 dB and 45 dB is available in 6 dBsteps in the biquad filter. Additional -5 dB to 0 dB gain programma-bility is implemented with 1 dB steps in the 1.2 V output buffer.Moving the gain fine tuning from the positive zero to the outputbuffer significantly reduces the complexity and the area consumptionof the positive zero. The resistor array of the lowpass filter consists ofparallel switchable resistors, each realized by a series/parallel ladderresistance structure. The strict use of unit resistor elements hasbeen relaxed by allowing one shorter resistor element in the ladder

5.2. TUNABLE BBF FOR 2G TO 4G SDR 133

structure, if its contribution to the overall resistance is small. Thisprovides a compromise between the unit and non-unit resistor strategywith good area efficiency and a very regular layout.

The GBP of the two-stage Miller compensated amplifiers can betuned by changing the bias current and programming the Miller capac-itance. Bias current scaling is used for high filter cutoff frequencies,to scale the power consumption with the signal bandwidth. In thecase of moderate to low cutoff frequencies, proper predistortion whiletuning the cutoff frequency for FFS is maintained by adjusting theMiller capacitance. The same constant-gm biasing scheme as in themulti-mode BBF is used to provide accurate GBP values.

5.2.2 Characterization ResultsThe power consumption of the basic modes of the tunable BBF islisted in Tbl. 5.3. The presented numbers include the power con-sumption of the 1.2 V output buffer, which draws about 2.1 mA todrive a 10 pF off-chip load. The buffer is included because it providespart of the gain programmability. The speed of the output buffer isnot programmable, therefore it consumes about 60% of the total BBFpower at moderate and low cutoff frequencies.

Table 5.3: BBF current drawn from 1.2 V power supply.Mode fc [MHz] Currenta [mA]40 MHz 40 15.820 MHz 20 6.710 MHz 10 4.35 MHz 5 3.62.5 MHz 2.5 3.61.25 MHz 1.25 3.5625 kHz 0.625 3.5312 kHz 0.312 3.5156 kHz 0.156 3.5

aIncl. ∼ 2.1 mA for output buffer


Fig. 5.11(a) shows the measured transfer functions of the expo-nentially scaled basic modes with all 6 dB gain settings. The detailview in Fig. 5.11(b) highlights the flat transfer functions, close to thetransfer function of the ideal prototype, for cutoff frequencies from156 kHz to 20 MHz. The highest bandwidth setting has slightlyhigher pass-band ripple, because the ratio of parasitic capacitance atthe amplifier input to feedback capacitance is increasing significantly.Fig. 5.11(c) illustrates the cutoff frequency programmability, 6 stepsare shown per basic mode. Only the transfer functions above 20 MHzshow some peaking, but the pass-band ripple stays always below 1 dB.Excessive RC tuning range allows to scale the cutoff frequency downto 115 kHz, below the nominal minimum setting of 156 kHz.

The accuracy of the programmable cutoff frequency after auto-matic RC calibration is shown in Fig. 5.12(a). The measurement wasperformed in the 15 dB gain setting. The error of the measured 3 dBfrequency is < 3% for cutoff frequencies below 5 MHz, < 5.5% up to20 MHz and < 8.5% for the highest frequency settings. The largestinaccuracies occur when the basic mode is changed. Within a basicmode, the 3 dB frequency accuracy is fairly constant or slowly driftsapart. This observation is confirmed by the frequency step increaseshown in Fig. 5.12(b). Large steps can be observed at the bordersbetween two basic modes. Within a mode, the step increase tracks theideal curve plotted in red. The steps with zero frequency increase aredue to the multiplication of the RC calibration code with the nominalcapaitance code, that can lead to the same result for two subsequentnominal capacitance codes. Within a basic mode, the step increase is< 2% for cutoff frequencies up to 20 MHz and < 3% up to 40 MHz.

Fig. 5.13 shows the input referred noise density of the tunable BBFfor the basic modes. The highest noise amounts to 83 nV/

√Hz in the

lowest cutoff frequency setting and is right at the edge of the tolerableBBF noise. For the highest cutoff frequency, the noise reduces to19 nV/

√Hz.

The stop-band IIP3 of the filter is between 19 dBm and 35 dBm,depending on the cutoff frequency setting. The linearity is lowercompared to the multi-mode filter presented in the previous section,because a reduced ratio of amplifier GBP to filter cutoff frequency hasbeen used. This measurement confirms the calculations performed in


103

104

105

106

107

108

−60

−50

−40

−30

−20

−10

0

10

20

30

40

50

Frequency [Hz]

Gain

[dB

]

40 MHz

20 MHz

10 MHz

5 MHz

2.5 MHz

1.25 MHz

625 kHz

312 kHz

156 kHz

(a) Exponentially scaled basic modes with all 6 dB gain settings

103

104

105

106

107

108

13

14

15

16

Frequency [Hz]

Ga

in [

dB

]


103

104

105

106

107

108

14

15

16

Frequency [Hz]

Ga

in [

dB

]

(c) 6 frequency steps per basic mode

Figure 5.11: Measured transfer functions of the tunable BBF.


105

106

107

−8

−6

−4

−2

0

Target 3dB frequency [Hz]

Err

or

[%]

(a) Error of the measured 3 dB cutoff frequency for all settings

105

106

107

−6

−4

−2

0

2

4

3dB frequency [Hz]

Ste

p incre

ase [%

]

Measured

Ideal

(b) Frequency step increase for all cutoff frequency settings

Figure 5.12: Measured 3 dB frequency accuracy.

Sec. 4.8.3 and underlines that further power saving by lowering theamplifier GBP leads to unacceptably low linearity.

The measured differential and integral gain error is below 0.4 dBand 1.2 dB respectively. These values are larger than for the prede-cessor multi-mode filter, because of systematic error in the resistorarray, where a limited accuracy of the resistor values has been ac-cepted deliberately to reduce the array size. This does not harm thefunctionality of the filter since the gain is strictly monotonic increasingand has sufficient resolution and range for a cellular receiver.

The mismatch between the I-path and the Q-path of the filter hasbeen measured at half cutoff frequency. The gain mismatch is smallerthan 0.2 dB and the phase mismatch is below 0.6 for all frequency andgain settings. These values are comparable to the results of the multi-mode filter and confirm good matching in the resistor and capacitorarrays.


0 10 20 30 40 500

100

200

300

400

500

600

700

800

900

Gain [dB]

Nois

e d

ensity [nV

/sqrt

(Hz)]

40 MHz

20 MHz

10 MHz

5 MHz

2.5 MHz

1.25 MHz

625 kHz

312 kHz

156 kHz

Figure 5.13: Measured average pass-band noise (input referred).

The residual DC offset after automatic calibration is below oneLSB for all mode and gain setting and the measured 1 dB inputcompression point is larger than 6 dBm for for a 100 kHz CW signalin the 0 dB gain setting of all basic modes.

5.2.3 Characterization SummaryThe measurement results of the baseband filter for a 2G to 4G softwaredefined radio are summarized in Tbl. 5.4. The chip has been fabri-cated in a 130 nm CMOS technology and the core occupies 0.68 mm2

of silicon area, featuring two baseband filters for the I-path and Q-path respectively, including biasing and calibration circuits. Themicrograph of the chip is shown in Fig. 5.14.


Table 5.4: BBF for 2G to 4G SDR characterization summary.Supported RATs All RATs with RF BW ≤ 80 MHzCutoff frequency 115 kHz to 40 MHz with < 3% resolutiona

Gain -2 dB to +45 dB in 1 dB stepsPower 3.5 mA to 13.3 mA from 1.2 V supplyb

Noise 19 nV/√

Hz to 83 nV/√

HzIIP3 ≥ 19 dBm in stop-band for all gain settingsICP > 6 dBm in pass-band at 0 dB gain settingIQ mismatch < 0.2 dB gain and < 0.6 phase mismatchGain accuracy < 0.4 dB diff. and < 1.2 dB int. gain error

a115 kHz achieved by using the overrange to compensate RC process variation.Nominal minimum frequency is 156 kHz. Maximum frequency limited to 40 MHzby amplifier speed.

bFor one BBF, incl. biasing and ∼ 2.1 mA for output buffer.

Figure 5.14: Chip micrograph of the tunable baseband filter for 2Gto 4G SDR.

Chapter 6

Summary andConclusion

The trend in the last years has shown that mobile communicationhas shifted from a voice oriented system towards a mobile enter-tainment environment. Hidden behind a high-resolution touch-screendisplay, mobile devices incorporate high-end processors, sensors andtransceiver circuits. The demand on high wireless data rates hasled to the development of new communication standards like LTEwith higher signal bandwidth and supporting new operation bands.A mobile device nowadays needs to support a multitude of cellularradio access technologies (RATs), because older standards as GSM arestill in operation and world-wide roaming is demanded by the user.This results in a challenging design for the transceiver circuit, whereprogrammability, performance and cost often conflict each other.

The multitude of wireless standards has pushed the idea to bringdigital signal processing closer to the antenna. However, the extraor-dinary large dynamic range requirements of cellular communicationrender direct digitization of the signal at the antenna impossible.Therefore a limited amount of analog circuitry is required for signalconditioning before the ADC. The software-defined radio (SDR) con-cept has turned out to resolve the issue by a compromise. Program-mable hardware is controlled by software according to the needs of the

139

140 CHAPTER 6. SUMMARY AND CONCLUSION

specific application. For the receiver circuit, a continuous-time directconversion architecture fits best to the SDR requirements because aminimal set of external components is required, leading to lower costcompared to the heterodyne architecture and programmability can beintroduced in the different blocks of the circuit.

This thesis has investigated the requirements and the design ofan analog baseband filter (BBF) for a direct conversion SDR. Therequirements for the receiver have been derived from the set of RATsto be supported, which includes GSM/EDGE, WCDMA, LTE/LTEadvanced, WiMAX and WLAN. The designed circuit has to supportbasically all wireless 2G, 3G and 4G technologies. It has been shown,how the specifications of the different RATs translate into require-ments for the receiver and can further be broken down to the seperatecircuit blocks.

The requirements of the BBF are closely linked to the performanceof the ADC. A multimode ∆Σ ADC has been assumed, because it cantolerate a certain amount of residual blockers, since the architectureprovides inherent filtering in the noise shaping and decimation process.A sixth order BBF has been evaluated to minimize the total powerconsumption of the BBF and the ADC. The BBF requirements includecutoff frequency programmability from 150 kHz to 40 MHz, 47 dB ofprogrammable gain and strict requirements on noise, linearity andI/Q matching.

The design of the BBF has been explored in detail. A 0.3 dB pass-band ripple Chebyshev filter has been chosen as prototype transferfunction, because of its steep roll-off and moderate in-band amplitueripple. Due to the high linearity requirement, it has beend decided toimplement the BBF as active-RC circuit, despite this technique is notas well suited for programmability as e.g. gm-C filters. The cutofffrequency of the BBF needs to be programmable by a factor of 267,therefore an elaborate strategy is required to fulfill noise and mismatchrequirements, while keeping the amplifier loading within reasonablebounds. The cutoff frequency is scaled by a two-fold programmabilityscheme. Coarse frequency selection is employed by scaling the resistorsor capacitors in large steps of about a factor two. Additional finefrequency selection is implemented in the capacitors with a resolutionbelow 3%. The programmable resistors and capacitors are imple-mented as arrays of parallel switchable elements.

141

It has been shown, how the resistor array can be implementedarea efficient, avoiding the necessity of a unit resistor element andstill achieving good matching, which is required for accurate gain andcutoff frequency.

For the design of active-RC circuits, the amplifier is often consid-ered ideal. However, the characteristic of the amplifier can only be ne-glected, if it provides large gain in the frequency range of interest. Thiswould require high-speed amplifiers and lead to unacceptably highpower consumption for wideband communication standards. Ampli-fiers with moderate speed and consequently lower power consumptioncan be used, if their characteristic is taken into account during thedesign of the filter. Finite amplifier gain-bandwidth product (GBP)and parasitic capacitance at the amplifier input node are the mostimportant sources of distortion in the transfer function. These non-idealities can either be compensated with additional circuit elementsor the filter can be designed to absorb the distortion. Since additionalcircuit elements are undesired, it has been shown how the predistortedpoles of the prototype filter can be calculated to compensate thenon-idealities. Cutoff frequency and gain programmability also haveto be considered for the predistortion. The speed of the amplifierneeds to be scaled proportional to the BBF cutoff frequency, whichis actually desired to scale the power consumption with the signalbandwidth.

The sensitivity of the active-RC filter to component variation hasbeen investigated for two architectures. It is well known, that leapfrogfilters have lower sensitivity than biquad implementations under theassumption of ideal amplifiers. But as soon as the amplifiers cannot be considered ideal anymore, the sensitivity of the leapfrog archi-tecture increases and eventually becomes comparable to the biquadcircuit. It has been shown, that a predistorted leapfrog filter can evenbecome unstable, if amplifiers with low GBP are used. Therefore,leapfrog implementations should be used with high amplifier speed,while the biquad architecture is favored for low-power implementa-tions.

The amplifiers need to comply with a set of requirements given bythe filter scalability and the predistortion. The resistive and capacitiveload is subject to large variation and a wide range of programmablespeed is needed. A Miller compensated architecture has been chosen,

142 CHAPTER 6. SUMMARY AND CONCLUSION

because of its good stability for various loading and well controllableGBP, which is required for the predistortion. The GBP is scaledby programmable Miller capacitance and tunable bias current, whichallows to save power for low cutoff frequencies. Power efficiency canbe improved by adding class-AB functionality to the output stage.These characteristics outweigh the inherent speed penalty given bythe Miller compensation principle.

Two 6th order multi-standard BBF have been implemented usingthe presented concept. Characterization of the two implementationsshows close matching to the expected performance and proves theconcept. The first design supports 2G, 3G and LTE by 8 discretefrequency settings with ±6% fine-tuning range. The measurementsshow high linearity of > 33 dBm IIP3 and > 10 dBm ICP and excellentcomponent matching with < 0.15 dB differential and < 0.3 dB integralgain error over the 47 dB gain range, programmable in 1 dB steps.Also IQ matching is far below the limit with < 0.1 dB gain and < 0.6phase mismatch. The noise performance fulfills the requirements withvalues between 12 nV/

√Hz and 68 nV/

√Hz. Power consumption per

BBF is between 2.2 mA and 8.3 mA, depending on the cutoff frequencysetting.

The cutoff frequency of the second design can be tuned quasi-continuously between 156 kHz and 40 MHz with a resolutions below3%. As ecpected, the linearity suffers from the reduced amplifier speedand is right at the edge of the requirements with > 19 dBm IIP3 and> 6 dBm ICP. Gain accuracy (< 0.4 dB diff. and < 1.2 dB int. gainerror) and IQ mismatch (< 0.2 dB gain and < 0.6 phase mismatch)are still well below the limits. Noise requirements are fulfilled withvalues between 19 nV/

√Hz and 83 nV/

√Hz. Power consumption per

BBF is between 3.5 mA and 15.8 mA, depending on the cutoff fre-quency setting. In contrast to the first design, this includes ∼ 2.1 mAfor the output buffer to drive the ADC. Improved power efficiency iswell visible at 10 MHz cutoff frequency, where the two designs take8.3 mA and 4.3 mA respectively.

This work has shown how a highly flexible BBF can be imple-mented with an optimized active-RC architecture. Inherent area andpower penalty compared to other architectures can be reduced by thepresented concept, while keeping the high reliability and linearity of

143

active-RC circuits. Nevertheless, other architectures like discrete-timeanalog filtering may become more attractive in the future due tosmaller silicon area, once they meet the challenging requirements forcellular communication.

Semiconductor technology scaling will allow the presented conceptto be used for even higher bandwidth settings thanks to increasedtransistor transit frequency, smaller switches and less parasitic capac-itance. Improved matching and high-density analog capacitors willlead to reduced resistor and capacitor area. Therefore the approachtaken in this work will stay attractive for future cellular receivercircuits.

Appendix A

Receiver Requirements

The noise and linearity performance of a RF circuit can be expressedin terms of noise figure and second respectively third order interceptpoints. This allows good comparison of different implementations.

A.1 Noise FigureThe noise figure of a circuit is defined as the ratio of the SNR at theinput to the SNR at the output

NF = SNRin

SNRout=

Pws,inPn,in

G·Pws,inG·Pn,in+Pn,add

= 1 + Pn,add/G

Pn,in(A.1)

where Pws,in and Pn,in are the power of the wanted signal and the noisethat is available at the input of the circuit, Pn,add is the noise poweradded by the circuit and G is the gain of the circuit. ConsequentlyPn,add/G is the input referred added noise power of the circuit. Thenoise figure is defined for a matched input scenario, therefore the noisePn,in is given by the source resistance RS, which is often specified tobe 50 Ω. The spectral density of the noise power available at the inputof the circuit is

Pn,in

∆f = 4kTRS

4RS= kT = −174 dBm/Hz (A.2)

145

146 APPENDIX A. RECEIVER REQUIREMENTS

where k = 1.38 · 10−23 J/K is the Boltzmann constant and a temper-ature T of 290 K has been used.

A.2 Intercept PointsIntegrated circuits are usually processing signals with small ampli-tude compared to the supply voltage. Therefore the small-signalnon-linearity is more important than distortion caused by saturationeffects. The small-signal output y (t) can be expressed as a polynomialfunction of the input signal x (t)

y (t) = α1x (t) + α2x2 (t) + α3x

3 (t) (A.3)

The input signal can generally be a single-tone signal, where thenon-linearity creates signal components at the harmonic frequencies.However, the harmonics are usually not critical in communicationsystems because they are located far away from the wanted signalin terms of frequency. Distortion created by non-linear processing oftwo signals is much more severe, because the distortion product canfall on the same frequency as the wanted signal. Therefore, secondand third order intermodulation is defined for a two-tone input signalx (t) = A1 cos (ω1t)+A2 cos (ω2t). Then, the non-linear terms of (A.3)become

α2x2 (t) = α2A1A2 cos ((ω2 − ω1) t) + . . . (A.4)

α3x3 (t) = 3

4α3A21A2 cos ((2ω2 − ω1) t) + . . . (A.5)

where only the components at ω2 − ω1, respectively 2ω2 − ω1, whichare assumed to fall on wanted signal frequency ωws, have been shown.

The intercept points are determined by setting A1 = A2 = Aws/√

2and using x (t) = Aws cos (ωwst). The output amplitude of the wantedsignal, i.e. the linear term α1x (t) is equated to the second and thirdorder intermodulation products in (A.4) and (A.5). Solving theseequations for Aws gives the input referred intercept points IIP2 andIIP3 expressed as squared voltage amplitude

V 2IIP2 = 4 ·

(α1

α2

)2V 2

IIP3 = 8√

23 ·

∣∣∣∣α1

α2

∣∣∣∣2 (A.6)

A.3. REFERENCE SENSITIVITY WITH TRANSMITTER LEAKAGE147

Fig. A.1 shows the power of the wanted signal (slope=1) as wellas the intermodulation products (slope=2 resp. slope=3) on a log-logscale versus the total power of the interferers Pintf . From this, thefollowing relationship for the m-th order intercept can be derived,expressing the powers in decibel

IIPm = m · Pintf − PIMm,ineq

m− 1 (A.7)

IIP2 = 2 · Pintf − PIM2,ineq IIP3 = 3 · Pintf − PIM3,ineq

2 (A.8)

Figure A.1: Graphical definition of input (IIP2/IIP3) and output(OIP2/OIP3) referred intercept points.

A.3 Reference Sensitivity with Transmit-ter Leakage

Taking the distortion power Pdist,tx due to transmit leakage for FDDoperation and the insertion loss ILrx of the RFFE into account, thenoise figure NF rx of the receiver circuit is given by

NF rx = 10 · log10

(10

Pn,th+NFsys−ILrx10 − 10

Pdist,tx10

)− Pn,th (A.9)


The distortion power strongly depends on receiver linearity and Tx-to-Rx isolation STx2Rx. Since the output power of the transmitter isspecified with respect to the antenna port, the PA power needs to beeven higher to compensate for the insertion loss ILtx of the RFFEin the transmit path. The power PTx2Rx leaked to the receiver inputat the transmit frequency and the resulting distortion power Pdist,txreferred to the receiver IC input as a function of IIP2 are given by

PTx2Rx = PAnt + ILtx + STx2Rx (A.10)Pdist,tx = 2 · PTx2Rx − IIP2UL + CorrFact (A.11)

where PAnt is the specified maximum transmitter output power,IIP2UL is the IIP2 at uplink frequencies and CorrFact is a correctionfactor, taking into account the difference in second-order distortioncreated by the modulated signal relative to that resulting from two-tone test signals [65]. Combining (A.9) and (A.11), it is obvious thatthere is a design trade-off between NF and IIP2UL for FDD systems.This equation can also be reorganized to calculate the required IIP2ULwith a given NF rx by expressing Pdist,tx as the difference betweenPnd,tot and the noise contribution due to a given NF rx.

Pdist,tx = 10 · log10

(10

Pn,th+NFsys−ILrx10 − 10

Pn,th+NFrx10

)(A.12)

IIP2UL = 2 · PTx2Rx − Pdist,tx + CorrFact (A.13)

The maximum transmitter output power is 24 dBm and 23 dBmfor WCDMA and LTE respectively, leading to PTx2Rx of -28 dBm and-29 dBm. Further, it is assumed that the receiver achieves a NF rx of4 dB for the FDD systems.

System level simulations show that the correction factor for theLTE uplink signal is 4.5 dB (setting CorrFact = 6 dB gives somemargin), which means that the distortion generated by the LTE signalis higher than the one of the two-tone test. The reason is the PAPR ofthe LTE uplink signal, which is a Single Carrier Frequency DivisionMultiple Access (SC-FDMA) signal. In the case of WCDMA, thetransmitter leakage is calculated with the correction factor from [65].

For a more accurate calculation of the reference sensitivity test,also the noise leaked from the transmitter at the receive frequency

A.4. BLOCKER TOLERANCE 149

and reciprocal mixing of PTx2Rx by the receiver LO phase noise canbe taken into account [18].

A.4 Blocker Tolerance

The calculation of the IIP2DL requirement at downlink frequencies issimilar as for transmitter leakage in the reference sensitivity test.

IIP2DL,Ant = 2 · Pintf − PIM2,Ant + CorrFact (A.14)

where Pintf is the blocker power level, PIM2,Ant is the distortion powerreferred to the antenna port that can be tolerated because the wantedsignal is ∆Prs dB above Prs and CorrFact is a correction factor like inthe case of transmitter leakage, but now for the downlink signal. ForGSM and WCDMA, the wanted signal is 3 dB above Prs, thereforePIM2,Ant can be as large as Pn,th + NF sys. In the case of LTE, at leastPIM2,Ant = Pn,th +NF sys +4.77 dB of distortion is allowed because thewanted signal is at least 6 dB larger than Prs. Strongest blocker forGSM is the -31 dBm GMSK modulated signal in the AM suppressiontest with a correction factor of -6 dB [18]. Blocker templates ofWCDMA and LTE are almost identical, the strongest in-band blockerhas a power of -44 dBm. Correction factors of uplink and downlinksignals are not identical, because different modulation schemes areused. Correction factors for the downlink signal are 5 dB and 7 dBfor WCDMA and LTE respectively. Since IIP2DL,Ant is referred tothe antenna port, the required IIP2DL of the receiver IC is lower byILrx.

A.5 Intermodulation

For the intermodulation test, the interferer closer to the wanted signalis a CW signal, while the second interferer, at twice the frequencyoffset of the first interferer, is a modulated signal. The wanted signalis again slightly higher than Prs (3 dB higher for GSM and WCDMA,at least 6 dB higher for LTE), allowing for certain distortion power.


Equivalent to the second order distortion, the required IIP3DL indecibel can be calculated as

IIP3DL,Ant = 12 · (3 · Pintf − PIM3,Ant) (A.15)

where Pintf is the sum of the two blocker power levels, PIM3,Ant is thedistortion power referred to the antenna port that can be toleratedbecause the wanted signal is ∆Prs dB above Prs. No correction factoris required because the amplitude of the CW interferer is squared bythe third order non-linearity, turning the resulting distortion productinto a frequency shifted and scaled version of the second interferer.The required IIP3DL to pass the intermodulation test and referred tothe receiver IC input is given by IIP3DL = IIP3DL,Ant − ILrx.

During the blocker test, the transmitter is operated 4 dB belowthe specified maximum output power and creates a harmful intermod-ulation product with the blocker at half duplex distance. Becausethe power of the CW blocker Pcw,in is not the same as the powerof the leaked transmitter signal PTx2Rx, the distortion power PIM3,cwresulting from a two-tone interference of power 2·PTx2Rx,Ant is allowedto be bigger by a factor of ∆P 2 = (PTx2Rx/Pcw,in)2 than PIM3,resulting from the actual test case [18]. The required IIP3UL, referredto the input of the receiver IC is therefore calculated in log scale as

IIP3UL = 3 · (PTx2Rx + 3 dB)− (PIM3 + 2 ·∆P )2 . (A.16)

The tolerable distortion power PIM3 is given by the amount of noiseand distortion Pnd,tot,Ant that can be tolerated because the wantedsignal is ∆Prs above Prs, minus the distortion created by secondorder non-linearity of the transmitter leakage. Additional noise anddistortion terms from reciprocal mixing and transmitter noise leakagewould further reduce PIM3 but have been neglected here.

Pnd,tot,Ant = Pn,th + NF sys + 10 · log10

(10( ∆Prs

10 ) − 1)

(A.17)

PIM2,Ant = 2 · PTx2Rx,Ant − IIP2UL,Ant + CorrFact (A.18)

PIM3 = 10 · log10

(10

(Pnd,tot−PIM2,Ant

10

))− ILrx (A.19)

A.6. CASCADED BLOCKS 151

where PTx2Rx,Ant = PTx2Rx + ILtx. The power of the CW blocker atthe receiver IC input depends on the duplexer isolation. As a worstcase, Pcw,in = −42 dBm is calculated from the blocker template andtypical attenuation characteristic of commercial duplexers.

A.6 Cascaded BlocksThe noise figure of two cascaded blocks can be calculated accordingto Friis’ formula

NF = NF1 + NF2 − 1G2

1(A.20)

where G21 is the power gain of the first block. The definition of

the noise figure requires a well defined input impedance, which isusually only available for the LNA and not for the mixer and theBBF. Nevertheless, an equivalent noise figure can be defined for eachblock for system level planning as

NFeq = 1 +V 2

n,ineq

G204kT0RSB

(A.21)

where V 2n,ineq is the noise power of the block, referred to its input, RS

is the source resistance at the input of the first block, B is the noisebandwidth and G0 = Zin1/ (RS + Zin1) at the input of the first block.Under matched condition, the expression can be simplified to

NFeq = 1 +V2

n,ineq∆f

kT0RS(A.22)

where the noise power of the block is expressed as spectral noise powerdensity in the numerator.

Cascading formulas can also be calculated for the second andthird order intercept points. Each block can be described by a thirdorder polynomial followed by a frequency selective stage as shown inFig. A.2 [18]. The polynomial models the block’s non-linearity andthe frequency selectivity is with respect to the wanted signal, i.e.


Figure A.2: Cascading non-linear frequency selective blocks.

A (jωws) = B (jωws) = 1. The distortion of the cascade can be ap-proximated by the polynomial w. Assuming that the intermodulationproducts add in phase, the coefficient γ2 is given by

γ2 = α2 |A (jωIM2)|β1 + α21 |A (jωintf)|2 β2 (A.23)

where ωIM2 is the angular frequency of the second order intermod-ulation product and ωintf is the angular frequency of the interferingsignal. The third order coefficient γ3 can be approximated by

γ3 ' α3β1 + α31 |A (jωnr)|2 |A (jωfr)|β3 (A.24)

where ωnr is the angular frequency of the nearby interferer and ωfris the angular frequency of the interferer more far away in a two-tone intermodulation test. The cascaded V 2

IIP2 and V 2IIP3 can then be

calculated with γ1 = α1β1 as

1V 2

IIP2=(|A (jωIM2)|

VIIP2,1+ α1 |A (jωintf)|2

VIIP2,2

)2

(A.25)

1V 2

IIP3= 1

V 2IIP3,1

+ α21 |A (jωnr)|2 |A (jωfr)|

V 2IIP3,2

(A.26)

Consequently, the linearity of a cascade suffers if the first stage pro-vides high gain. This conflicts with the requirement of low NF, whereit is advantageous to have high gain in front of the receive chain.Fortunately selectivity in the first stage greatly reduces the impact ofthe non-linearity of the second stage.

Appendix B

Filter Sensitivity

This chapter shows detailed derivations of the filter sensitivity oncomponent and amplifier variations.

B.1 Leapfrog Filter Sensitivity

Figure B.1: Signal flow graph of a 6th order leapfrog filter.

The transfer function of the leapfrog filter can be calculated fromthe SFG shown in Fig. B.1, using Mason’s formula as

H (s) = P0

∆ (B.1)

153

154 APPENDIX B. FILTER SENSITIVITY

where the forward path P0 is given by

P0 = 1s6 ·

∏6i=1 (CiRfi)

(B.2)

and the determinant ∆ is defined as

∆ = 1−∑i

Mi +∑i,j

MiMj −∑i,j,k

MiMjMk + · · · (B.3)

where Mi represents a loop in the SFG and products of two ore moreloops are only added, if the loops do not touch. The loops of Fig. B.1are given by

M1 = −1sC1Rb1

M2 = −1s2C1C2Rf2Rb2

(B.4)



(B.5)



(B.6)

M7 = −1sC6Rb7

(B.7)

From this, the transfer function H (s) can be evaluated symbolicallyby a suitable software like Matlab or Maple to calculate the coeffi-cients ai of the denominator polynomial as a function of the circuitcomponents.

H (s) =∏3i=1 ω

2pi

s6 + a5s5 + a4s4 + a3s3 + a2s2 + a1s+ a0(B.8)

The sensitivity is then also calculated by a symbolic derivative andnumerical evaluation of the result of

Saixj

= ∂ai∂xj· aixj

(B.9)

where xj is the j-th circuit element. The sensitivity matrix Sax has been

numerically calculated for the example 10 MHz, 0.3 dB pass-band

B.1. LEAPFROG FILTER SENSITIVITY 155

ripple, sixth order Chebyshev filter. The sensitivity of the leapfrogfilter pole frequencies and quality factors is then calculated by

S lfx =

(Sa

fp)−1 · Sa

x (B.10)

where Safp is the sensitivity of the coefficients ai on variations in the

filter pole frequencies and quality factors and can be derived directlyfrom (3.8) and (B.8). The resulting sensitivity matrix S lf

x is presentedin (B.11) with the respective component vector −→x in (B.12).


Slf x=

Sωp1

x SQp1

x Sωp2

x SQp2

x Sωp3

x SQp3

x

=

−0.

30−

0.00

−0.

19−

0.19−

0.00−

0.30

0−

0.01

0.01

0.06

−0.

090.

040.

04−

0.09

0.06

0−

0.26

0.16

−0.

16−

0.29

−0.

04−

0.04

−0.

29−

0.16

0−

0.23−

0.06

0.42

−0.

31−

0.11−

0.11

−0.

310.

420−

0.09−

0.22

−0.

03−

0.20−

0.26−

0.26

−0.

20−

0.03

0−

0.07−

0.13

0.76

0.17

−0.

93−

0.93

0.17

0.76

00.

47−

0.29

−0.

200.

01−

0.01

−0.

29−

0.01

0.01

−0.

200.

01−

0.01−

0.29

−0.

130.

16−

0.26

0.31

−0.

260.

16−

0.13

0.16

−0.

260.

310.

02−

0.06−

0.23

0.07

−0.

23−

0.06

0.02

−0.

06−

0.23

0.07

0.10

−0.

22−

0.09

0.51

−0.

09−

0.22

0.10

−0.

22−

0.09

0.51

−0.

14−

0.13−

0.07

0.04

−0.

07−

0.13−

0.14−

0.13

−0.

070.

04−

0.64

−0.

290.

470.

290.

47−

0.29−

0.64−

0.29

0.47

0.29

(B.1

1)

−→ x=[ C 1

C2

C3

C4

C5

C6

Rf1

Rf2

Rf3

Rf4

Rf5

Rf6

Rb1

Rb2

Rb3

Rb4

Rb5

Rb6

Rb7] >

(B.1

2)

B.2. PREDISTORTION SENSITIVITY 157

B.2 Predistortion SensitivityThe sensitivity of the predistorted filter poles with respect to theamplifier non-idealities can be calculated from the combined model in(4.27) which is repeated here as

p = p2

ωGBP· (1 +K2) + p ·

(1 + K1 |p|

ωGBP+ 1

ADC

)+ K1 |p|

ADC(B.13)

(B.13) is a second order equation of p and can therefore be solved by

p =−1− K1|p|

ωGBP− 1

ADC+√(

1 + K1|p|ωGBP

+ 1ADC

)2− 4 1+K2

ωGBP

(K1|p|ADC

− p)

2 1+K2ωGBP

(B.14)where only the positive sign has been considered for the square root,because only the lower pole is of interest here. The square root canbe approximated by the second order Taylor series around b2 as√

b2 − 4ac = b+ 12b · (−4ac)− 1

8b3 · (4ac)2 (B.15)

This is used to approximate (B.14) by

p ≈ −K1|p|ADC

− p

1 + K1|p|ωGBP

+ 1ADC

−1+K2ωGBP

·(K1|p|ADC

− p)2

(1 + K1|p|

ωGBP+ 1

ADC

)3 (B.16)

Considering only finite GBP and assuming infinite DC gain gives

p ≈ p

1 + K1|p|ωGBP

−1+K2ωGBP

· p2(1 + K1|p|

ωGBP

)3 (B.17)

For poles with high quality factors, p2 ' |p|2 can be assumed and thepole frequency can be approximated by

ωp = |p| ≈ Imp ≈ Imp1 + K1|p|

ωGBP

(B.18)


The sensitivity of the pole frequency to variations in the amplifierGBP is then calculated as

SωpωGBP

≈ K1 |p|

ωGBP

(1 + K2

1 |p|2

ω2GBP

)1

1+ K1|p|ωGBP

≈ K1 |p|ωGBP

(B.19)

The quality factor of high-Q poles can be expressed from (B.17) by

Qp =∣∣∣∣ ωp

2 Rep

∣∣∣∣ ≈ ∣∣∣∣ Imp2 Rep

∣∣∣∣ (B.20)

≈

∣∣∣∣∣∣ Imp2 Rep+ 2(1+K2)|p|2

ωGBP

∣∣∣∣∣∣ (B.21)

where (1 +K1 |p| /ωGBP) ≈ 1 has been used. The sensitivity of thepole quality factor to variations in the GBP follows as

SQpωGBP

≈ 2 (1 +K2)−ωGBPQp|p|

+ 2 (1 +K2)≈ −2Qp |p|

ωGBP(B.22)

This shows that the sensitivity of the pole frequency and quality factorof a high-Q pole scales with the ratio of predistorted pole frequencyto amplifier GBP.

For poles with low quality factor, (B.17) can be reformulated as

p ≈ p ·

(1

1 + K1|p|ωGBP

− (1 +K2) |p|ωGBP

)(B.23)

where the following approximation has been madep

ωGBP(1 + K1|p|

ωGBP

)3 ≈|p|

ωGBP(B.24)

Thus, for low-Q poles, p is a scaled version of p to a first approxima-tion. The sensitivity of the pole frequency is calculated from (B.23),using rule (3.6)

SωpωGBP

≈ K1 − 1−K2ωGBP|p| + 1 +K2

≈ (K1 − 1) |p|ωGBP

(B.25)

B.2. PREDISTORTION SENSITIVITY 159

Since the phase angle of a pole with low quality factor is not changedto a first approximation, the sensitivity of Qp to variations in theamplifier GBP is very low

SQpωGBP

1 (B.26)

The influence of finite amplifier DC gain on the predistorted polescan be analyzed from (B.16), assuming infinite GBP, which yields

p ≈p− K1|p|

ADC

1 + 1ADC

= p

1 + 1ADC

− K1 |p|1 + ADC

(B.27)

For poles with high quality factor, the frequency can be approximatedas

ωp ≈ Imp ≈ Imp1 + 1

ADC

(B.28)

which gives a sensitivity of

SωpADC≈

1ADC

1 + 1ADC

≈ 1ADC

(B.29)

The quality factor is approximated by

Qp ≈

∣∣∣∣∣∣∣∣Imp

1+ 1ADC

2(

Rep1+ 1

ADC− K1|p|

1+ADC

)∣∣∣∣∣∣∣∣ ≈

Imp2 Rep − 2K1|p|

ADC

(B.30)

and the resulting sensitivity is given by

SQpADC≈ 2K1

ADCQp− 2K1

≈ 2K1Qp

ADC(B.31)

For a low-Q pole, the pole frequency is approximated as

ωp ≈ |Rep| ≈∣∣∣∣∣ Rep1 + 1

ADC

− K1 |p|1 + ADC

∣∣∣∣∣ ≈∣∣∣∣|p| · (1 + K1

ADC

)∣∣∣∣ (B.32)


This results in a sensitivity of

SωpADC≈

−K1ADC

1 + K1ADC

≈ − K1

ADC(B.33)

The quality factor of a low-Q pole is not changed to a first approxima-tion, therefore the sensitivity on variations in amplifier GBP is verylow

SQpADC 1 (B.34)

Consequently, the sensitivity of the pole frequency and quality factorto variations in the amplifier DC gain is inversely proportional ADCand therefore very low for reasonably large DC gain.

Appendix C

Predistortion andTransistor Model

In this chapter, the derivation of the predistortion equations and theamplifier linearity are explained in detail.

C.1 Minimum GBP for PredistortionIt has been shown in Sec. 4.3.1, that the predistorted pole can becalculated from (4.22), which is repeated here as

p = p ·(

1 + p

α · |p|+ K1 · |p|

α · |p|

)(C.1)

where α · |p| = ωGBP was defined. For α 1, there is no solution for(C.1), because then 1 p/ (α · |p|) and (C.1) becomes

p

α · |p|+ K1 · |p|

α · |p|= p

p(C.2)

which contradicts α 1. This result is in accordance with theintuitive understanding, that an active RC circuit can not realize a

161

162APPENDIX C. PREDISTORTION AND TRANSISTOR MODEL

pole which is at higher frequency than the amplifier GBP. The polefrequency |p| can be expressed from (C.1) as

|p| = |p| ·

√(Repα |p|

+ 1 + K1 · |p|α · |p|

)2+(

Impα |p|

)(C.3)

Squaring both sides of the equation and then solving for |p| by thestandard solution of a quadratic equation, results in

|p| = −α |p|K1 − RepK1

K21 − α2

±

√(α |p|K1 + 2 RepK1)2 − (K2

1 − α2)(|p|2 + α2 |p|2 + 2αRep |p|

)K2

1 − α2

(C.4)

where |p| → ∞ for α = K1. Since |p| > 0 is required, the nominatorof (C.4) needs to be positive, which gives the condition(

K21 − α2) (|p|2 + α2 |p|2 + 2αRep |p|

)< 0 (C.5)

which is only fulfilled for α > K1. This means that a solution to (C.1)exists only if the amplifier GBP is at least K1 times larger than thedesired pole frequency. The solution (C.4) can be simplified somewhatto

|p| = −α |p|K1 − RepK1

K21 − α2

±

√|p|2 (α2 + α4) + |p| 2α3 Rep − Imp2K2

1

K21 − α2 (C.6)

The phase angle ∠ (p) of the predistorted pole is calculated from (C.1),with the amplitude |p| already calculated from (C.6) by

∠ (p) = ∠ (p) + arctan(

ImpRep+ α+K1 |p|

)(C.7)

C.2. PRACTICAL GBP FOR PREDISTORTION 163

C.2 Practical GBP for PredistortionEven if theoretically, a very low amplifier GBP can be predistorted torealize a certain desired pole, the pole location should be dominatedby the passive elements and not by the amplifier characteristic. There-fore, it is of interest, what GBP is required such that the frequencyof the predistorted pole is γ times smaller than the GBP. This iscalculated by replacing |p| in the squared version of (C.3) with |p|·α/γ.The equation can then be rearranged to

0 = α4 − α2 (γ2 +K21 + 2γK1

)− αRep

|p|(2 + 2γK1)− γ2 (C.8)

Since poles with high quality factor are more susceptible to limitedamplifier speed, Rep/ |p| 1 can be assumed and (C.8) can besolved as a quadratic equation of α2

α2 = 12

(γ2 +K2

1 + 2γK1 ±√

(γ2 +K21 + 2γK1)2 + 4

)(C.9)

α ≈√γ2 +K2

1 + 2γK1 (C.10)

where(γ2 +K2

1 + 2γK1)2 4 has been used for the approximation.

With K1 ≈ 3, the predistorted pole frequency is as large as theamplifier GBP (γ = 1), if the GBP is α = 4 times as high as the desiredpole frequency. If the passive components should clearly dominatethe pole location, say γ = 10, then the amplifier GBP needs to be13 times higher than the desired pole frequency. Adding some marginwill account for the approximations in the derivation and improve thesensitivity to variations in the GBP.

C.3 Predistortion with Combined ModelThe combined model is represented by the following equation (see(4.27))

p = p2

ωGBP· (1 +K2) + p ·

(1 + K1 |p|

ωGBP+ 1

ADC

)+ K1 |p|

ADC(C.11)


Insight into the influence of single parameters is given in Sec. 4.3.1.The solution of (C.11) is presented here and is meant to be used fornumerical calculation of the prototype poles for predistortion. Thesquared pole frequency |p|2 is expressed from (C.11) as

|p|2 =[

Rep2 − Imp2α |p|

(1 +K2) + Rep ·(

1 + 1ADC

)+ |p| ·

(RepK1

α |p|+ K1

ADC

)]2+[

2 Rep · Impα |p|

(1 +K2)

+ Imp ·(

1 + 1ADC

)+ |p| · ImpK1

α |p|

]2(C.12)

= [A+ |p|B]2 + [C + |p|D]2 (C.13)

This is solved for |p| by the quadratic equation

|p| = −b+√b2 − 4ac

2a (C.14)

with

a = B2 +D2 − 1 b = 2AB + 2CD c = A2 + C2 (C.15)

The phase angle ∠ (p) is subsequently calculated by

∠ (p) = arctan(

ImpRep

)(C.16)

with

Rep = Rep2 − Imp2α |p|

(1 +K2)

+ Rep ·(

1 + RepK1

α |p|+ 1

ADC

)+ |p|K1

ADC(C.17)

Imp = 2 Rep · Impα |p|

(1 +K2)

+ Imp ·(

1 + |p|K1

α |p|+ 1

ADC

)(C.18)

C.4. SINGLE TRANSISTOR NON-LINEARITY 165

C.4 Single Transistor Non-LinearityThe third order non-linearity of a single transistor is not modeledby the simple square-law approximation. Therefore, the mobilitydegradation θ is taken into account and the drain current can beexpressed by

Id = β

2 ·(Vgs,0 + vg (t)−Vth)2

1 + θ · (Vgs,0 + vg (t)−Vth) (C.19)

= Id0 ·1 + 2bvg (t) + b2v2

g (t)1 + avg (t) (C.20)

where β = µCoxW/L and

Id0 = β

2 ·(Vgs,0 −Vth)2

1 + θ · (Vgs,0 −Vth) (C.21)

a = θ

1 + θ · (Vgs,0 −Vth) (C.22)

b = 1Vgs,0 −Vth

(C.23)

For the Taylor series approximation, the derivatives of Id with respectto vg (t) are required.

dId

dvg= Id0 ·

2b+ 2b2vg + ab2v2g − a

1 + 2avg + a2v2g

(C.24)

d2Id

dv2g

= Id0 ·2b2 + 2ab2vg − 4ab− 4a2bvg + 2a2 + 2a3vg

1 + 4a2v2g + a4v4

g + 4avg + 2a2v2g + 4a3v3

g(C.25)

d3Id

dv3g

= . . .vg=0= −Id0 · 6a · (a− b)2 (C.26)

The coefficients of interest are the first and third order terms of theTaylor series evaluated at vg = 0

α1 = dId

dvg

∣∣∣∣vg=0

= Id0 · (2b− a) (C.27)

' Id0 · 2b = β · (Vgs,0 −Vth)1 + θ · (Vgs,0 −Vth) = gm (C.28)


α3 = 13! ·

d3Id

dv3g

∣∣∣∣vg=0

= −Id0 · a · (a− b)2 (C.29)

' −Id0 · ab2 = −β2 ·θ

(1 + θ · (Vgs,0 −Vth)) (C.30)

= − Id0θ

V 2ov

= − gmθ

2Vov= − g2

mθ

4Id0≈ −βθ2 (C.31)

where Vov = Vgs,0 −Vth.

C.5 MOSFET Hand Calculation ModelFor analog circuit designers, a simple but reliable model for the tran-sistor characteristic is very important. It allows to quickly understandthe general relationship between parameters and get insight into theoperation of a circuit. Computer simulations with complex transistormodels are then used to verify the functionality and the performanceof the circuit can be optimized.

The square law approximation is widely used to describe the I-Vcharacteristic of a long-channel MOSFET in strong inversion

Id,SI (Vgs) = 12µ0Cox

n

W

LV 2

ov · (1 + λVds) (C.32)

where Vov = Vgs −Vth and the threshold voltage is given by

Vth = Vth0 + γ(√

φS −Vbs −√φS

)(C.33)

Channel length modulation is often neglected by setting λ = 0. Theoutput resistance resulting from channel length modulation can becalculated by r0 = (λID)−1, where ID is the drain current in the DCoperating point. However, the accuracy of the output resistance isvery poor because of the simplistic modeling. The transconductancegm = ∂Id

∂Vgsis given by

gm,SI =√

2µ0Cox

n

W

LID = µ0Cox

n

W

LVov = 2ID

Vov(C.34)

C.5. MOSFET HAND CALCULATION MODEL 167

The drain current of a transistor in weak inversion can be expressedas

Id,WI (Vgs) = I0W

Le

VovnVT (C.35)

where I0 = 2nµ0CoxV 2T is called technology current and the transcon-

ductance is given bygm,WI = ID

nVT(C.36)

The characteristic of a MOSFET in the triode region (Vds < Vdsat =Vov) is described by

Id,Tr (Vgs) = µ0Cox

n

W

L·(

VovVds −12V 2

ds

)(C.37)

For small Vds, the on-resistance ron =(∂Id∂Vds

)−1can be approximated

byron = 1

µ0Coxn

WL Vov

(C.38)

Transistors in analog circuits are often operated in moderate in-version, between the strong and the weak inversion region, wherenone of the presented models fits very well. Therefore, a continuousmodel based on the EKV model has been developed in [119]. Thedrain-source current of a NMOS transistor in saturation (Vds > Vdsat)is given by

Id (Vgs) = 12µ0Cox

n

W

LV 2

ov,eff ·1

1 + θeffVov,eff· (1 + λVds) (C.39)

with

Vov,eff = 2nVT · ln(

1 + eVovnVT

)θeff = θ + 1

Ecrit · L(C.40)

The mobility degradation factor θeff models the effect of high verticaland horizontal electrical field, causing mobility reduction and velocitysaturation. For a PMOS transistor, Vgs must be replaced by Vsg in(C.39). Typical parameters for a 130 nm CMOS technology are listedin Tbl. C.1.


For high speed circuits, the MOSFET transit frequency fT is animportant parameter because it sets a basic limitation to the maxi-mum achievable speed with a specific technology. It is defined as

fT = 12π ·

gm

Cgs,sat + Cgd,sat(C.41)

Cgs,sat = 23WLCox +WCgs0 Cgd,sat = WCgd0 (C.42)

With the strong inversion, long-channel approximation and assumingCgs0 = Cgs0 = 0, (C.41) can be simplified to

fT '1

2π ·3µ0

2n ·Vov

L2 (C.43)

Table C.1: Typical parameters for a 130 nm CMOS technology [18].Symbol DescriptionVT=kT/q Thermal voltage, 25 mV at T = 290 KVth0 = 0.3 V Zero body bias threshold voltageγ = 0.5 V Body effect factorφS = 0.9 V Surface potentialn = 1.4 Substrate factorµ0,n = 30 · 10−3 m2/(Vs) NMOS low-field mobilityµ0,p = 10 · 10−3 m2/(Vs) PMOS low-field mobilityCox = 12 · 10−3 F/m2 Oxide capacitance densityθ = 0.3 V−1 Mobility degradation coefficientEcrit,n = 5 · 106 V/m Critical NMOS velocity saturation fieldEcrit,p = 15 · 106 V/m Critical PMOS velocity saturation fieldLD = 15 · 10−9 m Length diffusion, one sideL = Ldrawn − 2LD Channel lengthWD = 0 Width diffusion, one sideW = Wdrawn − 2WD Channel widthCgs0 = 300 · 10−12 F/m Gate-source overlap capacitanceCgd0 = 300 · 10−12 F/m Gate-drain overlap capacitanceλ0 = 0.1 · 10−6 m/V Channel length modulation factor a

aλ = λ0/L

Acronyms

Acronyms

1G First Generation2G Second Generation3G Third Generation4G Fourth Generation

ADC Analog-to-Digital ConverterAGC Automatic Gain ControlASM Antenna Switch ModuleAWGN Additive White Gaussian Noise

BB Base-BandBBF Base Band FilterBS Base StationBW Bandwidth

CA Carrier AggregationCC Component CarrierCDM Code Division MultiplexingCDMA Code Division Multiple AccessCFS Coarse Frequency SelectionCR Cognitive Radio

169

170 Acronyms

CT Continuous-TimeCW Continuous Wave

DAC Digital-to-Analog ConverterDFE Digital Front-EndDT Discrete-Time

EDGE Enhanced Data rates for GSM EvolutionENOB Effective Number Of BitsEVM Error Vector Magnitude

FDD Frequency-Division DuplexFDMA Frequency Division Multiple AccessFFS Fine Frequency SelectionFFT Fast Fourier Transform

GBP Gain-Bandwidth ProductGMSK Gaussian Minimum Shift KeyingGPRS General Packet Radio ServiceGSM Global System for Mobile Communication

ICP Input Compression PointIFFT Inverse Fast Fourier TransformIRR Image Rejection RatioISI Inter-Symbol Interference

LAN Local Area NetworkLHP Left Half PlaneLNA Low-Noise AmplifierLO Local OscillatorLTE Long Term Evolution

MEMS Micro-Electro-Mechanical-SystemMIM Metal-Insulator-Metal

Acronyms 171

MIMO Multiple-Input Multiple-OutputMS Mobile Station

NF Noise Figure

OFDM Orthogonal Frequency-Division Multiplexing

PA Power AmplifierPAPR Peak-to-Average Power RatioPCB Printed Circuit BoardPM Phase MarginPVT Process-Voltage-Temperature

QAM Quadrature Amplitude ModulationQPSK Quadrature Phase-Shift Keying

RAT Radio Access TechnologyRF Radio FrequencyRFFE RF Front-End

SAW Surface Acoustic WaveSC-FDMA Single Carrier Frequency Division Multiple AccessSDR Software Defined RadioSFG Signal Flow GraphSIR Signal-to-Interference RatioSNDR Signal-to-Noise-and-Distortion RatioSNR Signal-to-Noise RatioSR Software RadioSSB Single-Sideband

TDD Time-Division DuplexTDMA Time Division Multiple AccessTD-SCDMA Time Division Synchronous CDMA

172 Acronyms

UMTS Universal Mobile Telecommunications System

WCDMA Wideband CDMAWiMAX Worldwide Interoperability for Microwave AccessWLAN Wireless Local Area Network

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Curriculum Vitae

Rene BlattmannBorn March 18, 1983 in Winterthur

Professional Experience

2014 - Today ams International AG, RapperswilAnalog Design Engineer

2014 (2 months) Advanced Circuit Pursuit (ACP) AG, ZurichAnalog Design Engineer

2009 - 2014 Integrated Systems Laboratory, ETH ZurichResearch and Teaching Assistant

2007 (5 months) Sensirion AG, StafaInternship

Education

2009 - 2016 Integrated Systems Laboratory, ETH ZurichPh.D. Candidate in Electrical Engineering

2002 - 2008 Eidgenossische Technische Hochschule (ETH)Swiss Federal Institute of Technology, ZurichMaster of Science in Electrical Engineering

1995 - 2002 Kantonsschule Zurcher Unterland, BulachHigh School: Eidgenossische Matura Type C

187

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Rights / License: Research Collection In Copyright - Non ... · a multitude of wireless communication standards. The dynamic range requirements of cellular communication is too challenging