RFIC Loadpull Simulations Implementing Best Practice RF and Mixed-

Signal Design using an Integrated Agilent and Cadence EDA tool Jayanta Mukherjee, Jason Parry, WenHua Dai, Patrick Roblin, Steven Bibyk, Jongsoo Lee

Department of Electrical Engineering

The Ohio State University

{mukherjj, parryj, daiw, roblin, bibyk, leej1}@ee.eng.ohio-state.edu

ABSTRACT

This paper describes the use of the newly developed Cadence to

ADS dynamic link in loadpull simulations for BiCMOS RFIC

design in a University environment. The process described here

helps a designer achieve an integrated design environment where

both RF design and traditional VLSI design principles can be

applied in an integrated manner.

1. INTRODUCTION

In recent years there has been noted thrust towards development

of RF IC’s using CMOS and BiCMOS technologies. While

traditional RF design employs design tools like Libra and ADS,

they prove to be insufficient for IC design primarily because of

lack of transistor IC models and secondly because of their inability

to provide layout facilities. From a RF design standpoint ADS

provides greater flexibility in performing the complex RF

simulation than that provided by Cadence. As an example in

Amplifier design projects we often need to do the Loadpull

simulations to achieve the desired design parameters like Gain,

IIP3, Noise Figure, Input and Output matching. On the other hand

traditional VLSI design tools like Cadence and Mentor Graphics

are more suitable for design layout. It is very tempting for a

designer to incorporate the features of both these powerful tools in

an integrated way so as to develop better designs. The cadence to

ADS dynamic link (IDF) provides a convenient way to do this. In

this paper we shall describe the use of this tool in performing

Loadpull simulations. The selected design is that of a BiCMOS

LNA using IBM6HP SiGe process.

2. THE PROCESS

The process can be summarized as shown by the flow diagram

below

Figure 1: Design flow for Load pull simulations

The first step in this process is to start the LNA design using a

standard configuration using two cascaded stages as shown in

Figure (2a).

In the next step a symbol of this design is generated as shown in

Figure (2b). Here each of the inputs and outputs of the LNA have

been represented by ports in the symbol. A point to note is that

only device directly associated with the process in question can be

incorporated in the symbol. This symbol can then be translated to

the ADS simulator directly. Once translated, an appropriate

process file should be incorporated in the design as shown in

Figure (2c). All other circuit elements like sources and

terminations have to be separately connected in ADS using the

standard elements already provided in ADS.

(a)

(b)

(c)

Figure 2: Diagram showing how a schematic is imported from Cadence into ADS through the use of symbols

The load pull setup involves a harmonic balance simulation on a

sweep of the load impedance. For computing the gain a single tone

signal is applied at the input. Further, the amplitude of this signal is

also swept. At each point of the load sweep, the values

corresponding to the Gain of the amplifier is obtained. For

computing the IIP3, a two-tone signal at constant amplitude is

applied at the input of the LNA. The output spectrum thus obtained

and the gain computed from the previous step are used to compute

the IIP3 using the formula,

1312

13 PPPIIP , P1 is the first order harmonic and P3

is the third order intermodulation

product

For computing the Noise Figure a similar operation is carried

out on an S parameter simulation. A sample loadpull setup for

Proceedings of the 2003 IEEE International Conference on Microelectronic Systems Education (MSE’03) 0-7695-1973-3/03 $17.00 © 2003 IEEE

computing IIP3 has been shown in Figure (3). The results obtained

from these simulations can be easily plotted in raw form and have

been shown in Figure (4).

ADS provides very little means of processing this raw data to

obtain the load pull contours. MATLAB proves to be more

convenient for this purpose. This raw data can be very easily

transferred to a MATLAB data file, which can then be plotted as

shown in Figure (5) to represent the load pull curves.

Figure 3: Load pull set up for IIP3 and Noise Figure Simulations

The point A in all the three curves correspond to the optimum

load termination for the given LNA, since the load corresponding

to point A provides a good compromise between the three main

design parameters namely, Gain, IIP3 and NF. A combination of

on chip capacitance and spiral inductors can be used to achieve this

termination .As shown in Figure (6), for the example LNA the

termination was obtained using a single spiral inductor only.

Figure 4: Sample IIP3 raw data display in ADS

3. CONCLUSION

The dynamic link provides a convenient way to combine the

advantages of ADS and Cadence and has proved to be an effective

tool in Amplifier design. The above-mentioned steps can be easily

repeated for a Power Amplifier (PA) design or even for a Mixer

design. The LNA shown in Figure (6) gives a NF of 1.9dB, IIP3 of

–5.8 dBm and a gain of 17.5dB.

Figure 5: Loadpull curves plotted using MATLAB

Figure 6: Final LNA schematic with appropriate terminations

REFERENCES

[1] Designing an LNA for a CDMA front end, Jarek Lucek and

Robbin Damen, RFDesign (www.rfdesign.com), Feb 1999

[2] E8970A RFIC Dynamic Link to Cadence Documentation,

Agilent Technologies

[3] Advance Design System 2002 Documentation, Agilent

Technologies.

[4] Virtuoso Schematic Editor Documentation 2002, Cadence

Design System

Proceedings of the 2003 IEEE International Conference on Microelectronic Systems Education (MSE’03) 0-7695-1973-3/03 $17.00 © 2003 IEEE