RF System On Chip Quadrature VCO Comparison 1/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

Fortià Vila Vergés

19th June 2007

Introduction Design procedure Comparison Conclusions

Design and comparison of several 2.5-GHz CMOS

Quadrature VCO using Epson CTH180nm technology

Design and comparison of several 2.5-GHz CMOS

Quadrature VCO using Epson CTH180nm technology

RF System On Chip Quadrature VCO Comparison 2/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

11 Introduction

22 Design procedure

33 Coupling capacitors VCO

44 Common point VCO

55 Crossed capacitors VCO

66 Conclusions

RF System On Chip Quadrature VCO Comparison 3/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

VCO

Introduction Quadrature

Amplitude & Stabilization Time

Phase noise

RF System On Chip Quadrature VCO Comparison 4/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

Fixed parameters

Design Procedure Capacitance

Transconductance Transistors design

TOT 20

Tank TOT NMOS LOAD TUNNING

TUNNING

TANK

1C 600fF

W L

C C C C C

C 80fF

C 600fF 120fF 80fF 400fF

m

2g 1mS

Rp

mg 10mS

m bias

Wg 2K ' I

L

Power consumption<1mW

High Q inductor (19-6.8nH).

High PSRR rejection.

Low power supply (1.2V) Coarse with a capacitor bench

Fine with the varactor

Source degradation

Capacitive Q

Transistor losses

Load impedance

Start-up

W/L=600

L=180nm

W=100μm

Differential LC-tank topology

RF frequency 2.5GHz

RF System On Chip Quadrature VCO Comparison 5/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

Schematic

Coupling Transistors VCO Quadrature generator

Design quadrature ratio

cross _ pair

Quad

WWidth _ ratio 10

W

Better phase noise

Worse phase error

RF System On Chip Quadrature VCO Comparison 6/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

Coupling Transistors VCO Stabilization time & Vp Phase error

Output power & phase noise Noise summary

Biasing: 7.860e-13 81%

Quadrature: 5.36692e-14 6%

RF System On Chip Quadrature VCO Comparison 7/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

Schematic

Common Point VCO Quadrature generator

Main idea

Odd harmonics in differential mode

Even harmonics in common mode

RF System On Chip Quadrature VCO Comparison 8/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

Common Point VCO Stabilization time & Vp Phase error

Output power & phase noise Noise summary

Bias: 6.08e-13 78.6%

Quadrature: 3.31e-15 0.42%

RF System On Chip Quadrature VCO Comparison 9/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

Schematic

Crossed Capacitors VCO Quadrature generator

Biasing solution

Rbias (20K ) LPF MHz Pnoise(1MHz) Tstab

Rbias (20M ) LPF KHz Pnoise(1MHz) Tstab

Transmission gate

Pnoise(1MHz) Tstab

RF System On Chip Quadrature VCO Comparison 10/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

Crossed Capacitors VCO Stabilization time & Vp Phase error

Output power & phase noise Noise summary

Bias: 5.16e-15 8.5%

Quadrature: 6.29e-18 0.1%

RF System On Chip Quadrature VCO Comparison 11/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

ComparisonCoupled

Transistors VCOCommon Point

VCOCrossed

Capacitors VCO

Output Voltage Signal (Vp)

530mV 580mV 450mV

Stabilization Time

90ns 35ns 180ns

Phase Error 3º 1º 0.1º

Phase Noise -109.4 dBc -110.2 dBc -121.3dBc

Min. Harmonic difference

-50 dBm -52 dBm -48 dBm

RF System On Chip Quadrature VCO Comparison 12/12

Fortià Vila Vergés Universitat Politecnica de Catalunya E.T.S.E.T.B.

11 This results are under a low power consumption, low power supply & high PSRR context.

22 Using short channel transistors degrade the gain.

3 3 Technology mismatch it’s another important factor.

4 4 Avoid transistors if we can use passive elements.

5 5 Noise contribution has more to do with a topology than a device.

Conclusions