RF Power Amplifiers and MEMS Varactors - McGill …digitool.library.mcgill.ca/thesisfile112576.pdf · Cette thèse est concernée par la conception et l'exécution des amplificateurs

RF Power Amplifiers and MEMS Varactors

by Sareh Mahdavi

Department of Electrical & Computer Engineering McGill University, Montréal

November 2007

A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Master of Engineering.

© Sareh Mahdavi, 2007

1+1 Library and Archives Canada

Bibliothèque et Archives Canada

Published Heritage Bran ch

Direction du Patrimoine de l'édition

395 Wellington Street Ottawa ON K1A ON4 Canada

395, rue Wellington Ottawa ON K1A ON4 Canada

NOTICE: The author has granted a nonexclusive license allowing Library and Archives Canada to reproduce, publish, archive, preserve, conserve, communicate to the public by telecommunication or on the Internet, loan, distribute and sell theses worldwide, for commercial or noncommercial purposes, in microform, paper, electronic and/or any other formats.

The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission.

ln compliance with the Canadian Privacy Act some supporting forms may have been removed from this thesis.

While these forms may be included in the document page count, their removal does not represent any loss of content from the thesis.

• •• Canada

AVIS:

Your file Votre référence ISBN: 978-0-494-51467-2 Our file Notre référence ISBN: 978-0-494-51467-2

L'auteur a accordé une licence non exclusive permettant à la Bibliothèque et Archives Canada de reproduire, publier, archiver, sauvegarder, conserver, transmettre au public par télécommunication ou par l'Internet, prêter, distribuer et vendre des thèses partout dans le monde, à des fins commerciales ou autres, sur support microforme, papier, électronique et/ou autres formats.

L'auteur conserve la propriété du droit d'auteur et des droits moraux qui protège cette thèse. Ni la thèse ni des extraits substantiels de celle-ci ne doivent être imprimés ou autrement reproduits sans son autorisation.

Conformément à la loi canadienne sur la protection de la vie privée, quelques formulaires secondaires ont été enlevés de cette thèse.

Bien que ces formulaires aient inclus dans la pagination, il n'y aura aucun contenu manquant.

Abstract

This thesis is concerned with the design and implementation of radio frequency (RF)

power amplifiers and micro-electromechanical systems - namely MEMS varactors. This

is driven by the many wireless communication systems which are constantly moving

towards increased integration, better signal quality, and longer battery life.

The power amplifier consumes most of the power in a receiver/transmitter system

(transceiver), and its output signal is directly transmitted by the antenna without further

modification. Thus, optimizing the PA for low power consumption, increased linearity,

and compact integration is highly desirable.

Micro-electromechanical systems enable new levels of performance in radio-frequency

integrated circuits, which are not readily available via conventional IC technologies.

They are good candidates to replace lossy, low Q-factor off-chip components, which have

traditionally been used to implement matching networks or output resonator tanks in class

AB, class F, or classE power amplifiers. The MEMS technologies also make possible the

use of new architectures, with the possibility of flexible re-configurability and tunability

for multi-band and/or multi-standard applications.

The major effort of this thesis is focused on the design and fabrication of an RF

frequency class AB power amplifier in the SiGe BiCMOS 5HP technology, with the

capability of being tuned with extemal MEMS varactors. The latter necessitated the

exploration of wide-tuning range MEMS variable capacitors, with prototypes designed

and fabricated in the Metal-MUMPs process.

An attempt is made to integrate the power amplifier chip and the MEMS die in the same

package to provide active tuning of the power amplifier matching network, in order to

keep the efficiency of the PA constant for different input power levels and Joad

conditions.

Detailed simulation and measurement results for ail circuits and MEMS deviees are

reported and discussed.

Il

Résumé

Cette thèse est concernée par la conception et l'exécution des amplificateurs de puissance

de la radiofréquence (RF) et des systèmes micro-électromécaniques - comme les

varactors de MEMS. Ceux-ci sont conduits par de nombreux systèmes de communication

sans-fil qui se déplacent constamment vers une croissance en intégration, une meilleure

qualité de signal, et une plus longue vie de batterie.

L'amplificateur de puissance consomme la majeure partie de la puissance dans un

récepteur/système émetteur (émetteur récepteur), et son signal de sortie est directement

transmis par une antenne sans modifier davantage. Ainsi, pour optimiser la PA pour une

consommation de puissance basse, une linéarité accrue et une intégration compacte sont

fortement souhaitables.

Les systèmes micro-électromécaniques (MEMS) permettent de nouveaux niveaux

d'exécution dans des circuits intégrés de radiofréquence, qui ne sont pas facilement

disponibles par l'intermédiaire des technologies conventionnelles d'IC. Ils sont de bons

candidats pour remplacer les composants hors puce de bas facteur-Q, qui ont été

traditionnellement employés pour mettre en application les réseaux ou les réservoirs

assortis de résonateur de rendement dans des amplificateurs de puissance de la classe AB,

de la classe F, ou de la classe E. Les technologies de MEMS rendent également

lll

l'utilisation possible de nouvelles architectures, avec la possibilité de re-configuration et

de tunabilité flexibles pour des applications multibandes et/ou multistandardes.

L'effort principal de cette thèse est concentré sur la conception et la fabrication d'un

amplificateur de puissance de la classe AB de fréquence de RF en technologie de SiGe

BiCMOS 5HP, avec les possibilités de l'accord avec les varactors externes de MEMS. Le

dernier a rendu nécessaire l'exploration des condensateurs variables de large-accord de la

gamme MEMS, avec des prototypes conçus et fabriqués dans le processus de Métal

MUMPS.

Une tentative est d'intégrer le morceau d'amplificateur de puissance et la matrice de

MEMS dans le même paquet pour fournir l'accord actif du réseau assorti d'amplificateur

de puissance, afin de garder l'efficacité de la PA constante pour différents niveaux de

puissance d'entrée et conditions de charge.

Des résultats détaillés de simulation et de mesure pour tous les circuits et dispositifs de

MEMS sont rapportés et discutés.

lV

Acknowledgments

First and foremost, I would like to thank my supervisor Professor Mourad El-Gamal for

his patience, invaluable guidance, encouragements and for giving me the opportunity to

pursue a masters' degree at the McGili Radio-Frequency Integrated Circuits (RFIC) lab.

1 would also like to thank ali the members of the RFIC lab especialiy Nicolas Constantin

and Tommy Tsang, who were always there to help and patiently answered my questions.

1 would like to thank Laurent Mouden from École Polytechnique de Montréal who helped

with the wire-binding of my chips. 1 am also grateful to Michele Perucic for her help with

the setting up SiGe environment in Cadence.

Many thanks to other members of the RFIC group Mohamed Shaheen, Jane Yu, David

Hong, Frederic Nabki, Kuan-Yu Lin, Hanzhen Zhang, Barry Zhao, and Erica Kwizak.

My deep gratitude to my good friends Y asmin Ahmad, Patricia Lee, and Hung Pao Yang.

1 sincerely thank my sister Sajedeh, and my brothers Saied and Sadegh for their

understanding and support.

This thesis is dedicated to my parents Ra'na Shahintabe and Gholamreza Mahdavi for ali

their love, support, and encouragement.

v

Table of Contents

1 INTRODUCTION ..................................................................................................................................... 1

1.1 MOTIVATION ........................................................................................................................................ 2

1.2 LITERA TURE REVIEW ......... ························ ........................................................................................... 4

1.3 OBJECTIVES .......................................................................................................................................... 7 1.4 THESIS ÜUTLINE ................................................................................................................................... 7

1.5 CONTRIBUTIONS ................................................................................................................................... 9

2 POWER AMPLIFIERS .......................................................................................................................... 10

2.1 PA ME TRIC DEFINITIONS .................................................................................................................... 11 2.1.1 Output Power and Power Gain .................................................................................................. 11 2.1.2 Efficiency ................................................................................................................................... 12

2.1.2.1 Gollector Efficiency .......................................................................................................................... 12 2.1.2.2 Power-Added-Efficiency ................................................................................................................. 12

2.1.3 Linearity ..................................................................................................................................... 13 2.1.3.1 Sources of Nonlinearity .................................................................................................................. 14 2.1.3.2 Measures of Linearity ..................................................................................................................... 15

2.1. 4 Stability ............. ......................................................................................................................... 15 2.2 CHOICE OF ARCHITECTURE ................................................................................................................. 16

2. 2.1 Linear Amplijiers ..................................... .................................................................................. 17 2.2.1.1 Glass A ............................................................................................................................................. 17 2.2.1.2 Glass B ............................................................................................................................................. 19 2.2.1.3 Glass AB ........................................................................................................................................... 20

2.2.2 Nonlinear Amplifier ................................................................................................................... 20 2.2.2.1 Glass G ............................................................................................................................................. 20 2.2.2.2 Glass F .............................................................................................................................................. 21 2.2.2.3 Glass E ............................................................................................................................................. 22

2.2. 3 High-Linearity and High-Efficiency RF PA - Tradeoffi ............. ............................................... 24 2.2.4 Analysis ofClass AB Power Amplijiers ..................................................................................... 24

2.2.4.1 Harmonie Termination .................................................................................................................... 27 2.2.4.2 Tunable Load Resistance .............................................................................................................. 27

2.3 PA DESIGN TECHNIQUES .................................................................................................................... 28 2.3.1 Power Match vs. Corifugate Match ............................................................................................ 29 2.3.2 Load-Pull Technique .................................................................................................................. 31

3 DESIGN OF POWER AMPLIFIERS ................................................................................................... 33

3.1 PA DESIGN IN A SIGE TECHNOLOGY .................................................................................................. 33 3.1.1 Choice ofTechnology ................................................................................................................. 33

VI

3.1.2 Power Amplifier Specifications .................................................................................................. 34 3.1.3 Single Transistor Design ............................................................................................................ 34

3.1.3.1 Biasing Circuit Design .................................................................................................................... 35 3. 1.3.2 Power Core Design ......................................................................................................................... 38 3.1.3.3 Input Matching Network .................................................................................................................. 42 3.1.3.4 Output Impedance Transformation ............................................................................................... 42 3.1.3.5 Simulation Results .......................................................................................................................... 44

3.1.4 Multiple Transistor Design ........................................................................................................ 45 3.1.4.1 ESD Protection ................................................................................................................................ 48

3.2PALAYOUT ........................................................................................................................................ 49

3.3 EXTRACTED PA SIMULATION RESULTS .............................................................................................. 51

3.4 PACKAGE, BONDWIRE, AND PCB MO DELS ......................................................................................... 53

3.4.1 Bondwire Mode! ......................................................................................................................... 54 3.4.2 Package Mode! ........................................................................................................................... 54 3.4.3 PCB Track Mode! ...................................................................................................................... 55 3.4. 4 Final Simulation Results ............................................................................................................ 55

4 MEMS TUNABLE POWER AMPLIFIER ........................................................................................... 56

4.1 MEMS TUNABLE CAPACITORS .......................................................................................................... 57 4.1.1 Overview .................................................................................................................................... 57 4.1.2 Principle ofOperation ............................................................................................................... 58

4.1.2.1 Parallei-Piate MEMS Varactor ....................................................................................................... 58 4.1.2.1(a) Type II Vertical Varactor ........................................................................................................... 60 4.1.2.1(b) Type III Vertical Varactor ......................................................................................................... 61

4.1.2.2 Laterallnterdigitated MEMS Varactors ........................................................................................ 61 4.1.2.3 Semi-Fractal Varactor ..................................................................................................................... 62

4.1.3 The Metal-MUMPS Process ...................................................................................................... 63 4.1.4 MEMS Varactor Design in Metal-MUMPS ............................................................................... 64

4.1.4.1 Suspension Design ......................................................................................................................... 66 4.1.4.2 Signal Pad Design ........................................................................................................................... 68

5 MEASUREMENT RE SUL TS ................................................................................................................ 69

5.1 THE TEST SETUP ................................................................................................................................. 69 5.2 STAND-ALONEPOWERAMPLIFIER TESTING ....................................................................................... 71

5.3 MEMS VARACTORS TESTING ............................................................................................................. 74

5.4 MEMS-TUNABLE POWER AMPLIFIER TES TING .................................................................................. 78

6 CONCLUSION ........................................................................................................................................ 81

6.1 SUMMARY .......................................................................................................................................... 81

6.2 TOPICS FOR FUTURE RESEARCH ......................................................................................................... 82

7 REFERENCES ........................................................................................................................................ 84

APPENDIX A: ADS MO DEL FITTING ................................................................................................. 92

vii

List of Figures

FIGURE 1.1: SIMPLIFIED TRANSMITIER ARCHITECTURE ...................•.........•..........•...•.....•••.....•..•.....•••......... 1

FIGURE 1.2: GENERIC SINGLE-ENDED PA HIGHLIGHTING SECTIONS THAT GAN BE INTEGRATED AS MEMS-

BASED COMPONENTS .......•..............•...........................•.......•.............•................•............•............••.•..... 2

FIGURE 1.3: POWER AMPLIFIER OUTPUT POWER PROBABILITY DENSITY FUNCTION FOR IS-95 URBAN AND

SUBURBAN ENVIRONMENTS [5], [6] .....................................•.........................................•...................... 3 FIGURE 1.4: THE POWER-CONTROLLABLE CLASS-E PA IMPLEMENTED IN [9] WITH TUNABLE OUTPUT

CAPACITORS ................................•..............................................•.........•......•......................•...............•.. 4

FIGURE 1.5: SIMULATED RESUL TS OF POWER-ADDED-EFFICIENCY VERSUS OUTPUT POWER FOR THE

POWER-CONTROLLABLE PA PROPOSED IN [9] ..................................................................................... 5

FIGURE 1.6: SIMPLIFIED CIRCUIT OF ELECTRONICALL Y TUNABLE GLASS E PA DEVELOPED IN [1 0] ............ 6

FIGURE 1.7: SCHEMA TIC OF THE OUTPUT MATCHING NETWORK WITH FOUR MEMS SWITCHES (M1-M4) AND ONE (SEMICONDUCTOR] VARACTOR. C1-C8 ARE FIXED CAPACITORS. MUNIS A MICROSTRIP

TRANSMISSION UNE (14] ....................................................................................................................... 6

FIGURE 1.8: RESULTS OBTAINED BY HAVING TUNABLE MATCHING NETWORKS IN [14]. THE DOTS

REPRESENT THE OPTIMIZED OUTPUT POWER AS A FUNCTION OF FREQUENCY. EACH CURVE

REPRESENTS THE FREQUENCY RESPONSE OF THE AMPLIFIER WHEN IT IS OPTIMALL Y CONFIGURED

FOR ONE SPECIFIC FREQUENCY [14]. ................................................................................................... 7

FIGURE 2.9: HARMONIC DISTORTION AND CARRIER-TO-INTERMODULATION RATIO ................................... 14

FIGURE 2.1 0: GENERIC SINGLE-ENDED PA. ............................................................................................... 17

FIGURE 2.11: CLASSA COLLECTOR CURRENT AND VOLTAGE WAVEFORMS .............................................. 18 FIGURE 2.12: CLASS B COLLECTOR CURRENT AND VOL TAGE WAVEFORMS .............................................. 19

FIGURE 2.13: (A) TRANSFORMER-COUPLED PUSH-PULL PA, (B) COMPLEMENTARY PA ...............•........... 20

FIGURE 2.14: CLASS C COLLECTOR CURRENT AND VOL TAGE WAVEFORMS .............................................. 21

FIGURE 2.15: CLASS F COLLECTOR CURRENT AND VOL TAGE WAVEFORMS ....................•.......................... 22

FIGURE 2.16: CLASS E PA CIRCUIT. ··························································································•·············•·· 23 FIGURE 2.17: CLASSE COLLECTOR CURRENT AND VOL TAGE WAVEFORMS .............................................. 23

FIGURE 2.18: GLASS AB COLLECTOR CURRENT WAVEFORM ...........................•.........................••......•.•..... 25 FIGURE 2.19: CLASS AB COLLECTOR VOL TAGE WAVEFORM .....................................•....•....•..................•... 25 FIGURE 2.20: THE GENERAL MATCHING T-NETWORK. ...............................•..........................••..................... 30

FIGURE 2.21: EXAMPLE OF LOAD-PULL CONTOURS FOR A GIVEN PA. ....................................................... 32

FIGURE 3.22: ONE-STAGE POWER AMPLIFIER WITH ACTIVE BIASING ......................................................... 35

FIGURE 3.23: ACTIVE BIASING CIRCUIT ....................................................................................................... 36

FIGURE 3.24: BIAS NETWORK WITH THE POSSIBILITY OF A THERMAL RUNAWAY ........................................ 37

FIGURE 3.25: CRITICAL RF PATHS IN THE PA ..................................................................................•.....•... 39

FIGURE 3.26: INITIAL PACKAGE PIN MODEL. ..........................•.•.•..........................••.........•.......•.......•........... 41

FIGURE 3.27: TwO-COMPONENT MATCHING NETWORKS: (A) LOW-PASS AND (B) HIGH-PASS ...................•...•. 42

V Ill

FIGURE 3.28: SINGLE-TRANSISTOR PA LOAD-PULL CIRCLES FOR MAXIMUM Pour······································ 43 FIGURE 3.29: SINGLE-TRANSISTOR PA OUTPUT POWER CHARACTERISTICS VS. INPUT POWER ............... 44 FIGURE 3.30: SINGLE-TRANSISTOR PA POWER GAIN .........................................•.•................•.................... 45 FIGURE 3.31: BIASING SCHEMES FOR PARALLEL TRANSISTORS ................................................................. 46

FIGURE 3.32: 0FF-CHIP POWER-COMBINING .............................................................................................. 47 FIGURE 3.33: ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT ...............................•....••....................... 48 FIGURE 3.34: SEPARATION AND ISOLATION OF RF SIGNALS TO MINIMIZE INTERFERENCE ........................ 49 FIGURE 3.35: LAYOUT VIEW OF A BOND-PAO WITH ESD PROTECTION ......................................•••.•............ 50 FIGURE 3.36: FINAL PA LAYOUT .............................................................•.......................•..............•............ 51 FIGURE 3.37: EXTRACTED PA GAIN AT 10 = 10 MA. .................•.............................•..............................•.... 51

FIGURE 3.38: EXTRACTED PA POWER-ADDED-EFFICIENCY, PAE, AT 10 = 10 MA ....•...........•...•......•.•.•..... 52 FIGURE 3.39: THE SETUP FOR DEVELOPING EMPIRICAL MODELS FOR THE PCB TRACK, THE BONDWIRE,

AND THE PACKAGE PIN ........................................................................................................................ 53 FIGURE 3.40: BONDWIRE MODEL FOR A 1 MM OF BONDWIRE .......................................................•............. 54

FIGURE 3.41: A SINGLE PACKAGE PIN MODEL. .........................................•......•....•..............•••................•.... 54

FIGURE 3.42: PCB LINE MODEL PER 50 MILS (0.127 CM) ..............................................................••.......... 55 FIGURE 3.43: S21 RESPONSE OF THE PA WITH THE NEW AND MORE ACCURATE MODELS IN PLACE ........ 55 FIGURE 4.44: TWO-PLATE ELECTROSTATICALLY ACTUATED MEMS VARACTOR ....................................... 58 FIGURE 4.45: TYPE Il PARALLEL-PLATE MEMS VARACTOR WITH WIDE TUNING RANGE ............................ 60 FIGURE4.46: TYPE Ill PARALLEL-PLATE MEMS VARACTORWITH VERYWIDE TUNING RANGE ..•.......••..... 61 FIGURE 4.47: INTERDIGITATED LATERAL MEMS VARACTOR. ..................................................................... 62 FIGURE 4.48: TOP VIEW OF THE SEMI-FRACTAL MEMS VARACTOR .......................................................... 63 FIGURE 4.49: 0VERVIEW OF THE METAL-MUMPS STRUCTURAL LAYERS ...............•....•............................ 64 FIGURE 4.50: TOP VIEW OF THE VARACTOR DESIGNED IN METAL-MUMPS .............................................. 64 FIGURE 4.51: FUNCTIONAL MODEL OF THE DESIGNED TWO-PLATE WIDE RANGE VARACTORS .................. 65 FIGURE 4.52: T-TYPE SUSPENSION AND THE EQUIVALENT SPRING MODEL. ............................................... 67

FIGURE 4.53: THE GSG SIGNAL PAO FOR ON-CHIP PROBING .....................•.•.........•..........•.....•..•.......••...... 68

FIGURE 4.54: THE CROSS SECTION AL VIEW OF THE RF PAO IN METAL-MUMPS .......................................... 68 FIGURE 5.55: THE PA DIE ........................................................•.................................................................. 69 FIGURE 5.56: (A) THE PA DIE PLACEMENT IN THE PACKAGE, (B) THE TOP VIEW OF THE PCB CONTAINING

THE STAND-ALONE PA ........................................................................................................................ 70 FIGURE 5.57: THE MEASURED S11 AND S21 FOR THE UN-MATCHED STAND-ALONE PA. ............................ 71 FIGURE 5.58: SIMULATED S11 AND S21 FOR THE UN-MATCHED STAND-ALONE PA .................................... 72 FIGURE 5.59: MEASURED S11 AND S21 FOR THE STAND-ALONE PA ........................................................... 73 FIGURE 5.60: THE MEMS VARACTORS DIE ................................................................................................ 74 FIGURE 5.61: THE MEMS SPIRAL-ARMS 1 PF NOMINAL CAPACITOR ......................................................... 75 FIGURE 5.62: CAPACITANCE OF SPIRAL-ARMS 1 PF NOMINAL CAPACITOR AS A FUNCTION OF FREQUENCY

AT0VAND35V .....................................................................•........•.................•....•.•..•••.•.................. 75

FIGURE 5.63: CAPACITANCE OF THE SPIRAL-ARMS 1 PF NOMINAL CAPACITOR AS A FUNCTION OF

ACTUATION VOLTAGES AT 630 MHz AND 1.88 GHz ...........•...•........•.•....•....................•.......•............ 76

FIGURE 5.64: FUNCTIONAL MODEL OF THE TWO-PLATE WIDE RANGE VARACTORS WITH TUNING STEPS .. 77 FIGURE 5.65: THE PACKAGED MEMS-TUNABLE POWER AMPLIFIER. ......................................................... 78

FIGURE 5.66: THE MEASURED S11 AND S21 FOR THE UN-MATCHED MEMS-TUNABLE PA. .....•........•........ 79 FIGURE 5.67: THE MEASURED 811 AND 821 FOR THE MATCHED MEMS-TUNABLE PAS .................................. 80 FIGURE A.68: THE BLACK BOX AND THE EMPIRICAL RLC MODEL FOR CHARACTERIZING THE PACKAGE PIN,

THE BONDWIRES AND THE PCB TRACES ............................................................................................ 93 FIGUREA.69: THE SIMULATION SETUP FOR THE MODEL FITTING SCHEME ................................................. 93

IX

List of Tables

TABLE 2.1: EFFICIENCY OF GLASS F PA WITH RESPECT TO THE NUMBER OF HARMONICS [15]. ............... 22

TABLE 2.2: PA LINEARITY AND EFFICIENCY TRADEOFFS .....................................•...........•........................... 24

TABLE 3.3: THE CURRENT CAPABILITY OF SIGE TRANSISTORS .................................................................. 39

TABLE 3.4 POWER GAIN AND PAE AS FUNCTION OF la··············································································· 52 TABLE 4.5: CAPACITOR PLATE DIMENSIONS ................................................................................................ 66

TABLE 4.6: CAPACITOR SUSPENDING ARM DIMENSIONS ............................................................................. 67

TABLE 5.7: MEASUREMENT RESULTS FOR MEMS VARACTORS AT 1.88 GHz ........................................... 77

x

/"'"',

Chapter 1 : Introduction

1 Introduction

A power amplifier converts the radio frequency, RF, input power and DC power from the

supply into RF or microwave output power. Figure 1.1 shows a simplified wireless

transmitter architecture. The precise frequency of the output signal is set by the voltage

controlled oscillator, VCO, and the phase-locked loop, PLL. The power amplifier, PA,

then amplifies the desired radio frequency signal to a specified power level before it is

radiated by the antenna. A matching network, MN, is used to set the output impedance of

the ,pA for maximum efficiency or power transfer. The application of power amplifiers

are not limited to wireless communications; they also find widespread use in radar, RF

heating, plasma generation, laser driving circuiting, magnetic resonance imaging, and

miniature DC-DC conversion [1], [2].

r---------, 1 1

1 1

1 1

1 1 1

1

1

Figure 1.1: Simplified transmitter architecture.

1~

Chapter 1: Introduction

Biasing Circuit

V cc

RFC Output

Matching Network

Transistor

Figure 1.2: Generic single-ended PA highlighting sections that can be integrated as MEMS-based components.

The emerging micro-electromechanical systems technology, MEMS, offers the

possibility of improving the RF integrated circuit performance in terms of size, linearity,

and power consumption through simple surface micromachining techniques. This

technology thus has the potential of overcoming the limitations that are conventionally

inherent with the power amplifier design.

1.1 Motivation

The trend in wireless communication systems design in general is towards more

integration, lower power consumption, and better signal quality. In terms of power

amplifier design, similar trends are also seen. Figure 1.2 demonstrates a generic single

ended power amplifier. Practical PA design involves a great deal of optimization; for this

reason the input and output matching networks are often realized through discrete

components to allow for flexibility. The se components are good candidates to be

implemented by MEMS-based tunable capacitors or inductors. Another possibility is to

use high quality factor MEMS resonators as tho se in [3] and [ 4] in the output resonator

tank in class AB, class For classE amplifiers (to be discussed in detail in chapter 2).

2


5% 1 1

1 ' Urban PDF ------· if ' Suburban PDF -4% _,.....

.tl' \"" ~~~ ,. '\

~ 3% ' ~ ' ;~' ' '\. ::c \ ca

J:l \.

"' v ~ e " ; 2% Il.

;/' / \. 1 ... .;' / ... \ 1 ~ '" ..... 1%

/ ....... ~/ ""~

/ ....... ..........

. 20 ·10 0 10 20 30 Pout (dBm)

Figure 1.3: Power amplifier output power probability density function for IS-95 urban and suburban environments [5], [6].

Since the power amplifier is the most power-consuming deviee in the whole

receiver/transmitter chain improving the efficiency of the PA can significantly increase

the battery life and therefore the talk time. In the power amplifiers used in wireless

communication, the required level of output power varies depending on the distance from

the base station. The efficiency of a power amplifier is usually optimized to be maximum

at the peak output level and decreases significantly for lower power levels. However, as

seen in Figure 1.3, the wireless transmitter is required to transmit at the peak level only

during a short period of the operating time. On average, most of the transmitted signais

are at much lower power levels [5], [6]. Consequently, to preserve the battery life and

increase the talk time, it is desirable to be able to keep the efficiency constant for various

output levels [7]. One way to achieve this is by using variable matching networks to

obtain a better average power consumption.

3


1.2 Litera tu re Review

The output power level in a PA can be adjusted by varying either the lev el of the RF

drive or the quiescent bias point of the power transistor. The idea of actively tuning the

output and, to a lesser degree, the input impedances of a power amplifier is not new.

However, only a few attempts have been made in this regard. Semiconductor-based

junction varactors have been used in the output matching network to maintain either

constant efficiency over a given output power range, or constant power over a limited

frequency range [8], [9], [10], [11]. Other variations include schemes where the

efficiency is kept constant by switching arrays of variable transformers or FET transistors

[12], [13].

In [9] a power-adaptive Class E power amplifier, based on high-Q semiconductor

varactors, is implemented in 0.6-flm CMOS technology. Figure 1.4 shows the proposed

class-E PA with the MOSFET transistor acting as a switch which tums on and off at the

input frequency. L 0 and Co are set to re sonate at the input frequency th us passing a

sinusoïdal current to the Joad RL. When the Joad value is Jess than the optimal Joad value

required for maximum output power, the output power and Power-added-efficiency

decrease sharply (see section 2.31).

L=r=---T RL

I Cp Junction Va~ ! 1 Vc1 Vc2 -="

Figure 1.4: The power-controllable class-E PA implemented in [9] with tunable output

capacitors.

4


50

0+-------~----~~~~--~--------~ 467 ~~8 38<' 3'15 309 276 249 224 203 16$ 170 T$6 14) 132 123 114 106 il8.

6

Figure 1.5: Simulated results of power-added-efficiency versus output power for the power-controllable PA proposed in [9].

To overcome this problem, a three-element n-matching network is proposed in [9]

consisting of two tunable varactors and an inductor to transfer the 50 n extemalload into

an optimal load required at the drain of the power transistor for maximum power-added

efficiency; thus ensuring maximum power transfer. The tunable capacitors are

implemented with semiconductor junction varactors. In order to ensure that the varactors

are reverse-biased the voltages Vc1 and Vc2 should be very high, for which purpose

"charge pumps" are needed. The simulated results presented in [9] are shown in Figure

1.5: It is clear that the power-added-efficiency has been kept relatively constant over an

output power range of 370 mW. It should be noted that the frequency of operation is not

specified by the authors in [9].

In [10], F. H. Raab presents a 20-W classE power amplifier at 31 MHz with MOSFET

transistors operating form 20 V power supplies. As will be discussed in detaillater, class

E operation requires a certain drain-shunt susceptance and load-series reactance at every

given frequency for correct operation. As shown in Figure 1.6, the output tuning network

developed in [10] employs fixed inductors, L2B and L3, and high-voltage MOSFET

varactors, C4 and C7 to obtain constant output power over the 19 to 31 MHz frequency

('.. range.

5


PATENT PDI>ING

L2A ltF T2 OUTPUT

flF DRIVE

-..

T1 f 1

Il

Figure 1.6: Simplified circuit of electronically tunable classE PA developed in [10].

In recent years, sorne attempts have been made to utilize the MEMS technology in the PA

design context. In [14] MEMS switches are used in the output matching network of a

class AB power amplifier to select one of the 16 output matching networks in the 8- 12

GHz frequency range, Ml-M4 in Figure 1.7. However, the design depends on

semiconductor-based voltage-controlled varactors to fine tune the impedance. By tuming

the MEMS switches on and off and varying the bias point of the varactor, the frequency

response of the amplifier is optimally configured for one specifie frequency as seen in

Figure 1.8. The design, however, requires extra circuitry to determine which switches

should be tumed on at any given time.

mlin

aractor

Figure 1.7: Schematic of the output matching network with four MEMS switches (M1-M4) and one [semiconductor] varactor. C1-C8 are fixed capacitors. mlin is a microstrip

transmission line [14].

6


30T-------------------------------------~

25

.. ... '

-20 e Dl '-8.5GH:z :E.. 15

8 0.. 10

' . 5 ' ••

' 1

1 , /

\.· 0+-~----~r-------~-----'---T----~--~

- -9.5GHz .... •10.5GHz

- • 11.5GHz • Envelope

B 9 10 Frequency (GHz)

11 12

Figure 1.8: Results obtained by having tunable matching networks in [14]. The dots represent the optimized output power as a function of frequency. Each curve represents the frequency response of the amplifier wh en it is optimally configured for one specifie

frequency [14].

1.3 Objectives

As seen in the literature review, no work has been done so far to implement tuning of

power amplifiers by means of MEMS varactors. The goal of this research is to use

MEMS varactors designed in the Metal-MUMPS process to tune the output impedance of

a class AB SiGe power amplifier such that the efficiency is kept constant over a range of

power levels. The best class of power amplifiers that best demonstrates the relationship

between input and output power, as well as between the efficiency and linearity, is the

class AB PA (re fer to chapter 2). A variable biasing network is included in the design to

vary the quiescent current of the power transistor. The designed MEM tunable capacitors

can be reconfigured through a control voltage and offer a very wide tuning range over a

wide frequency spectrum.

1.4 Thesis Outline

The thesis begins with an overview of wireless transmitter architectures with special

attention to the power amplifier and its applications. The need and motivation for power

amplifiers with constant efficiency and/or linearity are presented. An overview of the

7


micro-electromechanical deviees and their possible applications m power amplifier

design follows.

In chapter 2, the principles of power amplifier operation are presented. The metrics that

are conventionally used to characterize the be havi or of the PAs, such as linearity and

efficiency, are defined. The inherent tradeoffs between the linearity and efficiency are

also discussed. Next, the different power amplifier operating classes, namely class A

through class E, are presented. Relevant to the topic of this thesis, class AB architecture

is studied in more detail. Design techniques and issues specifie to high power amplifier

design such as large-signal S-parameters, power matching, and load-pull techniques are

presented in detail.

Chapter 3 deals with the design of power amplifiers. This includes the design of the

power core, biasing circuits, and input and output matching networks. Paralleling

multiple transistors in order to obtain higher gain and related problems such as power

combining and splitting are discussed next. Load-pull technique is revisited in the context

of practical PA design. Empirical models are developed for the printed circuit board

(PCB) tracks, the bond-wires, and the package ali of which contribute losses to the

circuit.

Chapter 4 is dedicated to radio frequency micro-electromechanical capacitors. The

operating princip les of different varactor structures such as parallel-plate and lateral inter

digitated are studied. Next, an overview of the Metal-MUMPS process is given. Several

MEMS varactors are designed taking advantage of the two structural layers available in

this technology. Related issues such as the suspension arms and signal pads are visited.

In chapter 5, the fabricated deviees are tested. First, the stand-alone power amplifier is

tested and the required input and output matching networks for maximum output power

are designed. Secondly, the behaviors of the MEMS varactors are established through on

probe testing. Next, the SiGe power amplifier and the MEMS varactors are mounted in

8


the same package. The overall PA is tested and the measured results are compared with

the simulation results.

Chapter 6 consists of a summary of the work done in this research and future work that

can be done to improve upon this project.

1.5 Contributions

The contributions ofthis thesis are summarized as follows:

1. This thesis, in addition to offering a summary of different classes of power amplifiers,

provides a detailed analysis of class AB power amplifier operation. More specifically, the

chip implementation of a 2.2 V class AB PA in a SiGe BiCMOS 5HP technology. Due to

the parasitic !osses associated with the package and the bonding wire, the measured gain

is lower than designed at the PCS band center frequency of 1.88 GHz.

2. Methodically describing the different modes of operation of MEMS variable

capacitors, and providing a design methodology for implementing wide tuning-range

varactors. Based on the mentioned methodology, various MEMS tunable capacitors are

successfully implemented in the Metal-MUMPS process. The wide- and very wide

tuning-range capacitors are successfully tested from DC up to 6 GHz.

3. An attempt is made to integrate the power amplifier chip and the MEMS die in the

same package to pro vide active tuning of the power amplifier matching network in order

to keep the efficiency of the PA constant for different input power levels and load

conditions.

9

Chapter 2: Power Amplifier

2 Power Amplifiers

In this chapter, the basic principles of power amplifier operation are discussed. The

power amplifier is one of the most important components in transmitters design. In a

conventional transmitter, the digital bit stream, after going through the required digital

signal processing, is converted to an analog signal which is then up-converted to the

desired frequency. The radio frequency, RF, signal is then amplified to the specified

power level through the power amplifier to be radiated by the antenna. Thus, the power

amplifier, PA, can simply be defined as the circuit that converts the DC input power into

RF (or microwave) output power. The applications of PA are not limited to wireless

communication; they also finds widespread use in radar, RF heating, plasma generation,

laser driving, magnetic resonance imaging, and miniature DC-DC conversion [15], [16].

Power amplifiers can be incorporated into transmitters in different architectures including

linear, Kahn, envelope tracking, outphasing, Doherty, and so on [16]. The output power

lev el of the PA is determined by the communications system specifications. The outgoing

signal should be high enough for the receiver to sense and recover it after ali the losses

encountered in the propagation path. For base-station applications, the transmitted power

needs to be in the order of hundreds of watts. For mobile wireless communications, this

value varies between hundreds ofmilliwatts, mW, to a few watts. In closer-range wireless

applications, such as the Bluetooth, powers in orders of tens to hundreds of milliwatts

r" suffice.

10


In section 2.1 the metrics that are used to characterize and quantify the performance of a

PA, such as efficiency and linearity, are defined. Unless the process of converting the DC

power from the battery to the RF power delivered to the load is lossless, the PA itself

becomes a large consumer of power, often more than what it delivers to the load. This

results in power amplifiers being the primary consumers of DC power in any transmitter

chain, hence the great emphasis on improving their efficiencies [17].

Next, different power amplifier architectures and operating classes, e.g. A through E, are

briefly discussed; since a class AB power amplifier is investigated in this research, more

emphasis is put on this specifie mode of operation. Finally, design issues that are specifie

to PA design su ch as large-signal S-parameters and the load-pull technique are presented

in detail.

2.1 PA Metric Definitions

In arder to be able to discuss the characteristics of power amplifiers comprehensively, to

classify the PA operating modes, and to make meaningful comparisons, a set of uniform

parameters must be defined. The basic set of parameters used for characterizing power

amplifiers are the output power, power gain, and efficiency. The linearity and stability of

the amplifier should also be taken into consideration. Each of these parameters is defined

in this section along with guidelines on measuring them in a PA circuit.

2. 1.1 Output Power and Power Gain

The power amplifier output power is generally specified in units of dBm, which is the

output power in dB with respect to 1 rn W. In other words,

P = lOlog Pw dBm 0.001 Watt

(Equation 2.1)

where Pw is the power in watts. So 1 W is equivalent to 30dBm, 100 rn W is equivalent

to 20 dBm, and so on.

11


Another metric often considered in PA design is the power output capability (or transistor

utilization factor) which is defined as the output power per transistor, normalized for peak

collector voltage and current of 1 V and 1 A, respectively [18].

The power gain is defined as the ratio of the source, or input, power to the load, or output,

power. When expressed in dB it becomes:

Gain (dB) = Pout (dB) - P;n (dB) (Equation 2.2).

For sorne applications, the gain is specified at the 1-dB compression point and is referred

to as the "compressed" gain [3].

2.1.2 Efficiency

2.1.2.1 Collector Efficiency

The DC power in portable applications cornes from the battery, a source with a finite

available power; bence, the power consumed in the PA is the main source of degrading

the battery life. Collector efficiency, 1f, is one of the metrics that quantify how efficiently

the DC power is converted to RF power:

(Equation 2.3),

where PoutRF is the RF output power and Pvc is the input DC power. The limitation of

collector efficiency (or in the case of MOS transistors drain efficiency) as a metric is that

it does not take into account the RF power delivered to the deviee from the source. As

most high frequency power amplifiers have rather low gain, the collector efficiency can

overrate the actual efficiency of the power module [ 17].

2.1.2.2 Power-Added-Efficiency

The power-added-efficiency, P AE, is a better indicator of the power amplifier' s

efficiency, since it takes into account the RF input power, P;nRF, by subtracting it from

the output power. The PAE is defined as:

p -P p AE = out RF inRF (Equation 2.4).

PDC

12


Rearranging the components, the above relation can be rewritten in terms of the power

gain of the amplifier, G, and the collector efficiency, 11 [17]:

1 PAE = (1- G)IJ (Equation 2.5).

The power-added-efficiency is a reasonable measure of PA performance wh en the gain is

high; it can, however, become negative when the gain of the amplifier is low.

An even more accurate indicator of efficiency that can be used under ali circumstances is

the overall efficiency, defined as:

IJoverall = p pout; (Equation 2.6). DC + inRF

The overall efficiency can be adjusted to take into account the power consumed by the

driver stage and the biasing circuitry as weiL In order to conserve the battery power and

avoid interference with the signais from other transmitters in the same frequency band,

the peak amplitude of the transmitter signais need to be kept below the rated "peak output

power" of the transmitter by about 10 to 20 dB; The peak output power is only needed

for the worst-case links [15].

2. 1.3 Linearity

Linearity, like efficiency, is a key factor in power amplifier design. Nonlinearities can

impair the replication of the amplified signal, resulting in distortion. Depending on the

specifie application, linearity may be the most crucial parameter that defines the way a

certain power amplifier is designed. In short, the constraints on how linear or undistorted

the output signal should be can very weil define which class of amplifier is employed.

Linear amplification is required when the input RF signal contains both amplitude and

phase modulation. Examples include single side band (SSB) voice, modem shaped-pulse

data modulation schemes (QAM, QPSK, CDMA) and multiple carriers (OFDM or

orthogonal frequency-division mulitplex). Signais such as continuous wave (CW), FM,

classical FSK and GMSK, on the other hand, have constant envelopes (amplitudes) and

therefore do not require linear amplifications [15], [19].

13


2.1.3.1 Sources of Nonlinearity

Intermodulation distortion is a major source of distortion in power amplifiers and can

cause the output amplitude to differ in shape from the input signal. When two or more

signais with different frequencies are applied to a nonlinear amplifier, the output will

contain additional frequency components called intermodulation products. The

generation of spurious frequencies and intermodulation distortion can lead to serious

problems in multi-carrier wireless transmitter systems, where the spurious signais can

appear in the adjacent channels and contaminate them. This sort of nonlinearity is mainly

caused by the variable gain or saturation of the RF transistors [16], [17].

Another source of signal distortion is the nonlinear phase characteristics of the amplifier.

Ideally, in arder to have no distortion, the power gain transfer function should be constant

as a function of frequency. In practical applications however, both linear and nonlinear

phase shifts are present. A linear phase shift produces a constant time delay at the signal

frequency, whereas a nonlinear phase shift produces different time de1ays for different

frequencies, thus introducing unwanted phase modulation. Amplitude-ta-phase

conversion can arise from a voltage-controlled capacitance that the designer has no

control over [16], [20], [21].

~ Il. .. .,..

' ' ' ' : IMD

' ' ' Second Harmonie ' --

Third Harmonie

f 2f1-f2 f1 f2 2f2-f1 Frequency

F1gure 2.9: Harmomc d1stort1on and carner-to-mtermodulat1on rat1o.

14


2.1.3.2 Measures of Linearity

Based on the specifie signal and application, linearity is characterized and measured by

various techniques. Sorne of such techniques are carrier-to-intermodulation ratio, noise

power ratio, and adjacent-channel power ratio.

Carrier-to-intermodulation ratio, C/I, is the traditional measure of linearity and compares

the amplitude output at the desired frequency to the intermodulation-distortion products.

For this purpose, the power amplifier is driven with two tones of equal amplitude placed

at± ~f around the fundamental frequency. Nonlinearities create intermodulation products

at frequencies corresponding to the sums and differences of multiples of the carrier

frequency. The amplitude of the third order intermodulation distortion product, IMD, is

compared to the signal amplitude at the fundamental to obtain the C/I (Figure 2.9). A

typical IMD value for linear PA's is -30 dBc or better.

Noise-power ratio, NPR, is a method of measuring the linearity of a power amplifier for

noise-like and broadband signais. In this case, the PA is driven with Gaussian noise with

a notch in one part of its spectrum. Nonlinearities cause power to appear in the notch;

NPR is then defined as the ratio of the notch power to the total power.

Adjacent-channel power ratio, ACPR, is the most widely used measure of linearity in

shaped-pulse digital signais such as the NADC (North American digital cellular) and the

CDMA (code-division multiple access). ACPR characterizes how the nonlinearities affect

the adjacent channel by comparing the power in a specified band outside the signal

bandwidth to the power in the carrier signal [15], [16], [19], [22], [23].

2. 1.4 Stability

The stability ofPA's should also be considered. As will be seen in chapter 3, the parasitic

inductances and capacitances may form a resonant tank and cause undesired oscillations.

In order to investigate the small-signal stability of an amplifier, the whole circuit,

including the input and output matching networks, is considered as one black box and its

15

'

/~ 1


stability is verified for a 50 .n input and output load. Based on the S-parameters, the k

factor is defined; if the k-factor is larger than unity, at the specifie bias and frequency, the

amplifier is stable:

k __ 1-jS11j

2 -jS22j

2 + D2

21821Jjst

2J (Equation 2.7),

and

D = S11S22-S12S21 (Equation 2.8).

In order to verify the large-signal stability of a PA, the circuit is excited with an RF pulse

and the transient response of the PA is verified. If the response is free of ringing, the

power amplifier is stable [1], [17], [18].

2.2 Choice of Architecture

Power amplifiers are divided into different classes of operation, based on where the

deviee is biased and whether the deviee is operated as a switch or not. The design

constraints on linearity and efficiency de fine the PA architecture employed. A rough

grouping of power amplifiers can be done based on the linearity of the output signal of

the power module. According to this classification, class A, B, and AB fall under linear

amplifiers, whereas class C, F, and E fall un der nonlinear power amplifiers. A variety of

other modes of operation also exist that are a combination of the above mentioned modes.

In this chapter, the operation of each of the above classes are described. Since the goal of

this research is to design a linear power amplifier with tuning capabilities, class AB

operation is investigated in more detail.

16

V cc

RFC


Output Matching Network

Transistor

Figure 2.10: Generic single-ended PA.

2.2.1 Linear Amplifiers

2.2.1.1 Class A

In class A operation, the power transistor is in the active region during the whole RF

cycle. This is achieved through biasing the transistor such that the quiescent current is

half of the maximum current of the transistor. In other words,

1 _]max Q-

2 (Equation 2.9),

where IQ is the quiescent current and IMAX is the maximum collector current that the

transistor can sustain. Due to the biasing, both the positive and negative swings of the

input signal affect the collector current, and therefore class A provides the highest gain of

ali types of power amplifiers.

As shown in Figure 2.11, the collector current and voltage waveforms are perfect

sinusoids, hence the linear amplification in this mode. The output power delivered to the

load is vo:t 1 2R, where Vout is the voltage on the load and R is the load resistance.

17


The transistor acts as a voltage-controlled current source: the collector current is

controlled by the base-emitter voltage. Linear amplification implies that increasing the

quiescent current or decreasing the RF input signal level will decrease the harmonies and

the intermodulation distortion. The low harmonie content of this mode of operation

means that it can be used at frequencies close to the maximum operating frequency,

F MAX, of the transistor.

The maximum theoretical efficiency of class A is 50 %. The efficiency of practical class

A amplifiers is even lower due to the presence of the on-resistance of the transistor, the

saturation voltage of the transistor, and the parasitic losses. It is further degraded by the

fact that practical loads are not solely resistive and contain reactive components too; in

essence, more output current or voltage needs to be extracted from the PA to de li ver the

same output power to the load. In short, due to the inherent characteristics of class A

amplifiers, they are often used in high frequency applications where high linearity and

gainarerequired [2], [15], [17], [18], [20], [24], [25].

Figure 2.11: Class A collector eurre nt and voltage waveforms.

18


Figure 2.12: Class B collector current and voltage waveforms.

2.2.1.2 Class B

In class B operation, the base of the transistor is set at the threshold of cutoff such that

transistor is on during half of the RF cycle, resulting in a collector current that is a half

sine wave. For this purpose, the quiescent current is set to

J _]max Q- ;r (Equation 2.1 0).

The collector current and voltage waveforms are shown in Figure 2.12. Since the

amplitude of the collector current is proportional to the amplitude of the RF input signal,

the shape of the collector current waveform is fixed and the amplification is linear. The

output power is th us controlled by the RF drive lev el and varies as vo:, 1 2R . The

efficiency varies linearly with the RF output voltage, and can ideally reach ;r 14 ( ~

78.5%) at the peak output power.

Class B is generally used in a push-pull configuration to provide amplification over the

entire cycle. Due to the limitations of RF p-type power transistors, the use of

complementary topologies is limited to audio, low, and medium frequency. At HF and

VHF frequencies, a transformer coupled push-pull configuration is used to allow

broadband operation with minimum filtering. Transformer-coupled push-pull and

19

.r---\


complementary PA configurations are shown in Figure 2.13 [2], [15], [18], [20], [24],

[25], [26].

V cc

V cc

Q1 Output Filter

RL ~ '"'v

Q2 RL

(b) -

- -Figure 2.13: (a) Transformer-coupled push-pull PA, (b) complementary PA.

2.2.1.3 Class AB

The ideal class AB amplifier is biased between class A and class B, as a re suit of which

the collector current can swing between zero and IMAX· The efficiency is between that of

class A and class AB and increases as the quiescent current is decreased. The class AB

operation is discussed in detail in section 2.2.4.

2.2.2 Nonlinear Amplifier

2.2.2.1 Class C

The base of the transistor in a class-C PA is biased near the cutoff for more than half of

the RF cycle. The transistor is cutoff un til the RF signal applied between the base and the

emitter makes it conduct. A high-Q parallel-tuned resonant circuit is usually used at the

output stage to recover the signal at the fundamental frequency and suppress the

harmonies. Class C is extremely nonlinear, but its efficiency can theoretically be

increased toward 100% by decreasing the conduction angle toward zero. This, however,

20


causes the output power to decrease toward zero and the input drive to increase toward

infinity. A typical compromise is a conduction angle of 150° and ideal efficiency of 85%.

Examples of collector current and voltage waveforms are shown in Figure 2.14.

In case of MOS transistors, when the transistor is driven into saturation, the output

voltage is locked to the supply voltage and the efficiency is stabilized, thus allowing

linear high-level amplitude modulation. Class C is widely used in vacuum tube

transmitters but is impractical for sol id state PAs. The main reason is that class C requires

low collector (drain) resistance, making the implementation of parallel-tuned output filter

difficult. lt is also difficult, especially in case of bi polar transistors, to set up the bias and

the drive to produce a true class C waveform [2], [15], [18], [20], [24], [27].

Figure 2.14: Class C collector current and voltage waveforms.

2.2.2.2 Class F

Class F takes advantage of harmonie resonators at the output to boost both efficiency and

output power by reshaping the collector waveforms. This is done through a series and a

shunt resonator tank. The series tank is tuned to the third harmonie, while the shunt tank

is tuned to the first harmonie. The resultant output voltage contains one or more odd

order harmonies and approximates a square wave, while the output current contains even-

21


arder harmonies and approximates a half sine wave. As seen in Table 2.1, as the number

of the harmonies increases, the efficiency increases from 50% to unity. The class F

current and voltage waveforms are shawn in Figure 2.9 [2], [15], [18], [27], [28], [29],

[30].

Table 2.1: Efficiency of class F PA with respect to the number of harmonies [15].

Number of Harmonies Efficiency (%)

2 70.7

3 81.65

4 86.56

5 90.45

3~~----~------~----~----~~

2.5 ------+-···········

i Vc 2 ------ ------------

Figure 2.15: Class F collector current and voltage waveforms.

2.2.2.3 Class E

In class E, a single transistor is operated as a switch that tums on and off at the input

frequency. The series resonator tank is tuned to the first harmonie of the input frequency,

and the collecter voltage waveform is the result of the sum of the DC and RF currents

charging the shunt parasitic capacitance, Cp in Figure 2.16. In the ideal of class E

operation, as the transistor tums on, the collector voltage drops to zero with a zero slope;

the result is an ideal efficiency of 100%, due to reduction of the switching lasses and

r---. elimination of los ses incurred when the parasitic collector capacitance is charged.

22


Optimum class E operation requires a drain susceptance of 0.18361 R and a drain series

resistance of 1.15R, and delivers an output power of 0.577V};D 1 R. The design of power

modules operating in class E requires a driver stage, usually a class F, to generate the

square waves required for the main stage to operate in this mode. Class E operation is

efficient even when a significant parasitic capacitance is present at the drain, which

makes it useful in many applications. Class E high frequency PAs with power levels

close to 1 kW can be implemented using low cost MOSFET technologies. The drain

current and voltage waveforms for a class E PA is presented in Figure 2.17 [2], [27], [28],

[29], [31], [32], [33].

VDD

Figure 2.16: ClassE PA circuit.

'

1 ' 1 • -- - • -1~-- ·- ------- ·r ·-- ·----·---- r ·----- ·------r··--------· ·

' ' ' . • ' 1 • • ' 1 • • ' 1 • 3 1 ' 1 • • ' 1 ' ' ' 1 • ' 1 1 1

• •-- • .1.- •--- • •-- • • .L •-- • •- ·•- •-- • .L- •---- • • • • -••'-•••••••••• • •

' 1 1 1 1 1 1 1 ' 1 1 1 ' 1 • ' ' 1 1 ' 1 1 ' 1

' ' ' ' ' ' ' ' ' • • • • • -,- • • • • •• ·- • • ·-- ---- • • -- • ·- ·- T ·-- • • • • • • • ---r---------2 • 1 • 1

' 1 • ' 1 1 1 1 1 1 ' ' 1 1 1 1

' ' ' ' ' . ' ' 1 1 ' 1 ----- -·------------- ... --- --------"---------- --- -----------' ' ' ' . ' ' . ' ' ' ' . . ' ' . ' ' ' ' . ' ' . . . -.- ... -,-.--.---.--- .. ,. - ... --- ---.- ---r------------' ' ' ' ' ' ' ' ' ' ' ' . '

0 pif2 3*pif2 2*pi

Figure 2.17: Class E collector current and voltage waveforms.

23


2.2.3 High-Linearity and High-Efficiency RF PA - Tradeoffs

In power amplifier design, linearity and efficiency are inversely related to each other.

ClassA operation offers extremely high linearity at the expense of low efficiency. Class

B has low distortion and the potential for good efficiency. Class AB enjoys the good

efficiency of class B with the low distortion of class A.

Switched-transistor PAs, such as class F and E, are very good in terms of efficiency but

can be extremely nonlinear. The linearity-efficiency tradeoffs are summarized in Table

2.2.

Table 2.2: PA linearity and efficiency tradeo ff s.

Mode of operation Efficiency Linearity

ClassA Low Very high

Class AB and B Medium High

Class C High Low

Class F High Low

ClassE Very High Very Low

2.2.4 Analysis of C/ass AB Power Amplifiers

As discussed before, in linear power amplifiers the quiescent current determines the

method of operation, and thus the efficiency and power output capability. Class AB has

higher efficiency than ClassA and higher linearity than Class B.

24


Io

····i···----~---···1·····

1 : ' J • 1 ... ,----·--t-·····1··· 1 : 1

••••..• '.J •••••. ,.:. ..•••• J.. : 1 : 1

1 1 1 ... , .......... J.. .. ... : ... ............. l, ......... ...

1 1 : 1 ' 1 : 1 • 1

...... :..... -------~------l- ··--t--··· .t ..... : 1 1 1

·····!······ ··-···+······~ ···--j-···· ~--··· : t : ••••••••••• , .. 1 --- ....... •• • • •• -- - ••••• : 1 1

1 1 ' : 1

... "' ...... - .. : .. "' .......... J •• ' 1

1

1 1 • 1 ï ··---~---····r 1 : 1 1 • 1 1

3rr/2 2'Jr

Figure 2.18: Class AB collecter current waveform.

1 1 1 1 --------- __ ... _____________ , ______________ ,___ _ ________ .__________ --1 1 1 1

' ' ' ' ' ' ' ' ' 1 1 1 1

••••••••••• •T•••••••••••••.,•••••••••••••-o• •••••••••••r"••••••••••• •

' ' ' ' ' '

VQ +----+---P------1---.....,,__---l Vt ' ' _, ______ ------- _._ ____ ---------

' ' ' ' ' --------- ... --------- ___ , ______________ .. ____________ _

' ' ' ' ' ' ' ' ' '

0 rr/2 r:t12 1T 3rrl2 21f

Figure 2.19: Class AB collecter voltage waveform.

25


Based on Figure 2.18, the collector RF current can be written as

l.c --{1Q +1pkcos(8), if -a/2(8(+al2

0 , else (Equation 2.11 ),

where a is the conduction angle. The DC component of the current is obtained by:

1 ___ 1_ af12

1 cos(&)- cos( a 1 2) dn

u (Equation 2.12), DC 27! -a/

2 max 1-COS(a /2)

where ]MAXis the maximum current in the power transistor. Based on Equation 2.12, the

quiescent DC current for class A is 1 max 1 2, and that for class B is 1 max 1 :TT • As a result,

the DC current for class AB operation becomes:

J max (J ( J max

:TT Q 2 (Equation 2.13).

Similar to Equation 2.12, the magnitude of the nth harmonie is given by:

In = .!._ aT 1 max cos(&)- cos( a 1 2) cos( nO) dB :TT -a/ 2 1-cos(a/2)

(Equation 2.14).

Referring to Figure 2.19, VQ is defined as the bias voltage level at the base of the RF

transistor. As the transistor is biased closer to cutoff, higher drive levels are required to

maintain a peak current of ]MAX· For example, as the operation moves from class A

towards class B, the drive level has to be increased by a factor of two in order to get the

same peak current. In other words, a 6 dB increase of input power level is required,

which translates into class B gain reduction [1], [34], [35].

A common solution is to "under-drive" the amplifier or operate the amplifier at lower

drive levels than is needed, in order to keep efficient operation at higher gains (through

IMAX). For example, instead of increasing the input drive by 6 dB from class A to class B,

it can be increased by 3 dB. In this case, at zero bias, the current maximum will

26


be 1m~ instead of IMAX· To offset this reduction in maximum linear power, the load

resistance can be increased by the factor of J2 . Overall, efficiency of 78.5% can be

achieved with only 1.5 dB reduction of gain [34], [36], [37].

2.2.4.1 Harmonie Termination

One of the important elements in a class AB design is the resonator tank at the output. A

truncated sine wave has high harmonie contents; the tank provides a harmonie short that

prevents the generation of harmonie voltages at the output. The shunt capacitor chosen

for the harmonie tank must be large enough to short ali harmonies except the fundamental

to ground. The final output signal will be a sine wave whose amplitude depends on the

RF input signal level, P;n, and load resistance, RL. In practical applications RL is chosen

such that, under the maximum drive, the voltage swing makes use of the full range, i.e.

the amplitude approaches the DC supply.

2.2.4.2 Tunable Load Resistance

Two important issues in RF power amplifier are the rapid drop in efficiency as the input

drive level decreases, and the need to control the power over a wide dynamic range. Both

of which can be solved by using a variable load.

The concept of under-drive mentioned in section 2.2.4 can be applied in this context. In

class AB, the under-drive efficiency is not as high as the fully driven case because the

input drive, P;n, is not as high, according to the power-added-efficiency relation

(Equation 2.4). If the load resistance, RL, can be changed dynamically with P;n, thus the

drop in efficiency, due to the drop in P;n, can be counteracted, enabling control over the

output power over a wide dynamic range.

The voltage and current that appear at RL, at the fundamental frequency, are related

through Ohm's law:

(Equation 2.15),

27


where h is the output current at the fundamental as frequency defined by Equation 2.14.

If RL is made variable as Ro , then as h goes from zero to 1 max , v0 remains constant:

vs 2

v,~(~}· = Ro (/max .vs) (Equation 2.16).

vs 2

=VDC

Assuming an ideal harmonie short, the output power becomes po = VDC 1 max vs .

2 2

Note that, according to the above equation, the output power depends on Vs and 1s

independent of P;n. In which case the efficiency also becomes independent of the input

drive [34]:

pout RF tJ=-

PDC

7&' (VDC )(/max) = VDCVslmax l Z Vs

7&' =

4

2.3 PA Design Techniques

(Equation 2.17).

Power amplifier design differs from other amplifier designs due to the mere presence of

large collector (or drain) signais. The small-signal S-parameters are not sufficient

anymore for defining and characterizing the behavior of the amplifier. Similarly, the

conjugate matching does not provide the best power transistor for large output signais.

These parameters have led to the introduction of large-signal S-parameters and the

development of different load-line matching approaches specifie to PA design.

Small-signal analysis is based on the assumption that the deviee currents and voltages

undergo small fluctuations about constant DC bias conditions. Under this assumption,

approximate linear relationships between deviee currents and voltages can be derived. In

28


large-signal operation, on the other hand, there are large variations in currents and

voltages. Meaning that linear 1-V relationships are not adequate to characterize the

deviees.

2.3.1 Power Match vs. Conjugate Match

Conjugate matching is the matching technique used in ali law-power amplifier designs.

The conjugate match states that, for maximum power transfer, a given load should be

matched to the conjugate of the source impedance. In other words, if the source and load

impedances are given by zsource = Rs + xs and zload =RI+ xl' then

(Equation 2.18).

The conjugate matching technique however, neglects the fact that the voltage source may

have limited physical conditions, especially in terms of the voltage that it can sustain

across its terminais. Conjugate matching for a source of 50 n requires a load of 50 n. If

the voltage source in question is the output of a previous stage amplifier with a current of

1 A, a load of 50 n means that a voltage of 25 V will appear across the output of the

previous stage transistor, which may be well over its physicallimits [1].

In power amplifier design, the load impedance is selected based on the maximum

physical current and voltage of the transistor. In other words, the value of the load

impedance that extracts the maximum power from the transistor without exceeding the

RF voltage swing limit of the transistor or the de supply. The value referred to as Zopt can

be approximated to first arder as:

z = vmax apl J

max

(Equation 2.19).

In actual PA design, the value of Zopt is determined through load-pull techniques to be

discussed in section 2.3.2. It has been shawn that power match gives at least 2 dB

improvement in output power compared to conjugate match [1].

29


Port1 Port2

Figure 2.20: The general matching t-network.

Assuming that the value of Zopt is already known for a given PA, a matching network can

be designed to power match the output impedance of the PA, Zout, to this optimal value

[38]. The matching network is assumed to be a t-network with the reactances shawn in

Figure 2.20.

Referring to Figure 2.20, if Port 2 is terminated with an impedance ZB, the equivalent

impedance looking into Port 1 simply becomes:

Z X x,;

1 = J 11 + -.-_.:::;'----jX22 +Zs

(Equation 2.20).

Similarly, if Port 1 is terminated with an impedance ZA, the equivalent impedance

looking into Port 2 is derived to be:

Z X X(2

2 = J 22 + -.--=-]Xli +ZA

(Equation 2.21).

Separating the resistive and reactive components, Equation 2.20 and Equation 2.21 can

be written as:

(Equation 2.22),

(Equation 2.23),

30


(Equation 2.24),

(Equation 2.25).

Solving Equations 2.22 through 2.24 yields:

(Equation 2.26),

(Equation 2.27),

(Equation 2.28),

where

These equations can be programmed into Excel, where the power-match network can be

easily created once the values of Zopt , Zout , and the frequency are specified.

2.3.2 Load-Pu/1 Technique

The load-pull technique consists of loading the PA with different impedances and

verifying the output power level as function of the impedance to determine the best

output load. A load-pull system consists of a test fixture and a pair of low-loss,

accurately resettable precision mechanical tuners. Data are measured for a large number

of impedances and plotted on a Smith chart. The accuracy of the plots depends on the

accurate calibration of the tuners, both in terms of impedance and losses [1], [34], [39],

[40].

The load impedances that deliver a given RF power level with a specified collector

voltage lie along parallel-resistance lines on the Smith chart. Similarly, the impedances

31


for a specified current level follow series-resistance line. The resultant is that constant

power contours are elliptically shaped rather than being circular as seen in Figure 2.21.

The transformation of the collector impedance through the parasitic collector capacitance,

and the bondwire and package inductances causes the constant-power contours to become

distorted and rotated [15], [17]. It should be noted that the power and efficiency contours

are not necessarily aligned. Similarly, maximum power and maximum efficiency do not

necessarily always occur for the same load impedance. This is especially true at higher

power levels and can be seen in Figure 2.14 as weiL

Maximum PAE Contours

Maximum Pout Contours

Figure 2.21: Example of load-pull contours for a given PA.

32

Chapter 3: Design of Power Amplifier

3 Design of Power Amplifiers

The goal of this research is to design and fabricate a MEMS-tunable RF power amplifier

based on a SiGe technology. In this chapter, the PA design methodology is presented:

First, a power amplifier utilizing a single power transistor is designed along with the

required biasing circuitry. Design aspects related to both operation at RF frequency, such

as bondwire and package parasitics, and specifie to PA design, like the load-pull

technique, are presented in the design context. In order to obtain higher gain, the multi

transistor PA design and the issues related to this topic such as power-splitting and -

combining and layouts are investigated. The be havi or of the complete design is presented

in terms of output power, gain, PAE, and IMD. In the last part on this chapter, empirical

models are developed for the bondwires, the package, and the PCB tracks and the PA

design is revisited based on these models.

3.1 PA Design in a SiGe Technology

3. 1.1 Choice of Tech no/ogy

The RF power amplifier in this research is designed using a SiGe hetrojunction bipolar,

HBT, transistor. Commercial power amplifiers are currently designed and manufactured

in two competing technologies: Gallium Arsenide, GaAs, HBTs and Silicon Germanium,

SiGe, HBTs.

33


Gallium Arsenide is the technology of choice for linear power amplifiers for commercial

handheld wireless communications. GaAs HBTs offer higher power gain, efficiency,

linearity, and breakdown voltages compared to SiGe HBTs. They however have a lower

base-to-emitter tum-on voltage, or threshold voltage, than their SiGe counterparts. This

makes the SiGe a better choice for low-voltage applications, where the supply is limited

to below 3 V. Moreover, SiGe offers a better cost benefit: SiGe dies are fabricated on 8-

inch wafers where as GaAs wafers are usually 4- and 6-inch large. Considering the yield

benefits of larger wafers, the average cost of a SiGe power module can be one half or

even one quarter that of a comparable GaAs module [ 41] - [ 48].

3. 1.2 Power Amplifier Specifications

The goal of this section is to design a linear power amplifier to investigate the possibility

of tuning it using MEM deviees. Since the matching is done off-chip, the linearity and

efficiency of the PA can be adjusted as needed. The PA is designed to used for the

Personal Communications Service, PCS, band. The North American PCS band is defined

in the range of 1.85 GHz to 1.91 GHz for mobile to base applications. The design

frequency in this work is thus set to 1.88 GHz, i.e. in the middle of the PCS band. The

objective is to extract a maximum of 25 dBm of power from the PA with an IMD of -25

dBc or better, and the maximum attainable efficiency. The ultimate goal is to be able to

tune the output load with respect to the input drive level to keep the efficiency at

maximum values.

3.1.3 Single Transistor Design

The initial design goal is to meet the design specifications using a single power transistor.

A one stage amplifier with the biasing network is shown in Figure 3.22.

34

r·\


VcoNr V cc

V cc

RFC

Coecoupling

Figure 3.22: One-stage power amplifier with active biasing.

3.1.3.1 Biasing Circuit Design

The design of the biasing circuit is an important part of the PA design. The performance

of the amplifier cannat be sacrificed by having a poor DC biasing network; the specifie

DC parameter set by this network should be stable over transistor parameters and

temperature variations. In applications where the temperature changes are not significant,

resistor biasing networks are used. However, when the temperature variations become

significant, active biasing becomes essential [20].

The transistor parameters that are affected most by temperature variations are: lcBo

(reverse current), hFE, and VBE· IcBo doubles with every 10°C increase in temperature.

VBE has a negative temperature coefficient; i.e.

(Equation 3.1).

35

' .~

Chapter 3: Design ofPower Amplifier

VcoNT Vcc

RFC

Figure 3.23: Active biasing circuit.

The DC current gain, hFE, is defined as the collector-to-base current at constant VCE; hFE

increases linearly with temperature at a rate of 0.5%/°C [20].

The biasing network shown in Figure 3.23 acts as a variable voltage source with low

resistance. The two back-to-back diodes are used to prevent thermal runaway. In the

absence of the diodes a voltage of approximately 2 VBE, due to Qhias and QRF, appears

across R3 (Figure 3.24). As the temperature increases, 2VBE decreases (according to

Equation 3.1), which translates into an increased IBJ and therefore an increased IB2· The

increase in the base currents increases the temperature even further and ultimately results

in a thermal runaway. The presence of diodes D1 and D2 means that the voltage-drop

across R3, ignoring the drop ac ross R1, is approximately 2 VBE- 2 VBEdiode, which remains

constant with temperature variations, hence preventing thermal runaway.

Another measure that ensures thermal stability is the presence of the resistor R1 in the

emitter of the bias transistor. Any increase in IB2 results in an increase in the voltage-drop

across Rb and therefore reduces IB2 through negative feedback.

36


VcoNr V cc

• • •

RFC

Figure 3.24: Bias network with the possibility of a thermal runaway.

The resistor divider, R:z and R3, is used to present a fraction of the control voltage, VcoNT,

to the base of the bias transistor, thus enabling finer tuning of the voltage. The voltage set

by the bias network, VB in Figure 3.23, appears at the base of the RF power transistor

through the extemal RF choke. The role of the RF choke is to prevent the RF signal from

the source to leak into the biasing circuit. The reactance of the RF choke should be at

least 10 times the value of R in order to have a minimum loading effect on the power

circuit, i.e.

R x <Lo- 10 (Equation 3.2),

where R is 50 n and Xw is the reactance of the choke. Furthermore, the following

relation also holds:

(Equation 3.3),

where Q is the quality factor of the choke. For a Q of 10, the minimum value of the

choke, for it to have negligible effect on the circuit, is 0.42 nH at 1.88 GHz and 0.88 nH

at 900 MHz [49]. In the design presented here a 1 JlH off-chip choke with a self-resonant

frequency of 10 GHz is used.

37


The required resistor values are determined by simulating the bias network in Cadence.

The objective is to provide a collecter current range of 1.25 mA to 80 mA to the power

transistor by extemally varying the control voltage VcoNT· The resistors are realized using

the on-chip resistors available in the SiGe technology. R1 and R3 are both PBD resistors

with values of 50 n and 100 n, respective! y; R2 is a 2 kQ FRD resistor. Both are

polysilicon resistors placed over a deep trench in order to reduce their parasitic

capacitances. The difference between the two is that PBD resistors have a sheet resistance

of 220 Q/o while the sheet resistance of the FRD resistors is higher, namely 1500 Q/o

[2], [35], [50].

3.1.3.2 Power Core Design

The quiescent current in class AB operation is set between that of classA and class B [1],

namely,

Jmax (1 (Jmax re Q 2

(Equation 3.4).

By performing simulations to characterize the DC behavior of the various transistors

available in the BiCMOS 5HP technology, the maximum collecter current for each

transistor is obtained and summarized in Table 3.3. Based on these values and according

to the above relation, the range of the quiescent current for class AB operation is

determined. This technology offers vertical HBT NPN transistors with the emitter width

fixed at 0.5 j..lm, while the length of the emitter can be changed from 2.5 1-1m to 20 j..lm.

The higher emitter length allows the transistor to handle more current, thus the transistor

has a higher individual power gain. The high breakdown transistors, NPNHB, have

higher collector-to-emitter breakdown voltages, but lower stand-alone gain. This trade..:

off becomes cruciallater on when deciding which transistor type is to be used as the main

power transistor.

At low frequencies, an emitter resistor, RE, may be used in the power transistor to provide

quiescent current stability. At higher frequencies, however, the presence of RE not only

lowers the gain but may also cause oscillation by forming a parallel resonant tank with

38


the parasitic capacitances. As a result, the emitter of a power transistor, especially at GHz

frequencies, is grounded [20].

a e . : T bi 3 3 Th e curren

Transistor- Emitter width

x length

NPN2-0.5 x 5

NPN2- 0.5 x 10

NPN2 - 0.5 x 20

NPNHB2 - 0.5 x 20

Biasing Circuit

t capa 11ty o 1 e bTt fS"G t . t rans1s ors.

Irated Class AB IQ Range

(mA) (mA)

45 0.64-1

88 1.9-3

160 7.6- 12

120 7.6- 12

V cc

Figure 3.25: Critical RF paths in the PA.

The package model and the bondwires parasitic inductances should be taken into account

from the early design stages. At high frequencies, the bondwires that connect the on-chip

bond-pads to the package pins exhibit significant inductance. The bond wire parasitic

inductances become especially important when in one of the critical paths of the design

shawn in Figure 3.25. The inductance of the bondwire in the input and output RF paths,

critical path 1 and 2, can be absorbed into the input and/or the output matching networks.

The parasitic inductance in path 3 however has a direct degrading effect on the gain of

the PA.

39


The inductance ofthe bondwire can be approximated by [51]:

(Equation 3.5),

where 1 and r are the length and radius of the bondwire in meters, respectively; 11 is the

permeability of the wire in Hlm. The rule ofthumb often used in RF designs assigns 1 nH

of parasitic inductance for every 1 mm of bondwire.

Great care must be taken to minimize the parasitic inductances in the grounded emitter of

the RF power transistor, especially since every dB of gain at RF frequencies counts. One

way to address this issue is to place the power transistor at the layout stage, with respect

to the chip border, and to keep in mind the placement of the package pins, such that the

bondwires for the critical paths will be as straight and as short as possible. Another

important solution is to assign two or more pins to a given grounded emitter. Ideally, two

identical electrically-parallel inductors have an overall inductance of one half. This is true

only if the two inductances are placed physically at a 90° angle to each other, otherwise

the equivalent inductance will be higher than 0.5 due to mutual coupling. In case of two

bondwires that are both physically and electrically parallel, the overall inductance is

about 7110 of the initial inductance [52].

The usual practice is to assign two ground pins to each emitter. Having more pins means

a slightly lower equivalent inductance, but it also requires a larger package with a larger

cavity, which calls for longer metal paths on chip, and longer bondwires. At this design

stage, two package pins are assigned to ground the emitter of the power transistor. Given

the dimensions of the Si Ge chip to be manufactured and a rough number of the required

pins, a 44-pin ceramic quad flat package, CQFP, is chosen. Taking into account the

dimensions of the package, each bondwire is modeled by a 3 nH inductor.

The package too exhibits losses at high frequency. The most important of these are the

series-inductive losses and shunt capacitive losses. A simple model for the pins of a 24-

pin CQFP is provided by the Canadian Microelectronics Corporation (CMC) which take

into account the coupling between adjacent pins as shown in Figure 3.26. As will become

40


apparent later, it was found that this model is not accurate for the 44-pin CQFP at a GHz

range. The losses associated with the package are inevitable; the power amplifier should

be designed around these losses.

254.7 pH 2 n

2.54.7 pH 2n

-----------

Pinn

Coupling Cap 3.75 fF

Pin n+l

Figure 3.26: Initial package pin model.

Similar to the RF choke, the reactance of the decoupling capacitor should also be at least

10 times 50 n in order for it to have negligible loading effect on the main circuit. The

following relation should also be satisfied:

R Xco = Q (Equation 3.6)

where Ris 50.Q and Q is the quality factor of the decoupling capacitor. For a Q of 10, the

minimum value of the decoupling capacitor is 17 pF at 1.88 GHz and 35 pF at 900 MHz.

The decoupling capacitor used here is an off-chip 0.01 JlF capacitor with a self-resonant

frequency of 40 GHz.

As discussed in section 2.2.4, the shunt-tuned output resonant tank is set to resonate at the

fundamental frequency and bypass the harmonies contents; i.e. z1o = oo, z12 = 0, Zp = 0,

and so on. In essence, in the absence of a complementary or transformer-based

architecture, the tank recovers the sinusoïdal shape of the signal. The resonant frequency,

W 0 , of a parallel resonant circuit is given by:

41


1 OJ = -- (Equation 3.7)

0 JLC

where L and C are the inductance and the capacitance of the tank, respectively [17]. The

capacitance, C, should be chosen to be large enough to short all higher order harmonies

to ground. A reasonable value at 1.88 GHz would beL = 1 nH and C = 7.2 pF.

3.1.3.3 Input Matching Network

After supplying the RF transistor with the correct quiescent current, the input of the PA

bas to be conjugate matched to the source, in order to transfer the maximum power from

the source to the PA. Using the small-signal S-parameter analysis in Cadence, the input

impedance of the power amplifier under a specifie biasing at a given frequency is

obtained. The matching is done based on the equations presented in section 2.3.1. There

are two possible two-component matching networks: low-pass (Figure 3.27 (a)) and high

pass (Figure 3.27(b )). In order to prevent node X to be DC ground, the low-pass matching

network is used in the design here. Other options in elude using a T- or a n-network.

3.1.3.4 Output Impedance Transformation

As discussed earlier, the matching requirements in power amplifier are quite different

from that for other types of amplifiers. Conjugate matching does not often yield the best

1oad impedance for maximum output power or efficiency. To complicate the matter

further, the Joad-pull circles for maximum output power and maximum efficiency do not

always coincide, this is especially true at higher power levels.

(a) (b)

Figure 3.27: Two-component matching networks: (a) low-pass and (b) high-pass.

42


Be fore performing the load-pull procedure, the output impedance of the PA, Zout, under a

certain biasing condition is determined by S-parameter analysis. Next, the load-pull

analysis is performed to determine the optimum load impedance, Zopt, either for

maximum output power or maximum efficiency. The load-pull contours in Cadence are

obtained through Spectre's Periodic Steady-State analysis, PSS, and by using the

PortAdapter from the standard "rfExamples" library. At a given drive lev el and

frequency, both the phase and magnitude of the output reflection coefficient, r, are swept

and constant-power contours on the Smith chart are obtained [53]. Using the general

matching technique detailed in chapter 2, Zout is matched to Zopt through a T -network.

The load-pull contours showing the normalized optimal output impedance are presented

in Figure 3.28. The load-pull simulations in Cadence take a long time and do not always

converge. Simulating with more points results in closed contours but may also cause the

simulator to fail to converge. It should be noted that the Cadence analysis tool is capable

of providing the maximum power contours and not the maximum efficiency ones. ADS

on the other hand is a much more powerful tool.

Figure 3.28: Single-transistor PA Joad-pull circles for maximum Pout·

43

20

~ 10 E m "0

0.0

-10


Periodic Steody State Response

Pin (dBm)

Figure 3.29: Single-transistor PA output power characteristics vs. input power.

3.1.3.5 Simulation Results

The input drive power is swept with the output matching network in place. The resultant

output power characteristics and power gain are shawn in Figure 3.29 and Figure 3.30,

respectively. The maximum obtainable gain with one transistor is only 12 dB; the gain is

not enough for the targeted application. The most obvious way to increase the gain is to

use a larger size power transistor. Since the largest transistor size in this technology, with

an emitter length of 20 J.lm, has already been employed, this option was exhausted. More

than one transistor can be put in parallel to increase the overall gain. As will be shawn

later, this presents challenges with regard to power distribution and combining and the

lasses associated with it. The ground pins for the emitter can also be increased to sorne

degree; nonetheless, this did not help increase the gain by much.

Another important issue is the collecter breakdown. The voltages that appear across the

collecter of a power transistor are inherently large. There is a certain amount of voltage

the transistor can handle before the collector-emitter junction gives away. For this reason,

the high breakdown transistors are used in the power core which, even though have a

higher junction breakdown, still cannat handle power levels higher than the given level.

44


P~ri~di' St111~d<; ~t~Jte A:iii-~PQ"I'f~

12 .,~. <)

l1

Figure 3.30: Single-transistor PA power gain.

3. 1.4 Multiple Transistor Design

Putting multiple transistors in parallel increases the overall output power while

decreasing the output impedance. In addition, when too many transistors are paralleled,

the output parasitic impedances ( e.g. the collector-to-substrate parasitic capacitance) will

overcome the transistors output impedances resulting in gain reduction rather than gain

enhancement. Performing simulations with different numbers of transistors showed that

the optimal number of transistors in parallel for this specifie application is four. With

more than four transistors, the output power and gain do not exhibit a significant increase.

The biasing network designed in section 3 .1.3 .1 for the single transistor can be used with

multiple transistors design as well, since the base biasing voltage is transferred through

the RF choke. The issue that arises is the splitting of the input RF power and the

combination of the output power from the different transistors. Different matching

schemes are also possible. Either the matching can be done at one stage for all the

transistors, Figure 3.31 (a), or each transistor can be primarily matched to a value

between 10 n and 25 n and then matched to 50 nin a second stage, Figure 3.31 (b) [54],

[55], [56].

45


Figure 3.31: Biasing schemes for parallel transistors.

In the initial design, the output powers of the four transistors were added on-chip and

then taken off-chip to the load; in ether words, only the transistor multiplicity was

increased. Extensive simulation showed that under this condition, the individual

transistors broke down at about 0 dBm of input drive since, as mentioned before,

paralleling the transistors directly reduces the output impedance. Using high breakdown

NPN transistors with the largest emitter length, NPNHB 0.5 x 20 J..lm2, improves the

situation but not significantly. The problem is alleviated to a great extent by combining

the power from individual transistors off-chipas demonstrated in Figure 3.32. In fact, by

introducing the package parasitics to the signal path, the load-line has moved to a new

location to prevent the breakdown of the transistors. The new load-line presents the

transistors with a lower collector voltage which implies that the individual transistors are

not driven at their full power capabilities, and the larger output power is achieved

basically by the power-additive nature of the parallel transistors.

Similarly, at the input side there can be severa} ways of delivering the RF drive to

individual transistors. One way is to have one path for each transistor, i.e. four input

paths in total. Even though there are enough pins on the package for this purpose, the

bonding wires will have different length for each one. Another way is to have one single

line bringing in the RF drive into the chip and then splitting on-chip. The third method is

to have two input RF pins, each splitting into two once inside the chip. In this case the

bondwires corresponding to these pins will have comparable sizes, thus minimum phase

delay between the inputs and lower distortion at the output.

46


Reference Plane

RF in RF out MN MN

Reference Plane

Figure 3.32: Off-chip power-combining.

Simulations were performed under all the mentioned conditions. The optimum option for

this specifie design is the third solution (Figure 3.32). It should be kept in mind that each

of these methods presents the input of the PA with a different impedance: The input

impedance is not decoupled from the output impedance, meaning that, in this design,

using two pins for the RF input presents the PA with the best load-line at the input and

the output reference planes.

The input impedance of the multi-transistor PA is also conjugate matched to the source

impedance of 50 n. The reference plane for input matching is before the power is split up

in Figure 3.32. Likewise at the output side, the matching reference plane is after the

power combining node, same node as the output resonant tank. So, this power amplifier

in reality consists of four integrated power modules that are matched and combined off

chip. Once the input power-splitting and output power-combining methods are

established, iterative simulations are run to find the optimum number of transistors.

Under these circumstances too, the optimal number of transistors are found to be four -

having more than four transistors does not contribute significantly to the output power.

47

(~


Bond-pad

To Vww To VHIGH

Figure 3.33: Electrostatic discharge protection circuit.

3.1.4.1 ESD Protection

Care must be taken to protect the PA against electrostatic discharge, ESD, that can

destroy or damage the chip. Bipolar transistors are more rugged with respect to

electrostatic discharge, compared with CMOS transistors where the gate oxide can be

very sensitive to this phenomenon. The ESD protection circuit used in this design

consists of four back-to-back diodes that are placed close to critical bond-pads. The

diodes are reverse-biased under normal operating conditions through Vww of 0 V and

VHIGH of 2.2 V. When an electrostatic discharge occurs, the ESD protection network acts

like a capacitor and directs the built-up charge to ground. A schematic view of the ESD

protection network is shown in Figure 3.33.

The ESD protection circuit should be designed with small size deviees and be placed

close to the bond-pads to reduce its effect on the circuit in normal conditions [57].

Nevertheless, since it acts like a capacitor, it can charge and discharge during the

operation of the PA. The most pronounced effect of ESD protection is on the gain of the

amplifier; the priee of protecting the PA from electrostatic discharge is a gain reduction

of 2 - 2.5 dB. The presence of the ESD protection also causes serious complications with

load-pull simulations in Cadence to the extent that they hardly converge [58].

48


3.2 PA Layout

The important issue of the layout stage is floor planning, with the objective of

minimizing the lengths of the critical RF paths and the RF signal interferences. This is

achieved by placing the RF input, RF output, and RF ground bond-pads at 90° with

respect to each other; with the DC signais occupy the remaining part of the chip as shown

in Figure 3.34. As mentioned earlier, since a maximum of 44 pins are available in the

package, two ground pins are assigned to the grounded emitter RF transistors. A

grounded bond-pad is also placed between each RF bond-pad to shield the active signais.

The supply voltage, VCC, for the bias network is also separated from the VCC of the

power core to minimize any interference through the supply.

In order to create a low resistance path to ground for surge currents and protect the chip

from ionie contamination during fabrication, a guard ring is placed along the chip border.

For specifie details on guard ring requirements for this specifie technology, please refer

to the SiGe Design manual [59].

ICChip

Figure 3.34: Separation and isolation of RF signais to minimize interference.

49


Protection

Figure 3.35: Layout view of a bond-pad with ESD protection.

The SiGe technology contains standard bond-pads that are placed over the n+ region in

the p- silicon substrate to shield it against noise. The dimensions of the standard bond

pads are 109 x 109 11m2• The bond-pads can also be protected by local guard rings to

provide more signal isolation; in this case, the local guard ring is to be tied to the lowest

potential, VSS. A bond-pad with the accompanying ESD protection circuitry is shown in

Figure 3.35. Note the close placement of the ESD protection to the bond-pad and the

biasing of the diodes.

The final PA layout is presented in Figure 3.36. The thicknesses of the metal paths differ

based on the average current they carry and the current ratings of the specifie metal layer.

One last detail to note is the serpentine shape of the RF input lin es to ens ure comparable

phase delays in the four paths.

50


Figure 3.36: Final PA layout.

3.3 Extracted PA Simulation Results

The power amplifier layout is extracted in Cadence. The extraction will take into account

ali the losses associated with the metal paths, the bond-pads, and the parasitic

components. The extracted PA gain and P AE for a quiescent current of 10 mA are shown

in Figure 3.37 and Figure 3.38, respectively. Large-signal stability simulations, based on

the guidelines in chapter 2, show the PA to be stable under the operating conditions.

13.12!

12.12!

11.0

~ 10.0

9.12!0

8.12!0

7.12!0 -212!.00 -11.25 -2.500

Figure 3.37: Extracted PA gain at 10 = 10 mA.

51

~ ..


20

10

Figure 3.38: Extracted PA power-added-efficiency, PAE, at 10 = 10 mA.

The quiescent current is swept, through VcoNT, and the resultant gain, power-added

efficiency, and linearity results are tabulated in Table 3.4. In order to have a better view

of the real capabilities of the power transistors, the input drive power under which the

breakdown occurs under each bias condition is also reported. Note that the given

quiescent current is per transistor. The trend in moving from the class B behavior towards

the class A behavior is clearly seen. At low quiescent currents, the efficiency is high but

the linearity is also low. As the quiescent current is increased, and the PA moves towards

class A, the efficiency drops but the deviee becomes more linear.

T bi 34 P a e . owergam an d PAE f as fi unct1on o 112-

IQ Gain (dB) Maximum Breakdown IMD~

(mA) (for P;0 = -10 dBm) PAE(%) Power (dBm) (dBc)

5 13 60 5

10 12.8 23 6

20 12 14 8 -17

30 10.6 12 10 -40

40 9.8 9 10 -44

51 8.8 2 12 -46

* IMD: Intermodulation Distortion.

52

1


3.4 Package, Bondwire, and PCB Models

The models used in the initial design for the package and bondwires were found later on

to be not accurate enough. Moreover, the printed circuit board (PCB) path losses should

have been accounted for in the design. For this purpose, empirical models were

developed. Utilizing the 44-pin QCFP package, an input pin is bonded and grounded as

depicted in Figure 3.39. This setup allows the designer to devise a model for the

components that will have the most degrading effects on the PA output, namely the

bondwires, the package, and the PCB tracks. One-port S-parameters of this deviee are

measured using a vector network analyzer, VNA, and imported into the Advanced Design

System, ADS, environment. There are several advantages in using ADS for developing

empirical models. The most important is the easy interaction between ADS and the

majority of measurement instruments which facilitates the import and export of data. The

significance of easy interactivity becomes evident when compared with the Cadence

simulating tool where it is very difficult to import arrays of data into the system.

Moreover, ADS has user-friendly pre-defined tools for model generation and

performance optimization. For this purpose, initial rough models are setup for each

component and ADS tools are used to fit the S-parameters to the RLC networks. For a

description of the model fitting scheme that is used in ADS please refer to Appendix A.

Figure 3.39: The setup for developing empirical models for the PCB track, the bondwire, and the package pin.

53


3.4.1 Bondwire Mode/

The bondwire is modeled by series inductive and resistive components. In the original

design, it was modeled with an inductor with value of 1 nH/mm. In the new model, the

inductive component is kept the same but resistive components have been added to model

the losses that are independent of frequency. The fitted bondwire model for a 1 mm of

bondwire is shown in Figure 3.40.

213 fH 1 nH 213 fH

80.3 mn 80.3 mn Figure 3.40: Bondwire model for a 1 mm of bondwire.

3.4.2 Package Mode/

The fitted package model is far more complicated than the one used before. The initial

package pin model, shown in Figure 3.26, was a single RLC network. The behavior of

the actual package pins however turned out to have more of a distributed nature.

Moreover, the series inductive losses and the shunt capacitive losses add up to far greater

values than what the previous model had. The empirical model for a single package pin is

presented in Figure 3.41; the sub networks are designed to be identical.

Figure 3.41: A single package pin model.

54


3.4.3 PCB Track Mode/

Modeling the PCB tracks is more complicated than the bondwire and package. In the

initial design, a PCB line was modeled as a 0.5 nH inductor. For the empirical madel,

every 50 mils (0.127 cm) of the PCB track were modeled with an RLC network as seen in

Figure 3.42. When the PCB lasses are accumulated, they become significant. This is

especially true in the output path where four branches are used, with the best case length

of 400 mils (1.0 16 cm) and worst case 1ength of 500 mils (1.27 cm).

827 pH 315 mO

T 2191F

Figure 3.42: PCB line mode! per 50 mils (0.127 cm).

3.4.4 Final Simulation Results

After incorporating the new models into the design, the PA simulations are rerun. The

response shows that the off-chip losses are so high that the output of the PA is degraded

to a great extent; the S21 response is shawn in Figure 3.43. In chapter 5, these results are

compared with the actual measured results and solutions for improving the gain are

discussed.

••

Figure 3.43: S21 response of the PA with the new and more accu rate models in place.

55

Chapter 4: MEMS Tunable Power Amplifier

4 MEMS Tunable Power Amplifier

Micro-electromechanical systems (MEMS) enable new levels of performance in radio

frequency integrated circuits which are not readily available via conventional IC

technologies. The low quality factor of IC passive elements, such as inductors,

capacitors, and filters, force the designers to use off-chip elements. Off-chip components

are undesirable due to the parasitic losses associated with the component itself, the

soldering, and the PCB tracks. Moreover, large value extemal components often have

low self-resonance frequencies making them unsuitable for RF applications. RF Micro

electromechanical deviees offer the opportunity to integrate many RF subcomponents

that are traditionally implemented off-chip. RF MEMS have entered the

commercialization phase in 2003 offering compact, low power, low loss, highly linear,

and high Q solutions. They also make possible new architectures, with the possibility of

reconfigurability and tunability for multi-band or multi-standard operation [60], [61].

In this part of the research, MEMS variable capacitors are designed and implemented in

the Metal-MUMPs process. First, the mechanical and electrical operations of MEMS

tunable capacitors are viewed, and different mechanisms for achieving tunability are

discussed. Next, an overview of the Metal-MUMPs process is presented. Several varactor

designs based on the capabilities of the Metal-MUMPs are proposed. Finally, the

designed varactors are visited in the context of power amplifier matching and load-pull

analysis.

56


4.1 MEMS Tunable Capacitors

4. 1. 1 Overview

Variable capacitors are used in a number of RF circuits, such as voltage controlled

oscillators, matching networks for power amplifiers, and loaded-line phase shifters. In all

of which, the performance of the circuit is directly related to the quality of the variable

capacitor. Depending on the application, the requirements on MEMS capacitors differ. In

voltage-controlled oscillators, for example, the quality factor of the MEMS varactor

should be as high as possible. For matching purposes, on the other hand, a wide tuning

range is important.

Traditionally, variable capacitors m microelectronic systems have been implemented

using p-n junction diodes or MOS capacitors. The se deviees have a relative} y poor tuning

range, are extremely non-linear, and have significant parasitic losses through the

substrate. MEMS varactors can handle large voltage swings. In p-n junction capacitors,

the voltage swing is limited in order to ensure the proper biasing of the p-n junction, in

other words to always keep the junction reverse-biased.

The most important drawback of semiconductor varactors is the dependence of the

capacitance on the RF signal level, which makes the component behavior highly

nonlinear. In case of MEMS capacitors on the other hand, good linearity is inherent.

Since the mechanical resonant frequencies of micro-machined tunable capacitors usually

lie in the 1 0-1 00 kHz range, these deviees do not respond to RF frequencies and therefore

do not produce a significant amount of harmonie distortion [62], [63], [64].

There are severa} issues associated with MEMS varactors. One drawback is the need for

large actuation voltages, sometimes in ex cess of 40 V. Another issue is the series resistive

losses resulting in a low unloaded Q.

57


Suspended Plat

Fixed Plate

Figure 4.44: Two-plate electrostatically actuated MEMS varactor.

4. 1.2 Principle of Operation

MEMS-based tunable capacitors have been implemented using a variety of techniques

and mechanisms. The most commonly used structures rely on varying the overlap area of

the capacitor by changing the distance of either vertical plates or lateral fingers meant to

increase the fringing field. These two methods of tunability are presented here in detail.

Other modes of operating MEMS varactors have been explored in [65], [66], [67]. These

tunable capacitors require customized manufacturing capabilities, such as the ability to

slide the dielectric material and/or the presence of piezoelectric materials, and do not

demonstrate a significant advantage in terms of performance and will not be considered

here.

4.1.2.1 Parallel-Piate MEMS Varactor

A functional madel of a two-plate electrostatcially actuated MEMS tunable capacitor is

shawn in Figure 4.44. The top plate is suspended by arms having an overall spring

constant of k wh ile the bottom plate is fixed. The capacitance of this structure, assuming

air as the dielectric, to first order is given by:

C = &oA 0 d (Equation 4.1)

58


where A is the overlap area of the two plates, d is the gap between the two plates under

the no-bias condition, and 80 is the permittivity of air. Applying a bias voltage of V(t)

results in an electrostatic force that pulls down the top plate towards the bottom plate,

thus varying the inter-plate capacitance according to Equation 4.2:

C= &OA d-x

(Equation 4.2)

where x is the displacement of the top plate due to the applied bias, V(t). The resto ring

force of the spring however opposes the electrostatic pull-down. As long as the gap

between the two layers is larger than a third of the original gap, the two forces are in

equilibrium. If the gap displacement becomes larger than this critical value, the

electrostatic force overcomes the spring restoring force and the top structure collapses

completely on the lower electrode. This phenomenon, known as pull-in, limits the

displacement of the movable plate, x, to d/3; thus the maximum value of capacitance

before failure, CMAX, is limited to i &oA. Based on Equation 4.3, the tuning range of the 2 d

simple two-plate electrostatically-actuated MEMS varactor is limited to 50% [62], [68],

[69]:

C -C Tuning Range = MAX

0

Co (Equation 4.3)

The pull-in voltage is dependant on the spring constant of the suspension arms, k, the

distance between the plates, d, and the plate area, A, as described by the following

equation:

vpull-in = (Equation 4.4)

The vertical electrostatially-acutated capacitor is the simplest form of a MEMS varactor

to implement by surface micromachining; the only drawbacks are the need for large

actuation voltages and the performance limitations imposed by the pull-in effect.

Different MEMS-based varactor designs have been implemented which through the

addition of an extra structural layer, take advantage of the readily available surface

micromachining techniques while enjoying much wider tuning ranges. Two of these

generic structures, referred to as Type II and Type III, are discussed here.

59


k

V(t)

Figure 4.45: Type Il parallel-plate MEMS varactor with wide tuning range.

4.1.2.1(a) Type II Vertical Varactor

Figure 4.45 illustrates the schematic for a type II parallel-plate MEMS varactor. At }east

three structural layers are required to construct the two gaps and separate the actuation

electrodes E1 from the main capacitor plate E2 . For extended tuning range, the un-biased

capacitor gap d1 should be larger than one third of the electrode gap d:z, i.e. dz 2: d:z/3.

Upon the application of actuation voltage, V(t), the movable top plate is pulled down

towards the bottom plate, in this case, the distance that defines the onset of pull-in is d2/3,

as opposed to the shorter distance of d1/3, hence the maximum achievable capacitor,

CMAX, becomes ~ &oA. Therefore the tuning range, TR, becomes: 2 d 2

TR = 3d! type!I 3d - d

1 2

(Equation 4.5)

which can be as high as 84%, depending on the technology specifications that define the

available gaps [70], [71], [72], [73].

60


Figure 4.46: Type Ill parallel-plate MEMS varactor with very wide tuning range.

4.1.2.1(b) Type III Vertical Varactor

The tuning range of the parallel-plate varactor can be further extended by using a two-gap

type III structure, as illustrated in Figure 4.46.

In this class of variable capacitors, the actuation electrodes E1 are kept separate from the

main capacitor plate E2 and the gap between the suspended membrane and the signal

electrode, d1, is smaller than a third of the distance between the membrane and the

control electrodes, d2, i.e. d1 :::; d2/3. As a result, the pull-in of the control electrodes does

not occur before the suspended membrane touches the signal electrode. Thus, the

maximum achievable capacitor is determined by the dielectric material that is on top of

the signal electrode E2• The tuning range can theoretically go to infinity; in practical

applications however tuning ranges as high as 280% have been reported [69], [72], [73],

[74].

4.1.2.2 Lateral lnterdigitated MEMS Varactors

Figure 4.47 shows a laterally-driven interdigitated tunable capacitor where one set of the

combs is fixed while the other set is free to move. Upon the application of a voltage, the

electrostatic force at the fringes of the fingers causes in-plane actuation of the movable

61


combs. The tunability is thus achieved by varying the overlap area of the capacitor. The

tuning range of a lateral capacitor is not limited by a pull-in voltage; tuning ranges of

200% have been achieved with this structure [75], [76], [77]. The only real limitations are

the mechanical characteristics of the comb fingers and the suspension spring. Long

fingers increase the fringing field capacitor and allow larger tuning, but are also more

susceptible to breaking during the manufacturing and testing phases. Also, the greater the

number of fingers, the larger the gravitational force, thus the higher the chances of

suspension arm failure. Compared with vertical MEMS capacitors, the interdigitated

varactors usually have lower Q-factors and low self-resonance frequencies, which makes

them not suitable for RF applications [78], [79], [80].

4.1.2.3 Semi-Fractal Varactor

In the microelectronics industry, fractal capacitors have been investigated. They make

use of both vertical and lateral electric fields to increase the capacitance per unit area,

which can result in considerable reduction in the chip space consumed by the capacitors

[81]. An ideal case in the MEMS-based varactor design would be a fractal MEMS

capacitor that benefits from the increased capacitance density offered by fractal structures

and the tunability offered by MEMS varactors. A similar structure is proposed in [82],

however, no analytical expression for the capacitance is offered.

Figure 4.47: lnterdigitated lateral MEMS varactor.

62

/"'~ 1 ',


Figure 4.48: Top view of the semi-fractal MEMS varactor.

A top view of the semi-fractal MEMS varactors is shown in Figure 4.48. The semi-fractal

capacitor is similar to a simple MEMS varactor, with the difference that the top plate is

made of interdigitated fingers to increase the capacitance per unit area.

4.1.3 The Metai-MUMPS Process

The Metal Multi-User MEMS process, Metal-MUMPS, surface micromachining

technology is used to implement the MEMS varactors designed in this research. As seen

in Figure 4.49, the important feature of this process is the presence of a 20 11m thick

nickel structural layer covered by 0.5 11m of gold. The second structural layer is a 0.7 11m

thick doped polysilicon which can be suspended over the silicon substrate. A 0.35 11m

thick ni tri de layer is deposited on top of the polysilicon; this layer acts as a dielectric and

prevents short circuits in case the metal layer collapses on the poly. The gap between the

metal and the polysilicon is 1.1 11m and the gap between the suspended polysilicon and

the un-etched substrate is 0.5 Jlm. A 25 Jlm cavity is etched in the silicon substrate over

which the polysilicon structural layer can be suspended. A combination of platinum and

chrome are used to anchor the metal layer to the substrate [83]. It has been shown that

removing the substrate results in higher self-resonance frequency and quality factors in

general due to the reduction of parasitic capacitive losses to the silicon substrate [84].

63

' l


Figure 4.49: Overview of the Metai-MUMPS structurallayers.

The presence of two structurallayers, where both can be made movable, and two gaps,

makes the implementation of wide tuning range varactors with this technology possible.

Also, the low resistivity of the metal structural layer lowers the series lasses in the

capacitive plate, the suspending arms, and the signal pads to a great extent. However,

since the other structural layer is polysilicon, high values of Q cannat be expected [85].

4.1.4 MEMS Varactor Design in Metai-MUMPS

Figure 4.50 shows a top-view schematic of the MEMS capacitors designed in the Metal

MUMPS process.

Figure 4.50: Top view of the varactor designed in Metal-MUMPS.

64

t

t

•


Figure 4.51: Functional model of the designed two-plate wide range varactors.

In order to understand the operation mechanism of this particular capacitor, the cross

section along the AA' line is given in Figure 4.51. Both the polysilicon and the metal

layers are suspended. The polysilicon layer is set to ground, while a DC voltage is

applied to the metal layer. The electrostatic force initially pulls down the metal

membrane towards the polysilicon, varying C1, until it collapses onto the polysilicon

membrane. Due to the presence of the thin nitride layer on top of the poly, short circuit

does not occur. Since the poly membrane is also free to move, the collapsed structure

moves toward the silicon substrate this time varying the C2. The two phase tunability of

the total capacitance results in an extended tuning range. Note that C3 denotes the

parasitic capacitance of the metal layer to the substrate which is not very significant due

to the presence of the trench, but still can deter the overall performance.

Using Equation 4.1 and assuming an initial gap of 1.1 Jlm, the top plate dimensions for

different capacitances are calculated and tabulated in Table 4.5. The dimensions of the

bottom plate are the same as that of the top plate. Uniformly spaced ho les are etched in

the bottom and top plates to facilitate the removal of the sacrificial oxide between the

polysilicon and the substrate and the polysilicon and metal. As discussed in section

4.1.2.3, the structures that combine the fringing capacitance of interdigitated capacitors

with the vertical plate varactor concept are of interest. For each of the simple varactor

structure, an equivalent semi-fractal structure is also included. The semi-fractal designs

65


are expected to have higher initial capacitances, but may be more susceptible to failure

due to gravitational forces because the weight of the plate is not uniformly distributed.

Table 4.5: Capacitor plate dimensions.

Capacitance Length

0.05 pF 80 f.1m

0.1 pF 112 f..lffi

0.5 pF 250f.1m

1 pF 353 f..lffi

2pF 500 f..lffi

5pF 800 f.1m

4.1.4.1 Suspension Design

The suspension structures that are most often used in MEMS varactors are of the T -type.

As seen in Figure 4.52, the T-type suspension can be modeled to a first degree by a series

and parallel combination of springs. The equivalent spring constant of each suspending

arm is given by [62]:

k = 2k,k2 k, +2k2

(Equation 4.6)

where k1 and k2 are the elasticity constants corresponding to L1 and L2, respectively, and

are determined through:

(Equation 4. 7)

where W;, L;, and T; are the width, length and thickness of the bearn as indicated in

Figure 4.52, respectively. E is the Young's modulus of the structural layer, 200 GPa for

the nickel structure and 158 GPa for the polysilicon layer. The overall spring constant is

4k for a plate supported by 4-arms.

There is a large temperature-dependent stress in metal structures. The stress is caused by

the difference in the coefficient of thermal expansion of the metal and the substrate, as

well as between the metal and the polysilicon [69]. A curved suspension design, which is

66


basically a quarter of a circle with a given width, fixes the metal plate in the plane

parallel to the substrate while allowing horizontal rotational movements in the metal

structure; thus partially absorbing the stress [73], [86].

Figure 4.52: T -type suspension and the equivalent spring model.

Using the plate dimensions given in Table 4.5 and limiting the pull-in voltage to 10 V,

the required dimensions of the arms can be calculated based on Equations 4.4, 4.6 and

4.7. Low actuation voltages require long arms, which increases the chance of failure due

to gravity since the spring is also suspend and is thin. The calculated values for the arm

dimensions are summarized in Table 4.6. The longer part of the arms, L 1, can be either

realized as a straight cantilever or a serpentine arrangement. For comparison purposes,

bath cases were included in our designs.

T bi 4 6 C a e . : apac1 or suspen mg arm "t d" d" amensaons.

Capacitance Width Length

0.1 pF 10 f.!m 1300 f.!ID

0.5pF 20 f.!ID 970 f.!ID

1 pF 30f.!m 880f.!m

2pF 40f.!m 772 f.!m

SpF 50 f.!ID 612 f.!m

67


.. 100 1..1 ~

Figure 4.53: The GSG signal pad for on-chip probing.

4.1.4.2 Signal Pad Design

The signal pads are designed for on-chip probing with Ground-Signal-Ground, GSG,

probes with a pitch of 150 Jlm (Figure 4.53). The ground pads are 100 x 100 J.Lm2 and the

signal pad is 70 x 70 Jlffi2 to minimize capacitive losses to substrate. As seen in Figure

4.54, the signal pads are implemented using the 20.5 J.Lm thick nickel-gold layer which is

anchored to the substrate by a platinum-chrome layer, two nitride layers with total

thickness of 0.7 Jlm, and the 2 Jlm thick isolation oxide. The theoretical pad resistance is

given by:

sA C pad =- (Equation 4.8)

x

where A is the area of the signal pad, i.e. 70 x 70 J.Lm2, and x is the thickness of the ni tri de

and oxide layers, which amounts to 2.7 J.Lm. The calculated value of Cpad is 0.055 pF. The

above calculation does not take into account the fringing field capacitance of the signal

pad which results in the actual value of the capacitance being larger. In [69] it was shown

that removing the substrate from under the signal pads can increase the Q from 3.5 to 182

at 1 GHz and to 119 at 2 GHz.

0.7

Figure 4.54: The cross sectional view of the RF pad in Metal-MUMPS.

68

Chapter 5: Measurement Results

5 Measurement Results

The packaged power amplifier module is tested by means of a printed circuit board, PCB.

The MEMS capacitors are tested separately to determine their capacitances and tuning

ranges. The measurement results are presented in this chapter and are compared with the

previously obtained simulation results.

5.1 The Test Setup

The picture of the manufactured power amplifier die is shown in Figure 5.55. Initially,

the die is mounted on a 44-pin gold-plated Ceramic Quad Flat Package, CQFP, with a

0.56 x 0.56 cm2 cavity. The placement of the die in the package is shown in Figure

5.56(a). The placement is such that the critical RF paths are minimized as much as

possible.

69


Figure 5.56: {a) The PA die placement in the package, (b) The top view of the PCB containing the stand-alone PA.

A printed circuit board, PCB, is designed to test the packaged PA employing off-chip

matching networks. In the PCB layout severa} issues are taken into account to minimize

the parasitic losses as much as possible. The lengths of the PCB traces carrying RF

signais, whether input or output, and the RF ground should be minimized. The use of a

bottom ground plane ensures the minimization of the RF flux loop area, and thus the

parasitic inductances. Also, a separate PCB trace is allocated to each RF ground pin,

which reduces the effect of ground bounce [87], [88]. For the off-chip components that

are in the input/output paths, small footprints are used to minimize the parasitics. By

simulating the coplanar structure of the PCB traces in ADS, the width of the PCB routing

paths are set to 0.508 mm, 20.0 mils, with 0.305 mm, 12.0 mils, of clearance to achieve

50 n lines. Wide traces have lower inductance per length and are especially suitable for

lines that carry large currents since the heat dissipation is more easily achieved [89], [90].

End launch gold-plated SMA connectors are used for RF input and output; these SMAs

have lower loss and better voltage standing-wave ratio, VSWR, at RF frequencies

compared with vertical and horizontal SMAs (Figure 5.56(b)).

70

•


5.2 Stand-alone Power Amplifier Testing

The PCB with the packaged power amplifier die is tested for DC characteristics. The

testing includes measuring the DC voltage at the accessible nodes, as well as the DC

current flowing through the biasing network and the main PA core. Once the correct DC

behavior is established, the RF characteristics of the PA are measured using the Agitent

8753D 60Hz Vector Network Analyzer, VNA. Initially, the input and output matching

networks are shorted in order to obtain the behavior of the PA core along with the

bondwires, the package, and the PCB traces. The measured input reflection coefficient,

Su, and the gain, S21, for the un-matched PA are presented in Figure 5.57.

10

0 --...... ...... èïi -10 .._.. ca "0

-20

0

1.62 GHz -24.4 dB

2 3

freq, GHz

4 5

40~----------------------~--------------~

20

--...... 0 N' .._.. (/) ar -2o "0

-40

-60-t--,--,---,---,--t-,----rl

0

1.48 GHz -29 dB

2 3

freq, GHz

4 5

Figure 5.57: The measured 811 and 5 21 for the un-matched stand-alone PA.

71

~ ..


The corresponding Su and S21 obtained by simulating the stand-alone PA are presented

in Figure 5.58. According to the simulation, the gain is expected to drop to zero at 910

MHz. The simulation also predicts a gain of 4.3 dB at 630 MHz. The measured results

show that the gain drops to zero at 660 MHz and the gain at 630 MHz is 0.92 dB. In both

cases, the Sn and S21 responses show a dip. The simulation predicts the Sn dip at 1.49

GHz and the measured response shows the dip at 1.62 GHz. Similarly, the S21 is

predicted to have its lowest value at 1.8 GHz while the actual circuits exhibits the notch

at 1.5 GHz. So, even though the numerical values do not fully agree, the shapes of the

simulated and measured responses are similar. Referring back to Figure 5.57, at

frequencies above 660 MHz, as seen in chapter 3, the losses associated with the

bondwires, the package, and the PCB traces become so high that they reduce the gain to a

great extent.

,.. ,..

.... M

-f8 -

t

.. , .... f

f 1

_, J., L ~····, ..

10

~St

"li)

-20

->•

--•ht

-~ec

630MHz -1.45 dB

'"···-,--~ .. _./_ ·1'!---.........

11 630MHz 4.3 dB

'"""""' .. .,._

1.49 GHz -2.3 dB

1.88 GHz -38 dB

1.8 GHz -62 dB

.,

'"' '"'"

Figure 5.58: 5imulated 511 and 8 21 for the un-matched stand-alone PA.

72

/~


In the next step, the S-parameters of the input-matched PA are measured and imported

into the ADS and load-pull simulations are performed to determine the optimum load for

maximum power transfer. The optimum load is determined to be 1.4- j 13.5 Q. Based on

the fact that the output impedance of the input-matched PAis 0.1 + j 15.5 Q; according to

the general matching equations of section 2.3.1, the output matching network for

maximum output power, consisting of series capacitors and a shunt inductor, is designed.

The measured S 11 and S:u for the input/output matched PA are shown in Figure 5.59. It is

evident that, due to the input conjugate matching and output power matching, the gain

has increased from 0.92 dB at 630 MHz to 9.44 dB at the same frequency. ln other

words, the power matching results in about 8.5 dB increase in output power.

0

-5 ........ ........ ...--...- -10 _.. en _.. co "U

-15

-20

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

freq, GHz

20

0 ........ ........ ...-N - -20 en -co "U

-40

-60 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.

freq, GHz

Figure 5.59: Measured 511 and 821 for the stand-alone PA.

73


Figure 5.60: The MEMS varactors die.

5.3 MEMS Varactors Testing

Figure 5.60 shows a microscopie view of the MEMS varactors die. The fabricated

MEMS varactors are tested on-die using a probe station. Two DC sources are put in

series to achieve actuation voltages up to 35 V. The actuation voltage is applied to the

MEMS deviees through the built-in biasing-tee of the Agilent 8753D 6GHz Vector

Network Analyzer. The DC voltage that the Network Analyzer can tolerate is specified as

40 V. In order to ensure the safety of the test equipment, the maximum applied voltage is

kept at 35 V. Most of the fabricated MEMS structures are single-ended and are tested

using a single GSG probe. Two probes are used to test the differentiai capacitors. Figure

5.61 shows a closer view of one of the MEMS deviees, namely the nominal 1 pF

capacitor with spiral arms.

74


Figure 5.61: The MEMS spiral-arms 1 pF nominal capacitor.

Figure 5.62 compares the impedance characteristics of the spiral-arms 1 pF nominal

capacitor as a function of frequency at actuation conditions of 0 V and 35 V; the obtained

tuning range is 260% at 630 MHz and 355% at 1.8 GHz for this capacitor.

630MHz 5.7pFat35V

1.88 GHz 1.43 pF at 0 V

1.88 GHz 6.5 pF at 35 V

630MHz 1.58 pF at 0 V

freq (SO.OOMHz to 2.000GHz)

Figure 5.62: Capacitance of spiral-arms 1 pF nominal capacitor as a function of frequency at 0 V and 35 V.

75


Capacitance vs. Voltage

7

6 lt.ss GHz l /

5 r -v· ·;

Cl) Il\ CJ 4 c

di630MHz J9 "ëj

[3 Cil r ()

2 ... 1

0

<::> ~ <o "~).. "fo ~ 1' ~ ~1).. ~~)..~ ~~ <t Voltage

Figure 5.63: Capacitance of the spiral-arms 1 pF nominal capacitor as a function of actuation voltages at 630 MHz and 1.88 GHz.

As explained earlier, the varactors exhibit a two-stage tuning behavior (Figure 5.63). At

voltages lower than 25 V, the capacitance increases slowly with increasing actuation

voltages. At voltages between 25 and 32 V, depending on the size of the varactor under

test, a sudden jump in the capacitance is observed. The observed behavior is a direct

consequence of the two-gap structure of the Metal-MUMPs process which is repeated in

Figure 5.64 for convenience. The first tuning is due to the actuation of the metal

structural layer, i.e. C1. When the actuation voltage reaches the pull-in voltage of the

metal-polysilicon gap, the metal collapses on to the polysilicon. However, due to the

presence of the 0.35 ~-tm-thick nitride dielectric layer which is deposited on top of the

polysilicon, a short circuit does not occur. The second tuning is then due to the actuation

of the combined metal-polysilicon layer over the etched substrate, i.e. C2• The pull-in for

this structure occurs at voltages higher than 35 V. However, due to the limitations of the

VNA, the maximum directly-applied DC voltage is kept around 35 V.

76


Figure 5.64: Functional model of the two-plate wide range varactors with tuning steps.

The measurements are done at 1.88 GHz and 630 MHz for four dies. The average results

at 1.88 GHz for wide-tuning range MEMS varactors are summarized in Table 5.7.

Comparing the results based on the plate structure, normal vs. semi-fractal, presents

interesting points. Even though semi fractal plates have higher capacitances under zero

actuation voltages compared with simple plate structures, they exhibit lower capacitances

at higher actuation voltages. This can be due to the un-uniform plate surface that reduces

the effective area when the actuation voltage is applied. Another issue is the arm

structure. It seems that the spiral arm structures (Figure 5.61) have the best elasticity

behavior and therefore yield the best results.

Table 5.7: Measurement results for MEMS varactors at 1.88 GHz.

Nominal Arm Plate Capacitance Capacitance Tuning

Capacitance Structure Structure atOV at35V Range

0.1 pF Spiral Normal 0.69 pF 1.42 pF 102%

0.1 pF Spiral Semi-Fractal 0.67 pF 1.23 pF 81.5%

0.1 pF Straight Normal 0.69 pF 1.59 pF 129%

0.5pF Spiral Normal 1.67 pF 7.7pF 358%

0.5pF Spiral Semi-Fractal 1.6 pF 4.53 pF 181%

0.5pF Straight Normal 1.02 pF 4.02 pF 294%

0.5pF Curved Semi-Fractal 1.14 pF 1.98 pF 71.6%

1 pF Spiral Normal 2.34 pF 11.2 pF 375%

1 pF Spiral Semi-Fractal 2.38 pF 10.8 pF 350%

2 pF Straight Semi-Fractal 3.78 pF 13.87 pF 266%

77


5.4 MEMS-Tunable Power Amplifier Testing

As the last stage of testing, the power amplifier die and the MEMS die are mounted

inside a 68-pin CQFP package with a 1.02 x 1.02 cm2 cavity. Two of the MEMS

capacitors with wide tuning ranges are differentially bonded to the package. The selection

of the MEMS capacitor is done on the PCB by soldering a short circuit path to either of

the capacitors. The overall circuit is initially tested for DC behavior, then the RF

characteristics are measured with the VNA. Similar to the stand-alone PA, the input and

output matching networks are first shorted in order to investigate the behavior of the

packaged power amplifier along with the effect of the PCB traces. The losses associated

with the bondwires and package are expected to be higher for this new setup, due to

severa} factors. First, the package pins, unlike the 44-pin package, are aluminum and not

/.-.., gold-plated. Second, due to the larger size of the cavity, the bondwires are also longer.

78


Even though care has been taken to keep the critical paths such as the RF grounds and RF

input to minimum, the RF output is much longer than ideal due to the geometry and the

position of the dies inside the package. Moreover, the low Q-factor of the MEMS deviees

also contributes to the output tosses. The measured Sn and S2z characteristics of the un

matched MEMS-tunable PA are given in Figure 5.66. As expected, the S21 under the un

matched condition is lower than that of the stand-alone PA, -8.9 dB vs. 0.92 dB at 630

MHz. Also, no gain at any frequency is seen.

--...... ...... -- -10 en --al "'C

-15

-10

~ -15 ...... ~ -20 en --al "'C -25

-30

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.

freq, GHz

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

fre , GHz

Figure 5.66: The measured 5 11 and 5 21 for the un-matched MEM5-tunable PA.

79

~ i '


After conjugate-matching the input, the output impedance is found to be 94.7 + j14.8 n.

Load-pull simulations are performed to determine the optimum load for maximum output

power to be 110 - j 17.5 .Q. Matching the output impedance to the optimum load through

a T -network, the S 21 of the full y matched PA is found to be -11.5 dB at 630 MHz as seen

in Figure 5.67; the power amplifier still exhibits no gain over the frequency spectrum.

The main reason for absence of gain is the lasses incurred in the RF output path. The

main contributing factors to which are the long bondwires (as evident from Figure 5.65),

the lassy package pins, and the low Q-factor of the MEMS deviees. Currently, work is

being done to optimize the PCB mainly through on-board bonding to minimize the

effects of package losses and reduce the lengths of the bondwires, which due to time

constraints are not included in this thesis.

-2

:::::::::: -4 ...... :s -6 Cl)

m "C -8

-10

-10

--...... -20 ~ Cl) m -3o "C

-40

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

freq, GHz

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

fre , GHz Figure 5.67: The measured S11 and S21 for the matched MEMS-tunable PAs.

80

Chapter 6: Conclusion

6 Conclusion

6.1 Summary

The growing demand for wireless communication systems IS demanding increased

integration, better signal quality, and longer battery life. The power amplifier consumes

the most power in the whole receiver/transmitter system, and its output signal is directly

transmitted by the antenna without further modification. Th us, optimizing the PA for

lower power consumption, increased linearity and integration is highly desired. One way

to ac hi eve this objective is to actively vary the output matching network of the PA for

maximum output power, as the input RF drive or the output load conditions vary. MEMS

variable capacitors were designed to be used as part of an active matching network. The

major effort of the thesis was focused on the design of MEMS tunable class AB power

amplifier in the SiGe BiCMOS 5HP technology, and the designed implementation of

MEMS variable capacitors in the Metal-MUMPS process.

In chapter 1, the motivations and objectives for power amplifiers design, in general, and

tunable PAs, in particular, for RF applications were introduced. Chapter 2 dealt with the

power amplifier operation principles, the methods of characterizing and quantifying the

PA performance, and the classification of power amplifiers based on their modes of

operations with special attention to class AB operation. Design techniques specifie to

81


high power amplifiers including large-signal S-parameters, power matching (as opposed

to conjugate match), and the load-pull technique were also addressed in detail.

Chapter 3 was dedicated to the design of the SiGe BiCMOS power amplifier. The issues

regarding the design of the power core, biasing circuitry, input and output matching

networks, and power splitting/combining were addressed. The load-pull technique was

employed to determine the output matching network for maximum output power. In this

chapter, empirical models were developed for parasitic losses resulting in the PCB paths,

the package pins, and the bond-wires.

In chapter 4 MEMS variable capacitors for RF applications were designed. MEMS

tunable capacitors operating principles and different varactor structures were

investigated. Very-wide tuning range tunable capacitors were designed taking advantage

of the two structural layers offered in the Metal-MUMPS process. The measurement

results for the fabricated varactors were given in chapter 5, where it was shown that the

capacitors covered a frequency range from DC to 6 GHz, with tuning ranges as high as

375%.

Chapter 5 summarized the measurement results for the stand-alone power amplifier and

the MEMS-tunable power amplifiers. In the first case, the packaged, input/output

matched PA exhibits a gain of 9.44 dB at 630 MHz. It was shown that the gain at higher

frequencies is low due to the parasitic losses of the bond-wires, the package pins, and the

PCB tracks.

6.2 Topics for Future Research

The idea of actively tuning the matching network of a power amplifier by means of

MEMS variable capacitors for better efficiency and output power was explored in this

thesis. MEMS capacitors have the potential of offering greater degree of integration as

well as better performance, reduced power consumption and better linearity, for the

design of power amplifiers. This thesis highlighted the areas that needed further research

82


in order to attain the specified goals, as weil as ether areas that can benefit from the

integration with MEMS.

a) In order for a power amplifier design to be of any practical use, it should be fully

packaged. This leads to the issue of characterizing and developing accurate models for

the packages. In practice, the losses incurred due to the package and bond-wires can have

devastating effects on the performance of the circuit, and thus have to be taken into

account from the very early stages of design.

b) In this thesis, the emphasis was on class AB power amplifier and its tunability, since it

offers the best tradeoff between linearity and efficiency. However, switched-mode power

amplifiers, such as class E and class F, can also be good candidates for integration with

MEMS. One area where MEMS can be used is for the output resonant tank, which is

cri ti cal to the operation of the se PAs. The resonant tanks are conventionally implemented

as LC networks which are either on-chip, thus having lower parasitics but generally

invariable, or are off-chip, hence suffering from large degrees of parasitic losses in favor

of being tunable. These tanks can be replaced by in-package high-Q MEMS resonators

such as the ones designed in [3] and [4].

c) In this thesis micro-electromechanical variable capacitors with very wide tuning ranges

were implemented successfully. However, the designs were based on first order

simplified equations of the spring constants, pull-in voltages ... ect. If simulation models

are developed and are available for a given MEMS technology, the potential of the

technology can be explored to a fuller extend, and even better structures can be designed

and fabricated.

83

Chapter 7: References

7 References

[1] Cripps, S.C., RF Power Amplifiers for Wireless Communications, Artech House, 1999

[2] Sokal, N.O., "RF power amplifiers, classes A through S - How they operate, and wh en to use each", Professional Pro gram Proceedings of Electronics Industries Forum ofNew England, May1997, pp. 179-252

[3] Clark, J.R.; Bannon, F.D.; Ark-Chew Wong; Nguyen, C.T.-C., "Parallel-resonator HF micromechanical bandpass filters", IEEE International Conference on Solid State Sensors and Actuators, Vol. 2, June 1997, pp. 1161 - 1164

[4] Kun Wang: Ark-Chew Wong; Nguyen, C.T.-C., "VHF free-free bearn high-Q micromechanical resonators", Journal of Microelectromechanical Systems, Vol. 9, No. 3, Sept. 2000, pp. 347-360

[5] Kipnis, I., "Refining CDMA mobile-phone power control", Microwaves and RF, Vol. 39, No. 6, June 2000, pp. 71 -76

[6] Fowler, T.; Burger, K.; Cheng, N.-S.; Samelis, A.; Enobakhare, E.; Rohlfing, S., "Efficiency improvement techniques at low power levels for linear CDMA and WCDMA power amplifiers", IEEE Radio Frequency Integrated Circuits

Symposium, June 2002, pp. 41 - 44

[7] Raab, F.H.; Asbeck, P.; Cripps, S.C.; Kenington, P.B.; Popovic, Z.B.; Pothecary, N.; Sevie, J.F.; Sokal, N.O., "RF and microwave power amplifier and transmitter technologies- part 5", High Frequency Electronics, January 2004, pp. 46-54

84


[8] Leuzzi, G. and Micheli, C., "Variable-load constant efficiency power amplifier for

mobile communications applications", 33rd European Microwave Conference, Vol.

1, Oct. 2003, pp.375- 377

[9] Tu, S.H.L., "A power-adaptive CMOS classE RF tuned power amplifier for wireless

communications", IEEE International Proceedings on SOC [Systems-on-Chip} Conference, Sept. 2003, pp. 365 - 368

[10] Raab, F.H., "Electronically tunable class-E power amplifier", IEEE MFT-S

International Microwave Symposium Digest, Vol.3, May 2001, pp.1513- 1516

[11] Neo, W.C.E.; Liu, X.; Lin, Y.; de Vreede, L.C.N.; Larson, L.E.; Spirito, S.;

Akhnoukh, A.; de Graauw, A.; Nanver, L.K., "Improved hybrid SiGe HBT class-AB

power amplifier efficiency using varactor-based tunable matching networks", IEEE

Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Oct. 2005,

pp. 108- 111

[12] Coder, A.C. and Brown, E.R., "The feasibility of a variable output matching circuit in a high-power SSPA", IEEE Radio and Wireless Conference, Aug. 2002, pp. 189-

191

[13] Tu, S.H.-L. and Toumazou, C., "Design of highly-efficient power-controllable

CMOS class E RF power amplifiers", Proceeding of the I999 IEEE International Symposium on Circuits and Systems (ISCAS '99), Vol. 2, May- June 1999, pp. 602

-605

[14] Qiao, D.; Molfino, R.; Lardizabal, S.M.; Pillans, B.; Asbeck, P.M.; Jerinic, G., "An

Intelligently Controlled RF Power Amplifier With a Reconfigurable MEMSVaractor Tuner", IEEE Transactions on Microwave Theory and Techniques, ,Vol. 53, No. 3, March 2005, pp.1089 -1095

[15] Raab, F.H.; Asbeck, P.; Cripps, S.C.; Kenington, P.B.; Popovic, Z.B.; Pothecary, N.;

Sevie, J.F.; Sokal, N.O., "Power amplifiers and transmitters for RF and microwave",

IEEE Transactions on Microwave Theory and Techniques, Vol. 50, Issue 3, March

2002, pp. 814 - 826


Sevie, J.F.; Sokal, N.O., "RF and microwave power amplifier and transmitter technologies- partI", High Frequency Electronics, May 2003, pp. 22-36

[17] Pozar, D.M., Microwave Engineering, Wiley, 2005


Sevie, J.F.; Sokal, N.O., "RF and microwave power amplifier and transmitter

technologies- part 2", High Frequency Electronics, May 2003

85


[19] Duclercq, J., "GSM base station power amplifier module linearity", Microwave Journal, Vol. 42, No. 4, April1999, pp. 116- 127

[20] Gonzalez, G., Microwave Transistor Amplifiers: Analysis and Design, Prentice Hall, 1997

[21] van der Heijden, M.P.; Spirito, M.; Pelk, M.; de Vreede, L.C.N.; Burghartz, J.N., "On the optimum biasing and input out-of-band terminations of linear and power efficient class-AB bipolar RF amplifiers", Proceedings of the 2004 Meeting of

Bipolar/BiCMOS Circuits and Technology, Sept. 2004, pp. 44 - 4 7

[22] Larson, L.; Asbeck, P.; Hanington, G.; Chen, E.; Jayamaran, A.; Langridge, R.; Xuejun Zhang, "Deviee and circuit approaches for improved wireless communications transmitters", IEEE Persona! Communications, Vol. 6, No. 5, Oct.1999, pp. 18-23

[23] ITS Electronics Inc., "Multiband linear power amplifiers", Microwave Journal, Vol. 41, No. 10, Oct. 1998, pp. 154- 158

[24] Ortega-Gonzalez, F.J., "High efficiency power amplifier driving methods and circuits: Part 1", Microwave Journal, Vol. 47, No. 4, April2004, pp. 22-38

[25] Kushner, L.J., "Output performance of idealized microwave power ampli fiers", Microwave Journal, Vol. 32, No. 10, Oct. 1989, pp. 103- 116

[26] Paidi, V.; Xie, S.; Coffie, R.; Moran, B.; Heikman, S.; Keller, S; Chini, A.; DenBaars, S.P.; Mishra, U.K.; Long, S.; Rodwell, M.J.W., "High linearity and high efficiency of class-B power amplifiers in GaN HEMT technology", IEEE

Transactions on Microwave Theory and Techniques, Vol. 51, No. 2, Feb. 2003, pp. 643-652

[27] Raab, F .H., "Class-E, class-C, and class-F power amplifiers based upon a finite number of harmonies", IEEE Transactions on Microwave Theory and Techniques,

Vol. 49, No. 8, Aug. 2001, pp. 1462- 1468

[28] Sowlati, T.; Salama, A.T.; Stich, J.; Rabjohn, G.; Smith, D., "Low-voltage, high efficiency GaAs class E power amplifiers for wireless transmitters", IEEE Journal of Solid-State Circuits, Vol. 30, No. 10, Oct. 1995, pp. 1074- 1080

[29] Sowlati, T.; Greshishchev, Y.; Salama, A.T.; Rabjohn, G.; Stich, J., "Linear Transmitter design using high efficiency class E power amplifier ", IEEE

International Symposium on Persona!, Indoor and Mobile Radio Communications,

Vol. 3, Sept.l995, pp. 1233- 1237

86


[30] Grebennikov, A. V., "Circuit design technique fro high efficiency class F amplifiers", IEEE MTT-S International Microwave Symposium Digest, Vol. 2, June 2000, pp. 771 -774

[31] Sokal, N.O., "Class-E RF power amplifiers", QEX, Jan.- Feb. 2001, Pp. 9-20

[32] Sokal, N.O., "Class E high-efficiency power amplifiers, from HF to microwave", IEEE MMT-S International Microwave Symposium Digest, Vol. 2, June 1998, pp. 1109- 1112

[33] Sokal, N.O. and Sokal A.D., "ClassE- a new class ofhigh-efficiency tuned singleended switching power amplifiers", IEEE Journal of Solid-State Circuits, Vol. 10, No. 3, June 1975, pp. 168-176

[34] Cripps, S.C., Advanced Techniques in RF Power Amplifier Design, Artech House, 2002

[35] Grillo, G. and Cristaudo, D., "Adaptive biasing for UMTS power amplifiers", Proceedings of the 2004 Meeting of Bipolar/BiCMOS Circuits and Technology, Sept. 2004, pp. 188- 191

[36] Larson, L.E., RF and Microwave Circuit Design for Wireless Communications, Artech House, 1996

[37] Zhang, X.; Saycocie, C.; Munro, S.; Henderson, G., "A SiGe HBT power amplifier with 40% PAE for PCS CDMA applications", IEEE MMT-S International

Microwave Symposium Digest, June 2000, pp. 857- 860

[38] Webb, J., EM Transmission and Radiation (course notes), McGill University

[39] Cripps, S.C., "A theory for the prediction of GaAs FET load-pull power contours", MTT-S International Microwave Symposium Digest, Vol. 83, No. 1, May 1983, pp. 221-223

[40] Geis, L.A. and Dunleavy, L.P., "Power contour plots using linear simulators", Microwave Journal, Vol. 39, No. 6, June 1996, pp. 60-70

[41] Nellis, K. and Zampardi, P., "A comparison of bipolar technologies for linear handset power amplifier applications", Proceedings of the Bipolar/BiCMOS Circuits

and Technology Meeting, Sept. 2003, pp. 3 - 6

[42] Nellis, K. and Zampardi, P.J., "A comparison of linear handset power amplifiers in different bipolar technologies", IEEE Journal of Solid-State Circuits, Vol. 39, Issue 10, Oct. 2004, pp. 1746- 1754

87


[43] Moniz, J.M., "Is SiGe the future of GaAs for RF applications?", ]9th annual

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1997, 12-15 Oct. 1997,

pp. 229-231

[44] Ali, F.; Gupta, A.; Higgins, A., "Advances in GaAs HBT power amplifiers for

cellular phones and military applications", Digest of Microwave and Millimeterwave Monolithic Circuits Symposium, June 1996, pp. 61 - 66

[45] Beckmann, S.; Sommet, R.; Nebus, J.-M.; Jacquet, J.-C.; Floriot, D.; Auxemery, P.;

Quere, R., "Characterization and modeling of bias dependent breakdown and self

heating in GalnP/GaAs power HBT to improve high power amplifier design", IEEE

Transactions on Microwave Theory and Techniques, Vol. 50, No. 12, Dec. 2002, pp.

2811-2819

[46] Halchin, D. and Golio, M., "Trends for portable wireless applications", Microwave Journal, Vol. 40, No. 1, Jan. 1997, pp. 62-78

[47] Johnson, J.B.; Joseph, A.J.; Sheridan, D.C.; Maladi, R.M.; Brandt, P.-O.; Persson, J.; Andersson, J.; Bjorneklett, A.; Persson, U.; Abasi, F.; Tilly, L., "Silicon-Germanium

BiCMOS HBT technology for wireless power amplifier applications", IEEE Journal ofSolid-State Circuits, Vol. 39, No. 10, Oct. 2004, pp. 1605- 1614

[48] Johnson, J.B.; Joseph, A.J.; Sheridan, D.C.; Maladi, R.M., "SiGe BiCMOS

technologies for power amplifier applications", IEEE 251h Annual Technical Digest,

Gallium Arsenide Integrated Circuits (GaAs IC) Symposium, 2003, pp. 179 - 182

[49] Krauss, H.L., Bostian, C.W., and Raab, F.H., Solid State Radio Engineering, Wiley,

1980

[50] Pusl, J.; Sridharan, S.; Antognetti, P.; Helms, D.; Nigam, A.; Griffiths, J.; Louie, K.; Doherty, M., "SiGe power amplifier ICs with SWR protection for handset

applications", Microwave Journal, Vol. 44, No. 6, June 2001, pp. 100- 13

[51] Lee, T.H., Planar Microwave Engineering: a Practical Guide to Theory, Measurement, and Circuits, Cambridge University Press, 2004

[52] El-Gamal, M. N., RF Microelectronics (Course notes), McGill University

[53] "SpectreRF User Guide", Cadence Design Systems,, Version 5.0, June 2003

[54] Dye, N. and Granberg, H., Radio Frequency Transistors: Princip/es and Practical

Applications, Butterworth-Heinemann, 1993

[55] Kazimierczuk, M. and Sokal, N.O., "Cause of instability of power amplifier with

parallel-connected power transistors", IEEE Journal ofSolid-State Circuits, Vol. 19,

No. 4, Aug. 1984, pp. 541-542

88


[56] Allison, R., "Silicon Bipolar Microwave Power Transistors", IEEE Transactions on Microwave Theory and Techniques, Vol. 27, No. 5, May 1979, pp. 415-422

[57] Ming-Dou Ker and Bing-Jye Kuo, "ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme", IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 6-8 June 2004, pp. 383-386

[58] Ma, Y. and Li, G.P., "InGaP/GaAs HBT RF power amplifier with compact ESD protection circuit", IEEE MTT-S International Microwave Symposium Digest, Vol. 2, June 2004, pp. 1173 - 1176

[59] "SiGeHP (BiCMOS 5HP) Design Manual", SiGe Technology Development, IBM Microelectronics Division, May 2001

[60] Mansour, R.R.; Bakri-Kassem, M.; Daneshmand, M.; Messiha, N., "RF MEMS Deviees", Proceedings of International Conference on MEMS, NANO, and Smart Systems, July 2003, pp. 103 - 107

[61] Bouchaud, J. and Wicht, H., "RF MEMS: Statues of the Industry and Roadmaps", IEEE Radio Frequency Integrated Circuits Symposium, June 2005, pp. 379-384

[62] Dec, A. and Suyama, K., "Micromachined Electro-Mechanically Tunable Capacitors and Their Applications to RF IC's", IEEE Transactions on Microwave Theory and Techniques, Vol. 46, No. 12, Dec. 1998, pp. 2587-2596

[63] Dussopt, L. and Rebeiz G.M., "Intermodulation distortion and power handling in RF MEMS switches, varactors, and tunable filters", IEEE Transactions on Microwave Theory and Techniques, Vol. 51, No. 4, April2003, pp. 1247- 1

[64] Tilmans, H.A.; De Raedt, W.; Beyne, E., "MEMS for Wireless Communications: 'From RF-MEMS components to RF-MEMS-SiP'", Journal of Micromechanics and Microengineering, No. 13, 2003,pp. 139- 163

[65] Ionis, G.V.; Dec, A.; Suyama, K., "A zipper-action differentiai micro-mechanical tunable capacitor", Microelectromechanical Systems Conference, Aug. 2001, pp. 29 -32

[66] Yoon, J. and Nguyen, T.C., "A high-Q tunable micromechanical capacitor with movable dielectric for RF applications", Electron Deviees Meeting, Dec. 2000, pp. 489-492

[67] Park, J.Y.; Yee, Y.J.; Nam, H.J.; Bu, J.U., "Micromachined RF MEMS Tunable Capacitors Using Piezoelectric Actuators", Microwave Symposium Digest, May 2001, pp. 2111-2114

89


[68] Dec, A. and Suyama, K., "A 1.9 GHz micromachined-based low-phase-noise CMOS

VCO", ISSCC Digest Technical Papers, February 1999, pp. 80-81

[69] Nieminen, H.; Ermolov, V.; Nybergh, K.; Silanto, S.; Ryhanen, "Microelectromechanical Capacitors for RF Applications", Journal Micromechanics and Microengineering, No. 12, 2002, pp. 177 - 186

T., of

[70] Zou, J.; Liu, C.; Schutt-Aine, J.E.; Chen, J.; Kang, S., "Development of a wide tuning range MEMS tunable capacitor for wireless communication systems", Electron Deviees Meeting, 2000, pp. 403 - 406

[71] Chen, J.; Zou, J.; Liu, C.; Schutt-Aine, J.E.; Kang, S., "Design and modeling of a

micromachined high-Q tunable capacitor with large tuning range and a vertical

planar spiral inductor", IEEE Transactions on Electron Deviees, Vol. 50, No. 3,

March 2003, pp. 730-739

[72] Tsang, T.K. and El-Gamal, M.N., "Very wide tuning range micro-electromechanical capacitors in the MUMPs process for RF applications", IEEE Symposium on VLSI Circuits, June 2003, pp. 33 - 36

[73] Tsang, T.K. and El-Gamal, M.N., "Micro-electromechanical variable capacitors for RF applications", 451

h Midwest Symposium on Circuits and Systems, Vol. 1, Aug.

2002, pp. 25 - 28

[74] Wong, W.M.Y.; Ping Shing Hui; Zhiheng Chen; Keqiang Shen; Lau, J.; Chan,

P.C.H.; Ping-Keung Ko, "A wide tuning range gated varactor," IEEE Journal of

Solid-State Circuits, May 2000, pp. 773 - 779

[75] Varadan, V.K.; Vinoy, K.J.; Jose, K.A., RF MEMS and their applications, Wiley,2003

[76] Rebeiz, G.M., RF MEMS: theory, design, and technology, Wiley, 2003

[77] De Los Santos, H., RF MEMS circuit design for wireless communications, Artech

House, 2002

[78] Yao, J.J., "RF MEMS from a Deviee Perspective", Journal of Micromechanics and Microengineering, Vol. 10, No. 4, Dec. 2000, pp. R9- R38

[79] Borwick, R. L.; Stupar, P. A.; DeNatale, J.; Anderson, R.; Tsai, C.; Garrett, K., "A high-Q, large tuning range, tunable capacitor for RF applications," ]5th IEEE MEMS International Conference, Jan. 20-24, 2002, pp. 669- 672

[80] Borwick, R. L.; Stupar, P. A.; DeNatale, J.; Anderson, R.; Erlandson, R., "Variable

MEMS capacitors implemented into RF filter systems," IEEE Transactions on

Microwave Theory and Techniques, Vol. 51, Jan. 2003, pp. 315-319

90


[81] Samavati, H.; Hajimiri, A.; Shahani, A.R.; Nasserbakht, G.N.; Lee, T.H., "Fractal capacitors", IEEE Journal ofSolid-State Circuits, Vol. 33, No. 12, Dec. 1998, pp. 2035-2041

[82] Seok, S.; Choi, W.; Chun, K., "A Novel Linearly Tunable MEMS Variable Capacitor", Journal of Micromechanics and Microengineering, Vol. 12, No. 1, Jan. 2002, pp. 82 - 86

[83] Cowen, A.; Mahadevan, R.; Johnson, S.; Hardy, B., "MetalMUMPs Design Handbook, Revision 2.0", MEMScAP Inc.

[84] Sun, Y.; Van Zejl, H.; Tauritz, J.L.; Baets, R.G.F., "Suspended membrane inductors and capacitors for application in silicon MMIC's", Microwave and Millimeter-wave Monolithic Circuits Symposium, June 1996, pp. 99 - 102

[85] Bakri-Kassem, M. and Mansour, R.R., "Two Movable-Plate Nitride-Loaded MEMS Variable Capacitor", IEEE Transactions on Microwave Theory and Techniques, Vol. 52, No. 3, March 2004, pp. 831-837

[86] Dec, A. and Suyama, K., "Microwave MEMS-based voltage-controlled oscillators", IEEE Transactions on Microwave Theory and Techniques, Vol. 48, No. 11, Nov. 2000, pp. 1943 - 1949

[87] Montrose, M.l., EMC and the printed circuit board: design, theory, and layout made simple, New York, IEEE Press, 1999

[88] German, R.F.; Ott, H.W.; Paul, C.R., "Effect of an Image Plane on Printed Circuit Board Radiation", IEEE International Symposium on Electromagnetic Compatability, August 1990, pp. 284-291

[89] Sadiku, M.N.O.; Musa, S.M.; Sudrashan, R.N., "Comparison of Dispersion Formulas for Microstrip Lines", IEEE Southeast Conf Proceedings, March 2004, pp. 378-382

[90] Robertson, C.T., Printed circuit board designer 's reference: basics, Upper Saddle River, NJ. Prentice Hall Professional Technical Reference, 2004

91

AppendixA

Appendix A: ADS Model Fitting

In this thesis, model fitting simulations in ADS are used to develop empirical models for

chip the package pins, the bondwires, and the PCB traces. The deviee under test is

characterized by means of a vector network analyzer (VNA), and the measured data are

imported into ADS as a black box with a given number of input and output ports. Next

step is to create a rough RLC model of the deviee under test based on its know behavior.

Each R, L, and C elements are assigned a variable, which is defined to have a certain

initial value within a practical range (Figure A.68).

The measurement equation is defined as:

dmSll = (abs(S(l,l))- S((2,2)))) (Equation A.l ),

where S(l, 1) is the one-port S-parameter corresponding to the RLC network and S(2,2) is

the experimental S-parameters corresponding to the actual deviee. The Goal of the

simulation (Figure A.69) is to set this difference to zero. In other words, the aim is to

vary the value of the RLC network components until the two sets of S-parameters are

matched as much as possible.

92

, L,

, L5û ,

. L-t..w.nH .

. R,

L=LinH R• .

R37'

AppendixA

· File="E:\Pbwér ,IX.mpli1ief'IPA mèasLirm'ent"reSultSI.oct19lpaCkaQe.S1 p"

: b oiuiW.ir:es 'L' 'L' A · L:'l · L51 f't36' . l=A nH . . L-t..w.nH. R=Rw Ohm . R, . Rë

Figure A.68: The black box and the empirical RLC model for characterizing the package pin, the bondwires and the PCB traces.

~IIAR ~-··.

test7 'Lt='0.827 {o} · 'Ct=0219{o} · ·Rt=0.315 {o} . .Lw;:::8 524!3-4 .{o}. Rw=0.321 {o} cp~O 1.69 {o} 'Lp=0458 {o} · · rp=6 .3 · { o} ·

. . . . . . . . . .

1 @.1 : S•PA~A~·E"FÊR$;·>11 .. : 1 ..... !!< _.'? .. :-PA .. '. L .. ·.i.._ .. · 1 . Zir.1 SP1

. Zit:~1

. Zin1=zin(S11..PortZ1)

start=·so ~~Hz . Stop='2 GHz. · Step=20 MHz

l"t~·j M_easEqn Meas1

· dr'nS11 = (abs((S(1 ;1)-8(2;2)))')

OptimG0a1·1 Expr="dmS11" SimlnstMceName="SP 1" Min: · Max=O. Weight=1 RangeVar[1]= RangeMin[1]= · RangeMax[1]=·

Figure A.69: The simulation setup for the model fitting scheme.

93

Documents

RF Power Amplifiers and MEMS Varactors - McGill …digitool.library.mcgill.ca/thesisfile112576.pdf · Cette thèse est concernée par la conception et l'exécution des amplificateurs