RF Design Environment Release Notesliterature.cdn.keysight.com/litweb/pdf/rfde2008update2/... · 2008-09-10 · A Note About Updates and MSR’s 5 RFDE 2008 Update 2 Release Notes

RF Design Environment Release Notes

August 2008

Notice

The information contained in this document is subject to change without notice.

Agilent Technologies makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Agilent Technologies shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material.

Warranty

A copy of the specific warranty terms that apply to this software product is available upon request from your Agilent Technologies representative.

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© Agilent Technologies, Inc. 1983-2008. 5301 Stevens Creek Blvd., Santa Clara, CA 95052 U.S.A.

Acknowledgments

Mentor Graphics is a trademark of Mentor Graphics Corporation in the U.S. and other countries.

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MATLAB® is a U.S. registered trademark of The Math Works, Inc.

ii

ContentsRFDE 2008 Update 2 Release NotesA Note About Updates and MSR’s ........................................................................... 5Data Display ............................................................................................................. 6

DFTool ................................................................................................................ 7Analog/RF Simulation............................................................................................... 7

Nonlinear Devices .............................................................................................. 9User-Compiled Models ....................................................................................... 9Verilog-A............................................................................................................. 10

Agilent Ptolemy Simulation....................................................................................... 12Examples.................................................................................................................. 13Momentum Virtuoso ................................................................................................. 15Connection Manager ................................................................................................ 15Printing/Plotting ........................................................................................................ 15Documentation Search ............................................................................................. 16Documentation/Online Help...................................................................................... 17Others....................................................................................................................... 18

Index

iii

iv

RFDE 2008 Update 2 Release Notes

RFDE 2008 Update 2 Release NotesThis document describes new features, functionality and known defects in RF Design Environment 2008 and wherever possible, provides a workaround. It also identifies errors and omissions in the documentation. The following table shows the version history for this document.

For more information concerning known issues in RF Design Environment 2008, or to report a new issue, refer to the Agilent EEsof Knowledge Center at:

https://edasupportweb.soco.agilent.com/portal/page?_pageid=36,41037&_dad=portal&_schema=PORTAL&ref=eesof_main2

A Note About Updates and MSR’sUpdate releases provide specific new features plus all the defect repairs normally found in a Maintenance Software Release (MSR). Since the Update release contains all the defect repairs of the MSR, MSRs will no longer be available.

General Information

Manuals that were updated for RFDE 2008 are dated January 2008, manuals updated for RFDE 2008 Update 1 are dated May 2008, and manuals updated for RFDE Update 2 are dated August 2008. Manuals that were not updated for RFDE 2008 are dated May 2007.

RFDE requires codewords to run. If you haven't got codewords you can request a codewords at:

http://eesof.tm.agilent.com/forms/codereqform.html

To install RFDE 2008, please refer to the RFDE 2008 Installation Manual.

Version Date Revised/New Issue Title

Initial Release January 2008

Update 1 May 2008 New “What’s New in RFDE 2008A Update 1”

New “RFDE remote simulation”

Update 2 August 2008 New “What’s New in RFDE 2008A Update 2”

A Note About Updates and MSR’s 5


What’s New in RFDE 2008A

RFDE Momentum has added a new easier to use graphical Substrate Editor for the 2008 release.

What’s New in RFDE 2008A Update 1

EDA00193968 - RFDE and Dynamic Link 2008 Update 1 will work with Cadence IC 6.1.2 in addition to IC 6.1.1, IC 6.1.0, and IC 5.1.41USR5 CDB. Note that IC 5.1.41 OpenAccess is no longer supported.

The same context file $HPEESOF_DIR/idf/skill/6.1.0/ads.cxt, which is built in IC 6.1.0, will be used when running RFDE and Dynamic Link 2008 Update 1 in Cadence IC 6.1.2, IC 6.1.1, and IC 6.1.0. As with previous releases, $HPEESOF_DIR/idf/skill/5.1.0/ads.cxt will be used for IC 5.1.41. You should let the code locate and load the correct context file automatically based on the Cadence version in use by loading $HPEESOF_DIR/idf/config/.cdsinit.

What’s New in RFDE 2008A Update 2

For Momentum EM:

• New Substrate Editor

• BroadBand Spice Engine

• Layout simplification through layout pre-processor

• Improved accuracy for structures containing slots and vias

Data Display

The undo operation may require screen refresh

Data Display does not always update the graphics properly after an undo operation.

Workaround: To refresh the screen, choose the Redraw View button in the toolbar.

6 Data Display


DFTool

Writing to a dataset fails using DFTool

DFTool reads, writes and displays dataset files under the <current_cell>/ADSsim/schematic/data directory. The subdirectory data may not exist. Without this subdirectory, the dataset file list will be empty and writing to dataset file fails.

Workaround:

You need to create a subdirectory called “data” under the “schematic” directory.

Analog/RF Simulation

RFDE remote simulation

EDA00193159 − In order to run RFDE remote simulation, you need to make sure that you can run spectre remote simulation from Cadence ADE. It is very likely that your login shell must be csh and you must have your environment set up properly for both Cadence and RFDE in your .cshrc.

AVM Noise Simulation Improvements

Ptolemy/Circuit Envelope co-simulation with AVM: ADS/RFDE 2006A Update Release 2 contains noise simulation improvements, particularly suitable for 1/f noise. Previous model generated too much noise, or required long simulation time. User documentation of the new feature is available in the Knowledge Center (search for “AVM Noise Simulation Improvements”).

TAHB_Enable=Auto in all designs opened in RFDE 2006A regardless of setting in an older version

RFDE 2006A features automatic divider detection. When Transient Analysis Harmonic Balance (TAHB_Enable) is set to Auto, the simulator applies TAHB if it detects the presence of a frequency divider. A limitation prevents RFDE 2006A from using the same setting for TAHB_Enable that was used for designs created in a previous RFDE version. Therefore, all designs opened in RFDE 2006A will have TAHB_Enable=Auto (the default). In a situation where a circuit is not a divider and you want to override the automatic setting so you can use TAHB, manually set

Analog/RF Simulation 7


TAHB_Enable=On. In RFDE, Transient Assisted Harmonic Balance is located in the Options dialog for the HB and Env analyses.

Use analogLib’s port component in place of ADS Term component

The Term component in ADS is used for measuring S-parameters; it is not provided in RFDE because the Cadence analogLib port component has the same functionality. Use the port component in RFDE with a blank source type.

Using pPar with the transmission line substrate parameter

When using RFDE with Cadence version 4.4.6, it is possible to pass certain string values into a subcircuit and use them on a component; however, Cadence version 4.4.5 does not support this. This applies to the Subst parameter on adsLib components such as in the microstrip and multilayer transmission line categories. For this, use the pPar function as described in the Cadence documentation. (Note that the pPar function works with numeric-valued parameters in both versions of Cadence. Also, note that the pPar function cannot be used to pass the model parameter of diodes and transistors.)

Oscillator phase noise pnmx improved and pnfm removed

Oscillator phase noise simulation now only computes pnmx. The pnmx flattening problems present at small offset frequencies have been fixed and pnmx now provides a good phase noise result for all offset frequencies. The pnfm result is no longer computed and existing data display setups from versions prior to ADS 2004A that plot pnfm will show up as <invalid>.

PackFFT parameter in HB simulation

The parameter PackFFT controls the frequency map packing for multitone Harmonic Balance. By default, when it is not explicitly set to ‘yes’ or ‘no’, the simulator enables it (i.e., ‘yes’). Setting PackFFT to ‘yes’ may improve the simulation speed and reduce memory consumption by using a smaller number of time samples (smaller FFTs), but at the potential loss of dynamic range and accuracy due to the aliased harmonics of the first fundamental now possibly landing on various mixing tones. For mixers and other applications with a single large dominant (LO) tone, that frequency should be assigned to the first fundamental and PackFFT should be set to ‘no’ so that any aliased harmonics of this large signal will just land on its own harmonics and not on mixing terms. If you are simulating mixer intermodulation or third-order intercept, it is recommended that this parameter be set to ‘no’ to achieve the most accurate

8 Analog/RF Simulation


results. In ADS, the parameter PackFFT is found on the Display tab of the HB and CE controllers. To set this parameter in ADS, check it on the Display tab and then set it to ‘yes’ or ‘no’ directly on the schematic. In RFDE, PackFFT is found in the Options dialog for the HB and Env analyses.

Nonlinear Devices

SiMKit 2.4 from NXP and PSP version 102.1, including the NQS version, are fully supported

Starting with ADS 2006 Update 1, SiMKit 2.4 from NXP and PSP version 102.1, including the NQS version, are fully supported.

Release 2006A contains SiMKit 2.3.2 device library from NXP (Philips Models)

Starting with 2006A the SiMKit device library from NXP (originally Philips) is included in the standard ADS/RFDE installation. The version contained in 2006A is SiMKit 2.3.2. The library is in the form of a dynamically linked library (dll) and is netlist-based. There is no corresponding UI palette in the UI. For further details and a design kit support for ADS UI please visit the NXP web site at:

http://www.nxp.com/Philips_Models/source_library/

User-Compiled Models

User-compiled models may need recompiling to work in ADS 2006A

You may need to recompile user-compiled models so they work with RFDE 2006A. Here are guidelines to help you decide if recompiling is necessary:

• If you are using a static linked user-compiled model, you must recompile the model source code and create a new static linked executable simulator.

• If you are using a dynamic linked user-compiled model, you must recompile the model source code and create a new dynamic linked library for Linux systems. This is not required for HP-UX and Solaris systems.

• Existing 32-bit shared libraries will not work with 64-bit simulators. For all practical purposes, a 64-bit simulator is a new platform, so all user-compiled



models must be recompiled for use with 64-bit simulators. The converse is also true: 64-bit user-compiled models cannot be used with 32-bit simulators.

Verilog-A

Verilog-A compiled files are version specific

The Verilog-A compiled files (CML files) are compiled when you run the first simulation, or when you run a subsequent simulation containing a modification of an associated Verilog-A source file.

For example:

CML files are version specific. In ADS 2005A version 1.20 is used. To avoid compatibility problems between different versions, these CML files are placed in the 1.20 folder of the cache directory.

For 2004A simulations the CML files are still located in the 1.12 folder of the cache directory. If you use 2004A, the appropriate version of the files will be picked up.

RFDE netlister fails on some RFlib views

The RFDE netlister fails to netlist some RFlib views. Examples include chebyshev_pb and checyshev_lp. These views netlist correctly in Spectre, but fail in RFDE.

More information about this issue may be found by referring to the Agilent EEsof Knowledge Center at:

http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=VerilogA.178

Compilation of large files on HP-UX

Compilation of large files (several thousand lines) on HP-UX is problematic with the supplied gcc compiler. The workaround is to use the cc compiler that is part of the aCC tool suite. In order to do so, you must have the cc compiler available on HP-UX. Appendix B of the “Using Verilog-A in ADS/RFDE” manual outlines how to switch from the gcc to the cc compiler. Note that the cc compiler that ships as part of the operating system will not work.

Use of $abstime and events in Cadence libraries

Many Cadence Verilog-A examples in rfLib, pllLib and ahdlLib use time-domain specific constructs. They use $abstime and take advantage of events. Such examples

10 Analog/RF Simulation


will not simulate properly with Harmonic Balance or Circuit Envelope. They will simulate properly with Transient and the results will agree with Spectre.

Lack of CML cache locking mechanisms

When Verilog-A modules are compiled to Compiled Model Library (CML) files, a CML cache directory is used. CML cache locking mechanisms have not been implemented in this release. This means that it is possible to encounter file sharing issues if multiple simulations using the same CML cache are run on the same platform at the same time.

Workaround:

To avoid this problem, simulate on two different platforms, simulate sequentially instead of in parallel, or use separate caches for each simulation.

Transient simulation speed

The performance of Verilog-A based models relative to corresponding C based models is analysis dependent. For large Verilog-A files, Transient simulations are generally within a 2X window while the other analyses (DC, AC, Harmonic Balance, Circuit Envelope) are generally within a 1.5X window. This is significantly faster than traditional interpreted approaches.

Compile time

The Verilog-A compile time can vary dramatically depending on the size of the Verilog-A file, the platform, and the processor. For small files on fast machines, it takes a matter of seconds. For huge files on slow machines, it can take minutes or up to an hour. Note that for simulations taking only a few seconds, the compile time can far exceed the simulation time. On state-of-the-art hardware, compile time is not a roadblock for most customers.

The ‘sim_veriloga’ license can be pulled when it is not used

The license associated with compilation and loading of Verilog-A modules is ‘sim_veriloga’. Simulations without Verilog-A content do not pull the ‘sim_veriloga’ license. The exception is when a Verilog-A file with a module which overrides a built-in component is placed in the Verilog-A search path. In this case, the ‘sim_veriloga’ license will get pulled, regardless of whether the component is used in the simulation or not.



Path to Cadence libraries

RFDE customers may want to use the Cadence libraries ahdlLib, rfLib and pllLib. These are available in $CADENCE_DIR/tools/dfII/samples/artist, where CADENCE_DIR is the Cadence installation directory. Please modify your cds.lib file to include the desired libraries.

RFDE netlister fails on some RFlib views

The RFDE netlister fails to netlist some RFlib views. Examples include chebyshev_pb and checyshev_lp. These views netlist correctly in Spectre, but fail in RFDE.

Agilent Ptolemy Simulation

OCEAN simulation complaints about registered ADS Ptolemy Trigger events for AMSD

If a Cadence OCEAN session loads “ads.cxt” and you run any simulation with ADSsim, spectre, ams, etc. you will receive warning messages advising you that some ADS Ptolemy trigger events did not execute properly. These messages can be ignored, as this doesn't effect the actual simulation or its results.


http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=RFDE_AMS.21

AMSD simulations with Ptolemy in OCEAN produce results in the wrong directory

If an AMSD netlist contains Ptolemy content and this is run using Cadence OCEAN the dataset may not be generated in the right location for viewing purposes. It may be under the simulation “netlist” directory instead of the “data” directory.

Workaround: To view the data after simulation, move the dataset from “netlist” directory to the “data” directory.



12 Agilent Ptolemy Simulation


HDL Cosimulation with Verilog XL not supported for LDV5.0

HDL Cosimulation with VerilogXL is supported only for LDV versions starting from 3.2 to 4.1. It is not supported for LDV5.0.

HDL Cosimulation in UI mode does not work correctly when used with sweep or optimization

If the parameter “HdlSimulatorGUI” is set to “On” during a parametric sweep or when optimizing designs that contain the components HdlCosim, NCCosim or VxlCosim, HDL Cosimulation will error out after the first simulation point.

Workaround: Set the parameter “HdlSimulatorGUI” to “Off” during sweep or optimization.


http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=Signal_Proc.3813

Running HDL cosimulation on Windows 64-bit machines in 32-bit compatibility mode

The ADS installer will create tools\bin and tools\bin64 subdirectories under your ADS installation are. To successfully run HDL cosimulation in 32-bit compatibility mode on Windows 64-bit machines you need to rename the bin directory to bin32 and the bin64 directory to bin.

Examples

RFDE 2008 with IC 6.1.0 and IC 6.1.1

If you are using Cadence Release IC 6.1.0 or IC 6.1.1, then you must have a writable ./.cds.lib with valid analogLib and basic definitions to load RFDE examples. This problem does not exist prior to IC 6.1.0.

Loading RFDE Examples will disable Spectre PDK Compatibility

Loading RFDE examples adds an entry for rfde.lib include to cds.lib. This undefines the Cadence analogLib and basic, then redefines them to use Agilent analogLib and basic.

Examples 13


Workaround:

Remove the rfde.lib include that was added to cds.lib, if you install an example.

Wireless Source Example: WCDMA3G_Source_Exprassion_Test dds can be improved

If the Stop time is reduced, the constellation diagram shows invalid.

This is because the constellation plots:

plot_vs(real(Q[1::2560][0]), real(I[1::2560][0]))

This can be improved by plotting:

plot_vs(real(Q[::,0]), real(I[::,0]))

Simulation time for Wireless Source Example, WLA_Source_Expression_Test can be reduced

The WLAN_SourceExpression example simulates for 16000 points but the expression only needs 80 µsec of data, which corresponds to approximately 6500 points. Setting the Stop time to 80 µsec will make this example simulate faster.

Examples will not open properly when using a new version of Cadence for the first time

When running a version of Cadence for the first time, RFDE examples will not open properly if the ‘What’s New’ dialog is displayed.

Workaround: Close the ‘What’s New’ dialog, quit the Analog Design Environment session, and open the example again.


http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=RFDE_SimUI.295

14 Examples


Momentum Virtuoso

Multi-layer pin support

Momentum Virtuoso does not support multi-layer (pins with the same x-y location but over layers) or multi-coordinate (pins with multiple coordinates on the same layer) pins.

Workaround: Reconfigure the pins.

Connection Manager

Connection Manager Server cannot be installed on 64-bit machines

Connection Manager Server must be installed on a true 32-bit machine and will not operate properly in 32-bit compatibility mode on 64-bit machines.

Printing/Plotting

Color images printed in black and white

Xprinter cannot print color graphics saved as EPS, PCL4, or PCL5 files. Try printing directly to the LaserJet 5M printer or assign the 5M to FILE instead of printer.

Printed and screen colors differ

The HP Color LaserJet printer has problems printing color hardcopy from UNIX installations using Xprinter if the PCL Cartridge driver is selected. The colors in the hardcopy produced using this driver do not match those displayed on the monitor.

Use the Color LaserJet PS driver when generating color hardcopy or print in monochrome.

HPGL/2 output and TrueType fonts

If your design contains any TrueType fonts and you print to file using the HPGL/2 format, your text will be lost. To preserve it, convert it to HersheyRomanNarrow as follows:

Momentum Virtuoso 15


• Component Text—Choose Select > Select All. Choose Edit > Component > Component Text Attributes. Select HersheyRomanNarrow from the Font type drop-down list and click OK.

• Other Text—Choose Select > Select All. Choose Edit > Edit Text. Select HersheyRomanNarrow from the Font Type drop-down list and click OK.

“Print to File” does not work properly when the destination directory is read-only

“Print to File” does not work properly when the destination directory is set to read-only. In this case, a file is not generated and no error or warning message is displayed.

Workaround: Make sure the destination directory is not read only.


http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=Hardcopy.446

The Print Setup Dialog may cause a crash on RedHat Enterprise v3 machines under certain circumstances

Bringing up the Print Setup dialog on RedHat Enterprise v3 machines may cause the application to crash under certain circumstances. This has only been observed once, but the root cause for this failure has not yet been identified.


http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=Hardcopy.442

Documentation Search

Boolean operators are not allowed in searches for exact phrases

When searching for an exact phrase, Boolean operators (AND, NOT, OR) are not allowed in the query. For example, the exact phrase “design and display” is not allowed, and the following message will appear:

“Bad query. Not expected in phrase: and.”

Workaround: Try to reformulate your query using an alternate syntax such as:

16 Documentation Search


design NEAR display


http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=Learning_Prd.4407

Running a second search in the Documentation window causes an error

When you run a search using the entry box available in the Documentation window, a Search window appears with the results. On UNIX, if you run a second search in the Documentation window (not in the Search window), a JavaScript error appears: “Search applet undefined”.

Workarounds:

• When the Search window is open, run any additional searches from the Search window.

• If you prefer running additional searches from the Documentation window, close the Search window first, or click Reload in the Documentation window's toolbar, then run the search.

Documentation/Online Help

Clicking Help in RFDE doesn't launch browser on Solaris 8

The browser may not be launched when you click a Help button in an RFDE dialog box.

Workaround:

To display help, you may need to first launch the browser by choosing Help > RF Design Environment Help.


http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=Help_Server.177

Limitations when using Automated Transient Assisted Harmonic Balance

When using TAHB, you should be aware of the following limitations:

Documentation/Online Help 17


1. There is a rare case in which the automatic frequency divider detection could fail to identify the presence of a frequency divider. The case is when the circuit contains a frequency divider and there is a source operating on not only a harmonic of a fundamental tone, but also the fundamental tone itself. In this case, TAHB will not be performed if TAHB is set to Auto, because the simulator would think there were no frequency dividers involved. The workaround is to set TAHB to On.

2. In ADS, TAHB is not supported for multiple HB controllers in a circuit. TAHB can be performed for only one HB controller.

Specifically:

• The simulation will exit with an error message if more than one HB controller has TAHB set to On. This is the same as in ADS 2005A.

• If only one HB controller has TAHB set to On and others have TAHB set to either Auto or Off, TAHB will be performed only for the one with TAHB set to On.

• If more than one HB controller has TAHB set to Auto, the simulator will turn off TAHB silently and proceed.

3. TAHB is not supported for Optimization, Yield, Yield Optimization, or DOE. If TAHB is set to On for any of these analyses, the simulation will exit with an error message. This is the same as in ADS and RFDE 2005A. If TAHB is set to Auto, the simulator will turn off TAHB silently and proceed.

Others

New license bundle behavior introduced to enable better use of mixed licenses

The license bundle behavior has been enhanced to improve the use of mixed licenses (standalone and bundle licenses together). To take advantage of this, you must manually set your license preference to multiple UI bundles in order for this new behavior to work. This is not the default and will not work if you are using the license preference tool.

Manually setting license preference:

• You can either set the license preference variable directly in the environment, or by editing the hpeesof.cfg configuration file.

18 Others


• The license preference variable can be of the form:

AGILEESOFD_LICPREF (global setting)

or

AGILEESOFD_LICPREF_machinename (local setting)

• Set the list of bundles you want to use. Multiple UI bundles as well as mixed bundle combinations can be used this way (a UI bundle contains ads_schematic).

For example:

AGILEESOFD_LICPREF_A0055737=ltp_rfic pb_ak1 ltp_rfic_rfde_combo

The new license bundle behavior looks at all the bundles in the license preference list and tries each one to satisfy the license request. If a bundle contains the requested feature but is unavailable, it continues down the list until it finds an available bundle, or a standalone feature if no bundles are available. This is the main difference between the new and old license bundle behavior.

NOTE The default bundle behavior will not change when using the license preference tool to set license preference.

WLAN_802_11b_TX WTB signal to ESG cannot be demodulated properly using the current default setting

For RFDE Examples/WLAN/WLAN_WTB_Test, using WLAN_802_11b_TX WTB under the default setting the signal downloaded to ESGc cannot be demodulated properly. This is because the default value of the parameter ESG_SampleClkRate is incorrect. This value needs to be set to 66 MHz instead of 80 MHz.

Workaround: To resolve this problem either change the ESG_SampleClkRate from 80 MHz to 66 MHz in the wtb design, or change the ARB Sample Clock from 80 MHz to 66 MHz for the ESGc ARB setup.


http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=Signal_Proc.3874

Others 19


USB hardware key not recognized in PCs using newer Intel chipsets

Some USB hardware keys are not recognized with systems using one of Intel's newer chipsets.

Workaround: To remedy this you need to download the latest FLEXid drivers from:

http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=191479

ADS Ptolemy content simulation in AMSD produces wrong data with Parametric Analysis and other tools

When Cadence AMSD-ADE (Analog Mixed Signal Designer integrated inside Analog Design Environment) simulation uses ADS Ptolemy AMS models that have measurement sinks, and the AMSD-ADE simulation uses tools like Parametric Analysis, Corner Analysis, Optimization, etc., the generated data will have only the ADS Ptolemy measurement data related to the last simulation point.



20 Others

Index
Numerics64-bit simulators, 9
AanalogLib

port component, 8AVM noise simulation

improvements, 7

Ccolor differences, 15color printing, 15Connection Manager, 15

DDFTool, 7

Eexamples

not opening properly, 14

HHB simulation

PackFFT, 8HPGl/2 fonts, 15

Llicense

bundles, 18

Ppin support, 15port component, 8port groups, 15pPar function, 8

Sstring values in subcircuits, 8

TTerm component, 8TrueType fonts, 15

Uuser-compiled models, 9

Index-1

Index-2

Documents

RF Design Environment Release Notesliterature.cdn.keysight.com/litweb/pdf/rfde2008update2/... · 2008-09-10 · A Note About Updates and MSR’s 5 RFDE 2008 Update 2 Release Notes