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Digital Logic Basics R2

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TTL & CMOS

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TTL versus CMOSCMOS to TTL

When connecting CMOS gates to TTL

Voltage YES

Current NO

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Fundamental Logic GatesOR Gate

Symbol Test Circuit

Timing Diagram Truth Table

C=A+BBoolean Ex ression4

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Fundamental Logic GatesAND Gate

Symbol Test Circuit

Timing Diagram Truth Table

C=A . BBoolean Expression5

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Fundamental Logic GatesXOR Gate

Symbol Test Circuit

Timing Diagram Truth Table

C=A

BBoolean Expression6

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Fundamental Logic GatesNOT Gate

Symbol Test Circuit

Timing Diagram Truth Table

B=ABoolean Expression7

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Fundamental Logic GatesNAND & NOR Gates

Symbols and Equivalent Circuits

B=A.B B=A+BBoolean Expression Boolean Expression

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Fundamental Logic GatesNAND & NOR Gate

Truth Tables

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Combinatorial Logic

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Parity Generation

8-bit Even Parity Generation.

A0A1A2

A3A4A5A6A7PB

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Parity Check

8-bit Even Parity Check.

PC

PC

PBEC

0 Data OK1 Error Occurred

EC

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Decoders and Encoders

Z0Z1

AB

Z0

Z1

Z2Z3

Truth TableTruth Table

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Multiplexers

Truth Table

SymbolEquivalent Logic Circuit

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Demultiplexers

Truth Table

SymbolEquivalent Logic Circuit

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Flip-Flops and RegistersRS Latch

Equivalent Logic Circuit

Symbol

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Flip-Flops and RegistersRS Latch

Timing Diagram

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Flip-Flops and RegistersGated Latches

SymbolEquivalent Logic Circuit

Truth Table18

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Flip-Flops and RegistersD-FlipFlops

SymbolEquivalent Logic Circuit

Truth Table19

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Flip-Flops and RegistersD-FlipFlops

Timing Diagram

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Flip-Flops and RegistersJK-FlipFlops

SymbolEquivalent Logic Circuit

Truth Table21

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Flip-Flops and RegistersJK-FlipFlops

Timing Diagram

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Counters

Timing Diagram

Output

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Counters

Equivalent Circuit of a 2-bit Counter

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How Hardware Engineers

Dene Digital Designs

Hardware Denition Languages VHDL Verilog

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Need Further

Assistance?

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