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Electronic Materials Letters, Vol. 7, No. 1 (2011), pp. 1-11

DOI: 10.1007/s13391-011-0301-x Published 27 March, 2011

Review Paper: Transparent Amorphous Oxide SemiconductorThin Film Transistor

Jang-Yeon Kwon, Do-Joong Lee and Ki-Bum Kim*

Department of Materials Science and Engineering, Seoul National University, Seoul 151-742, Korea

Thin film transistors (TFTs) with oxide semiconductors have drawn great attention in the last few years,especially for large area electronic applications, such as high resolution active matrix liquid crystal displays(AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs), because of their high electron mobil-ity and spatial uniform property. This paper reviews and summarizes recent emerging reports that includepotential applications, oxide semiconductor materials, and the impact of the fabrication process on electricalperformance. We also address the stability behavior of such devices under bias/illumination stress and criticalfactors related to reliability, such as the gate insulator, the ambient and the device structure.

Keywords: Oxide semiconductor, thin film transistor, transparent, reliability

1. INTRODUCTION

Active matrix liquid crystal displays (AMLCDs) are now-

adays the major device of flat panel display products that are

conventionally driven by an amorphous Si (a-Si) thin film

transistor (TFT). Drastic improvement of the driving tech-

nology and the electrical performance of a-Si TFTs make it

possible not only to switch pixels but to integrate the gate

driver. However, the growth of the high-end commercial

market with high resolution, such as 4000×2000 pixels, a

high frame rate (>240 Hz), and sizes larger than 70 inches

requires a higher electrical performance than the a-Si TFT

has achieved. At least 3 cm2/Vs of field-effect mobility is

required to satisfy such demands,[1]

which is not so easy to

achieve by modifying the conventional amorphous silicon

material. First of all, oxide semiconductor materials are

promising alternatives due to a relative high electron mobil-

ity (3-50 cm2/Vs)

[2,3], which is large enough to fabricate a

high-speed transistor for driving the AMLCDs mentioned

above. In addition, oxide semiconductor materials have an

amorphous phase in general, which shows uniform electrical

properties even with a large-area substrate and is strongly

advantageous for the display applications.[4]

The second potential application for oxide semiconductor

TFTs is the active matrix organic light-emitting diode

(AMOLED). For mobile devices such as cellular phones,

navigation, and notebook PCs, low temperature poly Si

(LTPS) TFTs currently drive AMOLEDs because it exhibits

a more sufficient and stable current supply into the organic

light-emitting diode (OLED) than the a-Si TFT. However,

the LTPS TFT has a problem with the spatial distribution of

electrical performances originating from non-uniformity of

grain sizes in the poly-Si film. Consequently, the LTPS TFT

is not suitable for the AMOLED TV. Even for a small size

AMOLED (below 5 inches), a compensation circuit for pix-

els is required in order to obtain uniform image quality for

the LTPS TFT. As a backplane for the AMOLED TV, the

stability of the oxide semiconductor TFT is superior to that

of a-Si, and at the same time, the uniformity is much better

than the LTPS TFT. These aspects have motivated many

demonstrations of AMOLEDs driven by the oxide semicon-

ductor TFT.[1,5-7]

Another apparent advantage of the oxide semiconductor-

based TFTs over silicon-based TFTs is that most oxide semi-

conductors are transparent in the visible light region and

thereby they can be used to realize transparent electronics,

including transparent displays. Such transparent devices can

be realized with the combination of a transparent insulator, a

transparent conductor, and a transparent semiconductor.

Most insulators, such as SiO2 and SiNx, do not absorb visible

light, and transparent conducting oxides (TCOs), such as

indium-tin oxide (ITO), Al-doped zinc oxide (AZO), and

indium zinc oxide (IZO), are well known and easily fabri-

cated materials with advanced technologies. Above all, the

oxide semiconductor could be the last key invisible material.

For instance, a transparent display is applicable to automo-

bile displays so that people can get information from the

transparent display as well as from a real environment, such

as in traffic situations while driving a car. Another promising

application may involve a see-through mobile phone that

would allow users to access both sides of the panel as inde-*Corresponding author: [email protected]©KIM and Springer

2 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor

Electron. Mater. Lett. Vol. 7, No. 1 (2011)

pendent touch screens and thereby to provide resourceful

user interfaces.

Oxide semiconductor TFTs fabricated on a flexible poly-

mer substrate have also been reported.[8]

Because the deposi-

tion of oxide semiconductors does not require a high

temperature process, typically via sputtering at room temper-

ature, device performances comparable to a substrate on

glass are achievable on a flexible substrate.

Beyond the display applications, some researchers are

investigating oxide semiconductor devices for functional cir-

cuits such as an inverter,[9]

an oscillator,[10]

a non-volatile

memory,[11]

and photo-sensors.[12]

2. OXIDE SEMICONDUCTOR MATERIALS

2.1. Binary oxide materials: properties of In2O3, ZnO,

and SnO2

Combining conventional TCOs, including In2O3, ZnO,

and SnO2In2O3, ZnO, and SnO2In2O3, ZnO, and SnO2In2O3,

ZnO, and SnO2In2O3, ZnO, and SnO2 been introduced.

These binary oxides have a wide band gap (>3.0 eV) that

allows transmission of the visible rays.[13]

In addition, they

exhibit much higher electrical conductivity (10-2 Ω

-1 cm

1 to

103 Ω

-1 cm

1) than the other insulating ionic compounds. This

has been attributed to the existence of native defects, such as

oxygen vacancies, cation interstitials, and substitutional/

interstitial hydrogen, that act as shallow donors.[14-16]

Because of these donors, the TCOs have a high carrier con-

centration of 1018

cm-3 to 10

21 cm

-3. Furthermore, a more

important factor is that these oxides have high electron

mobility (~10 cm2/Vs or higher) even if they are in the amor-

phous phase.[2,17,18]

Those TCOs commonly consist of heavy

post transition metal cations with an electronic configuration

of (n-1)d10

ns0, where n is the principle quantum number of

the cations ( ). Those vacant s-orbitals are spherical,

which indicates they are non-directional, and exhibit a large

spatial spread. Therefore, electron conduction can easily

occur even in the amorphous oxides via direct overlap of the

s-orbitals in the neighboring cations. For these reasons, the

In2O3, ZnO, and SnO2 have been widely considered as base

materials for amorphous semiconductors. However, those

oxides themselves are polycrystalline and thereby are not

appropriate as a channel material of the TFT due to poor uni-

formity.[2,15,19]

Therefore, formation of the amorphous oxides

by combining those individual TCOs has been one of the

critical issues in ensuring large-area uniformity.

2.2. Multicomponent oxide materials

One of the principles of forming amorphous materials is

mixing multi-components with different crystal structures.

The TCOs discussed above satisfy that criterion. For exam-

ple, In2O3 and ZnO have bixbyite and wurtzite structures,

respectively, and also exhibit different coordination numbers

to the oxygen as InO6 and ZnO4.[15]

These aspects allow In-

Zn-oxide (IZO) to have an amorphous phase. Consequently,

IZO has become an essential component for both the trans-

parent electrodes for flat-panel displays and the active layer

for TFTs.[20-23]

By varying the composition and the deposi-

tion conditions, IZO has exhibited a wide range of the resis-

tivity, 10-4 cm

-3 to 10

8 Ω cm. For instance, IZO films with 10

wt.% ZnO is mostly used in electrode applications,[20,24]

while the films with a comparable composition of In/Zn

(typically In 60:40 Zn) exhibit semiconducting behavior in

the resistivity range of 10 - 103 Ω cm.

[25] In addition, amor-

phous IZO has shown extremely high thermal stability even

up to 600°C.[26]

Due to these advantages, amorphous IZO (a-

IZO) has been one of the most extensively investigated

TCOs and semiconducting oxides for display applications.

Even though a-IZO films have exhibited adequate proper-

ties as a component of TFTs, such as excellent uniformity

and large mobility (>20 cm2/Vs), one of the critical issues

with this material is the controllability of the carrier concen-

tration. Because IZO typically exhibits a high carrier con-

centration of >1017

cm-3, this can lead to large off-current and

small on-off ratios.[18,19]

Therefore, to reduce the carrier con-

centration below that, doping has been conducted into the a-

IZO. For instance, Nomura et al. inserted Ga into IZO

(IGZO is most widely used semiconducting oxide cur-

rently).[2]

Their approach demonstrated that the carrier con-

centration of amorphous IGZO can be lowered below <1017

cm-3 whileits electron mobility (~10 cm

2/Vs) remains high.

The decrease of the carrier concentration has been attributed

to the high ionic potential of Ga3+

ions, which allows them to

tightly bind oxygen ions and thereby suppress the formation

of oxygen vacancies.[2,18,19,27]

Since the demonstration of

IGZO, similar approaches have been tried by inserting Hf,

Zr, Mg, La, Sc, and Si into a a-IZO matrix and tested as the

active layer of the TFTs.[28-33]

As in the case of the IGZO,

those oxides exhibited semiconducting behavior and had

amorphous or nanocrystalline-embedded amorphous phases.

Besides the IZO-based semiconducting oxides, there is

another class which contains SnO2 in which Sn4+

is one of

the heavy post transition cations that satisfies .[18,27,34]

Similar to IZO, ZnO and SnO2 easily form an amorphous

phase due to different crystal structures (ZnO: Wurtzite,

SnO2: rutile) and the coordination number to the oxygen

(ZnO4 / SnO6).[15]

This zinc tin oxide (ZTO) is cheaper than

the IZO-based materials by excluding the In, one of the

scarce and expensive elements.[34,35]

For the same aim as

with IGZO, there have been several attempts to dope ZTO

with various elements, such as Al and Zr, and the device per-

formance of those oxides have been tested.[36,37]

Detailed

issues of semiconducting oxides as the active layer of TFTs,

in terms of the process and the electrical performances, will

be covered in the following sections.

n 5≥

n 5≥

J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor 3


3. DEVICE CONFIGURATION

There are four major classes of configuration of oxide

semiconductor TFTs: (1) back channel etch (BCE) struc-

ture,[1]

(2) etch stopper (ES) structure,[38]

(3) top gate (TG)

structure ,[39]

and (4) double gate (DG) structure[40]

(Fig. 1).

First, the BCE structure is almost the same as the conven-

tional a-Si TFT, so it is easily adapted to process and design

current TFT-LCD mass production. However, because an

oxide semiconductor layer is exposed to a plasma environ-

ment which can be an energy source during the subsequent

deposition of the sour/drain electrode and passivation layer,

additional charge carriers could be generated, and the thresh-

old voltage moves to the negative direction.[41]

In addition,

because an oxide semiconductor is easily etched by a weak

acid, such as acetic acid (CH3COOH), the source/drain elec-

trodes should be etched via dry etch with a reasonable etch

selectivity between the semiconductor and electrodes. In

spite of these obstacles, the BCE structure is one of the ulti-

mate configurations for cost competitive TFTs.

The second class of configuration is the etch stopper struc-

ture. By inserting an etch stopper layer between the semicon-

ductor and source/drain electrode, most process obstacles

mentioned for BCE can be overcome. The source/drain elec-

trode and passivation layer can be formed without changing

the semiconductor properties, and the chip wet-etch process

for the source/drain can be carried out based on a high selec-

tivity between the electrodes and the etch stopper layer. In

this configuration, the deposition of the etch stopper layer

and an additional photo lithography process is inevitably

required.

The next configuration, the top gate structure, has an

advantage in the electrical performance of the devices over

the first two kinds of TFTs. For example, there is no overlap

between the gate and the source/drain electrode, and conse-

quently, it does not create a signal delay from the parasitic

capacitance. For LCD applications, however, because light

from the backlight unit reaches the semiconductors without

being blocked by the gate electrode, the stability of oxide

semiconductor for light illumination should be strengthened.

In addition, high power plasma is an additional process

obstacle to increasing the insulating ability of a gate insulator

deposited on the semiconductor.

Finally, the double gate is a good candidate for device

structure, if two problems, the complexity of the driving

scheme and the low electrical performance of the passivation

layer, are resolved, because it demonstrates higher electron

mobility and stability than the other three kinds of single

gate structures.

4. IMPACT OF A UNIT PROCESS ON ELEC-

TRICAL PERFORMANCES OF OXIDE SEMI-

CONDUCTOR THIN FILM TRANSISTOR

4.1. Gate insulator material and process

Silicon oxide and silicon nitride have been most widely

used as gate insulators for oxide semiconductor TFTs and as

well as for conventional Si-based transistors. For instance, P.

F. Carcia et al. compared silicon oxide and silicon nitride as

a gate insulators for oxide TFTs.[42]

They prepared several

kinds of ZnO films as a semiconductor by varying the oxy-

Fig. 1. Device configurations of oxide semiconductor (a) back chan-nel etch (BCE) structure (b) etch stopper (ES) structure (c) top gate(TG) structure (d) double gate (DG) structure. (a), (b) from [38]. (c)from [39]. (d) from [40].



gen partial pressure (pO2) during the deposition, which

means the electrical conductivity of the ZnO films was con-

trolled. Additionally, they fabricated TFTs with silicon oxide

and silicon nitride as gate insulators, respectively. The sili-

con oxidewas thermally grown. They prepared two samples

of silicon nitride. One was deposited by conventional plasma

enhanced chemical vapor deposition (PECVD), so the sili-

con nitride contained around 30% hydrogen in the film. The

other contained a relatively low hydrogen concentration and

was formed by the sputtering method. Figure 2 shows the

electron mobility of the TFT as a function of oxygen partial

pressure for the mentioned gate insulators. At a low pO2, the

mobility converged to around 5 cm2/Vs regardless of the

gate dielectrics. In contrast, as the pO2 increased, the mobil-

ity for thermally grown silicon oxide decreased by several

orders of magnitude, whereas the decrease for silicon nitride

was much less. In the ZnO film deposited on a silicon

nitride, oxygen vacancies were formed, which brought about

an increase in both the mobile electron concentration and the

electron mobility of the device. However, the ZnO grown on

silicon oxide contained accepter defects that resulted in a

decrease of the electron concentration by trapping the

defects. They concluded that photo luminescent results as a

proof for oxygen vacancies and accepter defects.

Besides SiO2 and SiNx, many kinds of high-k dielectric

materials, such as AlOx,[43]

HfOx,[43,44]

TiOx,[45]

AlN,[46]

BaSr-

TiOx,[47]

and HflaOx[48]

, have been used for gate insulators in

order to reduce the driving voltage and improve sub-thresh-

old properties.

The gate insulator plays an important role in TFTs in terms

of not only the initial electrical property of the device but

also the stability of the device under bias/illumination

stresses, because trapping holes induces an external stress

into the gate insulator and thereby degrades the device per-

formances. Therefore, controlling the trap defects in a gate

insulator is one of the key technologies necessary for

improving the reliability of the devices. This will be dis-

cussed further in section 4.2.1.

4.2. Source/drain electrode

In order to reduce the RC signal delay, the resistivity of

both the gate electrode and the source/drain electrode should

be decreased. Low resistivity materials, such as molybde-

nium, aluminium, and copper, are suitable for the source/

drain electrode. The contact resistance between the semicon-

ductor and the source/drain electrode are other considerable

factors for determining a material and a process for elec-

trodes. High contact resistance can induce the current crowd-

ing at output characteristics and finally increase the signal

delay even though the resistivity of the electrode material is

enough low. For example, Y. Shimura et al. measured and

compared the contact resistance between IGZO and various

metallic electrodes, including Ag, Au, In, Pt, Ti, ITO, and

IZO.[49]

All the materials except Au and Pt exhibited a linear

relation of current-voltage characteristics, while Au and Pt

resulted in Schottky contacts. They also reported that a

decreasing work function of the electrode material leads to a

reduction of the contact resistance and, finally, to high per-

formance of the devices (Fig. 3). Copper, which is a kind of

ultimate solution for an electrode, reacts with oxygen in the

oxide semiconductor and forms copper oxide which

increases the contact resistance. Furthermore, copper could

Fig. 2. pO2 dependence of saturation mobility for ZnO TFTs on dif-ferent gate dielectrics grown on Si. Mobility data on 100 nm and430nm SiNx:H are indicated as u(100) and u(430), respectively, inthe figure legend, while data on sputtered SiNx and SiO2 are indi-cated by u(SiN) and u(SiO2). Data from [42].

Fig. 3. Specific contact resistance obtained as a function of the workfunction (φ) of the electrode materials. Ti contacts have a large distri-bution in ρc (2.4×10-5-3.1×10-4 Ω cm

2), probably due to the forma-

tion of an oxidized interface layer. The φ values are 4.26 eV for Ag,5.1 eV for Au, 4.12 eV for In, 5.65 eV for Pt, 4.33 eV for Ti, 4.3-5.2eV for ITO, and 4.9-5.2 eV for a-IZO. The φ values of ITO and a-IZOvary in a wide range depending on surface state and bulk carrier den-sity. Data from [49].



be also oxidized during the deposition of SiO2 as a passiva-

tion layer which is necessary to improve the stability of

device. In spite of these obstacles, W.-S Kim et al. demon-

strated good performance of a device with a copper electrode

as a clue to low resistance metallization.[50]

5. STABILITY

In this section, we discuss the stability of oxide semicon-

ductor TFTs under bias and illumination. There are many

parameters for the stability of devices, such as an oxide

semiconductor material, the material composition, the

device structure, the gate insulator, the environment for

stressing, the electrical biasing conditions, and the intensity

of the illuminated light. This makes it difficult to compare

quantitative responses precisely and to summarize the phe-

nomena of stability succinctly. Based on the common results

reported by multiple researchers, we tried to understand the

reliability of the devices.

5.1. Bias stressing

5.1.1 Positive bias stressing

R.B.M. Cross et al. reported the reliability of oxide TFTs

under bias stress.[51]

They applied a gate bias of up to 30 V

and measured the change of the device parameters, such as

electron mobility (u), threshold voltage (Vth), and subthresh-

old swing (S.S.). Interestingly, bias stressing produces a par-

allel shift of Vth to the positive direction and no or little

change in u and S.S. values (Fig. 4). Similar results were

reported by J.-M Lee et al.[52]

(Fig. 5). For the case of stress

under gate and drain biases at the same time, Fujii et al.

reported an increase of Vth shift with an increasing gate

bias.[53]

However, the shift was not strongly dependent on the

drain bias. Similar results were also reported for a thermal

SiO2 gate insulator,[54]

PECVD SiO2, SiNx,[55]

and Al2O3.[56]

Positive bias stressing has usually been tested for the

AMOLED applications, because the TFT must supply a sta-

ble current for the entire operating time of the OLED. In

such a case, instability measurement is generally carried out

under a Vg=Vd>0 condition in order to supply a constant cur-

rent. A similar phenomenon was observed for constant cur-

rent stress experiments, which means the observation of only

a parallel Vth shift.[57-61]

An instability mechanism of the con-

ventional a-Si TFT under bias stress was interpreted by two

models.[62,63]

One was the defect creation in a channel and the

other was trapping in a gate insulator or at the interface

between the channel and the insulator. The former resulted in

the degradation of mobility and S.S., while the latter showed

only a parallel shift of Vth. Based on these observations, the

instability of oxide TFTs under positive bias stress was also

explained based on the charge trapping model, and the time

evolution of Vth was described by the stretched-exponential

equation.[52]

Even though most reports showed a positive shift of Vth

and little change of electron mobility under positive bias

stress, A. J. Flewitt et al. reported an increase of mobility by

increasing the occupancy of defects near the IZO conduction

band.[64]

5.1.2 Negative bias stressing

In general, oxide semiconductors have n-type characteris-

tics, so applying negative voltage at the gate is required for

turning-off the device. In particular, the total duration of the

negative gate bias applied on the switching transistor is

larger than that of the positive gate bias by more than 500

times in the case of AMLCD products. For an AMOLED,

the driving TFT must supply current for emission of light

and requires high stability under positive bias stressing asFig. 4. Threshold voltage shift as a function of time for various posi-tive bias stress voltage. Data from [51].

Fig. 5. Linear transfer IDS-VGS curve of a-IGZO TFTs as a functionof stress time (tST). The inset shows the bias-stress-induced shift oflog_IDS-VGS curve. The sweep was done at VDS=0.5 V in bothcurves. Data from [52].



mentioned in 4.1.1. However, switching the TFT is also

required for the AMOLED as is exactly in the same bias sit-

uation as that of the AMLCD. Therefore, a high reliability

with a negative bias stress is an indispensable requirement

for operating an active matrix display.

For instance, A. Suresh et al. reported a negligible shift of

not only mobility and the S.S. value but also Vth under nega-

tive bias stress.[65]

They observed a shift of over 5 V under a

+30V gate bias stress after 500 s. However, there was only

aslight change of the transfer curve between before and after

the negative gate bias stress (-30V). In another study, J. Y.

Kwon et al. observed a negative bias stability for both back

channel etch structure devices and etch stopper structure

devices under w/ and w/o illumination.[38]

For both struc-

tures, bias induced a small negative shift (below 1V) at the

early stage of the stress and little change for further stressing

time. K. H. Lee,[66]

H. S. Seo[67]

and T.Z. Fung[68]

also reported

a little degradation of those properties, but it could be recov-

ered with the following annealing process. Similar to the

positive shift, the negative shift of Vth could be explained by

a positive charge trap in the gate dielectrics. However, most

oxide semiconductors are n-type and contain little positive

charge to trap and to induce Vth shift in particular.

Meanwhile, in the commercial AMLCD device, TFT

experiencing a continuous pulsed gate voltage is also

exposed to the light, which is inevitable due to the presence

of the back light unit underneath. Thus, the device degrada-

tion under a negative bias and illumination stress at the same

time (called negative bias illumination temperature stress,

NBITS) is a critical issue to be resolved. It will be discussed

in next section.

5.2. Bias and illumination stressing

Stressing of bias and light at the same time (bias illumina-

tion temperature stress, BITS) is a more realistic test scheme

for display applications than stressing of only bias (bias tem-

perature stress, BTS). In the case of a conventional a-Si TFT,

the shift of transfer curve by bias stressing and the increase

of off-current by illumination stress could be observed.

However, no drastic degradation under simultaneous bias

and light stresses was found compared to under individual

stress. In contrast for the oxide semiconductor TFTs, the

shift of Vth was accelerated under BITS. Figure 6 shows the

evolution of the transfer curve under BTS and BITS, respec-

tively.[69]

For the positive bias stress, there was little differ-

ence between under BTS and BITS. However, the transfer

curve moved to the negative direction fast under BITS,

while no remarkable change was observable under BTS for

negative bias stress. This movement of transfer curve

became faster when the intensity was increased as shown in

Fig. 7. Since n-type oxide semiconductors have negligible

holes in the valence band, hole trapping in a gate insulator or

at the interface between the semiconductor and the gate

dielectric is extremely difficult even under the negative gate

Fig. 6. Changes in the ID-VG characteristics of ZnO TFTs (W/L =40 µm/20 µm) under 10 V gate bias stress with (a) Pill of 0 mW/cm2 and (b) 1.0

mW/cm2 and under -10 V gate bias stress with (c) Pill of 0 mW/cm

2 and (d) 1.0 mW/cm

2. VD is 15 V during the VG sweep. Data from [69].



bias. However, abundant holes could be generated by light

exposure. Drift of those toward the gate insulator and subse-

quent trapping by the negative electric field would result in

remarkable shift of Vth. In that report, this phenomenon was

explained by using the modified stretched exponential

model.

5.2.1. Gate insulator

In order to improve the BITS characteristics, the effect of

device components, such as gate insulator,[44,70,71]

environ-

ment,[54,66,72,73]

passivation layer,[74,75]

and device struc-

ture[38,76]

, on the stability has been studied. One of the key

parameters among them is the gate insulator because the

trapping process of photo-generated holes is strongly related

to the material and properties of the gate insulator. For exam-

ple, J.-Y. Kwon et al. compared several materials as a gate

insulator under BITS (Fig. 8).[44]

The device with SiO2 and

AlOx showed quite stable performances, which is well rec-

onciled with their wide band gap (over 8e V) prohibiting trap

of holes into the gate insulators. In contrast, the inferior sta-

bility of the device with a SiNx gate dielectric can be attrib-

uted to the enhanced hole injection or trapping due to the

smaller valence offset (~0.15V). The higher trap density of

SiNx compared to SiO2 was also supported by the fact that

SiNx film is often used as the charge trap layer in flash mem-

ory devices. The worst reliability of HfOx, even though it has

larger valence offset than SiNx, is probably caused by a high

leakage conduction via Poole-Frenkel trapping centers

which are easily observed in high-k dielectric materials. K.

H. Ji et al. also announced the superior reliability of a SiO2

gate insulator to a SiNx.[70]

As another method, the BITS

property could be also improved by controlling the mechan-

ical stress of the SiNx film.

5.2.2. Ambient interaction and passivation layer

It is well known that metal oxides are surface sensitive to

molecules in an ambient atmosphere.[77-79]

The adsorption of

oxygen onto the surface of the metal oxides introduces an

accepter-like surface state. When oxygen chemisorbs on the

surface, it is negatively charged by capturing an electron

from the conduction band, and consequently, surface of

oxide semiconductor is depleted. On the other hand, H2O

acts as a donor-like surface state based on a similar explana-

tion. For instance, Jeong et al. discussed how bias stressing

is able to lead to field induced adsorption and desorption of

O2 or H2O and how it affects device instability by varying

the carrier concentration of the oxide semiconductors (Fig.

9).[72]

Other experimental results for the effects of ambience

was reported by Lee et al.[66]

They carried out a BITS test in

a humid environment. As the humidity of environment

increased, Vth moved to the negative direction faster (Fig.

10). In that report, it was suggested that water molecules

supplied by the ambient condition generated metastable gap

states which brought about a large number of trapped elec-

trons and eventually an increase of hole carriers in the oxide

semiconductors, and finally the devices exhibited a negative

shift of the threshold voltage.

To improve stability by protecting the device from the envi-

ronment, a passivation layer becomes one of the key parame-

ters. SiO2 film was suggested as a superior passivation layer

for SiNx film.[74]

However, not only stability of the device but

of the interconnection should be considered in selecting the

passivation layer. Especially for a copper electrode as a

source/drain, which is indispensible for reducing signal delay

time, SiNx film is more stable than SiO2 film in general.

5.2.3. Device configuration

Device configuration could be another considerable factor

Fig. 7. ∆Von vs. stress time (a) and unified stress time t(1+ηPill) (b), when the ZnO TFTs (W/L=40 µm/20 µm) are biased in the strong off state(VG_ST=-10 V) during illumination with Pill of 0 to 2.6 mW/cm

2 (Lines are theoretical calculations). Data from [69].



for improving stability. The general merits and demerits for

each device structure has been already discussed in section

2. The etch stopper (ES) structure shows a quite stable BITS

performance compared to the BCE structure[38]

because the

etch stopper layer plays a role as another protection layer to

the ambient conditions (Fig. 11). In addition, a device with a

double etch stopper layer has been also suggested.[80]

The

double ES layer consisted of a lower ES layer for minimiz-

ing variation of oxide semiconductor properties during dep-

osition and an upper ES layer for protecting molecule

penetration from the ambient conditions. Another interesting

configuration is the double gate structure. Even though it is

relatively complicated due to the fabrication of another gate

on a passivation layer, it shows more stability than any other

single gate devices (Fig. 12).[76]

Fig. 8. Evolution of the transfer characteristics for the (a) SiNx/HfOx/HIZO, (b) SiNx/HIZO, and (c) SiNx/SiOx/HIZO devices as a function ofthe NBTIS time. (d) Vth shift as a function of the applied NBITS time for the HIZO TFT with various gate dielectric materials and structures.Data from [44].

Fig. 9. (a) Schematic showing the electric-field-induced adsorption of oxygen molecules from the ambient atmosphere under the application ofPGVS. (b) Schematic showing the electric-field-induced desorption of water molecules into the ambient atmosphere under positive VGS stress.Data from [72].



6. SUMMARY

The oxide semiconductor thin film transistor is a great

candidate for the backplane for next generation AMLCDs

and AMOLEDs because of its high electrical performance

and the good spatial uniformity. From the viewpoint of cost,

it is comparable to the conventional a-Si thin film transistor,

which is well-known as a low-cost device. It is thought that

the oxide semiconductor thin film transistor could be the

only candidate for next display module until now. Despite

the discussed strong advantages, research on stability is still

an emerging field. Not only material and process but also

structure and even environment are strongly related to reli-

ability. A more serious issue is the lack of basic understand-

ing of the ionic bonding-based semiconducting material

itself and of the mechanism of operating and degrading of

devices under various conditions.

However, since the first report on the oxide TFT in 2003,

many obstacles have been overcome by the efforts of dedi-

cated researchers within a shorter time than it took for the Si

device technology to be developed. If we consider the oxide

TFT as a new material and device, not a device derived from

Si technology, it will lead to a bright future for oxide TFTs.

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