Retiming with Interconnect and Gate Delay

CUHK CSE CAD GroupDennis Tong

29th Sept., 2003

Presentation Outline Retiming Revisit Retiming with Interconnect Delay Future Work Conclusion

Retiming Problem Formulation

given a sequence circuit G(V, E, d(v), w(euv)), retiming can be viewed as an vertex-to-integer mapping, r: V Z, where Z is the set of integers such that a new circuit G’(V, E, d(v), wr(euv)) is obtained.

wr(euv) = w(euv) + r(v) – r(u) 0

Retiming with Interconnect Delay Two Algorithms Proposed

an optimal approach gives optimal solution when both gate and

interconnect delay are considered

a near-optimal fast approach gives optimal solution when gate delay is neglected,

but still gives near-optimal results when both delays are considered

runs much faster

An Optimal Approach Extension from the Original Paper

“Retiming Synchronous Circuitry”, Charles E. Leiserson and James B. Saxe, Algorithmica, 6:5-35, 1991.

Main Idea transform retiming to a special case of MILP whi

ch is polynomial time solvable

Near-optimal Fast Approach give optimal solution when no gate delay Pre-processing

replace each gate by a wire represent gate delay d(v) by wire delay d(v1,v2)

d(v) v pre-process

v1

v2

d(v1,v2) = d(v)

d(v1) = 0

d(v2) = 0

Near-optimal Fast Approach Post-processing

remove registered “got retimed” into the gates use linear programming to minimize clock

v1

v2

“got retimed”into gate v post-process

v1

v2

“got removed”from gate v

Near-optimal Fast Approach Algorithm Overview

1. transform G(V,E) into a DAG G’(V’,E’)

2. construct timing constraints

3. solve the set of constraints

4. find optimum Topt by binary search

5. post-process flip flops “got retimed” into gates

Near-optimal Fast ApproachStep 1: Transform G(V,E) into a DAG G’(V’,E’)

– traverse G in a depth-first manner– break all back edges found– denote Vb the set of vertices have back edges (e.g., A and B Vb)

DFS traversal

A

B

C

A’ B’

G’(V’,E’)A

B

C

G(V,E)

Near-optimal Fast ApproachStep 2: Define Timing Variable tv

tv - for all v V’, denotes the maximum interconnect delay from a

register connecting to an input of v.

A

B

C

A’ B’

tc1

tc2

tc = MAX { tc1 , tc2 } = tc1

In general, tv is given by:

tv max { tu + d(u,v) (w(euv) + r(v) r(u)) T }u in(v)

in(v) : the set of vertices in V’ with an edge pointing to v in G’

Near-optimal Fast ApproachStep 2: Construct Timing Constraints

A

B

C

A’ B’

tc1

tc2

Given tv for all v V’ :

tv max { tu + d(u,v) (w(euv) + r(v) r(u)) T } (1)u in(v)

We have constraints :

tv T v V’ (2)

tv’ tv v Vb (3)

r(v’) = r(v) v Vb (4)

Near-optimal Fast ApproachStep 3: Solve the Set of Timing Constraints

Main Idea

A

B

C

A’ B’

Express tv for v V’ in terms of tu and r(u) where u Vb

Reduce the constraints involve tu and r(u) only

Use Bellman-Ford algo. to solve for tu and r(u)

Derive tv and r(v) by propagating tu and r(u) in G’

Near-optimal Fast ApproachStep 3: Express tv in terms of tu and r(u) where u Vb

uv - for all u, v V’ denotes the maximum delay among all the

directed paths from u to v in G’ when no retiming is done, reducing the delay by T if a register is encountered.

For example,AA’ = max { dABCA’ – 5T , dACA’ – 3T }AB’ = max { dABCB’ – 4T , dACB’ – 2T }

Combining tv and uv, (1) becomes:

tv max { tq + qv (r(v) r(q)) T } (1’)

A

B

C

A’ B’q anc(v)

anc(v) : the set of vertices in Vb with a directed path to v in G’

Near-optimal Fast ApproachStep 3: Reduce the constraints involve tu and r(u) only

A

B

C

A’ B’

Given tv for all v V’ :

tv tq + qv (r(v) r(q)) T } q anc(v)

Let v = tv + r(v) T for v Vb, the constraints become:

q + qv’ v (5)

q + qv v (6)

A system of difference inequalities

Near-optimal Fast ApproachStep 3: Derive tv and r(v) from tu and r(u) in G’

A

B

C

A’ B’Step 4: Find optimum Topt by binary search

Solve u for u Vb by Bellman-Ford algo.

Compute tu and r(u) given u = tu + r(u) T

Compute tv and r(v) for v V’ - Vb using (1’)

Experimental Results - I

NEAR-OPTIMAL

OPTIMAL

T’ – Topt

Topt

(%)

Circuits #V #E T’ runtime

(sec)

Topt runtime

(sec)

s1488 655 1405 18.85 0.28 18.82 5.62 0.16

s1494 649 1411 20.78 0.25 20.78 4.37 0.00

s3271 1574 2707 10.24 1.09 10.24 33.70 0.00

s3330 1791 2890 27.05 0.50 27.05 43.14 0.00

s3384 1687 2782 24.21 0.74 24.16 25.19 0.21

Testing Environment Intel Xeon 1.8GHz, 512KB cache, 512MB RAM ISCAS89’ suite

Experimental Results - IINEAR-

OPTIMALOPTIMAL

T’ – Topt

Topt

(%)

Circuits #V #E T’ runtime

(sec)

Topt runtime

(sec)

s4863 2344 4093 23.58 3.12 23.58 87.75 0.00

s5378 2781 4261 27.27 1.16 27.25 138.68 0.07

s6669 3082 5399 23.07 1.91 22.96 177.59 1.00

s9234 5599 8005 42.73 4.08 42.73 512.86 0.00

s13207 7953 11302 72.34 8.11 72.34 1161.07 0.00

s15850 9774 13794 67.82 24.02 67.82 1545.59 0.00

s38417 22181 32135 36.53 83.56 36.52 7680.79 0.03

s38584 19255 33010 94.26 445.63 N/A >15000 --

Future Work Multi-pin Net Handling

find a maximum sharing of flip flops in a net while the clock is preserved

avoid unrealistic increase in number of flip flops

u

v 1

v 3

v 2

flip flop shared in the stem

v1

v2

v3

u

unrealistic increase in number of flip flop

Future Work Circuit Delay Modeling

flip flop positions affect delay estimation load in each branch affect one another

retimed to X

X

Y