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Malte Backhaus, Vasilije Perovic, Branislav Ristic
26/7/2019Vasilije Perovic 1
Results with RD53A
prototype modules at ETHZ
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▪ Tests on bare HDIs already done (HV, thermal cycling, power dissipation) →
TrackerWeek November
▪ The first digital 2x2 TBPX modules successfully assembled and operated
(powering and scans) → TrackerWeek March
▪ The first chain of three digital modules successfully assembled and operated
→ TrackerWeek May
26/7/2019Vasilije Perovic 2
RD53A 2x2 TBPX HDI
HDI with adapter PCB HDI layout
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▪ HDIs populated by an external company
▪ Issues:
▪ Unusable pads
▪ Surface degradation
▪ FOD
▪ Flux flow
▪ Etchant damage
FOD and flux are successfully
removed during ultrasonic
cleaning
Cleaning + inspection required
to choose suitable HDIs
26/7/2019Vasilije Perovic 3
HDI optical inspection
and preparation
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▪ Ten digital modules built (without sensor) (S0, S1, S3, S4, S5, S6, S7, S8,
S9, S10) (three with wafer-probed chips)
▪ three with a silicon slab (glued on top of the four ROCs)
▪ four without (HDI glued directly on the ROCs)
▪ Wire bonding done at PSI for the first module, at ETH for the other nine
26/7/2019Vasilije Perovic 4
RD53A 2x2 TBPX module assembly
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▪ The first test is to check the performance of the
SLDOs
▪ A full VI curve is obtained by ramping the
current in predetermined steps and measuring
the input and the output voltages
Observations:
▪ If the SLDOs worked, the chip was
functional (digital scan, analog scan,
threshold tuning)
▪ Parallel powering is beneficial for the chips to
start at the same time
▪ S8, S9, S10 made using wafer-probed chips.
Now we can cross-check if anything changes
when the chips are operated in parallel on a
module.
26/7/2019Vasilije Perovic 5
SLDO testing
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▪ Input voltage with the spread of
~50mV at 4A → 12.5mΩ
▪ Some regulators start up at higher
input current (Parallel powering
scheme for the ROCs is beneficial)
26/7/2019Vasilije Perovic 6
An example of good SLDO performance (S4)
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▪ The chain consists of three
modules at the moment
▪ Option of one more with a sufficiently
long e-link
▪ Modules’ grounds are at different
potentials → thermal contact with
the cooling plate is achieved with a
thermal paste and sapphire discs
26/7/2019Vasilije Perovic 7
Building a serially powered chain of RD53A
digital modules
Module
1
Module
2
Module
3+
PSU
-
Module (chip side)Sapphire discThermal paste
Cooled aluminium slab
|| 26/7/2019Vasilije Perovic 8
Chain powering
Module 1
Module 2
Module 3
PSU
+ -
▪ Voltage drops are consistent with previous measurements
▪ V-I curves take the form seen on single modules
▪ Ground return resistance consistent with bare HDI
measurements → 40mΩ in total including connectors
|| 26/7/2019Vasilije Perovic 9
Threshold distribution
SINGLE
MODULE
CHAIN
WITHOUT
RETUNING
CHAIN
AFTER
RETUNING
Pixel-by-pixel
difference without
retuning
Pixel-by-pixel
difference after
retuning
No change in the threshold is observed after retuning
|| 26/7/2019Vasilije Perovic 10
Noise distribution
SINGLE
MODULE
CHAIN
AFTER
RETUNING
CHAIN
WITHOUT
RETUNING
No change in the noise is observed after retuning
Pixel-by-pixel
difference
without retuning
Pixel-by-pixel
difference
after retuning
||
While establishing the communication to a
module, the impedance of the module seen
by the power supply changes, affecting the
potential of the modules upstream in the chain
26/7/2019Vasilije Perovic 11
Noise in the power
Module 1
Module 2
Module 3
PSU
+ -
COMMUNICATION
||
While establishing the communication to a
module, the impedance of the module seen
by the power supply changes, affecting the
potential of the modules upstream in the chain
26/7/2019Vasilije Perovic 12
Noise in the power
Module 1
Module 2
Module 3
PSU
+ -
COMMUNICATION
|| 17/7/2019Vasilije Perovic 13
SLDO - VDDA - S8
ROC0
ROC2 ROC3
ROC1
|| 17/7/2019Vasilije Perovic 14
SLDO - VDDD - S8
ROC0
ROC2 ROC3
ROC1
|| 17/7/2019Vasilije Perovic 15
SLDO – VDDA - S9
ROC0
ROC2 ROC3
ROC1
|| 17/7/2019Vasilije Perovic 16
SLDO – VDDD - S9
ROC0
ROC2 ROC3
ROC1
|| 17/7/2019Vasilije Perovic 17
SLDO – VDDA - S10
ROC0
ROC2 ROC3
ROC1
|| 17/7/2019Vasilije Perovic 18
SLDO – VDDD - S10
ROC0
ROC2 ROC3
ROC1
|| 17/7/2019Vasilije Perovic 19
SLDO – VDDD – S10 – ROC2 – Ramp vs. ON-OFF
ON-OFF cycling
Ramp
SLDO consistently fails if ramped. Ramping involves increasing the
current stepwise, while with the ON-OFF cycling, the supply is switched off
and then on at every step.
||
S8
▪ First observation of such problem
▪ Unusual changes in the module impedance
▪ The output is following the input or is slightly under 1V
S9
▪ Fully functional (one SLDO following the input) ROC1 – A
S10
▪ ROC2 – D – common SLDO failure where output is around 200mV if ramped
▪ Operates nominally if switched on without the slow ramp
26/7/2019Vasilije Perovic 20
Summary of S8, S9, S10
||
▪ The behaviour of S8 does not change depending on the ramp.
▪ A hint may be in the changing impedance of the whole module
▪ S9 ROC1 – Analog SLDO works fine when not ramped
26/7/2019Vasilije Perovic 21
Failing SLDOs revisited
ON-OFF cyclingRamp
||
▪ Similar problem observed earlier on S5. Since the chips were not wafer-
probed, we have just erroneously assumed the SLDOs did not work
▪ S5 ROC2 Analog
26/7/2019Vasilije Perovic 22
Failing SLDOs revisited
ON-OFF cyclingRamp
||
▪ S5 ROC1 Digital
▪ Switches on even when ramped but only
at 5.3A input current (limit of the chain)
▪ Behaviour with ON-OFF cycling is normal
but the input impedance of the module
behaves differently
26/7/2019Vasilije Perovic 23
Failing SLDOs revisited
ON-OFF cycling
Ramp
Ramp
||
▪ Obtained a programmable current source to control the current ramp speed
(Special thanks to Alvaro for providing the supply!)
▪ The idea is to check S5 and S10 (three SLDOs in total), while S8 and S9
were sent to CERN
26/7/2019Vasilije Perovic 24
Failing SLDOs revisited
|| 26/7/2019Vasilije Perovic 25
S10 – ROC2 Digital SLDO
▪ The transition between the two behaviour modes occurs within 2ms
difference, i.e. the switch-on works reliably for ramp time of 16ms and fails
consistently for 18ms ramp time.
▪ Relatively close to the limit achieved with the power supply (approx. 5ms to
6A)
|| 26/7/2019Vasilije Perovic 26
▪ A good SLDO on the other hand can easily work fine with ramp times of up to
one minute.
||
▪ We did not manage to start it with the fastest ramp achievable with the power
supply. The measurement was performed with the TTI supply.
▪ Is it possible that at these ramp speeds we run into problems with
inductance? If yes, such chips should be marked during the wafer probing
26/7/2019Vasilije Perovic 27
S5 – ROC2 Analog
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▪ Starting with an increased current works but
1) It is pushing the current to the limit of the module/chain
2) The switch on occurs at a higher current than normally observed with the
previous SLDO tests
26/7/2019Vasilije Perovic 28
S5 – ROC2 Analog
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▪ Slow ramp results in a high start current. The starting itself seems insensitive
to the ramp speed provided that the current can be reached
26/7/2019Vasilije Perovic 29
S5 – ROC1 Digital
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▪ A fast ramp can switch the SLDO on
at a lower current as expected
▪ A delay is seen when ramping for
10ms (close to the limit)
▪ 11ms ramp results in a failure
26/7/2019Vasilije Perovic 30
S5 – ROC1 Digital
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▪ To do:
▪ Build more modules and continue testing
▪ Systematically measure behaviour in different failure modes
including the source of the failure (S8 and S9 are at CERN)
▪ Check for temperature dependencies etc.
▪ Check if the ramp speed limits change in a chain when different
modules are switched on and the potential changes.
▪ Wishes:
▪ SCCs with “failed” SLDOs, those with any anomalies. If you are
happy to give some for (temporary) adoption, please let us know.
26/7/2019Vasilije Perovic 31
Next steps
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▪ Assembly
▪ 10 digital modules built (no sensor), three of which with wafer-probed chips
▪ SLDO test showed two main modes of failure
1. Output following the input with an offset
2. Output remaining low (around 200mV)
▪ Sometimes the “failure” was due to the nature of the current ramp, except in
S8 where the failure was not resolved by increasing the ramp speed. The
impedance of the module still behaved unexpectedly.
Two ways to resolve the start-up were noted:
▪ The limit for the ramp to get the SLDOs to start is around 10ms. Possible
problems with the inductance?
▪ Increase the current (may not work when already operating close to the
limit)
We propose to implement VI scan with ON-OFF switching into the wafer
probing procedure and mark the chips that show different behaviour
26/7/2019Vasilije Perovic 32
Summary
|| 26/7/2019Vasilije Perovic 33
|| 26/7/2019Vasilije Perovic 34
S9 ROC1
Wafer probing results
|| 26/7/2019Vasilije Perovic 35