IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 40, NO. 2, APRIL 1993 114

Results of a Modulator Pulse Top Ripple Reduction Study

Curtis B. Figley, Member, IEEE

Abstract-This paper describes the design of a modulator which can produce high voltage klystron drive pulses with minimal ripple on the top. The design study focused on ways to reduce ripple and adjust the shape of the pulse to minimize variations in the final output of the klystron. Comparisons of the pulse performance for a range of possible loads were done to determine the sensitivity of the design to load characteristics. The resulting modulator design incorporates dual pulse Forming networks and uses a cancellation scheme to reduce ripple. The basic design, simulations and the performance of a low power prototype are discussed. A high power klystron modulator de- sign is summarized.

INTRODUCHON

E Saskatchewan Accelerator Laboratory (SAL) has T” recently completed the design of a modulator which can produce pulses with minimal ripple. The first high power modulator, which is presently being fabricated, will be used to drive a transformer coupled high power klystron. The load used in the study covered a range of typical values for the leakage inductance of the step-up pulse transformer and the stray capacitance of the klystron socket and support circuitry. Because the performance of the klystron transmitter depends critically on the drive pulses, special attention was paid to the ripple and rise time of the high voltage pulses.

The modulator was to be versatile in terms of impedance range, power level and pulse shape. The following speci- fications were used as a guide in establishing the initial component values. Typical load voltage and current re- quirements were 23 kV and 3300 A as measured at the pulse transformer primary (yielding a 75 MW peak, 75 kW average input to the klystron). Pulse top widths were to be between 1.2 ps and 1.8 ps with a pulse repetition fre- quency (PRF) of up to 360 Hz. Transition times were to be as short as possible to limit wasted energy while maintaining at most +0.05% RMS maximum flat top ripple.

Several different designs for the pulse forming network (PFN) were considered. Historically, these networks have been configured in a multitude of ways to optimize vari-

Manuscript received October 16, 1992; revised November 28, 1992. This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC).

The author is with the Saskatchewan Accelerator Laboratory, Univer- sity of Saskatchewan, Saskatoon, Saskatchewan, Canada S7N OWO.

IEEE Log Number 9206813.

ous pulse characteristics. For this project, a Guillemin “E’-style arrangement [l] was selected due to its simple construction. Generally, one or more networks are ar- ranged to give the proper output impedance while using realizable component values. Normally, the “E” networks are arranged with the mesh sections essentially identical. Subtle tuning of the relative inductance values along and between the networks is used to shape the output pulse. This can be a laborious and difficult process when the number of sections or networks is large or when extremely low ripple is desired. The following design simplifies the tuning procedure and provides a technique for obtaining excellent ripple performance.

Fig. 1 shows the basic design with sides “A’ and “B” connected in parallel to form the modulator network. The parallel arrangement was used for two reasons. The first reason was that to achieve the impedance with a single network implied an inductance smaller than in the paired case by a factor of four (assuming the total capacitance remained constant). The dimensions of a coil providing this inductance had inadequate spacing between turns and made it difficult to position the section capacitors. With two coils, the inductance of each was larger allowing reasonable physical dimensions and less stringent layout restrictions. This logic could have been extended to even more PFN banks, but increasing the number would have entailed the added expense of greater circuit complexity.

The impedances of the two lead sections were increased in order to limit the rise time and stress on the circuit. The initial impedance mismatch resulted in a smaller fraction of the pulse being applied across the load. The impedance of the first section of side “B” was increased by extending the inductor and of side “A” by a combina- tion of adding inductance and removing capacitance. The matched electrical length of the banks was preserved by an extra section on side “A.”

The second justification for the parallel PFN arrange- ment was the possibility of ripple reduction. Superimpos- ing the two networks’ outputs with the ripple components out of phase by half a cycle resulted in a significant improvement. The required phase shift was introduced by the extended first sections. The difference in the electrical “length” of the two extended sections produced the re- quired shifts.

A disadvantage of the cancellation technique was the increased rise time resulting from the loss of the higher frequency components. The number of sections required

0018-9499/93$03.00 0 1993 IEEE

I

FIGLEY: MODULATOR PULSE TOP RIPPLE REDUCTION STUDY

rE$L:!$F-7 &=0.5-2.2uH ADJUSTABLE IN TWO RANGES C;, = 2 x 3.2nf IN PARALLEL I I I I I I I I I

r I I I I I I 1

W E N D E D SIDE “A” PFN (21 SECTIONS)

115

CHARGE CHOKE/TRANSfORMER srw DOWN . m i , PRIMARY L=Z.JH

5H LFIL, MAIN HVPS

TRANSFORMER

Fig. 1. Simplified schematic of the high power modulator design. Note the extended lead sections on each pulse forming network that are used to tune the relative phase shift of the ripple.

for a particular rise time is therefore higher than in the standard designs.

The preliminary component selections were based upon the well developed design procedure for PFN’s (see for example [2] and [3]) . An estimate of the number of sec- tions N (if N s 1) in the standard E network is given by the equation

0.63‘pu [se N = - ‘rise

where rpulse is the half power pulse width and rrise is the fastest required rise time. The section time delay T, and characteristic network impedance 2, are derived from

‘, = -=4- ‘pulse L N C N N

where L , and C , are the section inductance and capaci- tance. The maximum value of the primary inductance of the charging inductor/ transformer combination (L,-,,RG,) can be found from the resonant charging condition and PRF by

The factor of 2 N results from the pairing of two similar networks, while the factor of 3 / 2 arises from the capaci- tors used to modify the relative length and impedance of each side.

The simple equation for N yields a value of about 10. Due to the expected rise time degradation caused by the loss of the higher frequencies, the value of N was some- what arbitrarily chosen to be twice this or N = 20. The estimated values of L , ranged from 0.5 pH to 2.2 p H while C , was fixed at 6.4 nF and L C H A R G E was initially 2.9 H. With a fixed capacitance the total pulse width varied from 1.1 ps to 2.4 ps, depending on the network impedance.

The PFN sections were formed by distributing pairs of capacitors along each coil. Paired capacitors were utilized to reduce the current in and minimize the series induc- tance of the capacitors. In addition, by selecting pairs, minor capacitance variations could be corrected. This also provides a simple way of altering the impedance since individual capacitors of C, /2 may be removed.

SIMULATION AND PROTOTYPE RESULTS

A simplified version of the modulator was simulated using the circuit analysis program PSpice [5]. The net- works, loads and tuning were adjusted to gauge the effect on the modulator performance.

116 IEEE TRANSACITONS ON NUCLEAR SCIENCE, VOL. 40, NO. 2, APRIL 1993

To facilitate simulation, the thyratron was replaced by the voltage controlled switch modelled in PSpice. The switch model is essentially a voltage controlled resistor. This implied that in the simulation the “diode like” action of the thyratron was ignored. This assumption was acceptable if the reverse currents were small and occurred only during the reverse recovery period of the thyratron (typically several tens of microseconds). During recovery, the plasma discharge within a thyratron is still present and will pass reverse current. However, the presence of the reverse current tends to hasten recovery by generating a reverse voltage on the thyratron. This limit is a problem only when severe negative mismatches occur during faults. The inclusion of an inverse diode circuit minimized this effect by shunting reverse currents into a matched load.

Parameters not included in the simulation were the frequency dependent resistance and the series inductance of the capacitors, the stray capacitance of the enclosure surrounding the PFN’s and the saturable inductor in series with the thyratron. These effects were left to the prototyping stage for further consideration.

The charging circuit was analyzed to determine the value of L,,,,,, needed to give a short period of relatively stable PFN voltage before each pulse. Decreas- ing the charge choke to 2.3 H produced a 200 ps null in the current and ensured that the charge cycle would be completed. The peak current in LCHARGE is 8 A giving a RMS current of 5.8 A.

The simulation was configured for the load shown in Fig. 1. This load could be configured to represent a wide variety of terminations by altering the relative values of each element accordingly. The loads for the analysis were divided into four broad categories depending upon the dominant components in the model.

The complex load used the values L , = 2.5 pH, L, =

220 pH, and C = 32.5 nF. These values are typical equiv- alent circuit parameters for a pulse transformer/ klystron combination. The current source used to model the klystron was

I = K,dn5V3

where Kp was the perveance of the klystron cathode, V was the voltage across the current source I and n was the turns ratio of the transformer. Since a real klystron acts as an almost ideal diode, the current source was restricted to conduction in one direction by setting it to zero for V I 0. At the nominal operating point of 22 kV the equivalent resistance of the klystron is - 7 R.

A nonlinear taper or profile was introduced to the inductor values along the PFNs to compensate for the primary magnetization current that was shunted by the transformer during the pulse (which reaches approxi- mately 2% of the pulse current for this pulse width). An example of a typical profile, neglecting the lead and tail end sections, is shown in Fig. 2. This graph shows that fairly subtle adjustments are required to the section in- ductance to achieve acceptable performance.

The success of the ripple cancellation technique was limited by the bandwidth of the delay introduced by the two lead sections. Ideally the delay should have been 180” at a frequency characteristic of the section time constant T,,,. Unfortunately, due to the tapering of the impedance to compensate for load droop and variations imposed by nonideal components, the time constant of the sections varied by about 15% along the networks. In addition, the power spectrum of each PFN’s output would in practice never be identical, making exact cancellation impossible.

To compensate for these problems a bandstop filter or trap was formed by connecting a tunable capacitor and resistor across a portion of the inductor on each leading section. The capacitors allowed fine tuning of the delay between each PFN while the resistive damping flattened the sharp resonance of the trap. The effect, shown in Fig. 3, reduced the ripple transmitted to the load. The higher characteristic ripple frequency resulting from the fine network mesh allowed the physical size of the trap compo- nents to be kept smaller.

A simulated voltage pulse for the transformer/klystron load is shown in Fig. 4. The pulse has a rise time consis- tent with the transformer specifications used in the model. The response of the transformer helped ensure that high frequency ripple did not appear at the output.

Typical pulses for the resistive, inductive and capacitive loads were simulated once the basic tuning characteristics had been determined from the complex load case. The choice of what constituted the “best” pulse was somewhat subjective in each case. The transition speeds could be improved if some ringing was allowed. However, since the primary concern here was ripple, only critically or over damped situations were investigated in any detail. The resistive load had a very high bandwidth. The high band- width allowed the fastest transition times but unfortu- nately did not inherently attenuate or damp the ripple effectively. In the inductive and capacitive cases, the rela- tively poor compliance of the loads improved the ripple reduction since the ripple frequency was high. However, the lower bandwidths also limited the transition speeds and introduced problems with over and undershoot. In all cases, the foregoing concerns could be addressed by judi- cious tuning of the inductance profiles with the worst compromise being in the transition speed.

A “resistive” load was implemented by assigning the following values to the load components. The series in- ductance L , was set at 0.2 pH and C was assigned 40 pF to account for stray effects in a practical circuit. The current source was given the value I = V/(7 RI where V was the voltage across the current source. The values of the section inductances were first optimized by eliminat- ing as much of the pulse top ripple as possible. The trap circuits were then tuned again to minimize the ripple. If the rise time was increased by adjusting the PFN taper, the ripple could be reduced by roughly the same factor as the rise time was increased.

The “inductive” load was similar to the resistive case except that the series load inductance L, was increased to

FIGLEY: MODULATOR PULSE TOP RIPPLE REDUCTION STUDY

0

117

E x p a n d e d S c a l e To i m p h a s i z e R i p p l e

1.15

1.1

1.05

1

0.95

I Normalized Inductance t Normalized Impedance +-

_._ 2 4 6 8 10 12 1 4 16 18 20

Section Number

Fig. 2. Normalized inductance and impedance profiles. The profiles for each PFN are identical.

-3 0 0 3 n F r e q u e n c y (WIZ)

Fig. 3. Frequency response of the combined network outputs. Note the strong attenuation at the ripple frequency of 3.5 MHz.

-2 1 .0 1 k V 1 I I I

-2 1 . 0 2 k V .

L - 9 ov \

R i s e T i m e 540ns I F a l l T i 4 I -20kV I

i 5 6 i 8 9 10

Time ( u s )

Fig. 4. Simulated voltage pulse on the complex load. Top trace has an expanded scale to emphasize the ripple.

5 pH. This was done to simulate the effect of a high leakage inductance in the pulse transformer. The simula- tion was tuned for the flattest voltage pulse across the current source.

The “capacitive” load represented extra stray capaci- tance added to the load. Transition times were largely limited by the time constant of the PFN impedance, load capacitance and terminating resistor value. In this case,

the value of L, was again 0.2 p H and L, was omitted. Capacitive loads of up to 50 nF in parallel with 7 R were driven.

A low power prototype version of the modulator was assembled to test the tuning and capabilities of the design (see Fig. 5). The main inductors were formed from 9.5 mm O.D. copper tubing wound on a 150 mm form. The pitch of the coil is 38 mm giving a total length for the inductors of 1.8 m. Inductances between sections were adjusted with pivoting loops mounted within the body of the main inductor. One tuning loop was centered within each pair of turns forming the inductance between adjacent capaci- tor taps. Varying the inclination of the loop with respect to the main coil axis varied the amount of flux canceled by the tuning loop. A portion of one of the inductor assem- blies is shown in Fig. 6. The inductors were then mounted within a copper lined box to introduce realistic stray effects. An impedance bridge was used to measure the total inductance of each coil. By selecting the area of the tuning loops to be approximately 70% of the cross sec- tional area of the main coil, the inductance could be varied by a factor of 2.4.

The PFN capacitors were made by connecting thirteen 470 pF silver mica capacitors in parallel. The section capacitance of 6.1 nF was slightly lower than the ideal value of 6.4 nF. A small thyratron (EEV CX2535) operat- ing at 78% of its peak repetitive current rating was used as the switch. The transformer was installed with a 1100 R resistor and 220 pF capacitor connected across the secondary as a load. The trap capacitors were set to their lowest values and the tuning loops adjusted to obtain the “best” pulse in terms of ripple and rise time. The trap sections were then varied to achieve the flattest pulse at the load (shown in Fig. 7).

Table I summarizes the simulation and prototype re- sults for the cases tuned for lowest ripple. The loads used for the prototype were the same as those assumed in the simulation. Although the inductances between sections were not directly measured, an inspection of the tuning

11s IEEE TRANSACITONS ON NUCLEAR SCIENCE, VOL. 40, NO. 2, APRIL 1993

_ - times of 1.2 ps and ripples of 0.5% peak.

The ripple and rise time capabilities for all load situa- tions were strongly coupled. If the rise time was mini- mized, there was a corresponding degradation in the rip- ple performance. This effect is apparent in the capacitive case where the tuning in the simulation achieved better rise and fall times at the expense of significantly higher ripple. In the inductive case, the transitions times of the current pulse were limited by the inherent L / R time constant of the load. Due to the long transitions times, the pulse did not have a well defined top. For high series (leakage) inductances, the impedance taper on the net- works required to force the load to comply to the short transition times drastically shortened the total pulse. In these cases, addition sections would be required to main- tain the pulse length specifications. In the resistive case, the simulation and prototype performances were essen- tially identical.

Fig. 7. Prototype modulator high voltage output pulse into a complex load. The baseline of the pulse has been shifted 2.560 V vertically. The vertical scale is 1 mV/div and the horizontal scale is 200 ns/div.

TABLE I SUMMARY OF PULSE CHARACTERISTICS FOR MINIMUM RIPPLE TUNING

Ripple Transition times*

Prototype Simulation Prototype Simulation

Load Peak RMS Peak RMS Rise Fall Rise Fall

Resistive 0.1% 0.04% 0.1% 0.04% 400ns 70011s 40011s 750x1s Capacitive 0.05% 0.04% 0.14% 0.06% 650 ns 750 ns 600 ns 500 ns

Inductive 0.15% 0.04% 0.2%' 0.06%t 800ns 130011s 950nst 172011s~ Complex 0.04% 0.015% 0.05% 0.02% 600 ns 700 ns 540 ns 920 ns

~~~~ ~~

* Rise and fall times refer to the main pulses first and last transitions,

Simulation pulse did not have a well defined flat top due to long respectively.

transition times.

FIGLEY: MODULATOR PULSE TOP RIPPLE REDUCTION STUDY 119

HIGH POWER MODULATOR IMPLEMENTATION Based upon the results of the study, a full scale modula-

tor was designed. An EEV CX1536 thyratron is used as the main switch. The thyratron anode is equipped with a saturable inductor magnetic assist to enhance switching by isolating the thyratron during initial turn on. This induc- tor saturates at about 10% of the main pulse current and subsequently has little effect on the circuit behavior. The reduced commutation losses should result in improved switch lifetime.

Another feature of the design is the opposite rotations or helicities of the inductors. The magnetic field devel- oped around a coil typically has a far field l / r2 depen- dence. When superimposed with opposite senses, the field produced by two coil drops with a l/r3 dependence. This reduces the interference induced in other equipment.

The inductor’s diameter of 15 cm and pitch of 3.5 cm provides sufficient high voltage clearance between the tuning loops and adjacent turns.

The charging high voltage is derived from a delta-wye connected step up transformer [4]. Primary voltage regula- tion to 1% is done by a three phase SCR regulator. Resonant charging through D E O L and LcHARGE typically doubled the voltage on the networks. Final regulation is achieved by “deQ’ing” the charging choke with a low voltage secondary winding. When the proper voltage is reached, a SCR in the charge choke secondary circuit is triggered and the energy remaining in the choke is dissi- pated. Using this technique, & 0.02% final regulation should be possible. The charge diode and choke are protected from fast transients by the choke L,,,p,,E, connected between the diode and the PFN’s.

The final regulation circuit is designed to allow up to 10% of the charging voltage to be clamped. Normally, the primary regulation is adjusted so that its lowest value is just above the final voltage required for PFN charging. This provides a sufficient margin for the deQ’ing to oper- ate and typically limits the loss to about 1 to 2% of the voltage. The extra capacity is included for set up and in case the primary regulator fails and ceases to limit the input volt age.

An end-of-line (EOL) clipper formed from a diode and resistor is connected across the PFN outputs. The EOL circuit forms a comparatively fast discharge path for any inverse voltages appearing on the networks. This provides protection if the event of a low impedance fault on the output which would cause high inverse voltages to be induced on the PFN’s.

The mechanical design of the modulator is straight forward. The PFN’s, main thyratron switch, EOL clipper and high power pulse monitors are submerged in an oil filled tank. The tank dimensions are 2 m long, 0.9 m high and 0.9 m wide. Pulses are delivered to the load via a coaxial cable harness made from either four 50 fl cables in parallel or one 12 cable depending upon the length of cable needed to connect the klystron and pulse trans- former. The oil tank is wrapped in a refrigerated jacket to regulate its temperature and to remove heat produced in

the submerged equipment. The main power supply, volt- age regulators and low power trigger generators are housed in a separate enclosure.

ONGOING INVESTIGATIONS While the full power modulator is being built, addi-

tional studies are planned with the prototype. The proto- type is being upgraded to operate at 5 kV. The original capacitors have been replaced by 6.4 nF (2 x 2.2 nF + 1 X 2.0 nF in parallel) disc ceramics rated to 6 kV to better mimic the final unit. The switch thyratron has been re- placed with a larger EEV CX1622 and the current and voltage monitors have been improved. A low power ver- sion of the magnetic assist has been fabricated to simu- lated the larger unit at full power. The tests completed at 1 kV will be repeated at higher voltages and currents to examine the effects of the magnetic assist, the length of output cable and end-of-line components.

One area of continuing interest and investigation is the thyratron model used in the circuit simulation. A model incorporating displacement currents, plasma quenching after firing and arc voltage effects is being investigated.

CONCLUSION The results of the modulator study indicate that the

design easily meets the transition time and ripple require- ments. The finely divided networks limit the initial ampli- tude of the ripple. This ripple can be reduced further by superimposing the output from two PFN’s out of phase. For the complex load, the combined effect is quite dra- matic since the compliance is already poor at the high ripple frequencies. Compared to the performance of the existing modulators at S A L , this design reduces the pulse top ripple by a factor of - 10 while simultaneously de- creasing the transition times. A full scale modulator has been started, and when completed, tests to confirm the results of this study will begin. The modulator should produce pulses with 0.04% peak ripple (0.015% RMS) with transition times of 600 to 700 ns.

The cost of this improvement is increased system com- plexity from doubling the number of sections. However, since the tuning loops simplify aligning the networks there is little additional effort required. The loops provide a convenient method of adjusting the inductance along the networks. With the offset caused by the asymmetry be- tween lead sections, the tuning loop inclinations along each inductor must match. This visual guide allows rapid tuning. The trap filters add an extra degree of control to achieve the flattest pulses.

REFERENCES [l] G. N. Glasoe and J . V. Lebacqz, Pulse Generators, New York:

Dover, pp. 175-224, 1965. [2] G. W. Ewell, Radar Transmitters, New York McGraw-Hill, pp.

[3] W. C. Nunnally and E. Chu, Power Modulator Technques, Power Modulator Short Course Notes, 19th Power Modulator Sympo- sium, San Diego, CA, June 1990. R. B. Neal, The Standford Two-Mile Accelerator. New York W. A. Benjamin, pp. 412-452, 1968. PSpice, Version 5.0a, released September 1991 by Microsim Cor- poration, 20 Fairbanks, Imine, California.

178-183, 1981.

[4]

[5]