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6 l't ¡r r*
"RESIDUT ARITHMETIC IN
DIGITAL COIIPUTERS"
RAMESH CHANDRA DEBNATH/ M.SC.
BEING A THESIS SUBMITTED
FOR THE
DEGREE OF DOCTOR OF PHILOSOPHY
IN THE
DEPARTMENT OF ELECTRICAL ENGINEERING
THE UNIVERSITY OF ADELAIDE
IVIARCl-i I979
SUIq¡4ARY
The number systems used have great impact on the
speed of a computer, At present at least 4 number systems
(binary, negabinary, ternary and residue) are in use eitherfor general purposes or for special purposes. The calîry
plîopagation delay which j-s inherent to all weighted systems
(binary, negabi-nary and ternary) is a limiting factor on the
speed of computations. tlnlike the weighted system, the
residue system is carry free which is the m¿rln attractj-vefeature of this system and therefore its potentiality in a
general purpose computer, in the light of present day tech-
nology, has been investigated.
As the background of the investigation the binary and
negabinary arithmetic have been thoroughly studied. A ne',r
method for fractional negabinary division, and a correction
on negabinary multiplì-cation have been proposed. It has
been observed that the binary arithmetic operations are fas-
ter thair thcse ir. negabinary syslem.
The residue system has got. problems too. The sign
detectj-on, operations j-nvolving sign detection (comparison,
overflow detection, division) and the resj-due-to--decimal- con-
version are difficult. Moreover, the residue systemT being
an i.nteger: systetn, makes floati-ng poinc arithmetic operatlcns
very difficult. The def:ails of the existing algorithms,/
methods to solve those problems
tigated and drawbacks of those
di scussed.
have been thoroughly inves-
algoritlrms/methods have been
. This thesis proposes a new method on multiplj-cative
overflow detect-ion in the residue system, a technique for
the determination of the first approximation for residue
integer division, algorithms for floating point arithmetic
operations in the residue system and a method for the res-
idue--to-decimal conv.rsion.
In order to verify those proposed methods and algor-
ithms a 16-15 moduli- residue arithmetic unit has been
designed using LS1 components. The unit together with (in
this case) an SDK-80 microcomputer can perform all the
integer and floating poi-nt arithmetic operations.
It has been obse::ved that t'he binary system still- main-
tains its predominance over the residue system in general
purpose digital computers. However, the residue system is
faster where there is no operation involvi-ng sign detection,
and also the carry free property, in very large systems, is
of great i-mportance j-n minimj-sing the chip connectíons and
inter chip delays. In future, investigation should be carried
out on the possibility of using VLS1 components which may up-
set the present conclusions which are generally in favour of
the binary system.
ACKNOWI,EDGEMENT
The autholî likes t'o acknowledge the contributions ofthose who have, directly or indlrectly, assisted in thisresearch and preparat-i-on of this t.hesis. The author ispleased to thank Dr D.A. Pucknell, the project supervisor,
for his invaluabÌe grlid"rr." and encouragement.
The author likes to thank the Radio Research Board of
Australia and the Col-ombo Plan Authority for their financialassistance for this project.
The author would like to thank t.he technical staff of
the Department of Electrical Engineering, University of
Adelaide and specially Mr R.C. Nash for his helping hand inthe computer laboratory.
The author is pleased to thank Mr D.C. Pawsey, senior
lecturer and Mr C.K. Linke, laboratory manager, of the
Department of Electrj-cal Engineerirg, universj-ty of Adelaide,
for their positive help in making a pleasant stay inAusf:ra1ia.
The author likes to thank Mrs Mercaa Fuss for her
excellent typing.
Fina1ly, the
Rani Debnath, for
author wislies to thank his wife, Mrs Asha
'Ehroughout the research.her encouragement
PAPER WRITTEN BY THE AUTHOR
with D.A. Pucknell, "Orr multiplicatlve overflow detection
in residue number system". Electronics Letters, Vol.L4,
No.5, March 1.978, Þp. L29-130.
ERRATA: "On multiplicativenumber system", Electronj-cs
L978, p. 385.
overflor^¡ detection i-n residue
Letters, Vol.14, No.l-2, June
[x]
Fr (ArB)
rr (a. e)
Fr (AlB)
r (n)
Pol (r (n) )
X+V
rn( x, v,....)SX or S (X)
x-
V
NOTATIONS
The highest integer value of X,but less than X. (X may be anarithmetic expressi-on also. )
Floating point au].dition/subtraction with operands Aand B.
Floating point multiplicat1onwith operands A and B.
Floating point division withoperands À and B.
Shift T to n positions left.(_
Pol-arÍse r (n) .
Replace the value of X with V.(/ may be an arithmetic or alogical expression. )
fnputs X, Y ,
Sign of X.
Swap the values of X and Y.
Residue of X with respect tomodule m.
Absotute value of X.
Gate with inputs b, c, . . .lz anooutput ,L at the location 4. on theresidue arithmetic unit (net-t)board.
and G.7 are the co-efficientsA.
Exponent of X.
MantÍssa of X.
E (X)F"n, ,t,]
G (X) 2E(X )
lx l* or [x ]*
lxlGate (qb,c,...Þ,L)
Coef f (a) :> d2 t a-7
Exp (X)
Mnr (x)
:l
0,2
of
Contains.
L/
3/
CONTBNTS
INTRODUCTION
1.1 Introductory Note
1.2 Number Systems an overview
ÏNTRODUCTÏON TO BINARY AND NEGABINARYNUMBER SYSTEMS,
2.L Binary Arithmetic
2.I.1 Binary Addition and Subtraction2.I.2 Binary Multiplication2.t.3 Binary Division
2.2 The Negabinary Number System
2.2.1 Negabinary Number Representation( lnreger)
2.2.2 Negabinary Number Representation(fraction)
2.2.3 Polarisation of Negabinary Number2.2.4 Negabinary Addition/Subrraction2.2.5 Negabinary Multiplication2.2.6 Negabinary Divislon2.2.7 A Correction Proposed on Varrable
Shift Ncgabinary Multiplication2.2.8 Method Proposed on Negabinary
Fracti-onal Divisicn
2.3 Concl-usion
RESIDUE ARITHMETTC LITERATURE REVTEW
3.1 Introduction
3.2 Integer Residue ArithmetÍc an outl j-ne
3.2.1 Addition, Subl-raction andMultipl j-cation
3.2.2 Division
Page
B
B
9
l_1
t4
15
15
15
16
l_6
20
20
22
27
2B
2B
29
29
2c)
1
1
2
2/
23
3.3 Overflow
3.3.1 Overflow due to Addition/Sul:traction
3.3.2 Mul-tiplicative Overf low
3.4 Floating Poj.nt Arithmetic in aResidue Number System
3.4
33
34
34
35
3
1 The Representation of FloatingPoint Numbers
3.4.2 Floating Point Arithmetic
Numbers to
36
36
40
40
43
43
43
44
50
52
59
59
61
65
65
66
66
71,
73
4/
5 Transl-ation of ResidueDecimal Numbers
3.6 Conclusion
RESIDUE ARTTHMETTCTECHNIQUE PROPOSED
ALGORITHMS AND
4.L Tntroducti-on
4.2 Multiplicative Overf l-owAspects
Theoretical-
4 .2.L Logarithmj-c Distribution ofResidue Numbers
4.2.2 Design Ideas for OverflowDetection
4.2.3 Desi-gn Example on OverflowDetection
4 3 General-
4.3.14.3.2
4.4.L4.4.2
4.4.3
¿.Á.a
4.4.5
Division
A Division Processthe first approx-successive approxJ-m-
Theoretical ConceptFloating Point Representationof a Number
Floatiug Point Arithmetic withZero ExponentFloat-ing Point Ar:j thmetic withNon-zero ExponentHow to find the co-eff-tcientof a mantissa
How to findimation andations
4.4 Floating Point Ari--hmetic
4.4.6
4.5 Output
4.5. 1
4.5.2
5.6
5.7
9
5. 10
5.11
Translation
Theoretical- AspectsConversion Prrccedure
ErrorPoint
in the Proposed FloatingArithmetic Operations
.TotB
73
74
74
75
77
79
79
90
9B
108
118
r26
t44
L47
L49
151
153
155
L70
A1
A7
A9
5/
4.6 Conclusion
DESIGN OF A REÀL TIME RESTDUEARITHMETIC COIVIPUTER
1 Introduction
2 Addition, Subtraction and Multiplicat.ion( rnteger )
3 Comparison
4 Overflow Detection
5.5
5
5
5
5
I5
Integer Division
Floating Point Arithmetic
Output Circuit of the RAU
Conversion of Residue Numbers toDeci-mal Numbers
How the Residue ArithmeticComputer Works
FIow to Operate the RAC
Conclusion
6/ CONCLUSTON
BIBLIOGRÀPHY
Appendix- 1
Appendix-2
Appendl x-3
Some fmportant Proofs
Floating Point Val-ue
Table of mantlssa and1exponent "f B
Appen<lix-4
Appendix-5
Appendix-6
Error AnalysisPoint Àddi-tion
of Floatingand Multiptication
Mixed Radix Conversion
Program Listings
A16
A24
A26
À
1 INTRODUCTION
1.1 Introductory Note
The number system has a great impact on the speed of
computer arithmetic which, together wÍth other factors
access ti-¡ne of memories, memory hierarchy and computer
architecture, inflüence the speed of a computer as a whole.
scientific probrems such as the solution of rarge sets of
linear equations, problems embracing the field of structural
design, traffic f-icw, signal processing etc. are associated-
with a great deal of computation. A number system with its
associated arithmetic algori-thms can greatly effect the
speed of computat j-on.
The choice of a number system depends on the availab-ility of efficient arithmetic algorithms. Technology also
influences the choice a great deal. For example, a decimar
system would be preferable to a binary system if technology
could provide low cost reliable ten valued logic circuits.one nuirrber system can offer advantages on a particular cper-
ation, but may be unsuitable from the consideration of over-
all s;peed of computatl-on. For example, in a resi_due system,
mu]-tiplication is faster, however, other operations such as
si-gn detection, comparison and overflow detection are slow
processes" rt is, therefore, worthwhile to investigate which
of the existing number systems can offer the greatest overall
1
2
speed advantage in computer arithmetic for general purpose
computers. The rest of this chapter is an overvj-ew of the
existing number systems and their advantages and disad.van-tages.
Chapter 2 ð,iscusses the arithmetic operations in binary
and negabinary systems. The existing arithmetic algorithms
in the resldue system have been discussed in Chapter 3. A
few improved techr:iques and algorithms for residue arithmetic
have been proposed in Chapter 4 and the design of a residue
arithmetic computer, on the basis of the proposed techniques
and algorithms, has been shown in Chapter 5. Chapter 6 glves
conclusions on the comparative studj.es of binary and residue
systems.
1-.2 Number Systems - an overview
To represent all numbers, a number system must have
unique sets of representation. A number system may be a
weighted system or a nonweighted system. Some examples of
the weighted systems are the binary system, negabinary
system, and ternary system,' whereas the residue system is a
nonweighted svstem.
A nurnber in a weighted system can be expressed as
x
where a.í
of weights. Tf
are the
N
= t aiwii=o
number system is
is a mixed radix
T,IJí ATC
ca1led
sets of integers and øi are the sets
the successive power of radix r,rJ, the
a fixed radix system; otherwise itThe binary sys t.em (w= 2) , negablnarysystem.
system (w= - 2 ) and ternary system (r,0= 3 ) are
fixed radix systems. Examples of a mixed
been given in Appendix 5.
3
in the family of
radix system have
Number systems which have found use in digital com-
puters are the binary system, negabinary system I f], lZl,ternary system [ 3] and the residue system. Tn subsequent
sections brief discussions now follow on these number systems.
L .2 .1 e*ilery. NumÞ_er S stem
The binary number system is a tr¡/o digit (0,1) number
system having a radix *2. The decimal value of a binarynumber depends on the posj-tion of 1. Thus for example
(11011) 2 = L -24+I -23+0.22+!.2r+L.20
= (27) to
Due to easy converslon from binary number to octalnumber (ø=8) and vice versa, some digital computers such as
the TBM-7099, Data General Nova-l, Nova-2 and many others,use the octal system for easy input-output operation. The
conversion of binary number to octal number is done by for-mlng groups of three consecutive bits and expressing each
group as an octal digit (O thrcugh 7). Thus above binarynumber can be expressed in octal form as
(01-1, 011)2 = (::¡r = 3.BI+3.80 = (27]lto
The octal number is converted to binary number by
simply expressing the octal digits in binary forln. Thus
(75)a = (111,101)2.
4
Presently some computers fBM-360, IBM-370 and many
mi-croprocessors make use of hexadecimal numbers (w=t6). The
sixteen digits of hexadecimal numbers are 0,L,2,3,4,5,6,7,8,9,A,B,C,D,E,F. A binary number is converted to hexadecimal
form by taking groups of four consecutive bits and represen-
ting each group by a hexadecimal digit. Thus
(1101, 1111)z = (DF)ro = 13.16t+15.160 = (ZZZ¡ro
l{hen hexadecimar digits are represented in binary form, itgives equivalent binary number. For example
(94)rs = (1001, 101-0)2.
Another code which is often used is the blnary coded
decimal number (eCO). This number is really a decimal number,
the digits of which are expressed in binary form. Thus
(789) r o = (0111, 1000, 1001) uro
B.inary states (0,1) are easily realisaÌ:le in a physical
system and is one of the main advantages of binary systems
and this is the reason why almost all present day computers
use binary number systems. The obvious disadvantage which isinherent in a1-1 weighted systems is the carry propagation
delay which limits the speed of computation for examÞle, inaddition and especially in multiplication which is a process
of additj-ons a¡rd shifts. Another disadvantage is the sign
correction required in complement (1's or 2's) multipli-cation.These are the reasons why the potentiality of other number
systems should be investigated. The speed of arithmetic i,s
particrrlarly important in the growing field of real tj.me
processing in which a v¡jde range of digital computers/micro-
processors are being applied.
5
I .2. Z _NeggÞl-ns.ry Numþe! Svst_em
A negabinary
digit system. But
For example
(a) (1101I) -z
(b) (0100r) _z
like a binary system, is a twosystem,
unlike the binary system the radix j_s -2
1. (-2)a+I. (-2) t+0. (-Z)2+L. (-Z) t+1. (-2) 0
16-B+0-2+1 = (7)ro
0. (-z) u+1 . (-2) 3+O . (-z) 2+t. (-2) 0
o-8+o+o+1 = (-7)ro
The advantage of this system is that no sign correctiorr
is needed for multiplicatj-on. The disadvantages are: (i)
duri-ng add.ition dcuble carries are generated (to be dj-scussed
in Chapter 2) and therefore it is difficult to mainr.ain speedy
propagation of carries, (ii) from examples (a) and (b), it is
seen that when the most signifi-cant l is in an odd posi.tion,
the number is negative and if it is in an even position, the
number is positj-ve. Thj-s means that the sign is implicit.The detection of implJ-cit sign is not so easy as that of
explicit sign as in the case of the binary system, and (ij-i)
from the example (a) it is clear that to repr-esent (7) ro ,
this system needs 5 bits, whereas the binary system need.s only
4 bits (¡ bits for magnitude + 1 bit for sign). Furthermore,
some of the arithmetic operations are not easy. Chapter 2
will dj-scuss its arithmetic operations.
L.2.3 Ternary Number Systems
A ternary lnteger number can be expressecl es
vN
T
r=oai3t
6
where cLí (i=o, 1,, .....,N) are the coefficients and can
have any value of the set (0,\,2) in an ordinary ternarysystem or any value of the set (-1,0,1) in a symmetric system.
This number system, specially the symmetric one, offers poten-
tial advantages fc¡r the following reasons (i) sign conversion
is easy (simple inversion) (ii) roundíng is done by simpry
t::uncating the number to the required numbe.r of <ligits (i_ii)
since the ternary system needs 58% less c1-igits than equivalent
binary number, addition and multiplicatj.on will be faster l+),[s] and there w11l- be a potential reduc'r-ion Ín wi.ring cost Io].
The Russian
ary computer. Itstate logic.
'SETUN' is an
used magnetic
example of
core s lzzl
a symmetri-c tern-
to realize three
A handful of papers j_s avaitabl_e on
ithms lq), [s], [z] and rernary swirching
arithmetic algor-
functions IB ]- [12].
The ternary system sounds promising for the future and
interest is rapidly growlng in the hardv¡are realization of
three vatued logic, [o], Ir:] lz+1.
I.2.4 Res j-due Numbel Sy.stem
The residue number system is not a weighted system.
Therefore its arithmetj-c operations are carry free which isthe main attractive feature of the system. since carry does
not propagate from one resio.ue to the next one, the speed ofaddition, subtraction and multiplicatj.on is faster than the
eqnivalent binary system. Ì.{oreoveri in the case of multip-l-ication, the storing of the partial prorluct is not required.
7
However, sÍgn detection and operations involving sign detec-
tion (comparison, overflow detection and division) are not
so easy as.in the binary system. Furthermore, sj-nce residue
arithmetic is an integer arithmetic, floating point arith-
metic is very dÍfficult. So far as j-t is known there is
only one residue computer developed by RCA [Zg ]. Limited
uses of residue numbers are found in error detection and
correction algorithms lzs] lzll. The details of residue
arithmetic operatj-pns will be discussed in Chapter 3.
INTRODUCTION TO BINARY ANDNEGABINARY NUMBER SYSTEMS
As has been discussed earlier, the binary number system
is a two val-ued (ù,1) number system with its radix (base) 2;
whilst the negablnary system j-s a two valued system with
radix -2. Since two state physical entities are readily
avai-lable the binary system has an advantage over all other
-systenìs. Holl'ever, carry propagation delay is the main dis-
advant-age of the binary system," specially in multiplication,
which involves a series of additions and speed is limited by
the carry propagation <lelay in the additions. For complement
numbers, multiplication needs sign correction for negative
operand/operancls .
fn the negabinary system the si-gn is implicit therefore
multiplication does not need correction for negative operands.
However, this system has got a twin carry problem which iseven worse than that of the binary system, and also due to
the implicit nature of the sign, the sign detection is not so
easy a.s .in the binary system.
Later sections give a review of arithmetic in binary
and negabinary systems.
2.L Binary Arithmetic
2
Any of the
ground to b-inary
standarct books l:0,
arithmetic" Binary
^-'131 ) can give the back-
numbers are presented
B
9
either in signed 1's complement form, or signed magnitude
form or 2's complement form, However, whatever be the form
of representatiorr, the sign is always represented by the most
significant bit (tuse¡ .
2.1,.1 Bina-sy Àddi-Eicn and Su.btr.asti-on
Tables 2.I, 2-2 and 2.3 show the
addition/subtraction of numbers in 1's
magnitude form and 2's complement form
algorithms of binary
complement form, signed
respectively.
Table 2.I
A1gor:ithms for binary addition/subtractionin l's complement form
Method Operation Remark
(i)
( ii)
(ii i)
(iv)
Direct Addition
Direct Subtraction
Addition by Subtraction
Subtraction by Addition
Treat sign bit as a numberas long as the registercapacity for the nunber isnot exceeded.
Add (or subtract) end roundcarry (or borrow), wheneverit occurs, to/fron leastsignificant bit of surn (ordifference) .
7=X+V7=X-VZ = X -V7=X+V
7 is l's complement of Y
Example: è^ddition of (+9) ro ano - (6) ,o in 1's complement.
0,10011, 1001
End Round Carry -->1 0 0010I
0 0011 (sum) "
10
Table 2.2
AlEorithms for binary additionr/subtractionin signed magnÍtude form
Addition
Subtraction
Same
DifferentZ*=X*+V*z*+x*-V*
Signs of X and }/ Operation Sign of Sum
sign (x)
sign (x), if itdoes not overflow;tgn (Ð , if itoverflolvssj gn (x), if itdoes not overflow
sign (x), if itoverflows
sign (x)
*
s]-gn
sign
(z) =
(z) =
(z) =
(z) =
(z) =
(z) =
s]-gn
Same z X* Y* sign
sign
Different 7* - Y* ¡ Yx sign
In Table 2.2 negative number 7* (after operation) is in2's complement form. To change negative 7* to the signed
magnitude form the magnitude of Z*is 2's complemented.
Example: Addition of X +0101 (+5 ) and V -1001 (-e) .
0101100 1
I 1100overflow
Therefore, the sign of 7x is 1 [ =
and the sum is 2's complement form of -4
converted back to signeo magnitude form,
s j-gn ( x)
. This must now be
l
i.e. to -0100.
1l_
Table 2.3
Algorithms for binary addition/subtractionin 2's complement form
Itfethod 0peration Sign bit
(i)(ii)
(ii i)
Di.rect AdditionDirect SubtractionAddition by subtractionof 2t s complement
Subtraction by Adclition
Treat sign bit as a number bitas long as register capacityfor nunber does not exceed.
7=X+7=X-Z=X-
v
vv
(iv) 7=X+V
V is the 2's complement of V.
Exarnple: Additi-on : *(fO¡rand -(7)ro
(0,1010) z(t, t_oo1) z(0,00Lr) z 3
From the study of algorithms in Tabl-es 2.7, 2.2 and 2.3
it is obvj-ous that 2's complement addition/subtraction iseasier than in any other form of representation. However, itis more difficult to form than 1's complement representation.
2.L.2 Binary Multipli cation
Bi-nary multiplication is generally a repeated addition
and shifting process. Multiplication can be performed hy using
one of the following wide-.Iy used nethocls [¡O].(i) Direct Multiplication Method
(ii) Burks Goldstine Von Neumann Method
(if f ) Robertson's !-irst Ivlethod
(iv) Robertson's Second Method
(v) Booth's Method
(vi) A Short Cut Multi-plication Method.
L2
Binary multiplicatj-on with signed magnitude form ofnumber is much easier since it does not need sign correctj_on,.
the sign of the resul't is the Exclusj-ve oR function of the
signs of the operands. The magnitude of the result is simply
the product of two magnitudes (operands). rn the case ofsigned complement numbers, the system needs correction if any
onerlboth of the operands are negative. The Direct Multiplic-ation Method and short cut Multiplication luethod are most
suitable for signeÈ magnitude multiplication. A1l the other
methods are suitable for signed complement mul-tiplication and
these algorithms have the property of needing correction forsi-gned complement multiplj-cation.
A varj-ation of the above techniques is a multipledigits multiplication method [90]. In this merhod the two
LSB of the multiplier are examined at a time and a decision
of operation/no operation is taken accordÍng to the Table
2.4. This technique is sultable for signed magnitude
multiplication.
Table 2.4
Table for decision modes in multipledigits multiplication
MultipJ.ier digits Operation Shift Riqht
00
01
10
11
No operation
Add multiple
Add 2 ' (multiplicand)
Add 3 (multiplicand)
2
2
2
2
13
In quatenary techniques [¡Z] three consecutive bits are
examined and decision of operation/no operation j-s taken
according to the Table 2.5. An extra one bit of storage is
needed at the LSD position of multiplier which is shifted
two bits rlght af'cer each examination; while the partial
product j-s not shifted.
Table 2.5
Tabl-e for decision nLodes inquatenary multiplication
Multipl-ier bits Operation
000
001
0 l_0
100
101
110
111
No operationAdd 1 (muì.tipticand)Add 2 ' (multiplicand)Subtract 2 . (multiplicand)Subtract 1 (multiplicand)Subtract 1 ' (multiplicand)No operation
Exanrple: Quatenary Mu1tiplj-cation with
Multiplicand X = 1100 : Multiplier Y
Initial Partial Product: 00000000Extra storage
Multjplier Register: 1111 i 0011,11 1
I
00001 1
1111
11110100 Subtract X
11110100 No operation
10110100 Addition of16x
Simultaneous multiplication [¡0 ] is a method of hardware
multiplication in which the shifted multiplicand is simul-tan-
eously added to the previous partial product. This technique
is f ast but expensive. Plenty of f -iterature ref erences [:A ]
[52] are available on this technrque.
RoM mulriplicarion IS¡ ] , lS+] i=multiplication.
L4
anothe:: approach to
Integrated circuits for multiplicarion [SS I [SA ] are
al-so avai-lable. These I. Cs can be cascaded to accommodate
nrrmbers of large word length.
2.L.¡ sj¿ar.y Ð:feion
Binary division is commonly performed using one ofthree methods [¡O ]
Method (iii) Non-restoring Method. The ¡nost comrnonJ.y usecl
method is the non-restoring method. The algorithm for the
non-restoring method has been given in Table 2.6.
Tab1e 2-6
Algorithm for binary division by thenon-restoring method
Remainder
Partial- remainder
Quotient
Correction
Rn = 2-rL rn
rn= 2rn-r+ Í-2q")Vgn = 1 if rn-r and Y
Ç[n = o if rn-t and Y
O-(-1+2-n) + î qiI=I
Add (-1+z-o¡
areare
ofof
same signdifferent
sr-gn2-( i-r )
Array
method have
circuit for
divisions irnplementing non-restoring divisionbeen proposed in [Sg] [O¿ ]. An irrregrared
binary division [ZZ ] is also available.
2.2
2.2.1 N .ine¡¡¿ Number
General expression for a
number i-s
resentation (fnteqers
negative radix integer
a(-ß) 6"i
where ai. ß-1
For negabinary the expression 2.I becomes
ø (-2) a"í (-2)'
No lj-teratu::e on the representati-on
abinary number is avai.lable, however, the
of fractj-onal number j-n neqabina-rir system
0
1ß
o
ns|IJ
=
1
1
nTJ
i=o
15
(2. r)
of fractional neg-
general expression
is given by
Q -2\
where0<a-i1
Thus (11011") _z = tx(-2) a+1x (-2)t+Ox( -2)'+lx( -2)r+1x ( -2) o
= 16_8+0_2+1 = (7) r o
and (01111,) _z = 0x (-2) {+lx (-2) 3+l-x ( -2)2+lx( -2) t
+lx ( -2) o
= _B+4 _2+L = _ (5) ¡ o
From above two examples, it is seen that, if the non-
zero MSB is in an even position, then the number is posicive,'
and if the non-zero MSB is in an odd posltion, then the
number is negative.
The conve:-'slon of integer number of positive base to
negative base and vice versa has been shov¡n in [00] - [0e].
2.2.2 lIçqeþf¡_rff lrlumJcer Repres_entation (ffactÍoq)
n.L1=O
a(-2) CL
- i.{- r(-2) -i+l
16
where a"í f (0,1)
The representation of fractional negabinary number
needs two extra bits before negabinary point.thus
Thus
(11.0111)-z
2.2.3 Polarisation gE Ne$þin_AÐa Numbe.r
Similar to, the 'complement'of Binary Numbers there
exists a 'Polarisation' IZO] of Negabinary Numbcrs. The
procedure to polarise a negabinary number can be stated as
follows: Starting from the LSB complement immediate
next bit following a '1' .
Example: (a) polarisation of (5) ro = (0101) -z is
(11!1) - z - (5) ro
(b) Polarisation of (-3) ro = (11-01) - 2 l_s
(0111) -z (3) ro
2.2.4 Neqabinary traction
A truth table for negabinary additicn, ês presented in
[OS], has been shown in Table 2.7.
Lx(-2) r+1-x (-2) o+Ox ( -2) - t+tx (-Z¡ - z
+l-x ( -2) 3+1x (-Z¡ - u
f r aìrgl- lroJ ,o .
L7
Table 2.7
Logic table for negabinary addition
Number
xy Sum, S Carry Cr Co
0
0
0
1
0
0
0
I
0
1
I0
1
0
i
0
ii
00
Twin Carry
The twin carry gro\^¡s to unmanageable numbers as the addition
moves towards the MSB position. However, carry-borrow tech-
niques [Og ] ana llZl can minimize the twin carry accümulatj-on.
The technique can be summarised as: A carry generated in any
bit position is consldered to be a borrow to the next bitposition¡ a borrow generated in any bit position is consid-
ered to carry to the next bit position. Example:
+
(5) ro
(3) ro
(8) ro 1 0 0 0
Truth tables of addition and subtraction, according to
carry-borrow technique, have been shown in Tables 2.8 and
2.9 respectively.
1
I0
I0
0
0
0
it
L
L8
Table 2.8
Addition Truth - Table
Carry
Ci
GeneratedCatry
ci* r
GeneratedBorrow
Bi*tXYBorrow Sun
Bi S
0
0
0
0
0
I
0
0
1
I
0
I
0
1
0
0
0
0
0
0
0
0
0
0
0
I
I1
0
0
1
0
0
0
1
7
0
a
0
0
1
0
0
1
0
0
L
0
0
0
x
0
0
I0
0
L
0
0
I
0
0
0
1
1
I
0
0
0
I
1
L
0
0
0
0
0
0
I
I
L
I1
I
19
Tab1e 2.9
Subtraction Truth Table
Numbers Carry
Ci
GeneratedCarry
Ci+ r
GenerateclBorror'¡
Bi+lxyBorrow Sun
Bi S
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
l-
0
0
1
l-
1
0
0
1
0
0
0
1
1
0
I
0
0
1
0
0
L
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
L
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
I
1
1
1
Subtraction can also be performed by the method of
addition of the polarised subtrahend l'lZ). This technique
is like subtraction by addition of a cornplemented subtrahend
in binary subti'action.
The addition and
have been of a 'ripple
carry look-ahead adder
subtraction methods discussed so far
carry' type. For fast addition, a
has been proposed by Agrawal Izo].
20
2.2"5 Neqabinary Multiplica-uion
The methods of multiplication in negative base have
been discussed in [70] and 114). Hoh¡ever:, a variable-bit-
shift negabinary multiplication process IZg] is an interes-
ting method. In this method trn¡o consecutive l-east signif-
icant bits of the multiplier are examined at a tj-me and the
decisi-on of arithmetic operation,/no operation is t.aken
according to the Table 2.LO-
Table 2.IO
Table for decision modes innegabinary multiplication
T\so bits ofmultiplier
/i+ r V i
Arithmetic operati-onrequired
Number of rightshift
No operation
Add Multiplicancl
No operation
Subtract Multiplicand
However, this method does not work when two bj.ts of the mul-
tiplier are 10. Multiplication of a non-zero multiplicand
with the multiplier 10, will produce zero result according
to table 2.IOi whereas the actual result should be (-Z x
multiplicand). Therefore, this method needs correction. A
correction has J¡een proposed in section 2..2.7.
2.2.6 Negabinary Divi sion
2
2
1
2
0
1
0
1
0
0
1
1
Elaborate discussions on J-nteger di.vision in the neg-
qiven in lzo ] ano [zr ].ative h¡ase systern Ìtave been
Agrawal has
division in
2T
presented the method of negabinary j-nteger
IZS¡, and this has been described below.
(1, b, and q be the non-zero dividend, non-zero
divisor and quotient respectively. The at b and
exp::essed as
Let
poJ.arised
q can be
(L=
Li=o
m-n+ 1Lo
6-r,
4í*n- I6rr- I
4i+n 4i+n-1
6n 6rr-r
&í*r*l eí+n
6"
ai( -2)í
6i ( -z ¡i
c¡ i( -z)í
mç
1=om
b
q
The division is started with a leading zero added to a" and
the most signifj-cant bits (t"ISss) of b alì-gned to a.. The
quotient bit is evaluated after shifting the polarised
divisor one bit to the right. The quotient is taken to be I
if the addition of the polarised divisor is possible. cener-
ally any one of the following conditions exists after shif-
ting the polarised-divisor one bit right when the l-th, quotie:rt
is being evaluated-
(i) o a-i
6'o
4s
(ir)
(iii)
eí+r'-2
Tn- z
0,í d-s
6o
4i+n- 1
6o- r
i+n- 2
n-2
a
6
&g
6o
If condition (fii) exists, the polarised additj-on is always
possible. If condition (ii ) exists, the polarJ-sed addj-tion
i s never pos,sible . If condition ( j" ) exi sts , polarl. sed addit-
ion Ís possible when the rnagnitude of Pcri is equal to or
smaller than the dividend (or thej-s given by the multiplication ofgiven as:
22
partial remainder) . pcri
6 ny e.rí, where ctcrí 1s
Bit No
Value of {cri
i
o
i-l í-2 i-3
I 1
2r0111I
the rightmost bit is 1 when i is even; otherwise it is zero.
Þ'cra 6'Q.rl
However, the method described above is not applicable
to negabinary fractional divisj-on. Therefore, one method for
negabinary fractional division has been proposed in sectj_on
2.2.8.
2.2.7 å correction propgsed on variaþle shiftneqabinary multiplication
Except for one correction, the method j_s the same as
that di-scussed in section 2.2.5.
Table 2.It
Algorithm for negabinary multiplication
Two bits ofmultiplier
ví*L viOperation Right Shi,'t
No operation
Add Multiplicand
Add (-2. rrlultiplicand)
Subtract MultipJ-icand
[-Z'(muttiplicand) is obtained by shifting multiplicand one
position left. ]
2
2
2
2
0
1
0
1
0
0
1
1-
23
The correction is only for V i+ t V i = 10.
EXa¡plç.: MultÍplication of (3) ro by - (10) ro
(3) ro
(-10) ro
(0111) -2101001110
1110(100110)-2 = (-30)ro
According to the proposed correction, the multiplier
is a 2-shift multiplier and algorithm is same as bhat of
binary multiple digits multiplicatj-on (table 2.4) .
2.2.8 Method Prgpo.Ped on_ Nsggþj-nall¿ Fr.a.cjio! Divi sion
The proposeC method assumes that both divisor and
divj-dend are fractional and divisor is greater than dividend
(i.e. X<y). The quotient Q can be written as (from negabin-
ary representation of fractional number section 2-2.2) "
e = atG2)'+ao (-2)'+a-r, (-2)-'*o- r(-2)-'+ t&-n(-2)-n
= -or(2)t+a.o (2) o*r!, a-í(-Ð-í
Let -a (Z)r+æo (2) 0 be represented by two bits QtQo
Therefore
(Negabinary Addition)
ne - QtQs+.'i a-í(-2)-íI=I
If CL_i = 1
(i)
(ii)
If tl-i = ot
(iii)
then
(-r)-í o-í = -1 if:(-f)-''a-í = lif
'then
i is an odd numk¡er.
í is an even number.
(-1)-'a-í = o
24
In the negabinary system -l is repl:esented by two bits,1 1. Therefore, at feast two bits are needed to represent
the set (0,1,-1) in negabinary system.
In other words 0 can be written as
Q = QtQo Iot ( -2) r-Fao ( -Ð ol.z-í
-i+1 -l= QtQu + (-a72 *0"s2
-at2-1+r+ao2-t can be denoted by two bits
Q-i+t Q-í
ThenO-eteo+ Q-í+tQ-í
(fne negabinary point lies just after Qo bit)
n+I
i= InL=
Irs][øaJ ro
X=
l-
nt=]-
Fig 2.I shows the flow chart of negabinary fractionaldivision process, and it is similar to the non-restoring
fractional division j-n the binary system.
Divide 15IO
364
byB l0
v- 3
(00.110007) - z
B( 01. l-0I) - z
1,,
(
00. 1100101 . 101
00.011001
00. L1001
00. 0101 101_.101
00. 0c1 1 1
00.0111
00.1L0101 . 101
00.0111
00 . 111
01 . 10101. r_01"
00.000
25
Addition, since sign does not agreesign agrees with the sign of V. Therefore
QtQo = 11
l-eft shift
polarisation
subtractionsign disagrees with that of Y.
Q oQ't = 00
left shift
polarisat j-on
additionsign agrees with that of Y.
Q-tQ-z = 01
left shift
Therefore
Therefore
polarlsation
subtraction(for zero rentainder Q-zQ-z = L t,since i=3 is an odd humber)
Therefore Q = etQo+8oe-t+Q-tQ-z*Q-ze-z
5- B'
26
tN ( xrY)
i.-0
?5¡: SY
T <_ X_YT + X+ Y
7ST = SY
<_.t Iq<- 00q r9o
Yes ls
?
n
T <-'ir-
X +Y+l
x <- porlt'(il ]
Q+- k:0q
rlq-k
PotI l)X+T <--i+
X+Yi+ t
END
5
T:07
Jlsod1SYST
ls
2
e- ll<- 0l1
Yes
Yes
¡¡. q. e 00-l.l -l
dd
lso,,
<- ltqo-i
- ot
Ye 5
Yes
N
No
No
Yc s
Ycs
Fig.2.1 Fiow chort of negobinory f roctionol division proccess'
27
2.3 Conclusion
The details of binary and negablnary arithmeticmethods have been discussed in the preceding sections. Itis clear from this study that al-l the methods of binary
arithmetic can, with slight modification, be used in neg-
abinary arithmetic. However, the twj-n carry propagation isthe main disaclvantage of the negabinary system. The carry-
borrow technique of additionr/subtraction is serial in nature;
therefore, it is inherently s1ow. The negabinary carry look
ahead adder is complex and has no speed advantage over abinary adder. Polarisatíon, similar to complement in the
binary system, is a serial type of operation,' therefore, it
is a slow process. Negabinary multiplication does not need
correction, but additions of partlal products (pp) are
slower, since negabinary addition is slower than binary
addition. The proposed negabinary fractj-onal divisionmethod is similar to the non-restoring binary fractionaldivision, however, since polarisation and negabinary adoition
are sl-ow in comparison with the complement and binary add-
ition, the process of negabinarlr division is slower than thatin the binary system. Above all it can be concluded that the
negabinary system has no speed advantage over a binary system.
Therefore, other irumber systems which are carry free are well
worth investigating,
3 RESIDUE ARTTHMETIC
I.,ITERATURE REVIEW
3. 1 fnt oducti-on
Due to the carry free property of residue arithmetic,addition, subtraction and multiplication are all faster inthe residue system than in the binary system. However, sign
detection, operations involving sign detection (comparison,
overflow detection) and dlvision are slow processes. Also
since residue ariLhmetic is an integer arithmetic, residue
floating point arithmetic is very difficult. Similar1y out-put translation (resj-due to decimal) which, aÌthough less
frequently usecl, is still a problem. However, due to the
carry free properties, residue arithmetic systems are, well
worth investigating as an alternative to the conventional
(binary) system. A comprehensiwe knowledge of residue arith-metic can be gained from [ze ] , lZgf.
To be of use in any general purpose computer any number
system needs efficient aJgori-thms on sign detecti-on, overflcw
detection, division, iloating point arithmetic and output
translation. Later work in this thesis investigates suitable
i-mprovement in some of these areas for the residue system.
The remaining sections of this chapter discuss resj-due
addit-ion, sr.rbtracti.on. multiplication, existÍng algor-ithms
on division, overflcl detection, floating point arithmetic
and output transl-ation.
2B
29
3.2 Tnteûer Residue Arithmetic an outlÍne
3.2"L Acldition Subtraction and Multipl ication
rf (Prr, þzx¡ þsx,
are the residues cf the
the residue system of
addi ti on/ subt::act ion
There are three
must be considered in
, Þay) and
(Vrqo Pzq, PsA,
operands X and V respectì-vely in
, ñ), then
mn
pn,j)
moduli *i (í=7,2,3,
and multiplication can be expressed as
(f) Ai{dition/subtraction:
lXtVl| !M
where m1
lX'/lr,r
= lnr*.n rql,-r', lpr*.P rql^r,
lnr*tnrql^r., ,lnn* tpnql
M-trl1= I
(ii) Multiplication:
lPrx'Pyll^r, lPr*'P4jl^r,
lPrx'Pr,¡ln r', ,lPn*'PnU,l ^n
Combinational logic or look up tables in suitabl-e mem-
ories can be used to impl-ement addition-subtraction and mul-
tiplication processes. The modulus whj.ch needs the most time
in operation determines the speed of each overall operation.
?t) Di.vi sion
3.2.2a Jhç tvpes of division
types of division [ze ] each of which
contemplati-ng poss.ible implementations.
Category 2z Scaling : Division by factor,/fact.ors of M.
Category 3: General Division : Division by any arbitrary
numbers.
Category 1: Division Remainder Zero :
of division, the dividend
divisor.
General Division is of particular
a general purpose computer both divisor
arbitrary numbers.
3.2.2b Methods of General Divlsion
There are at least two methods for
in a residue system - General- Division I
General Division II I Ze] .
Division I and is restricted by
General Divi-sion I needs a look
numbers 2' (í=0,L,2, ...., N) in
highest. poi^rer to 2 contained in
is formed in memories, where the
30
Tn this category
is a multiple of
interest, since in
and dividend are
accomplishing thís
I ze] , þol and
a special requirement.
up table which contains the
residue form. (u is the
f$ -rl). rhe l.ook up table
address represents the
General Division II process is slower than General
exponent (power) to 2 and the
in residue form. This method
and. the divisor Y
contents gj-ve the value oÍ
assumes that the dividend
and nonzero. The detail.s
2í
x
are posi-Live
gi-ven below.
of
the procedures are
(i) Find c(y) =2k. (Starting with the highest arldress
number ( N) , the contenLs of each location of the table is
compared with V, until 2l' < y .2k*') .
2N:
-c(v) '
and c(y)
(fi) Find the first approximation, F
and G(/) are the numbers of powers of 2
can be found by division of Category 1. )
31
(since 2N
t 2N, r
(i_ii )
chart
Follow the
of Fig. 3. 1-
j-terative process shown with the flow
To determine
[¡n ], it requires on
by fpsqfithmic search technique
average
(3.1)
F it requires
(3 .2)
c(v)
t-he
\ tog, " modular operations [¡o]
After c(y) has been obtained, to find(on the average) additional
(n+2) modular operations
Iterative process needs on the average
(Where n is the number of moduli; c = logz W:/Z-L))
c2
(n+1) modular operatiorrs (3.3)
Therefore +-otal division process requires, on the
averagen; -Log "
c+n+ , * i (n+l-)
operationsmodular (3.4)
32
STA RT
L +-0j <--oQr-êo
i e- i+t
R.<- X- Y.F)
ls
¡itiveRj
L
qL+<_
L+ I
F
YesIsR o?
lsF=0?
F <_ F/2
X<- Ra *ãou
ENO
Fig. 3.1 Ftow Chort 0f Iterot,ive Process inresidue irrteger clivisioll .
33
The first approximation F can be det.ermined by fgg_ç_
{fv¿.çfpn technique [¡O] from the value of E(X) and E(y) "
The steps that are followed are:
(i) Convert X to its mixed radix form (Appendix-s)
and pick up the most significant nonzero diqit
(ii)
auv"
Find
table which
2i' ( í=L ,2 ,
2N < (n-r) <
n(lLux+r )np)
table.
(say).
ç(.(aux+l )np) and c (øu*. nt )
the value
where N is
R
from a look up
of
such that
). Also find
another Ìook up
contains
N),
2N*1. (np mi= I l-
and E (au*np) from
(iii) t¡ind x' x- c(lctu*+1 )np) and determine
radix conversion.
the sign
If sj-gnof
is
X' by another mj-xed
negative c(X) = G(a"np)
and E(X) = n(arr*nr).
+1)np) and E(X) =
i where i = I,2,3, ....N).
otherwise c(X) = c((a
E(lau*+r )np) (e (x)
Similarly find E ( Y) .
u
UX
The F j-s given by
2E(X)-E(Y) (in residue form)
If two mixed rad.'i-x converters and assocj-a.ted look up
F
tahles are
ati-ons.
3.3 Overflory
If m, (i=1,213, n)t_
residue s¡,:stem and the modul-i
then t-he range of the numbers
available, F can be obtained in 2n rr,odular oper-
are the moclul-j. of a par.-ticul-ar
are pairvrise ::elatively p::ime,
that cen be rrniquely represented
l-s
the
of
gr_ven
range
negative numbers
-1] and
34
by M = *.t_, *r. If one of the moduli is even, then- l=r L
of the positive numbers (posit_ive half) and that
{o to tt/z
An overflow is said to have
an arithmetic operation exceeds M
half or negatlve half.
(negative half) are defined by
{¡rt/z to M-1} respecrively.
occurred if the result of
of positiveor the range
3. 3. 1 "a:¿eff].ç¡g due tq ditio subi:raction
An additive overflow can occur if two operands X and
/ are of same signs. rf oper:ands are positive and overflow
occurs, the result falls j-n the negative half. For negative
operands, the result falls in the positive harf. Therefore
additive overflow can be easj-ly detected by detecting the
incorrect sj-gn of the result. Subtractive overflow can occur
if the signs of the operands differ. since subtraction can
be reduced to addition (X + (-y) ), subtractive overflow
detection is similar to the additive overflow detection.
3. 3. 2 ¡4qlÇjplrcel;LvC overf low
When multiplicative overf-'l-ow occurs, one of the two
fol-l-owing phenomena occurs (-r.) the resul-t j-s of incorrectsign (exceeds the range of posit:i-ve half or negative half ) or(i-t¡ the result is of correct sign, but incorreet magnitude
(exceeds M) .
The overflow of 1=irst, category can be detected by
checi<ing the sign of the product- (wheL-her the slgn is incor-
rect)," When overflow is of secon,d catecrory, the following
35
relation I za] is va1id.
G
x
Then G
lxY lr'rx
* c(v) (3.5a)
Fi::st -lJj]-* t* calculated by techniques of General
Division I.x
arithmic search technique.x
time will be needed to find it. However, íf the expresslon
(3.5a) j-s w::j-tten as (3.5b), the division -ltn-l-O can bex
avoided.
c( (xy) r"l)G (X) I c(v) (i.5b)
c((Xy)r,r), c(X) and c(f) can be obtained by fast technique
proposed in [30]. Tf two mixed radix converters are available,
the overflow of second category can be detection with
4n modular operations (3.5c)
Multi.plicative overflow can also be detected by using
a redundant modulus [Za]. The time required. j-s at the most
3 MRC (t',lixcd Radix Conversioir,' Appendix-S) with n+1 moduli
plus 1 modular cperation. This is equivalent to .3n+1
modular operations. (1MRc is equi-valent to (n-Ð modular
operations fAppendi*-s] with n moduli).
3.4 1 tin Point Ari
At present it j.s diffjcu.Lt to perfo.rrn floatirrg point
arit.hmetic in a residue number systenì. There is a lj-mit-ed
amount. of published work on this problem, for example, [¡¡ "]
I xY I r,r
36
has proposed 2 as t.he base of the exponent, while [:Z] has
proposed a base cf 10. However, ho details of floating
point arithmetic operations have been given. The algor-
ithms p::oposed in [¡t] are of particular interest, since
details of arithmetic operations have been presented with
j-lIustration. Furthermore, the format used is different
from the conventional format. The details of the algor-
ithms ha,ve been given in the f ollowing sections "
3.4.1 The representati-on o f ! : o_a_!i¡9. p-e.i¡tç. number:s
A floating number can be represented as
k Me
(u-f ) ì e- is an integer
(,s I o)
(,5 o)
M
^where kl . *t-¿
^
8._X -k ML
L
b
M
M
M
fimii= t
1
and In1 4 Ir2 ( In3 < <mn
3.4.2 Floatinq Point Aqithmetic
LetX
*o* and VU
nIImii= I
and 7 - Fr(x o v) =krL¿z Mo,
arithmetrc operations (addition,
multiplication or division) .
kØ,t
M7M
^awhere O denotes
subtraction,
3.4.2a AlcloJij-thms_ f o¿ floatinq point addj.tionsubtr et- ion
ØX U
(ft is assumed that and X, / are positive)
( 1) F.ind A¿
FI (X!Y )
(2) rf Lø =
If it is
k brv m-a
Let the
(3) rf Az =
k
(4)
ø rf Lø > 2,
I, test whether Á
true Fl(XtY) - X
3l
>Aa
otherwise scale [Zg ]
Uø..
,l
x
m2
result be
mm^x ^ u*'
*o ,* "
mn.
^Tf it is truetest whethe:: ¿.. =
lt
Otherwise, scale k
KR
0,
SO
' ^r-r* t
a
KR
I'ind k= = k* r K*
mm,5+1
^a
b)' +zll a a*O* and the result be KR.
and set Lz = øX ,ì Áz^x.
þuut.to'mn+ I l-S
and m' l
zeros,
is done using redundant mod.ulus rn¡+1.
chosen that (M-1) ¡, + (NI . m¡+t - 1)-¿
(5) Find the
n+1) of k
If o"í are
(6)
set ¿ = 0z
,L=0z
mj-xed radix digits (1"í (i = 1,213,
_ which is associated with moduli mi.z
Otherwl se ,
zero diqi t "
increase ^ z
increase Q-z
denote by
IfU_
& the mostu
n*l, scale k,
signifj-cant non-
bv m and^
+1
0 and.by
by
1
1
rf ^ -zn, set á
z
(7) If U < n,
which can
U ancl á. ,
Tf^<n,qotoz-1 and decrease
âz+n
T_= A ,+ LL+ t mi
permanent table by using
1,, and increase .52 by U.
If ^
> n, increase ¿z- z
rt, go to step 5 "
multiolv kt4
be read fron-r
decrease ¿
by
by
a
step 5.
by /Jz
by
3B
(B) If U
k is normal-ized.7
+1) from look up
+1) and determine
multiply k- by m¿z
n, test whether á. 0. If it is true.
rf^ I o,z
table. Find
( (u lmo. )
( (rulmo.)
I21
2
fetch
lk.l -the sign. Tf
and decrease
sign is
¿ bv1z-
negative
7
3.4.2b Alqorithms for floatins poin! multipl j- cat j-on
(1) Find ln"lr. and lkrln,.{i = n*1, ni2t n+p)
by method of base extension IZe].rl¡,tuttiptication is done using p numbers of redun-Ldant moduli to prevent loss of information due to
multiplicative overflow. The redundant moduli
are so chosen that p < n and
(M-1) 2 m m m m -1).n+pn+I n+2'|(¡r-z14
and 'iln+r ( Irln+! < .... <
(2) Set e.
(3) rf ^ xk
za
k
z
a
Øz
=Ø+e ^.x^x
a0, find k
fíndk -kzxentat-ion of mr
wise, increase
result bv m6,,1!a
l_s
. kA, and
where the
from look
find
residue repres-
up tabl-e. Other-
k and scale thea
if 1_La
. ITI¡ r
read
bv 1,
md q*'
k*
(4) Find the mixed radix
(i = 1, 2, ...., n+p)
arezeros, setu^z= 0
the most significant
(5) If U > n*2, replace k
mn to get k..
digits
ofkz
O=, -z
non-zero digit by au.
(Appendlx-5 ) o"i
If all the digits
0. Otherwise denote
t: +u-n. )
!Ía rn, *t jz
kz
by
and increase ^
by LL-n. If ,5, = n, Set á
by 1. Go to step 4.
39
) and increase
a
0z
and increase L 7
(6) rf u n*1, replace k
7
by (kz I
^z+r
n,
mz
¿ bv1z'bv 1.
table,
If sign
. rf ^
retcrr Icompute
= n,
(M-1)
lk. l
zsetá =0andincrease7
(in resiclue form) fronr
Øz
+ (M-1) and find the sisn.
is posit j-ve, replace k, by (n. l^0 r., , )
and j-ncrease o, by 1
and increase u, by 1
rf [ -7set ó to
zzero
3.4.2c Al-qorj-thrns for f1oat-14q p_g¿n! clivi sion
Let X and / be the dividend and divisor respectively.
(1)
(2)
(3)
rind lk* l*1by method of
Multiulv kx
up table.rI The value ofL
a) rfL >' x-b) lfA
where B
c) rf.
rfd)
and ifrl*1 (i = n*1, n+2,
base-extension.
n+p)
by A which can be read from a look
A depends on and óU
and ¿
and Á
and C ^x
^ x
U
a
q
a
0
0Jr^
^
oq I O,
A=M
[=B.CX
nIT mií= 13
a
and
:îTm1
+t i-= ^
A M
B . D where
l
x-Áa*tA
^
If^<^,x u.
L x
^ X
a
qMA
^ x
nf = Tmii=n+ó y-,5 ,+ t
decrease a. by 1 and increase ^-
byz'n
(4 ) l-ind k (kx. A I kt) by scal-ing.z
k = 0,(rrz
division i,s undefined)
ltO
3. 5 Translation of Residue Numbers to Decimal Numbers
A number j-n residue form j-s not readily understand-
able. Therefore the resiclue systern needs a provision for
translating residue numbers to decimal numbers. Since
output translation is l-ess frequently used, more time can
be al-lotted for translation than for arj-thmetic operations.
The Chinese Remainder Theorem [ZS] can be used for
output translation provided that the system has the fac-
iJ-ity of mod-M operation. The A(X) method [34] does nor
need mod-M operation, however, it needs super modulus to
determine a(X). and the method is applicable only if the
base tÁ) (in this case 10) is pairwise relatively prir".e with
mi. Benerjee and Brzozowski [35] pointed out that the
method of base extension [24] can Ue used provided (i) gcd
(ø,mi) =1 or (ii) gcd (w,mi) I 1 for only one modulus and
(¿l ) ffi; for that particular modulus.I
lgca stands for greatest common djvisorl
3.6 Conclusion
It is obvious from above discussions that addition/srii¡traction and multiplication are straight forward operat-
ions; and delay is equal to the delay of one modular cper-
atlon. The c)peration-s can easily be j-mplemented with memor-
i-es (took up tables). Therefore there is no real problem inpractical implementation of these operations.
Division , hov/ever,
tion and multipJ-ication.
is not so easy as
Determinatlon of
addition/subtrac-
the first approx-
imation F which needs f-n12
logz c + n+
4t
moCular operations,)
using logarithmic search technique is obviously a t.ime-
consuming operation. However, fast division technique can
red.uce that time (for determination of F) to 2n modular
operations. This
faster. Still an
technique can be
improvernent, is
irìêêrrs that the dlvision process will be
investigation, whether a fast division
:Lmplemented in a different way with speed
wc::thwhi1e.
Mu-t-tipl-1 cative overf low detectlon in redundant res-
i.clue system is faster (3n + 1 modular ope::ations) than in
non-redundant system (4n moclular operatjons). However, a
redundant system needs an extra modular operation which may
not be desl::able. The choice of redundant modulus may be
critical. This means that if the redundant modulus gets
large, implementation of operation with that modul-us may be
difficult and operation may get slow. Again, the introduc-
tion of a redundant residue decreases the available range
of tÌre system which may not be appreciated. Therefore an
alternate approach Ís to choose the non-redundant system
and carry out an investigation for faster overflow detection
technique.
As discussed earlier floating point multiplication
and divj.sion need p numbers cf redundant moduli to prevent
loss of information due to rnultiplicative overflow. This
compels the system to have the capacity of (n+p) modular
operation units anC the capacity of l.iRC hrith (n+p) modul-i.
If p is large e"g" (p=n) , then MRC with (n+p=2¡) may be
difficu-lt. If p is chosen to be smaLl-er, each redundant
42
modulus u¡ill get larger (to meet the requiremenL stated
before) and mechanisation will be dj.fficult. Therefore it
is worthwhile to investigate alternative floating point
aì-gorithms and particularly those which can be implemented
wlthÍn the intege.r- residue ar'-ithmetic env-ironment.
In output translation, the Chinese Remainder Theorem
needs arithmetic r..'-ì-th mod-M which is a costly affair. The
A(X) method is restr'icted by the requirement tha'f: (ø,m. ¡
must be pain^lise relatively prime. In conversion of resiclue
numbers to decimal numbers, the base is l-0 which is a com-
posite of 2 and 5; and a residue system generally has one
even moduJ-us to have well-defined positive half and negative
harf; therefore the above requirements cannot be fulfilled.
The methocl of using base extension covers a wide range of
situations. However, in a system where IJ) . *i and gcd
(w,m=) I I, the base extension method Ís not applicable.a
fn that situation an alternatj-ve method must be investigated.
The next chapter proposes a
to the above problems.
few algorithms relating
APPEND TO CI{APTER 3 OF THTSIS
"Residue Arithmetic in D'igital Computers"
R.C. Debnath
FURTHER RELEVANT PAPERS
Jul I ien [82 ] establ i shes that the residue operations I i ke
addition, subtraction, mult'iplication and scaling can be easì1y'impl emented wi th I ook-up tab'les j n currentìy avai I abl e ROMs . He
also contends that scaling by the metric vector estìmate process ìsei ther equal ìy or more h'igh'ly ef f i ci ent than the exact divi si on
techni que. Res i due arì thmet'i c operati ons ( addi tì on , subtracti on ,
mul ti pì i cat'ion and scal i ng ) ímp'lemented wi th I ook-up tab'les ì n h'igh
densjty ROM can allow for a high speed digital processor.
The conversion of a residue number to a b'inary number is not an
easy process. The method based on the Chinese Rema'inder Theorem requ'iresresidue arithrnetic operation with Modulo-M, and ìs therefore a costlymethod. A nrore efficjent method is to use the Mixed Radix Decodìng
technique [83] " This technìque needs less memory ìocatìons and can
also be ìmplemented wjth current'ly ava'ilable ROMs or PROMs.
Add'i ti onal Ref erences : -
G.A. Julìien, "Residue number scal'ing and other operat'ions usìng
ROM arrays", IEEE Trans. on Computers, Voì .C-27, N0.4, AprììI978, pp.325-336.
t82l
t83l . A. Baraniecka and G.A. Jul1ien, "0n decoding techn'iques forresi due number system real i zatì ons of di g'ita'l si gnaì process i ng
hardware", IEEE Trans. on Circqits and Systems, Vol.-CAS 25,
N0.11, No. 1978, pp.935-936.
44
from the following groupings of the numbers from 0 to M/2.
Category 1-
Category 2
Group-0 =Group-1 =Group-2 =Group-0 =Group-1 =)Group-2 =)
(0,1);
(2,3,
((uf ,
(0,1) ;
(2,3,
((+þ ,
(M þ -rt(M
1,f +r, vr/ 2)
tr\f -tM/2)
From the groupings of the numbers, it is clear that-
no overflow occurs for (Group-0) . {(Group-1) or (croup-2)};
but overffow will occur for (Group-2) " (Group-2). Howe\/er,
there is no certainty whether overflow will occur for(croup-l-) . { (croup-1) or (croup-2)}. Even if overf low
occurs, it is not clear whether the product exceeds P(>z\ or
N(%) or (M-1). This is due to poor resolutÍon of nurnbers ingroups 1 and 2. Therefore a 'Logarithmj-c Distribution' which
gives hiqh resolution of numbers in groups is proposed.
4 .2 . i- Loqarithmi c Di stribution of resldue numbers
The numbers 0 to M/2 (positive half ancl the highest
negatj-ve number) are distributed among several groups accor-
ding to the tabl-e 4 . L.
r\f *t,
If g(x) and g (V) are
pectively, then it can be
(apr (a)) I rhat
Case (i) : if g (X) +-
case (ii) ; if g (X) +
Case (ii.i) : if tj(X) +
the group numbers of X anC l/ res-
shown from Table 4. i I Appendix-l;
U , no over,'ll-ow cccurs;
U, overflow must occur.
LJ, or¡erf J-ow may or may not-
45
occuri hohrever, if it occurs, the product will be of
incorrect sign.
Tabl-e 4 . L
Distribution of Numbers
0
1
2
3III
^ _1"
..-6+ l,s- tlw.¿
rñ-2Ár2
^_^+ 3vI .¿
Numbers
0
1
-3W -2-^*t
-> w.2-L*u
--> w .2
1
1
-^+^-1
-^+(Á+r)
-^+ l^+2)
qLa-up.
Á+1
u-L
-^+^vr.2
w.2
w.2
-,5+(Á+t)
-¿+(A-t)
-+. VrI.2
¿ w-2I,I
-+
W 1
-1
M/2
^
fwn"r" a n*1, such that 2n S lr{ < 2n+l; in
the highest power ro 2
wL
Q4í' and ¿ q/2
contained in 2M.
+ 1. When A is odd
other words U is
When A is even,
, vr= (yþ, and
^
nurnber
rounded
number
tq*t) /zf
or
However, in most1,
ï'rí'CASCS
the
or
value of W.
1)L a Lt
whe.re L is the
is not an integer
integer value of
The lowest
¿-1) is ¡tre
lowest integer
in the (a +1. ¡t h
ëþnumber. fn those cases closest higher
wþ to be the,M-'l1)':-s chosen
jn the (¿-i)th
integer value
group (i
of L/2,
in (a-ir-l-)th group. The lor,vest' rrumber
46
group (k = I ,2 , , ó -3 ) is given by 2k .w. However, Íncase (iii-) in some situations, mult1plication of two high-
est numbers in two separate groups may be equal to orgreater than M (due to rounding error and choice of the
closest- higher integer value of (\iþ or ë-þ for w) . under
these circumstances a minor adjustment of the highest int-eger is needed. The higl-rest number of the higher group ofthe two is clecreased by a minimum nurnber¡ say o, such that-
the product of the decrease¿ num¡er and the ot.her highest
number becomes l-ess than M. The lowest number of next
higher group (w-ith respect to the higher group of the tivo)
is d.ecreased by the same number cx,.
is a rational
or ëþnumber)
Tf7,
olf is an integer
and even, then
number (i.e. M or M/2
(Á-l)th group is to be increased by 1
ber of the (,s-Z¡th group is increased
Example 1:
16x15x13x11 = 34320
M < 216 ; therefo::e rj =
= 185'256¡ therefore W =
76/2+1-9
17160
lowest number of
the highest nuin-
1.
and m = 11,
r6.
l-86.
m 15, m =
t.he
arrd
by
13If m = 16,4
construct a
3
'group2
table' .
I
Solution:
(i)
(ii)
(iii )
( rv)
(v)
(vi )
Jvl =
2t5 <
þ(l{
^M/2 :
Table 4.2
47
Table 4.2
Group table for Example 1.
0
l_
2
3
6
L2
24
47
93
186
372
744
1488
297 6
5952
1 1904
->
+
---+
+
-à---+---i
+
5
l-1
23
46
92
185
?77
743L487
2975
5 951
11903
77L60
Group
0
1
2
3
4
5
6
7
B
9
l_0
11
T2
13
L4
15
Numbers
Example 2z Form=2,3
construct a
m=3,andm=13,2\
'grou.p table' .
Solut.ion:
(i)
(ii )
(iri)
(iv)
(v)
(v-t )
Pt=2x3xl-3=78
2e < M < 2t,' therefore U = 7
ëf = 6'24;thereforeW=7
^ = (q+L)/2 = 4
M/2 = 55
Table 4.2(a)
4B
Table 4.2(a)
Group table for Example 2
Nr¿ntloers. qroup
0
1
2
3
4
5
6
0
1
2
4
7
L4
2B
3
6
13
27
55
-+
--'__>
---+
It is seen from the table 4.2(a) that the product of
6 (ttre highest number in 3td group) and 13 (the highest,thnumber in 4"" group) is equal to 78 (=M) . Therefore the
hi.ghest number of 4th group is replaced by 1,2 and the low-
est number of 5th group is replaced by 13. The correct
'group table' is shown in table 4.2(b).
Table 4 .2 (b)
Correct Çrol1Ð table for Example 2
Ntimbers GEalB
0
1
2
3
4
5
6
0
1
2
4
7
13
2B
-+_.>
-.->--b
3
6
I227
55
49
Example 3: Ifm=2,m=LL,andm=32t
consl-ruct a 'group table' .
5
Solution:
(i)
(ii)
(iii- )
(iv)
(v)
(vi )
¡4- 2xtLx5 = 11-0
2e < M < 27 ; therefore rj = 7
ëþ = 7'4L; therefore W = I
ó - (a+I)/2 = 4
M12 = 55
Construct Table 4.3
Table 4.3
Group Table for Example 3.
0
1
2
4
8
16
32
3
7
15
31
55
Numbers Group
0
1
2
3
4
5
6
Therefore multiplicative overflows can be detected by
(a) testing for incorrect sign of the procluct, and (b) com-
paring the sum of group numbers of multiplicand and multip-lier with the total numbers of groups A. If sum is greater
than U, overflow must occur; if it is l-ess than A, overflow
wil-l not occur:
50
4.2.2 !çç.:gq. J-ùe*_e.s-- f,çr Overflow Detec'Lion
Since the group number:s descrj.bed pr:ev-ì-ousIy are
assigned to the positive numbers and to M/2, and a number
may be positive or negatj-ve, the inf crmat-.ion of slgn aird
magnitude of the number is essent-Ía.l . The MRC (eppendix-5)
is the only way to get sign and magnitude inform.ation.
From the mixed radix digits (MRD) of a negatlve number it
is possible to form the MRDs of its positj-ve 'counterpart'
Iappendix-1, (apl (b)) ].
When number of MRDs gets larger, a par"t.ition between
them is essential. This partition divides the L"iRDs into
t\^¡o parts the most significant part (MSP) and the least
significant part (LSP). If the modulus Mn is chosen to be
even, and is placed at the most signifi-cant digit (t"ISn)
position drt, then ArL contains the information of sign and
falls in the MSP. With the sign informat-ion and MRDs of
the LSP, a look up table is formed for the group numbers
of positive/'counterpart' positive numbers j-n the LSP. ('fne
table 1s formcd from the decimal value (DV) of the MRDs.)
mation
i-tive
sign
the
the
and the MIìD of MSP
IviRDs of the LSP are
DV of the MRDs.)
When the number
whether: the LSP
'counterpart' .
is negati.ve the MSP
is zero to form the
From this information
a look up table is
zeros. (rne table
needs the rnfor-
MR.D of the poG-
(zero-LSP), the
f ormed, as--suming
is formed from
The
Ir{RDs (MSp
group number of a
+ LSP) . Frorn ihe
nr¡mkrer: depencis
observat-ion of
oTì the DV
the range
of all
of
51
numbers in a group of the MSP and the DV of the MSIJ, i L
will be clear that the group number of certain MRDs of the
MSP will transit to the next higher group number if certain
minimum numJ¡er from the LSP is adcled to the DV of those
particular MRDs. Those MRDs may be 't-ermed as 'transition'
MRDs and the min-imum number required for transition as
'transition' number. The transi-tion number is identifÍed
by observing whether the number, obtained as a resul.t of sub-
traction of the DV of the MRDs in the MSP from the lowest
number in the next higher group (wittr respect to the group
of the MRDs in the MSP), falls within the range of the LSP.
Therefore along with the group tables for the IvISP an<l LSP,
there must be one table contain-ing the transition numbers
and another table giving the negative binary values (2's
complement) of the LSP. (ttre transltion nurrtber of the .non-
transition MRDs is taken to be zero.) The transition num-
ber is added to the negative value of the binary number of
the LSP. The carry from the most sigrlificant bit (MSB)
position indicates that the group number of the MSP must
transit to the next higher group. Therefore the carry is
added to the group number of the MSP. The group number of
a number is given by the group number of the MSP, oE the
group number of the MSP plus one if transtion occurs, or the
group number cf the LSP if the group number of tlre I'ISP is
zero.
Overflow j.s detected by comparing t.he sum of the group
numbers of operands wj-th the total number of groups and det-'
ectillq the incorrect sign of the procìuct"
52
4"2.3 Des_i.gn E-:g-Up_lS. on Overflow nClCC!¿p:f
The moduli ffiq = 16, ffi,, = 15, ffiz = 13 and m, = lL
have been chosen for this design example. The MRDs are
designated by î*, &3, &, and ar. The range of the LSp is
13x11 = 143 (0 to I42) and thar of rhe MSp is 16x15x13x11
13xl-l- = 34L7 7 i.e. from 1,43 to 34t71 . The rrighest nurnber
in the LSP is 142 and the MSp is norì-zero for a number
grea'ter than I42.
Examining the
MSP, Table 4
'transition'
4 which
numbers,
Table
shows
can
4.2 and the DV of
the rtransiti-on'
be formed.
tl-ie MRDs in the
MRDs and
Transiti-onNumber
Table 4.4
Transition MRDs and transition numbers
TransitionMRDs
&\, &,
0
0
0
0
1
2
5
L
2
5
10
5
11
8
t
t
t
t
t
t
t
t43286
7IsL430
2660
5863
1 1869
B
9
10
1iL2
73
14
186
372
744
14BB
2976
5952
11904
186- L43
372- 286
744- 7Is
1488- 1430
2976- 2860
5952- 5863
11904-11869
=43=86=?9=58=775
=83=35
The DV of theTransition MRDs
= d\.15. 13 . 11* d2.13 . 11
CorrespondingGroup of the
MRD
The lowestnurnber inthe next
higher group
Figure 4
flow detector.
incorrect sign
sign of the X,
l- show.s the circuit for multiplicative over-
The circuit in the sol id l lnect box detects
of the product. If the Excl_us 1ve OR of the
/ and Z (SX,Sli, andSZ) is '0,, the sign of
53
r- litt,
lxt lx hr IX t,,3 3t
T, 1
þ9]g.lt.t¡¡logates ). NZ( X ):'l'meàns lXlt3 and lXl¡¡åfe r,.'n- zeÌos.
NZtX)DI D2l, l,
xtD3 t, Dl.
SXSX r(x)
i.NZ(X)
ISY
NZ(x )
I( tI(
c(MsP )
l(x )
overtlow Il 'l'
f From 'sign detectort of Z
F¡9.¿.1 Schemotic diogrom forirr the 16-15-13-11
(x)
+9(Y !
I (x) I 1
rF From tgroup generatort ol Y
muttiplicotive overf lc\.',/ det ectío nresidue system.
3
I
S SX
Tsz
NZ(Yf)
I
¿RoM - IT¡ble lor Dl .(Sec f i9.4.2(a))
PRo M- z
Tabta for 02 .(See fig.6.2(b)).
(See f ig' 1,2(d','),
PROM - 4Tabls ¡e¡ e¡ and 01,
P RO M - 3
l¿bte lor D3(See lig.1.2(crt ,
on-zcr05 e
nd I(X).04 are
btT¿ ¡aX m¿âI n
PROM - 5
r a1, sx
a
.)
;t
ber offig. L.
UM lrsec (l
¿B-O-l¡-:--9Tabtc lo r
group
PRo M -flrensitionnumbers.(See fig.
t,
PI
L sIs ee
inary vatue
PROM-8Negal¡ve
BAau:-sTable I o r
grâupnumber ofSP. (S
Futt Adde rs.
Fult Adders.
G(LS
Carry
I
t,
2:lt(x
r¡ e¡F rtecls
PR0M 0r Logic ckt.
Gener¿tes 0VERFL0W signat.
Function of PROM-1 ; (256x4)
It forns a table of D l' where
D, = lo". 1l- + d, lr.,
wlrere tL" amd cL, are the lr{RDs of the LSP.
a If Xr,,- [r^r,l*],,' [.#,,],.2
& lxl ,,I
54
Fig 4 .?-(a) : Function of PROlt{-1
Fig 4.2(b) : Function of PR0M-2
Function of PROM-2 t [256x4)
It forms a table of Dr, where
Dz=lo, !7+et1 5, where
a., and a", are same as in Fig 4.2(a).
Function of PROM-3 t (256x4)
t forrns a table of D 3' where
3 IP¡,. 1*r,, -D Il6 r6
Fig 4 .2(c) : Function of PRONI-S
Function of PlìOtr{-4 ; (256x4)
It forms a t¿rble of ctr, lvhere
tla lxl,u D It5 15
15
D4 lo, | = d.', since 15 < l-616
55
I.'ig 4.2(d) ; Function of PROM-4
Function of PIlOlvf-5 (256x8)
It forns a table of nu, SX, I(X), wherc
&
I6
t1t, if
ln, Dul4
16
SX = '1r if. nu > 7 ; I(X)
Da and Du are nonzero
Fig 4.2(e) : Function of PR0M-5
Function of PROIT{-6 ; 1512x4l
It folms a table of group number of the MSP. If N7(x)
= t0' or tl-r and SX = r0;, the decinal value, DV(O) =
44 . 15. 13. 11 * D+ . 13. 11. If SX = '1' , NZ (X) = r0r and
Du is nonzero, the decinal value, DV(1) = (LS-a.+)
.15.13.11 + (15-Dq).13.11. If SX = rir, NZ(X) =r0rand D,, is zero, the decinial value, DV(2) = (16-a.q)
.1-5.13.11 + (15-D,f)'13.11. If SX = '1', NZ(X) =r1r,the decjmal value, DV[3) = (15 -cL+) .15.13. 11 'r (14-D+)
. L3,1,1,. Tire grou¡t nuntbels arc as-signed ¿lccording to
rhe Table 4.2.
Fig 4.2G) : Func.tion of Pl{0M-6
56
Function of Prom-7 t (s12xB)
It forms a table of rt:cansitionr number
according to the table 4.4.
Fig 4.2(Ð : Function of PR0M-7
Function of PROlt{-8 (512x8)
It forms a table of negative binary value of the
LSP fron its decimal value. If SX = f 0', t-he
decimal value, DV(4) = 42.tt + 4t. If SX = I l- |
and a, is zero, the decrmal value, DV(s) =
(I3-a"r).LL. If SX = 11' and a-, is nonzero, the
decimal value DV(6) = (12-a).11 + (11-ar). e,
and a, are same as shown in Fig a.2@)
Fig 4.2(h) : Function of PROM-B
Function of PROI'{-9 (sL2x4)
It forns a table of group number of the
LSP fron its decinal value (shown in Fig
4.2(h) according to the Table 4.2.
Fig 4.2(i) : Function of PR0M-9
Function of IrROM-l-0 (256x4)
It forns a table of overflow
overfiow) accorcling to
(i) Overflow = '0', if g(X)
(ii) Overflow = rlt , íf g(X)
(not final
= g(V) < L6
= g(V) > 16
57
Fig 4 .2(j) : Function of PR0M-10
the product is correct; otherwise the sign is incorrect..
However, false indication of overflovi is given if one oper-
and is negative and another is zero. The cj-r:cujt rj-qht side
of the circuit in solid-lined box detects whether any of
the operands is zero.
Sj-nce lXlt. and lXltt contaj-n the informatjon on 0.2
and ar it is not necessary to generate 0,2 and a1. This
saves use of one PROM. The circuit in the dash lined box
generates the sign of X (SX), the MRD (ou) and the informat-
ion of nonzero c-+ and Da. Two additional clrcuits- are
required - one is for generation of the sign of y (Sy), the
group number of y (g(V)) and Nl(V) and the other one is for
the sign of the result Z (SZ) .
Performance:
Delay in overflow detectj-on is the delay through the
longest path v¡hich, for the circuit in Fig 4.I, is through
the circuit reqr.ri-red for: overf l-ow detect:ion by the 'group-
ing technique' . Therefore
Delay, D= (Dl =
+ (Dz=
+(Ds=
5B
delay in sign detection)
delay in getting Group Number of the LSP)
B bits adder delay + 4 bits adder delay
+ 2zL multiplexer delay)
delay in PROM-l-0)
delay in OR-gate at the last stage).
Again
Let
Therefore
+ (D+
+ (os
Dt =
m.Ll
J.2
TRoo
T"u"
To*
2Tt + Tz where
access time of
access time of
(?-56x4) pnou
(256x8) PRoM
= delay in: delay in
= dei-ay in
a 4-bit full adder.
2:1 multiplexer"
OR-gate.
D - 2Tt +
= 3Tr +
T2+T3+37
T2 * T¡ + 3T
T1 + Ton+
+
T +
+
where T3 = access time of (512x8) PROM
However, delay in generating group number (Og) is the
delay in generating g (X) . Therefore Dg can be expressed as
Dg Dr *Dz *Da
2Tt*Tz*Ts+37
ADD MUX
T TADD MUX OR
(4.1)
+TADD MUX
using TTL components (raure o. g (a) ),multi.pl-icative overflow detection is given
D = 3 40+60+60+3.7t-
(4.la)
the delay in
h'y
4 + 4
59
The delay in generating grcup number is given by
= 1.2O +L20 -F2I +B
= 269 ns.
= 2.40+ 60+60+3-
= B0+60+60+2L +4
= 225 ns.
(4.l_b)
(4.1c)
Dg 7+4
4.3
The method of division conslsts of two processes
(i) determination of first approximatj-on F, and then (ii)
iterations using successive approximation. (fne successive
approximation is the number which is equal to the previous
approximation divided by 2 ) , Since the group number con-
tains the information on the magnitude of the number, i! ispossible to use the same piece of hardwarerused for gener-
ation of group numbers, for determination of first approx-
imation.
The F determined from the group numbers of the oper-
ands is alwalrs positive, however, division is not limitedto positive operands on1y. The cjetail of the technique fordetermination of the first approxi.mation and successive
approximation has been givenin section 4.3.2.
4"3
The
chart in
Exclrrsi.ve:
(X is the
1 A Division Process
division process can be best descrj-bed with a'flow
Fig 4"3. The sign of the result of division is the
OR function of the signs of the operands X ;"lnd y.
dividend and / is the divisor.)
60
No
No
No
No
l=ig. ¿.9 Flcw cha rt cÍ res¡due integerd iv i sion P rocess
iN ( x, Y )
I
q.û
0
enera)
e vhardware
Is
?
F 0
0, <i- AVi, 4- Y'F
of tlre resutt
Is
+'?
the sígn0oes0verf
7
W Iow
Is
2
W>C hange q to
its negative
fornr .
E NDe sign o
resultthe +t
ls
,,
x <-x- iÂ/X+X+W
q, +pi+l
-+
Yes
s2(
hardware.)F + Fl2.
gene rated by
Yes
YesYes No
61
4.3.2 Hotg to_ f .r.:ê the f :!_r_q! êpp_Ë_o_ì(r]la!-t-A.q
-an-è SUCCCSS]-V e aÐprox-]' mations
T\n¡o look-up tables are required
successive approximation,' one is used
one to get success-ive approximation.
depends on the group numbers g (X) and
t.o obtain F and
to get F and other
The value of I-
g (V) as shown beIow.
(i)
(ri )
rf s(x) > g(x)
rf s(x) < g(Y)
schematic
2e(xl -s(YlF
F 0
(r or successive approximation is tabled irr residue form. )
Fi.rJ 4.4 is a
cuitry required to
The dotted line in
bus can be used to
multiplexer. The
iterations and to
diagram of
successive
the computer cir-
approxination.
eitherXor/data
get F
Fig 4.4
and
indicates that
issue 'previous approximation' to the
function of the computer is to perform
issue X and V to get F or successive
approximation from previous approxirrration.
If the address iines of an available are equal to or
less than the sum of bits of each of the modul-1, then the
cJ.rcuitry in Fig 4.4 Ís not feasible. An alternate approach
rr¡hich needs a smaller number of address .l-lnes to PROIvI is
sh.¡wn in Fig 4.5. Tn this case the PROM forms table of F
(which also gives successive approxinLation), according to
the number output from the subtractor. If the (r:+1)th bit
is 'L' (i.e. negative) , the PROM gives zero value; otherwise
it gives the residue number of 2k (where k is the positive
out--put from t--he subtractor) " The conìputer receives t\,{o sets
of information one j-s F or successive approximation and
the other is the value of c-. r'or lth iteration the
{9(x)re(Y)}Or
þrevious . ,APProrirna tt on'
62
f o r gene rot ionve APProxirnr:ticn'"
X
9r.X)
F or Successive
AÞprox imationt
6rouP
Gene rat o r
c0þ'l
PU
T
E
R
2:1 MuttiPt exer
@sThe Tabtes cl F and
Sqccessiv¿ APProx irnatio nt'
is '0', muttiPtexersetects 9(X) ¿nd
g(y). Atso itdivides the tocat¡ons
of PROM s into two
hatves. 0ne hatflor F ¡ other hatffor tSu c cessiv€.Approx irnatíon"
Prev i ous,dpp rox iÌn at ion'.
9(Y )
Y
C
tDiuid" by 2'slgnal. ¡f it
Fig. h.trI Scl-remGtic "dioçrGm.of F qrì d Succes sc
63
X
9(x )
C
n bits -r
tDiv¡d. b
signat.C.
,2
l' se Iects
(n+r ) bits.
(n+t ) bits
F orS u c c ess ive Appro xim a tio n
Fig.4.5 Schemqtic diogrorn of on olternotecircuit f o;' F ond Success ¡ve
Approximotion.
v¡
I
t
I
GroupGenerator.
2"1
Mutt iptexer2:l
Muttiptexer.
n bits. n bits
Subtracter
c0M
P
U
ïE
R
g(Y )
0ne
Y
c
l b its.
tD
2'l'
ivide byt s ignat.setec t s
0ne.
EIgUrTable for F and
Successive Appro ximation.
n bits.
computer
V) which
j-ssues the value of C (through
equal to C' obtained during
a new value of C' which is
64
the data bus X or
(i-1) th iteration(c-f), and the
l-s
approxintation.
Si-nce
and receives
group number
ulus, it is
For example,
in Fig 4.5
5 address
the
is
number of bri.ts required to represent the
far less than the sum of bits of each mod-
16, 7-5, 13 and LI, the sum cf bits of
Since a 64k PROM (f0 address lines) is
the circuit j-n Fig 4.4 is not
can be implemented
possible to use
1n the case of
lines.
PROM with less address 1ines.
the residue system of rnoduli
each modu]-us is 16.
not yet ar¡a j lab1e,
feasible. Whereas the circu:Lt
Performance
Delay in obtaining F by the circuit j-n Fig 4-4 is
given by
D(1) D
with a PROMs with S,/more than
+ Tuux * Tr (4.2)
= delay in forming group.
= delay in 2:1 multiplexer.
= access time of the PROMs.
the circuit in Fig 4.5, delay is given
D
g
where
T¡,tux
T,
According to
g
by
D (2) D +T +T +TI MUX SUB F
t-rtINV
delay in
(4.3a)
where truu =
Agtrin T, uu =
where Tr*u =
addit-i"on "
delay in subtraction"
ADD.
f nverter,' and TADD
de-laf in
65
Therefore equ.
D(2) = Dg
For 16-15-13-11
(ranre 6.3 (a) ) ,
D (2) 225
(4 " 3a) becomes
+T +T +T +T (4.3b)MUX INV ADD F
modul.i system, and using TTL components
Dg = 225 ns (from 4.Lc) and
+4+3+7+(Tn,=35)
{a- ([Alß] ) ß]ßo
cLz ßl + cLt ßo
274 ns (4"3c)
* for DM751'7, a (gZ B) PROM IEO] l4"4
Thj-s section proposes a new form of representat-ion
of floating polnt numbert it is represented by an integer
multiplied by a suitable base of exponent depending on the
moduli of the residue system. An advantage of this form
is that floating arithmetic can be performed within the
integer residue arithmetic environment. without the need for
any redundant modulus. The lmplementation is therefore
economical-.
4 .4 .1 T'heoretical concs!
If R is the highest absolute value of mantissa of a
computing system, and ß is a posj-tive integer such that
(ß-t)' < R < ß", then any number A within the range from 0
to R can be represented by
A {[Alß] ]ßI +
l-t = 35 nsLF
(4.4\
Where (12 and G, are the co-efficj.ent-s of ßl a,nd ß0
r.e &2 Ialg] and cLt (A--{[Alß] ]ß)"
66
The
SimilarIy
range of
R can be
the co-efficients is from 0 to (ß-1).
represented by
+ rr (4.5)R'- rz ß
Case ( i) :
Case (ii) :
values of R
be denoted
t-.e.
l_.e
For ß2 = R, fz =
For (ß-1)2 < R <
that can satisfy
bY o"o* ttd Rrror
*"o" = (ß-1)ß +
and r 0
the max|mrrm and
al¡ol'e condition
(say)
( say)
ß
2ß ml_n].mum
of ß can
(4.0¡
(4.r0¡
R"r*
rr
r
2 : (ß-1)
r = (ß-1)
(ß-1)2 +
2 = (g-2)
lz
the
respectively and expressecL as
(ß-1) (4.6)
(4.6a)
(4.6b)
1 - (ß-2)ß + 2 ..... (4.7)
(4.7a)
(4.7b)r
4 .4.2 ¡l-o_e!:L¡O point representat j-on of a number
A number X can be represented in floating point form
bv x = Aßt (4. g)
Vthere A j-s the mantissa, and lies within the range
from 0 t'o R. ß is tire base of the exponent which must sat-
isfy the conditions stateci previously, and n is the exponent.
4.4.3 .¡'loating P_o_i4! Arithmetic withzerq-exponent
4.4.3a Fl-oatinc¡ point additi-qn'subtract.ion :with zero -e>(ponent
x
V
= Aßo
= Bßo
A & CL+ß1
= B = b2 ß + It,
67
Therefore
7
7
2
Fl (Xty) (ez 1
Þ
(ct2
2 + (a
br) ß + (a, + 6r)
Where
I2c+c
34A+ßA
(4.11)
(4.11a)
(4.l_1b)
(4. L2)
1
+
c
c
br)
br)(a"
4.4.3a (i) Floatinq point normalisat-ron(def i-ni-t-i on )
A number is said to be normalised i-f overflow occurs
when the nurnber is multiplied by the base of the exponeni.
4.4.3a(ii) Normalisaiion r.q f!.g_?_!r¡q poi4t _è,idi!¿g2lsubtraction (zero-exponen.t)
The process of normalisatj-on in floating point
addition,/subtraction has been shown with the flow chart in
Fig 4.6. The exponent generated durj.ng normalisation may
be termed as 'generated exponent' and denoted by g. In
case of addition nonzero value of g is 1.
4.4.3b Floatinq point mul.tiplication(zer_o exponen!)
7 - Fl (X.V)
From (¿. g) and (4. fO)
z (a b2)ßb)s'
g
2bl)ß + (o,
(aI b+
AAß2
+2 + (4.13)
68
ßW <--c
0oesove
?
w rf I o,¡v
K <- W +c.l
0oesflve?
K rftow
r <-[rc,-[ßlz])/n] T <- [tc,+þ t2Jrlt]l
No {Ê
P +-c, + T
Z: Kßf¡
Ißz P
END
Yes
Yes
T
* These are the steps
for rounding.
Fig.4.6 Process of normotisotion in ftootingPoint res¡due ocldclition /subtroction c
Where bA=&
(4.13a)
69
(4.13b)
(4.l-3c)
(4 . 14)
(4.14a)
A
4
z
2,
2CL
A=a"
a.A
(4,*
bt
b2
br
Again Z can be written as
z c+D) g2+D+ +c2
ß
ß I
2
Where D
D
2c2
2c I
Finally
_ [A3 lß]
= ¡a, lßl
=[a DBIlJ
l-\t
+ IA, D, ß]
z cg ß' i cz ß + cr
Dl + D2)Where ca (Au +
c2
cl
4.4.3b(r) in floating Lo j-ntmultiplicalion (zero-exponent)
Figure 4.7 shows the flow chart of normalisation for
floating point multipJication- The generated exponent, 9,
in case of multiplication, ranges from 0 to 2.
4 .4.3c Fl-oati- p--ar-n! divi s ion ( zero-exponent )
Normali sation
z
rle= Fr(xlY) = ale
= Kß-x (say)
A (1lB) (4.15 )
Where K is the mantissa (wj-thin the range from 0 to R) ,
and x is the exponent. The val-ues of x (except for B = 0 or
l-) 1ie between 2 and 3. The conversj.on of f ls to its equiv-
alen't f loating point number can be done by a look-up tal¡le.
70
Yes
Yes
Fig.l,.7 Process of normolizotion in flooting pointresidue rnultipticcrtion.
¡r These o re the ste ps
for rounLJing.
ßW <-c
oesove rf low
?
P <- W+ c
?
ov erf Iowoes
Scz +
2ï <- P.ß
K +-[(cr- lß12)l/nj K <-[(cz.fß/2]¡7ßl
u+- +c
oes
)T ove rftow
7=UU<-T+c
No
YesDo es
?
U ove rtow
z0
UßT a-[(cr-lß12]l/ßl T <--[(cr*[ ßl2lllßl
E ND
U (- P*T
1L
Isee Appendix-2 for the eval-uation of tls.]
Therefore 7 = A' Kß x
l^ -Y\n K)ß ^ ".... (4.f0)
(a . K) can be evaluated by floating point multiplic-
ation. That is
FI (a K) - vß4 (=.y) (4 .17)
Therefore Z = Yß g-x = vßq-* --a
(4.18)
Where m = q-x
4.4.4 Floatinq point Arithmetic w-ith non-,zero
Vßff
.exponent+
and \/ - B3oLet X -Aß
x-t-
^
where ¿ and t are the exponents of X and y
respectivelY.
Also X and !/ can be written as
(ar\ + o"r) g
(b2g + br)ß
A
t(4.1e)
(4.19a)
V{ithout loss of generality it can be assumed that
4.4 .4a Alqorílhms for alisnment anQ floatinq poin.Ladditi-s¡n/subt-rÈction (non-zero exponent)
Let k - ^-L
Case (i) : if lç = 0, then
Lst step : compute D = Fl (etn¡
= cgg (say)
/5>Í.
72
2nd step Compute p = ^
+9.
lz = cßPl.
END
Case (ii) : If k - L, then
*l-st step : Compute D =
(rr b, is negatÍve,
othenvise [ +ø | Z] )
[tr,, + ¡telzlrle]
acld | -ßlzl;
*2nd step : Compute D' = &n + D; I The
aligned mantissa takes the form of
(0.ß + ¡-).]
3rd step : compute T - Fl (AlD') = cgg (say)
4th step : Compute p = ,s+t; lZ = CßP ].
END
Case (fii) : If k = 2, then
2nd. stcp
3rd step
*lst step : compute D = [tO, + Ltglz]] l àlL-t '-J-'I
Et b., is negative, add [-glz]tLIo'uherwise [+glZ]. The aliçrned mantissa
rakes the forrn of (0.ß + ",].
compute T - Fl (AtD) = cgg (say)
Computep=^+grU=CßP].
END
(these are the steps for making the aligned mantj-ssa a
roundecl f 1gur. e. )
Case (iv) : If k >- 3, then Z = Aß
*
^
73
4.4.4b Floatinq poing multiplicationalqorithms- (-4çp_ zefo e4pp-!S]]! )
z Fl (x. v) (a. s) ßL+t
g1st
2nd
step
step
: Compute D
: Compute p
END
Fl (A'B) = cß
t+L+g t lZ =
( say)
cßp l.
4. 4 . 4c Floating point -d-fyåq--i.a.n alqorithms( no n - z e r o çëpp_qç¡-ï=)
z p1 (xlV)
l-st step :
2nd step :
Compute I)
compute p
END
= Pr (aln) = cß
= ,s+g-t ; lZ =
g( saY)
cgP l.
4.4.5 How to tirìQ the co-efficients of a mantisea
The co-efficients of a mantissa A (in residue form)
be obtained by following steps:
(residue integerdivision)
2nd step : ComPute &, = A (residuesubtraction)
4-4 6 Errqr in the Arogore-è flqatinq pointarithmetic operations.
can
1st step : comnute 4, = [å]
CL2
Errors in floati-ng Point
tiplication are introduced
an.i Fig 4.7) in normalisation-
error may origj-nate from (i)1
f,Loating point number of fr and
multiplication "
addition,/subtraction, and' mul-
during rcunding process (fig 4 -6
Tn floating point division
error in approximation of
(j r) error 1n floating Point
14
4.4-6a Error j-n floatins pA-1.4._t_ ed.gitf-A-A,/sub tr:actlort
The maximum relative error
addition isIslz]
Itax (e) in f loating
Max (e)
(appentl.ix-4
(4.20)R
(e) )
4.4.6b Elqçr in f loatinq Lq¡¡1_t_ multip.liçation
The maxj-mum relative error in float-ing point multip-
"l.lcatj-on, when ß-ì-_s odd, is girzen by
(..1 2(lßlz)¡' +g[slzliU("o)l -----r-- tt'2r)l-'-''Jooo* R \'r
(appendix-4 (26) )
!{hen ß is eIe_n, the maximum relatÍve error is given by
2 (lß 2)t'U {."¡ (4.22)
RMAX
(appendix-4 ; (27))
4.5 Output Translation
The method proposed here requires Chat Ø . *i for at
least one of the moduli. @ is the base to which con-
version is to be done.) However, there is no restriction
whether gcd(w,mil = l or not. The method can be applied for
conversion to any base provided abcve condj-tion is satj-sfied.
4 .5 .1 Theoretical Asr>ects
Any Ínteger Io can be expressed in base ilJ as
N N_I ifo = ú¿NøJ + c{¡-. 1r.ü + .."".' -l- a,i,N +
+ cLrt'J + ao
anNl
n=o
n
75
The coefficients or digits arL (n=0,1, N) are
given by drr-l = f.r-, Øf' for n = I,2, ....t N
where ro
For
lst step : Find f¡
fïllì-- Jt,l-specj-al case a¡
'N+.1.' gives the number of digits requi:red to repres-
ent the maxj.mum range of a computing system.
4.5.2 Conversion Proced.ure
The co-efficient (digits) in the base fil can be found
by repeating the following 3 steps N times.
n=1 2
2nd, step : Find Inb = dr.,
3rd step : Find a In-I n- I I nb
Last step (special) aN
To convert a residue numL¡e¡: to its equi-valent decimal
number at least one of the moduli must be greater than or
equal to 10" The residue cf that particular modulus will
represent the co-efficient (digit) after third step of the
procedui'e. Therefore only one residue is required to be
extracted.
F;l
76
Example:
Let B, 7 and 11 be the moduli of a residue system.
The hi-ghest pos.itive and negative numbers that can be
handled are (307) r 0 and (308) I o respectì-vely which are
three digits figures.
Take for an example a resj-due number (0,5,10) which
represents 208 in decimal- system.
Tbe procedure to get decimal digits out of 1-he residue
number is
(rne residue representation of 10 is (2,3,10))
Forn=1
First steP :
Second step:
Thi rcl step :
For n
First step :
Second step:
Third step :
= (0,5,10) | (2,3,I0) =
= (4,6,9)x(2,3,10) =
= (0,5,10)-(O,4,2) =
(2. ,2 ,2)
(4,6,9)
(0,0,c)I
I N-rt^)
in each it-eration is
rb
rl
2
I
(4,6,9)
(0 ,4 ,2)
(0,1,9)I
= (20)
= (200)
= (B)
t0
t'0ï
&
=
I
I
&
t00
2
zb
f,ast step for
(1 2 (2,2,
[nivi-sion in t]re fj-::st step
e::al residue division. The arrow
tlre base lol
["-2
I
(4,6,g) (2 ,3 , LO)
(2 ,2 ,2) x(2 ,3 , t})i
(4,6,9)-(4,6,9)
3rd digit is
= (2^, to
= (20\' '10
= (0)' '10
The:refore the decimal number is 208 (=a zxro2 +a rxro I +a oxl-o
o )
a gen-
i.nindicates the digits
77
The arithmetic operatj-ons requi::ed for conversion
are multiplication, divj-sion and subt-raction. Therefore
arithmetic unit must have t.he provision for subtraction,
multiplication and division in the residue numloer system.
4.6 Conclusion
According to the proposed method, multiplicative
overflow det-ect-io': in 16-15-13-1.1- moduli system is consid-
erably fast (269 ns). fn conventional fast technique,
using PROMs of 40 ns access time, the deJ_ay would be 640 ns
(- 4-4"40) . T'he hardware requirement is not insignificant,
however, since sanÌe piece of hardware can be sharecl for
sign detection and determination of first approxj_mation,
the overall cost will not be much. The delay in obtaining
the first approximation, according to the proposed technique
is 274 ns (eq 4.3c); whereas in conventional fast division
technique, the delay would be 2.4.40 = 32O ns.
Floating point arithmetic which was difficult j_n
residue system, no\^/ can easily be implemented using proposed
method. The prelirninary requirement is the existence of
residue int.eger addition. subtraction, multiplicat-ive,
division, comparison and multiplicative overfl"L)\lr detector.
Provided circuits for those operations and a look-up ta.t¡le
for approximate floatlng poj-nt number "t å exist, floating
point arithmetic operat-ion can be performed in software
(residing permanently in PROMs). Therefore implementation
of floating point operatr-on rvill be cost effective. One
departure from the convent-ional f.Loa'tlng polnt format (wirere
2 or 10 -is chosen to be the base of the exponent) is the
7B
choice of the base of the exponent which depends on the
moduli of the residue system and will differ from systen-r
to system. The main advantage of. this choice of the base
is that addition/subtraction/multiplication among the
co-efficients does not produce overflow. Therefore the
cost of usi-ng redundant moduli is saved.
Since output translation is a less f;:equently used
operation, more time can be allotted for thi-s operation.
where there exists all- the basic resi.due j-nteger operat-ions,
the proposed method for output translation can be j-mplemented
with no extra cost of hardware. Moreover, i-n a situation
where base extension cannot be applied, the proposed method
is the only cho j-ce.
5. DESIGN OF A REAL TIIUE RESIDUE
ARITHMtrTIC COMPUTER
5.1 Introduction
The aim of the deslgn of the Residue Arj_thmetic Com-
puter (naC¡ is to verify the algorithms proposed 1n the
Chapter 4, and study the feasibil-ity of residue system in a
general purpose computer. The functional blocks of the RAC
(r'ig 5.1) are (i) Intel SDK-80, B bit microcomputer (pig
5.2(a)) and (if) Residue Arithmetic unit. The microcomputer
acquires and mani-puÌates data, while the RAU does all the
basic residue arithmetic operations. The design of the RÀU,
floatj-ng point arithmetic and residue to decimal conver.sion
are the main topi-cs of discussion in this chapter.
From the consideratj-on of bit efficiency, moduli 16
and 15 (total 8 bits) have been chosen for the test s)zstem.
This gives the range of the system frorn 0 to 239 (lvl=16x1-5=
2401 . The positive half starts from 0 to Lt9, and negative
half f¡:om I2O to 239 representing . -L20 to -1 respectivelli.
board
Thc.re
(ris
The
(rtg
are
5.3
RAU has been designed on (22.Scm x 17.Bcm) vero-
5 .2 (b) ) witb wire wrappinE technique (rig 5 " 2 (c) ) .
altogether fifty TC chips and seventy-six resistors
and Table 5.1) .
llhe microcomputer
prograrnmable peripheral-
conirnunicates with the RÀU through a
intel:face (PPI) of the m-icre;cornputer
79
BO
(fig 5.4). The A-port of PPI issues operation codes (fanle
5.2) and operands, while B-port receives the results from
the RAU. The lower three lines (C0, c1 and C2) of C-port
gj.ves the information of the sign of the resul-t (C0), the
overflow (C1) and the Exclusive OR of the sign of divisor
and dividend (c27, and the higher three lines (C4, C5 and C6)
address the latches (table 5.3 and Fig 5.5) assigned to the
operands and operation codes. The operation codes and oper-
ands are each eight bits long. Of the eight bits of each
operands, the most significant 4 bits represent the residue
of module L6 (mod-16) and the least significant 4 bits rep-
resent the residue of modul-e 15 (mod-15).
The f/0 device specifies operations with alphabetlc
symbols (table 5.4) and issues operands to the microcomputer
which makes decision on the type of operatlon (decode),
enters the operands and operatj_on code to the RAU and then
gets the result from t.he RAU. The final result is displayed
on the f/O device in both residue and decimal forms with
overflow character (if any by '?' ) and sign character ('+'
or'-'). In case of compariscn, the character ) or =, or <,
representing x is greater than, ot equal to or less than y,
is dì. spl ayed.
The programmes
from locations
requl-red for al1 operations
400H t'o 49F H and from 800
re-síde in
PROMs
of the SDK-80 microcomputer memory.
l,ater sect--ions discuss the RÄU -i-n detail-.
il to FEFH,
B1_
The R AC
J-
Fig.5.1 Functionol blocks of the RAC
I
J
D
Ë
V
IC
E
i/0 M
¡
crocomputer
R
A
U
o1
Fig. 5.2 (a) The S D K- B0 microcompu te r.
B3
Fig. 5.2 (b) Top v iew of the RAU boqrd
8'+
Fig. 5.2(c) Bock vÍew of the RAU boord
LOæ
L àtch2
L¿tcht
Latch6
Latch
IPROM
3
Latch
IPRO M
't 0
PRO M
5
Latch
llPR OM
l2PRO M
Ht8
PR OM
H
Ël29
Mutt¡pIe¡er
r$
ËH
tËi-i.
I?
5
7
I
r3
t5t719
zt2325
27293l33
353739L143L5
L9
æEsSøsü<10a...r . i!2
@.-,-.r?-oH"f-;izz
@.,-æ 3 2
F..Æil 3 6
æ48iÑ* 50
a
PROM
Ë"r
l3PRO M
1/.
PRO M
r5PROM
¡5PROM
t7PRO M
+5V
5v
30MuI t ip texe r
37Muttiplexer
43Inverter
49Inverter
;L
tro¡f
É.
OJl'
Co
UI
q,Coo_Eo(J
oC,oo(4
Cog)LO(V)
c,olLL
l9PR0l.l
tt
PRO M
2tVultipIexer
32Multiplexer
PR0 tl
25Muttiplexer
33Mul.t ¡plexer
26Muttiptexer
Muttipterer
39AND
15OR
Multiptex er
46OR
28Mutt ¡ptere r
36FuIt Addcr
PftO M
3ll.luitiptexer
JõMul,t¡ple xer
50
EX. OR
til40
ANOtl
ANO
t7ANO
r.2
Inve rte:
1AInverter
22PRO M
1
0EX R
B6
Table 5.1
The list of components and theirtype numb er/ spec if icat ion
FunctionalDescription of
Components
Type Number/Specificat ion
Loca,tion on theäAU BoarJ Quantity
Quad Latch DM 7475
3601
D[,I 74LS83
DM 741,53
9322
DI,t 74 15 1
DM 74H08
DM 74S11
DM 7432
DM 74586
DM 74504
1.8 K A (%lI)
(36)
(30) , (31) , (37), (38)
(54) , (3s)
(24) -
(2e),(32) , (33)
(39), (40),(47)
(41)
(4s) -
(47), (s0)
(43) , (44)
(42) , (48), (49)
R1 R76
6
Inte 1
PromBipol ar
[zg]t7
76
4 Bit Full ADDER
Dual 4: L
Multipl exe:r
Quad 2-inputMultiplexer
B ChannelMul tipl exer
Quad 2-input AND
Triple 3-input AND
Quad 2-input OR
Quad 2-inputExclusive 0R
Hex Inverter
Resistors
1
4
2
8
J
1
4
2
3
for, .n" ,...Sernicoirductor
components used, excopt PRONfs, are of National
rart 1
B7
SDK- 80Mic rocompute r
Boo rd . +sV
&tttr9
1
2
3
4
56
7
ì(u
ooF
EL(,()m3É.
r+-
oVIt-o*o(UCco(J
G)glEIJ
g
0
1
21J
l.5
6
7
BI
20
2\222321
5
2627
I0
Þ
7
333
lr
I0
11
4213
4t,5
tE
25-Pin-CannonPtug _J
Fig. 5.1 Interconn¿ctlans betweenthe PPI of nrierocomputerand the edge connectors of theRAU boa rd ,
7
I
I
Ir 15
3
6
1
12
5
5
18
5
I7
20
I21
I2
10
2
B7
B3B6
iBzr- B5
Ë81È BL.
BO
c3c2cl
i cor- ClEoLoÈcs
c4
I
t-ß()È
rnLO(\¡æ
A7
A3A5
A2A5
A1
A1
AO
Â-(L
+5V{t
Table 5.2
operation Codes and their definition
B8
0peration Codes
þ7, 06, 05, 04, 03, þ2, 01, 0o
Definition
1
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
1.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
10
01
(i)
(ii )
(iii)
(iv)
(v)
(vi)
(vii)
(viii)
Add
Subtract
It{ulti p1y
Compare (Unsigned)
Cornpare (Signecl)
Get Fjrst Approxinate ofQuotie:rt (Integer Division)
Get a nunber divided by 2
Get the equivalent mantissaof the reciprocal of divisor(floating point division)
1
L
0
L
0
1
1
0
0
0
0
0
0
0
0
0
0L000000 (ix) Get the exponent of thereciprocal of the divisor
Table 5.3
Addresses of iatches
LatchesAddress
c7, c6, c5, c4, c3, c2, c1, c0
Latch of X
Latch of !/
Latch of Operation Code
100000
0
0
0
0
0
0
0
0
L
t
0
1
1
1
0
0
0
0
¿
3
3
_ 16d
r15e l'È
h 1l10
h) c
(de
5
a tgt15ct1o
(e)
2
c
hô
103
n' ''t 1556
235
at6
t t5
ito4)
s
($u
2
ch
10
t't5e 16
3(ds
e16
t15
ito
89
RAUBOA RD
18t716l5??212t9
c4
46c5
Irg'l
c6
ttig.5.5 Lotchirrg r¡f
operqnds -
r--
operatIon
co
d
e
Øz
ø4
6l
ø6
þr
x4
X5
4S
lr7
.lt
ctoÊ0
f
x
oØLo
-l-¿UoCCoc)oul'tf
LU
AO
5
QA
I(toE
A3
útF
I!o.z2
(ô
Iuoã
IJì
I1Jo
=
x7
0
Pe
rên
d
X
-l
oPefan
c
9)
X1
)oy1
y2
Y¡
y4
Ysy6'i7
Y
op*. ret i c; n e ocie oncl
90
Tab1e 5.4
Alphabetic symbols and operations
Alphabet Operat-i-on
A
B
c
D
E
F
G
H
fJ
Addition (lnteger)Subtraction (tnteger)Multiplication (Integer)Dj-visj-on (tnteger)Compar-ison (unsigned, Integer)Comparison (signed, Integer)
Addition (Floating Point)Subtraction (Ploating Point)Multiplication (r'loating Point)Division (Floating Point)
5,2 t Subtracti-on and Multi 1 ri n
Addition, subtraction and multiplication are performed
slmultaneously by means of six look up tables (fantes 5.5 (a) ,
5.5(b), 5.5(c), 5.5(d), 5.5(e) and 5.5(f)) stored in six
(256x4) lntel Bipolar PROM (3601), each having a 70 ns
access time. T\¡¡o PROMs are assigned to each operatj-on; one
is for mod-16 and the other is for ¡nod-15 operatioi:s (fiq
5.6 (a) , 5.6 (b) and 5.6 (c) ) .
The lower 4 address lines (pins 5,6,'7 and 4) are
connected to *;he 4 data lj-nes of operand x," while the higher
4 address lines (pins 3,2,1 and 15) are connected to the 4
data lines (corresponding residue) of operand y.
Irne proqram listings have been shown in Appendix-6,"
AP 0(a).1
9L
Table 5.5 (a)
Look up Table (Addition in lrlocl-16)
Each hexadecimal di git representsrloler 4 adclress bits t
0
O1234567B9ABCDEF
O1234567B9ABCDEF
234567B9ABCDEFO].
34567BgABCDEFO12
4 5 67 8 9AB CDE F O L23
56789A8C0EF01234
67B9ABCDEFO12345
1,
2
3
4
5
6
7
8
9
A
B
C
D
E
F
L23456789ABCDEFO
EactrhexadecinaldigitrepresentsIhigher4 addressbitsr .
9AB
ABC
BCD
CDE
DE F
EFO
F01
012
t23
F
0
1
2
5
4
8
9
A
B
C
D
E
F
0
7
8
9
A
B
C
D
E
F
cDEF0123456
DEF0t234567
8F012345678
0123456789
t234s6789A
23456789A8
3456789A8C
456789A8CD
56789AtsCDE
92
Table 5.5 (b)
Look up Table (Addition in lvlod-1.5)
Each hexadecimal digit TepresentsI lor'¡er 4 address bitst
0
01234s6789ABCDEF
0123456789ABCDE0
t23456789ABCDE01
23456789A8CDE012
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
34567B9ABCDEOT23
Eachhexadecimaldigitrepresentsrhigher4 addressbitsr .
4
5
6
7
B
9
A
B
C
D
E
0
5
6
7
I
9
A
B
c
D
E
0
1
67B9ABCDEOL234
78948C08012345
89ABCDEOT23456
9ABCDEOT234567
ABCDEOT2345678
BCDEOL23456789
cDE0723456789A
DE0L234s6789AB
E0123456789A8C
012 3 4 s 6 7 B 9 A B C n
123456789ABCDE
234s6789ABCDE0
93Table 5.5 (c)
Look up Table (Subtraction in Nfod-16)
Each hexadecimal rlj-git representsrlorver 4 address bitst
Eachhexadecinraldigitrepresentsrhigher4 addressbitsr .
0
1
)
3
4
5
6
8
9
A
B
C
D
E
F
0123456789ABCD8
0123456789ABCD8F
FO1234567B9ABCDE
EFO1234567B9ABCD
DEF0t23456789ABC
CDEFO1234567B9AB
BCDEFO1.234567B9A
ABCDEFO1234567B9
948CDEF012345678
8 9 A B C D E F O T 2 3 4 5 6 7
789ABCDEFO123456
6 7 8 9 A B C D E F 012 3 4 5
678gABCDEFO1234
56789ABCDEFO123
456789ABCDEFO12
34567B9ABCDEFO1
23456789ABCDEFO
5
4
3
2
L
94
Table s.5 (d)
Look up Table (Subtraction in Mod-15)
Each hexadecimal digit representstloler 4 address bitsr
0 01
EO
DE
CD
BC
AB
9A
B9
78
67
s64s34
23
t2
01
0123456789ABCDEF
EachhexadecinalcligitrepÏesentsrhigher4 addressbits' .
1
2
3
4
5
6
7
B
9
A
B
C
D
E
F
2
1
0
E
D
C
B
A
9
8
7
6
5
4
J
2
3
2
1
0
E
D
c
B
A
9
8
7
6
5
4
3
4
3
2
T
0
E
D
C
B
A
9
I
7
6
5
4
5
4
3
2
1
0
E
D
C
B
A
9
I
7
6
5
6
5
4
3
2
1
0
E
D
C
B
A
9
8
7
o
7
6
5
4
3
2
L
0
E
D
C
B
A
9
8
7
I
7
6
5
4
3
2
1
0
E
D
C
B
A
9
8
9
8
7
6
5
4
3
)
L
0
E
D
C
B
A
I
A
I
B
7
6
5
4
3
2
1
0
E
D
C
B
A
B
.1{
9
B
7
6
5
4
3
2
1
0
E
D
C
B
C
B
A
9
B
7
6
q
4
3
2
1
0
E
D
C
E
C
B
A
9
8
7
6
5
4
3
2
1
0
E
D
DO
DE
CD
BC
AB
9A
B9
78
67
56
45
34
23
L2
01
EO
95
Table 5.5(e)
Look up Table (Multiplication in Mod-16)
O1234567B9ABCDEF'
0000000000000000
Each hexadecinial. digit representst lower 4 address bits I
BCAB642OECAB642
F8DC8A987654327
Eachhexadecinaldigitrepresentsrhigher4 addressbitst .
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
123456789ABCDUI.'
2468ACEO2468ACE
3 6 9 C F 2 5 B B E T 4 7 A D
4BCO4BCO4BCO.lBC
5AF49E38D27CT68
6C2BE4AO6C28E4A
785C3A18F6D4829
808080808080808
9284D6F81A3C587
44E82C60A4882C6
B61C72D83E94FA5
c840c840c840c84DA741EBB52FC963
96
Tab1e 5. s (f)
Looh up Table (Ì,{ultiplication in lt{od-15)
Each hexadecimal- digit representsrlourer 4 address tlits t
O1234567B9ABCDE
0 00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
00
00
EO
DO
CO
BO
AO
90
80
70
60
50
40
30
20
10
00
0
2
4
6
B
A
C
E
1
3
5
7
9
B
D
0
0
3
6
9
C
0
3
6
9
C
0
J
6
9
C
0
0
4
oo
C
L
5
9
D
2
6
A
E
J
7
B
0
0
5
A
0
5
A
0
5
A
0
5
A
0
5
A
0
0
6
C
3
9
0
6
C
5
9
0
6
C
3
9
0
0
7
E
6
D
5
C
4
B
3
A
2
9
1
B
0
0
B
1
9
2
A
3
B
4
C
5
D
6
E
7
0
0
9
C
6
0
9
3
C
6
0
I
3
C
ó
0
0
^
5
0
A
5
0
A
5
0
A
5
0
A
q
0
0
B
7
3
E
A
6
)
D
9
5
L
C
B
4
0
0
C
9
6
3
0
C
9
6
3
0
C
9
6
5
0
0
D
B
9
7
5
3
1
E
C
A
B
6
4
2
0
Eachhexadecinaldigitrepresentsrhigher4 addressbitsr.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
91
+ 5v rããxë^<ìñ5 '5ðxäðs:ss +5v
CJd\¡Þc)(t)
ÞC'(tr¡\
(1)
Fig.5. 6(sl
l"lod - 16 Mod - 15
Circuit for the 16-i5 moduti crddltion.
+5vYXXXX\<<q <XXXX\<q\<\ 6ì Ur I\ 1 Sr g¡ Õt (èi ¡\i j ¡;l Lú 6ä- r- Þ.,
+5v
UIc cdl Itr N)
Mod- I S Mod- 15
Fig.5.6(b) Circuit for the 16-15 rnodutî subtrqçtion.
5ãõXëts;X :rNããõtssts+5v +5v
t! G'(^, c
À,
Mod-16 Mod -t 5
Ø tJt tn ulc€,cc..\l.!tcn\¡
acc,a¡
CG^
ca¡,
It/)c
(-7
cc¡- (J!r Cn \¡
co
\ cocf,.
PR0t,t (7\
a,ct A ts)
r/l N\¡
PR OM (B}
'\)
\ll h,J(rr
(ô o
PROM (9}
àlôctr l\)
(tl \¡ (lì (¡1
PROM (ro)
,DdjË
UN\ t,T
7t
ul
PR0M (11)
(¡'ó=Ë
rtl À NlJt
PR0M (12)
¿að:ß
t, \¡ gl fn
Fig.5.6(c) Circuit for the 16-15 moduli rnuttptieation.
98
5.2 (a) De_ley in Addil-ion, Subtraction andMul tiplicat j-on
The delay in addition,/subtractl.on/multiplication
1 PROM delay
70 ns (access time of 3601 PROM)
5. 3 Co¡nparison
There are tl.'c types of comparÍsons compari-sons with
signed numbers and comparisons with unsigned numbers. Com-
parisons with s:Lgned numbers involve either no operation or
subtraction; whereas comparisons with unsigned numbers
inrzolve either addition or subt::action. Table 5.6 is a truth
table showing the comparisons, operations required and dec-
ision modes. It is clear from the Table 5.6 that subtraction
is requJ-red (in both types of comparisons) it the signs of X
and }/ agree; while addition is required (comparison with
gned number) if the signs of X ancl / do not agree.
99
Table 5.6
Truth table for decision modes in comparison
SignedNumbers
Decision
0
1
0
0
1
0
0
L
0
0
1
0
0
1
0
0
1
0
0
1
lt
0
0
0
l"
0
1
1
1
0
0
0
1
1
1
0
0
0
L
1
7
0
C
0
0
7
L
1
1
0
0
0
0
0
0
1
1
1
1
L
l_
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
I
1
1
1
1
L
t
1
1
L
1
1
0
0
0
0
0
0
0
0
0
0
0
0
SUB. O x> y
x<yX=V
x> y
x<vx>yx<vX=V
x> y
x<yX=V
x> y
x<yX=V
x<yx> v
X=V
x<yx> v
X=V
No 0p
No 0p
SUB
il
ll
lt
il
tr
ADD
tt
il
lt
lt
SUB
It
0
1.
0
0
1
0
0
1
0
0
1
0
0
1
0
[t'tote: SUB Subtraction; ADD Addition]
100
Comparisons require the sign of X, !z and the sign of the
resurt of addition or subtraction. However, the results ofaddition, subtraction and multiplicabion are generated sim-
ultaneously. Therefore, depending on signs of X ancl y, the
result of addition /subtraction is to be selected for sign
d.etection.
The sign is detected by a look up table (rabte 5.7)
implemented v¡ith a PROM. 'rhere a-re artogetherthree sj-gn
detectors; one is for X, one for V and the other one for the
result (one of the results of addition, subtracti-on and mul-
tiplication) .
Fig 5.7(a) and 5.7(b) show rhe clrcuits used tor sign
detection of X and f respectively. The data l-ines of the
residue of mod-16 are connected to the lower 4 address linesof the PRoMs and that of mod-l5 to the higher 4 address llnes.The most significant bit of the output indicates the sign
(' 1' for negative, '0' for positive) and the least signlfic-ant bit indicates zero/nonzero of the nurnber ('1' for zero-
number). Thus SX and ZX give the information sign and zero/
nonzero of X respectJ-ve1y. Similarly so for y.
The appropriate result j-s multipJ exed to the sign
detector by two bits (03, dîl of the respective operation
code (fig 5.S). However, þT is not connected di.rectly to the
selection pin (pin-i-4) of the mult:iplexers (two dual 4z1
multiplexers), since in case of comparison, the result ofeither addiLion or subtraction is 'fo be se-l.ected" Table 5.8
shov¡s the states of the selection pins and bhe sel-ected in-puts.
10L
oTable 5.7
Look up table for the sign and zero-nonzeroof a num.ber
Each hexaclecinal digit lepresentsIlorver 4 address bitsr
O1234567B9ABCDEF
Eachhexadecimaldigitrepresentsrhigher4 addressbitsr .
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1B
00
00
00
00
00
00
00
BO
88
8B
88
8B
88
8B
i.8
00
00
00
00
00
00
BO
B8
88
88
88
88
88
8E
08
00
8
B
0
0
0
0
0
0
0
0
I
8
8
8
8
8
I
B
B
0
0
0
0
0
0
0
0
8
8
B
8
B
I
(t
Ò
B
0
0
0
0
0
0
0
0
B
8
8
I
B
8
B
B
8
0
0
0
0
0
0
0
0
8
8
8
B
B
8
B
8
oo
0
0
0
0
0
0
0
0
I
8
I
8
B
8
I
8
8
0
0
0
0
0
0
0
0
8
8
B
B
B
B
B
8
B
0
0
0
0
0
0
0
0
0
B
8
I
B
B
B
8
I
0
0
0
0
0
0
0
0
0
8
8
B
B
8
B
8
B
0
0
0
0
0
0
0
0
0
I
8
8
8
B
8
8
I
0
0
0
0
0
0
0
0
0
8
I
B
8
B
I
I
8
0
0
0
0
0
0
0
0
0
B
B
8
8
B
8
I
8
0
0
0
I02
xãär.äérã+5v
Fig. 5 .7(o)
+5v
SX
Circuitin the
sy
+5V
zx
for sign detection of
16-15 residue sYstem'
X
idt-¡-(^'Nro
+5v
f or sig n detection of
16-15 residue sYstemCircuitin the
PR OM (I g)-\ N) (,
FJ(O
5 --1 Or grl (tl
ni\)ro
7¡.
PR OM (15 )
N(o
¡-{Cnul G'N)(^)n(,\:
Fis. s.7 (b) Y
103
Table 5. B
The states of the select-ion pi-ns andcorresponding selected inputs
States ofSelected Pins
2, L4
Sel-ectedInputs
'03of
' and. '01' (inverted '01)operation codes (table 5 "2)' r03', '01'
Addition
Sukrt ract-i on
Mult.iplication
Not used
From the Table 5.8 it is clear that'03' and'01' can be
di;ectly connected to the selection pins 2 and 14 respec-
tively. However, since in comparisons the sign of the res-
ult of addj.tion (if the signs of X and l/ do not agree) /subtraction (if the signs of X and / agree) is required and
the '03' bit of addition, subtraction and comparison codes
(rab1e 5.2') 1s same (zero) , only '03' bit is directly conn:-
ected,' whereas 'S-i' is gated thqough the Excluslve OR (44,
t,2,3) to change conditionally the logic state of '01' to
select the result of addition,/subtraction for sign detection
during com;:arison.
For addition, subtraction and multiplication 'þ7' and
'06' of the operation codes (rabte 5.2) are zeros; therefore
the output of the AND gate (39 ,2, L,3) is ' O ' . The 'õ-1 '
passes out through the Exclusive OR (44,L,2,3) without inver-
sion. In case of comparÍson, subtractiotr and dlvision, t-Ìre
'þ-1 'which is t.he input to the Exclusive oRs (44,5,4,6) and
(44 ,I ,2,3) is ' 1 ' . The output f ::c-¡m the Exclusive OR (44 ,5 ,
0
1
0
0
0
1
0
1
0
l_
0
0
1
1
4,6) is the::efore
of the signs
ter (48, I,2) ,
ofX
Therefore the 'SC' is also
di.visor and dividend. In
gate (45,1,2,3) is '1' .
not agree 'St-' will be ' 1
will be ' 1' v¡hich inverl-s
104
the invertecl S/. The actual Exclusive OR
and y (SX,Sy) is the output from the inver-since 'SC' = 1 @ Sy o SX = Sy @ SX = S/ @ SX.
the Exclusive OR of the signs of
comparisons, the output of the OR
If the signs of the X and / does
and the output of the AND gate
Of ' (=' l-' in comparison) to '0' .
Theref ore the states of the selection pins 2 an<1 1,4 are 'O'
and '0' respectively and the result of addition will be
sel-ected. ITowever, if the s-igns of .{ and / agrees '3?, wil.lbe '0' and so the output from the AND. Therefore the output
of the Exclusive oR (44,I,2,3) will be 'õT' (='f in compar-
ison) ; the states of the sel-ection pines 2 and L4 are '0'and '1' respectively and the result of subtractlon will. be
selected for sign detection.
The outputs from the multiplexers are connected to the
sign detector (enou (fa¡¡. 'SZ' gives the sign of the result(addition/subtraction/multiplication) Z and ZZ gives the in-formation of zero/nonzero of the result
fUcte 'Lhat the Exclusive OR (44 ,5 ,4 , 6 ) and the inverter (48,
L,2) could be omitted by connecting S/ to the pin 10 of the
Exclusive OR (44,10,9,8) and the output from it ('SC') to the
pin 2 of the AND gate. However, it has not omitted, slnce
this circuit is also part of overflow detector (fiq 5.10)
v¡here the sign of the subtrahend is to be j.nverted by'01'(='f in subtraction) for subtractive overflow detection].
3
t2
{uiÀJ
oìä
2
ô.1
MultiPtexer{co
MuttiPte xe rl\)
2\¡ 'D \(.o
or6rrtN
MultiPtexe r€l o
2
¿,
Multiplexer\t .f,
(gr )
ëH€HQå
ßz)
<<ØV¡ÞÞCCccc]c'(nòr¡¡'tJr¡\
(¡¡Ð(¡,
(sa )
3.\¡øUn
ì9l¡J
Lo À)
PRO M (1/, )
=<(rL4ÞÞccGc,gËt¡N(^rtvl4rÀJ
B
09
3
t2
l_0s
gl .€
51.(t-4]l 6
SS
1st. Ex-0R)
44fiJü
6
O
6tr_ TfOr-()ctCJocçaco
C)
oc')Ð
UJ
19, \.o\ \¡
a
atlx
(Lt-l
2nd.Ëx-0R/
(lrl-l
sc (4 5)
øB)tö
19{(3s)
+-3rd. Ex-0R
+ 5v
SZ zz
Círcuit for sign detection of theresult of oddition/subtrnction /muttipticotio¡r in the 1ö*15 - resicJue
systerÍì.
33utØÞÞccccooâojoJo
s.lr)
(¡o)
+5v
Fig. 5 ,8
106
The finar decision in comparison is done with a lockup table (Table 5.9) formed in rhe pRoM (ZZ¡ (ri_g 5.9) .
Altogether 32 locations (locations DoH to DFH and FoH toFFH) are required. The contents of the odd locations give
the decision modes of comparison with sigr,ed numbers, where-
as the contents of the even locations give the decisj_on
modes of comparison with unsigned numbers. The 'þ7, bit ofthe operation code determines whether the l-ocations read are
even or odd. If 'þ7' is 'L', the odd locations are selected;otherwise the even locations.
The
C01 = '1'indicates
output C00
indicates X
X is equal
'f indicates X
is greater than Y
toV
is less
; whi-1e
than
Cþz =
yì
tl_'
Table 5.9
Look up table for decision modesin comparison
D
F
4 bits of each hexadecimal digit representtSVt, tSZt, tZZt and tþ7t
The secondbit of eachhexadecinaldigitrepresents
rSXt
01234567 sgABCDEF2244iI0022242L00
1 1 L 4 L 2.0 0 2 1 4 4 L 2 0 0
1,07
+5v
ø7
zzszsy
+5v
Fig. 5.9 Círcuit for decisíon rnoddsin comPorison in 16 -1 5- residu e
syste m .
5
50
R
l2
il
t0
l23lI
5
6 P
R
0M3
2
1
r5
108
5. 3 (a) Delay in Compar j-son
From Fig 5.8 and 5.9,
Delay in comparison = 1 PROM delay for operatlonof addition/subtractlon.+ 1 tutultiplexer delay
+ (¡ Exclusive OR + 1 inverter+ 1 AND) delay.
+ 1 PROM delay fortion
+ 1 PROM delay formodes.
sign detec-
decision
(70+ 2o+3x7+1"0+9+70+70) ns
= 270 ns (for the elements usedi-n the test facilities) .
5.4 Overflow Detection
Fig 5.10 shows the circuit for overflow detectÍon in
addition, subtraction and multiplication. The circuits in
the dash-lined box detect additive,/subtractj-ve overflow,'
while the rest of the circuit is needed to detect multiplic^
ative overflow.
5.4 (a) Multiplicative Overflow Detection
V'Ihen multiplicative overflow occurs
be of incorrect sign or may be outsj-de the
system.
the product may
range of theI
An overflow characterised by j-ncorrect sj gn is detec-
ted by the circuit shown in the solid-lined box. The signal
'SC' is the Exclusive oR of the signs of X and / (rig 5. B) .
In Fig 5.8, 'þ-f is 'O' for multiplication and addition.
Therefore the output 'SS' from the Exclusive OR (44,5,4,6)
is really S/ (sign of V) and the output'SC' from the Exclus-
1- 09
ive OR (44,10,9,8) is the Exclusive OR of 'Sy' and 'SX, (the
signs of x and V) . Tabre 5.10 is the truth table of overflow
characterised by incorrect sign.
Tab1e 5.10
Truth tabl-e of overflow characterised byincorrect sign
Sign of X, SX sign of V, SY sign of Z, SZ Overflow
0
1
1
0
1
0
0
1
0
1
0
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
I
1
1
1
From the Table 5.10 the overflow 6(þ') is given by
ó(þ'' :ï l;".,î'From Fig 5.8 SC = '0,1' e 'SY'
For: multi-plication and additj,on,
SC=S/@SX.
The expression (5.1) becomes
6(þ') = SC Ø SZ
'[T' is 'o' , rherefore
(5.3).
@ 'sx, (s.2)
a
110
In Fig 5.10, the output from the Exclusive OR (43,I,
2,3) is the Excl-usive OR of 'SC' and 'SZ'. However, a false
slgnal of overflow occurs when a negative number j_s multi-plied by zero" The zero operands are detected by the
inverters (49 ,3 , 4) and (49 ,5 , 6) and AND gate (39 ,6 ,7 , B) . Ifone of the operands is zero the output from the AND gate
(39,6,7,8) will be '0'; so is the output from the 3-input
AND gate (4I,5 ,3, L ,6) ( OT is , 1 , for multiplication) .
This means no overflow indication wj-Il be given.
The circuit outside the boxes (fi-g 5.1-0) detects over-
flow by 'group technique'. The PROMs (18) and (f0¡ form look
up tables (fable 5.L2) of group numbers of !¡ and X respec-
tlvely (where X and / are the numbers from 0 to +119 and -1
to -L2O) corresponding to the Table 5.11. (fne number of
groups is 8, since 27 < 240 < 28 and nt = 16.)
Table 5.11
Table of numbers and their correspondinggroup number
Numbers Group Number
0
1
2+3
4
I -+1516
32
64
-+ 31
->63+L20
0
1
2
3
4
5
6
7
111
Tab1e 5.12
Look up table of group number of X or V
Each hexadecimal digit represents tlie residueof N{od-16
0
Eachhexadecinaldigitrepresentstheresidueof ¡nod-15.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0123456789A8CDEF
04s6677777776654
514 s 6 6 7 7 7 7 7 7 7 6 6 5
6524s66777777766
6 6 s 2 4 5 6 67 7 7 7 7 7 7 6
7 6 6 5 34 s 6 67 7 7 7 7 7 7
7 6 6 s 3 4 s 6 67 7 7 7 7 7
7766s3456677777
77766s34s667777
777766543s66777
7777766s4s56677
77777766s435667
777777766s43566
6777777766s4256
667777777665425
7 7 7 7 7 7 7 6 6 5 4 L
677777776654
6
6
6
5
6
4
7
7
7
7
7
7
7
6
6
5
0
TI2
+5v\i6r)ljls(^ttú-O
Të
(/.9) (49) (41)
+ 5v XXXXXXXX{('rr¡¡\(, l\)rC¡ +5v
I
o
(16t
ula¡
'oN'
g¡ l,ll
Ulxìgf\,
t¡ñFä
(1¡ )
(16)(39)
€¡¡\t I
Fig. 5 .1 0
(43 ) t11t
€tXrl
u.7l
(41) )t
u7t
(46 t (15 )
¡1t0verf Iow.
ctors Ot the R AU board -
Circuít f or overflow detection ìn the16-15 res id ue sYSte rn
'10 l1
a(^,@ .Dô
otF.
n¡\nõ'co
PROM (16)I'o o
¡.\¡ølt,l LN\¡ (tl L'ì ul
PR 0 M (18)JJ
.D o f\t
tf¡
l")rÆ
13 F.ADDER (36I
l.'l ¡., o, ll'
é-or^*
3
21
6
51
1l
213I
673
12
6
15
3
12
If the sum of the group numbers
than B, overflow must occur, if less
not occur, íf equal to 8 overflow may
if overflow occurs, the si-gn will be
113
of X and / is greater
than B overflow does
or may not occur, but
incorrect.
The group numbers are addecl- with the Full Adder. Ifthe sum exceeds B, the M.S.B. (at Pin 15) will be 'l-' and atleast one of other three bits wilt be nonzero. The firsttwo OR gates (46,2,L,3) and (46,5,4,6) detect whether the
least signifÍcant three bits is nonzero. rf it is nonzero
and the M.S.B. is '1' , the output from the AND gate (4'l ,5,6,6) will be 'f i.e. overflow has occurred..
In multiplication 'þ2' is '0' . This means that the
output from the additive/subtractive overflow detectors(dash-lined box) is '0'. However, 'F' opens the ÀND gate
(47,L,2,3). The output from the OR gate (46,13,L2,LI) gives
the information of multiplicative overflow ('f indicatesoverflow) .
5.4 (b) Additive and Subtractive Overflow Detection
After inverting the sign of the subtrahend, the sub-
tractive overflow is same as the adCi-tive overflow detection.The inve¡sion 1s done by the Exclusive OR (44,5,4,6) of Fig
5.8. In subtraction 'þT' is '1'; therefore the output 'SS'
= 37. In addj-tion ' pf is 'O'i therefore the output is 'SS'
= Sy. An additive overflow is saicl 1-o occur if the sign ofthe operands are same and the sign of result is incorrect.The Table 5. j.3 is a truth tabl-e of additive,/subtractive over-
flow decision modes.
LI4
Table 5. 13
Truth table of additive/subtractiveoverflow decision modes
'ss , Sy/Sf Sj-¡rn of X, SX Sign of Z, SZ overflow
0
I
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1"
1
From the truth
expressed as
d (0)
table the additive overflow d (0) can be
='SS'. SX. SZ +'SS'. SX. SZ
This function is to be ANDed with 'þ2'the overflow is due to addition/subtraction.
actual expression becomes
d (ol = 'þ2' . d (O) = 'þ2' . ('3s '. sT. sz +
(s.4)
to signify that
Therefore the
,SS,. SX. 9l(5.s)
The implementation of the expression (5.5) needs three
inverters, tü¡o 3-input AND gates, one 2-input OR gate and One
2-inputANDgate. Assuming 'SS' exists, the total de1ay,
accordlng to the delay characteristics of the components used
in the test circuj-t, is One 2-input AND gate delay (g'S
ns) + One 3-input AND gate delay (4'75 ns) + One 2-input OR
gate delay (tZ ns) 25 ns.
The actual circuit of additive,/subtractj-ve
is shown in the dash-lined box of Fig 5.10. The
expression ú(A) of the circuit is
d (A) = (,þ2, . SX. 'SS') @ (,Q2,. g. SZ)
where SC 'ss' @ sx (rig 5.8)
115
overflow
logic
(5.6)
To form ('SS' @ SX) does not need any extra Exclusive
OR, since this signal already exists (for multipticativeoverflow detection). Only requì-rement is to invert to form
'ss' @ sx.
Therefore implementation of expression (5.6) needs
One fnverter, tÍro 3-input ÀND gates, and One 2-input Exclus-
ive OR. The gate counts are less than that woul-d be required
to implement the expression (5.5). Assuming 'SS' exists, the
deJ-ay is --- One fnverter delay (g ns) + One 3-input AND gate
delay (4'lS ns) + One Exclusive OR delay (l ns) = 15 ns. The
delay is less than that would be for the expressi_on (5.5).
However, the expression (5.6) can be reduced to the
expression (5.5)
(,þ2'. SX. 'SS') @ ('þ2'. SC. SZ)
,þ2'. [(SX. 'SS') @ (SC. SZ)]
' þ2' . ISX.
'þ2' - t tsx
'ss' . (sc. sz) + (sx. ,ss'). se. sz]
+ 'SS' ) ' (SX o-*S3l . SZ + SX. 'SS'.
(SX @ 'SS' + SZ) ]
116
'þ2',. Itsx *SZ + SX.
sx. 'ss,) .
sx. 'SS' + V) ]
Szl.
'0' . therefore the out-
detector is '0' . The
gives the information
indicates overfl-ow) .
'ss' )
'ss'
(sx.
(y.'SS' +
'SS' +
,þ2' . tsx. '33' . sz + sx. ss.
In addition,/subtraction 'þ2' -i s
put from the multiplicative overflow
output from the OR gate (46,13,13,11)
of additive/subtractive overflow ('1'
5.4 (c) Delay j-n Multiplicative Overflow Detection
Multiplicative overflow detectj-on needs trn/o processes
(i) detecticn of incorrect sign of the result and (ii) detec-
tÍon whether the product is outside the range of system
(using group technique)
(i) The detection of incorrect sign of the product
involves in detection of the sign of the result, 'SZ'.
De1a1r in finding 'SZ' is (from Fig 5.8)
D 2T +37 +T +T +T (5.7)SZ 3 xoR I AND MUX
(Ot 2 ,5, one T: is needed to form product term)
where t3 = the access tj-me of (256x4) pnotq.
TxoR = the delay in the ¡ixclusive oR'
Tt = the deJ-aY in the Inverter'
T¿,ut = the delay in 2-input AND gate '
TMux = the delay in 2 : i- multipl-exer -
For the components used in the circuit in Fig 5. B
tAND-IT: T0nstTXOR=7ns,T
= 20 ns. Thereforeïnu"
10ns i 8.8 ns
TT7
Dr, = L40+2L+10+B'8+20 =
From Fig 5.10 (circuit in the
detecting incorrect sign, DIS
Drr=DsztT3a"o*Txon
200 ns.
solid-lined Box), the delay 1n
is given by
* To* (5.7a)
where T
(since delay
in detecting
= the delay in
= the delay in
3-input AND gate.
OR gate.3AND
ORT
T L4 ns (for the OR-gate used
is less than the delay
'SC' has been omitted.)
in the circuit 5.10)
in forming 'SC'
'SZ' , delay in
(z T*o*)
forming
OR
Therefore
(ii)
nique' DGT
Dr, = 2oo+7+8. B+l-4 = 230 ns
Delay in overflow detectron
is given by (from Fig 5.10)
D"t=T3*T¿,oo+ATon+
(s.7b)
by 'grouping tech-
2TAND
(5.7c)
where Taot = the delay in adding 4 bits. For the
adder used in Fig 5.10, TADD = 25 ns. Tirerefore
D = 7O+25+4xI4+2x8.8
= L69 ns (5.7d)
From (5.7b) and (5.7d), it is seen that the overflow detec-
tion by 'group technique' j-s faster than by 'incorrect sJ-gn
detectj-on' technique. This is due to the fact that the sign
detection is not needed for the formation of group number.
The (5.7a) gives the actual expression for delay in multiplic-
ative overfl-ow in the present system.
5.4 (d)
Delay
is given by
Delav iltdetection
additive/subtractive overflow
l_ 18
ADDin additive/subtractj-ve overflow
(from Fig 5.10)
D =D +T +27ADD SZ XOR OR
=2OO+7+2x14
= 235 ns (for the components
detection D
(5.2e)
used inFig s.10)
5.5 Integer Division
fnteger division needs a first approximation of the
quotient and then proceeds by successive approximations each
of which is a number equal to the preceding approxlmation
divided by 2. The first approxÍmation is formed from the
information of the group number, g(X) of the dividend and
the group number , g (V) of the divisor according Lo the Table
5.14. (fne first approximation and the successive approxim-
ations are positj-ve numbers. )
Table 5.L4
Table of first approximatj-on of quotient
Condition First Approximation
rf g(x) > g(V) 2s (x) s (v)
rf g (x) s (v) Zero
(oivisj-on of zero or by zero j-s aborted.)
Tab1e 5.15 shows the possibl-e values of first
imations (in power of 2) and their residue forms in
and mod-15.
apprîox-
mod- l- 6
119
Tabl-e 5. 15
Possible values of first approximations
First ApproximationFirst Approximation in
residue formmod-16 mod-15
7
6
5
4
3
2
1
0
Since the successive approximation is the number equal
to the precedi-ng number divided by 2, Table 5. 15 also g j-ves
the possible values of successive approximation (except Z7 ) .
For the successive approximations, the number to be
divided by 2 is supplied by the X-data bus (ri-g 5.11). How-
ever, all eight bits need not be multiplexed. Frcm the T'able
5.15, it is clear that the resiclue in mod-L6 is either
zeÊo or equal to the residue in mod-l5. There.'ore only six
bits of information 4 bits of the residue in mod-15, 1 bit
of zero-nonzero information of the residue in mod-16 and one
extra bit signifying 'division by 2' , are required. The
requirement of 'division by 2' is commucicated by the 'Ô3' bitwhich iS connected to the input pin 13 of the multiplexer (34)
and to the selection pin 1 of the multi1:lexer (34) and (35).
B
4
2
1
I
4
2
1
0
0
0
0
0
8
4
2
1
0
2
2
2
2
2
2
2
2
0
T]Ccc)o=
oC
J.ocr
l.-¡--?
oJuO
+E
a I¿à
xã v,
o.-þ(uÈ
: =
o_tslJo'i
',n
OO
€l_l-Ø
o_¡- o. Ln;o-
I
-(OãE
-Ø
G)
tø-C
.';o+
¡¿
()oo.-
C)
l/l'{-
rf)ólr.
rn+
lnIÌt02rf,IÌto
Oc\¡!-t
ct¡rì
x4x5X6
x7
ûzgy0X
Ogy'X
Ix2
gy2X3ø3
gx0
gxl
AP
O
PI
AP
2
P3
AP
4
AP
5
AP
6
AP
7
AP
O
AP
'
AP
2
AP
3
AP
1
AP
5
AP
6
AP
7
l2t1
P'o
LI
321r5 567
rtt\'
Itl\'
ox2ø
3aolt
oì\'att
ocD
r¡,\'lfl
nl
tr1x9?Àr-9);¿
l?
235b34 0
I7I2
08.
IJxlrlJÀt--JÐ
2355t0t13I
1l:P
'oo-
9
567
12
321l55
R s4
R53
R 5659
R 58
R 57
121,
l{hen '03' goes high, four bits of the residue (X3,X2,
X1,X0) in mod-15, one bit of zero/nonzero informati-on of the
residue (X7 ,X6,X5,X4) i-n mod-l-6 and. '03' (- '1') are selected
to the output of the multiplexers (Z:t multiplexer). I¡Íhen
'03' goes low the group number of X, (gXI,gXI,gX2) and the
group number of y (SVj,gVL,gV2) are selected instead. (fne
group number of X and / are generated by the PROMs (f0¡ and
( 18 ) respectively of the circuit in Fig 5 . l- 0 . )
The multiplexed outputs are fed to the PROMs (19) and
(20¡ which form two l-ook up tables of the first approxi-mation
and successive approximations. one *-able (raUte S.16(a))
gives the residue in mod-16 and the other table (raUte 5.16
(b)) gives the residue in mod-15. Lo,cations (00H to 07H) ,
(10H to 17H), (20H to 27H) , (ZO H to 77 H) alrogerher
64 locations are allotted for first approximations and locat-
ions (80 H to 9F) altogether 32 locations are all-otted for
successive approximations .
The integer
can be shown with
division is an lterative process; and
the flow chart of Fig 5.L2.
ir
L22
0t23456789ABCDEF
Table 5.16 (a)
Look up table for first approximation andsuccessive approximation in mod-16
0000000000000000010000
Z E R O2L00042100842100842100000000000000200000000000
Z E R O
0
1
2
4
I
0
0
0
1
L
2
4
8
0
0
0
I
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
I
9
A
B
c
D
E
F
L23
0
Tabl-e 5;16 (b)
Look up table for first. approximation andsuccessive approximation in mod-15
000000000100000002100000042L0000 Z E R O
0842L00001842100021842L00421842108102000400000000010200040000000
Z E R O
L23456789ABCDEF
0
I
2
3
4
5
6
7
I
9
A
B
c
D
E
F
L24
Ycs
Yes No
No
Yes
No
No
No
Process ol integer division in the l6-15 residuesystem.
IN (X,Y )
l<-0; j+0; <-0
Input first approxima-iion: F.
I
Is
f =o ?
T<_Y Does
overftow?
t
7
the re sutt+t
Isth e sign s ign
r e sutt7
of+
Is
thethe
Q.ê 0- qq<- q
q, <- q,Ftag overf low.
ENDT ove rftow
2
Does
ls
?T X
he sign of the+
Is
resutt?
X <- X +Tx (--- x-T
Yes
Q¡*r* Q¡ + F,
i <--- i+1
Y¿s
+ /z;i+-i+t
No
Yes
Fig. 5 .12
125
Iterative processes continue such that the iterative
values of X continue to decrease. Therefore T (in Fig 5.12)
is added or subtracted from the iteratj-ve values of X depend-
ing on the sign of the result (Exclusive OR of the signs ofX and }/ i.e. SX O Sy). From Table 5.I7, it is obvious thatT is added if the sign of the result is negatj-ve; otherwise
T j-s subtracted. (The first approximations and the succes-
sive approximatioi:s are positive.)
Table 5.L7
Tab1e to decide whether T is to be' added or subtracted
SY SX Sign of TSign of
SXthe result@ sy Operation
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
Subtraction
Addition
Addition
Subtracti-on
(The sign of T follows SY. )
The quotient generated is in positJ-ve form. Therefore
it is ccnverted to negative forr.t (subtracting frorn zero), ifthe sign of the result is negati-ve.
The division of M/2 (fZO
a problem. M/2 is a negative
part' posj-tive M/2. The sign
is positive; whereas quotient
in this case) by
and there is
1 presents
no 'counter-number
of the
(M/2)
result of above divisionis negative.
L26
However,this problem can be solved by software. When
the positive approximations are added successively, the lastaddition will show overflow wÌ:,en M/2 is divÍded by 11. There-
fore when sign of the result is posj-tive and overflow occurs,
then overflow signal is to be flagged. If the sign of the
result is negative and overflow occurs, the quotient is M/2.
(ffre software listings have been shown in Appendix-6; Ap6(a).)
5.5(a) Delay i-n findinq approximations
Delay in finding the first approximation, DFA is given
by (ris 5.11)
DFA = Delay in finding the group number of X and V
+ I multiplexers delay (fig 5.11)
+ 1 PROM delay (rig 5.11)
= 1 PROM delay (rig 5.l_0)
+ 1 multiplexer delay + 1 PROM delay.
For the components used for the test circuit,
DFA = 70 ns + I7 ns + 70 ns = L57 ns (5.8)
Delay in findrng a successive approxlmation Oro is given by
(from Fig 5.11) '
DSA = 2 OR gate delay
+ 1 multiplexer ,1e1ay + 1 PRCM delay.
= 2xI4+L7+10 = 115 ns
(for the components used in the circuit).
5.6 Tloatinq Poiht Arithmetic
In this case the base of the exponent is chosen to beI' 12
S = @t¡2¡'' = (L20)'2 = 11. A number X j-s expressed as
I27
X A. 1ln (s. g)
where A is the mantissa and n is the exponent, the range
of which is from 0 to +119 and from -1 to -I20.
In floating point operations each mantissa is separateci
into two terms such that
A = az.Lt + o.y (5.9a)
0"2 and a1 êF€ the co-efficients of l-power and O-power of
11 respectively and the range is from 0 to 10. The steps to
find the co-efficients are
(i) o.z (Integer Division)
(ii) d.¡ A a.2.IL
During normalisation a co-efficient oí is needed to be
rounded. The steps that are requj-red for rounding are
11 l(rr a is negative (-5) is added; otherwise +5)
í- I
a +T
toí-, t 5
(i) Find T
(ii) Find the rounded a.1
Floating point arithmetj-c is done by sottware (appendix-6 (b) )
which resides in the PROMs of SDK-80 microcomputer.
5.6 (a) Floating Poip!. Addition
The floating point addition can be described with the
flow chart of Fig 5.13 (a) , 5.13 (b) and 5. 13 (c) .
L28
Yes ño
No Yes
No Yes
Addit¡on of Mantis:¿=.
Fig. 5.13(a) I Ftow chart of Floating Point Addit ion f n thel6-lS resídue system
E
IN( XJ }
X = A.11ntY = 8.11
n2
A:05
nl e0
n2e0
Coeff (A):) ql ,O2br bzCoeff (B)
Te-(nt-nz)
Negative ?
IsT
oiÈb1 ¡ o2+ b2
S(qt) --- 5(bl); Sloz)S S(bz)
Atignmeiìt of Mantissa.
NormaIisation.
Erponent & Sign Ot The
Resu I t
END
r29
Yes
Yes
No
Fig. 5 .13 (b, Proce s s
addition
* Process of rounding .
of atignment and ftoating point
in the l6- l5 residue system .
Yes
Yes
T
Is>t
?ls
?T 2
Is
?T 1
T(2) <- O2 + 2
T(r) <- o1 + þ1
T(2) <- O2
T(l)ê01
Normalisatíon 7
lss(bz) = 1'
*bt+ +
I
bz- 0Sign detect ionof the mant i s sa
of the re sul t n *bz<-0bt <-
END
Iss(b1)='r'
2
br+ bz+bze- 0
br <- bz+
bz <-0
130
No
Process
add it io n
Yes
of normati sat ion in
in the l6-15 residu e
No
floating Point
system.
T + T(2).1.|
Does
ove r7
T ftow
T+ T+Til)
YesDo
ov?
T c rftes
t+tT(tIs)
2
T<- lry,] Tê.t
T+-T(2)+TExpt X) <-Exp(X)+1
Yes
Mnt(Z | + T
Exp(Z¡+- ExP(X)
Find the sign of
Mnt (Z )
EIiD
Fi9. 5.13(c)
131
5.6(b) Floatinq Point Subtraction
After the subtraction of the mantissa of subtrahend
from zero, the floating point j-s same as floating point
addition. The flow chart of Fig 5.I4 shows the floatingpoint subtraction.
5.6 (c) Floatlnq Point Multiplication
The theory behind the flóating point multiplicarionhas been given in sections 4.4. 3 (b) and 4.4.4 (b) . The
floating point multipl-icatj-on in 16-15 moduli system can
be describe<l with rhe f low chart of Fig 5.15 (a) , 5.15 (b) .
To find the exponent of the result, Exp(Z) is a bitcomplicated process. The Exp(Z) can be written as
Exp(Z) = Exp(X) + Exp(Y) + g
where g is the 'generated exponent' (section 4.4.4 and
Fis 5. 1-5 (b) )
Vthen Exp(X) and Exp(/) are positive, the overflow in
E*p (X) + Pxp (!/) j-ndicates that nxp (Z) is outside the range.
(g is always positive.). When Exp(X) and Exp(l¡) are negacive,
Exp(X) + Exp(/) may overflow, however, Exp(Z) may or may not
remain wi-thin +.he range due to the addition of g.
In later case it has beenobservedthat when Exp(Z) 1s
really within the range, and if Exp(X) + Exp(y) overflows,
addition g makes a second overflow such that Exp(Z) comes
within the range.
t32
X = A.11
l= 8.1 1
IN (XY)
n1
n2
B O- B
Ftooting oddition
E ND
Fig.5.1t, Flow chortsubtroction insystem.
of ftootingthe 16- 1 5
pointresidue
133
rN(xy)¡= A-ilnl; Y= 8.tfl2
Coeff(Al+a1ra2Coef f (B) :+ br, bz
T(3)<_a2.b2 ) T(2lea2.bl
T(l) <- at - b2 ; T(0, <- al. bt
t {P.| ] 7 TU,t<-T(2)-T-tl ; T(3)eT(3)+T
t-[Hl ; T(5) eTfii- T.lr ¡ T(3)<- T(3)+ T
T(2) <- T(r.) +T(5) ¡ t - [.,I!E] ; T(t) <- T(ol- T
T(2t + T(2) +T .
Norrnatisation
Fi nd Exp (Z )
Find sig n of Mnt (Z
ENt)
Fig.5.15(o) Ftow chort of flooting poínt
muttipticqtion in the 16-15 res¡cue
system.
134
No Yes
No
Nc
No
No
Fig. 5.15(b) Ftow chart of normatisation in the l6-15 moduti
f loating point muttiptícat ion .
T<- T(3)'11
DocS
ove ra,
T ftow
T(5)+T+l(3)ls
T(2) +, 2
T(4'+ 2
Does
ove?
T(5) rf tow
T(6)<- T( 5). r IT(4'<- il
2
t(z)+T(31+T(4)T (6, overflow
oes
7
T(4) <- T(6) + T(l) g<- 2
0oes
ov7
T(4 ) erf tow
IsT(1) '+' ?
Mnt(Z) ê- T(¿)
g<-0 T(4)<- T(4 ) <- fi(1)+5
Mnt(Z¡ <-T(5) +T(4)Exp (Z) <-Exp(X) + Exp(y).rg
g<- 1
Yes
END
135
Therefore if overflow occurs twice or overflow does
not occur at all, Exp(Z) is v¡ithin the range, otherwise
EXP(Z) is outside the range. The flow chart of Fig 5.15(c)
explains how to determine whether Exp(Z) overflows or not.
5.5(d) Floatinq Point Division
The flow chart of Fig 5.16(a) shows the floating pointdivj-sion. (The division of zero or by zero is aborted.)
The mantissa and exponent "t * are Eenerated with two
look up tables,' one is for the mantissa "t å and the otherfor the exponent
"t *
The mantissa of the result, Mnt (7) is found by float-ing point murtiplication of the mantlssa of x and that "t å.This multiplication results in a 'generated exponent' , g.
The calculation of the exponent of floating pointdivision is complicated too.
Exp(Z) = [exp(X) nxp(V)] + [g + EE] (rts s.1o(a))
Exp(X)-Exp(}/) may overflow,- however, Exp(Z) may remain
within the range due to addition of the te.rm I g+EE ] which may
be positive or negative and does not overflow.
(g =0or1or2 andEE=0or-1or-2 or-3)
Applying the same reasonings as given in determining the over-
fl-ow conclition of Exp(Z) in case of floating multiplicatlon,the overflow condition of Exp(Z) in case of floating pointdivision can be shown with the flow chart of Fig 5.16 (b) .
136
T <- Exp(X) * Exp(Y)
T overf tow
D oes
2
T+- T + gT <-T + g
Yes NoT overflow
Does
7
T ove rf tow
Does
?
No ove rf low
0verf Iow0verflow.
Yes No
No Ye s
Fíg.5.15(c) Overftow detectíon of Exp(Z) in
flooting point muttipticotion in the
16-15 resid u e syste m
t37
rN(xy)X = 4.11
n1
)(B
E x p
EM + Mnt
EE
Mnt( Z) e- Ft.Pt. (A'EM )
Erp(Zl+Erp(X)- Exp(Y)+ 9+ EE
END
Fig.5.16(ol Flow chortdivision insyste m .
of f lootíng point
the 16-15 residue
No Yes
Does
T ove rflow?
Yes
Overf low detect io n offtooting point divisionres¡d ue syste m .
No
tn16-15
T+Exp(X)-Exp{Y)T0)+ 9 + EE
TI
Doesov¿ rf
T ê- T + T(l)T- T + T(l)
Yas NoT ov e rftow
0oe s
7
0v e rf[ ow No ove rf lowNo ove rf [ow
Fis. 5 .16 (b) Exp(Zlín the
the
-2
of
138
5.6(e) GgnerjrFion of mantissa and exponent "f +
For a base of exponent ß, a general method to calculate
mantissa and exponent of f n"r been described in Appendix
Applying that method the values of mantissa and. exponent
for the base of exponent ß=11 (eleven) have been tabul-
in decimal and residue forms shown in Appendix-3.
1B
ated
The mantissa and exponent of * in resj-due form areIJ
stored in PROMs (fiq 5.17). The value B is fed to the PROM
(I7), (21) and (231 through the X-data bus and PROM (17) and
(Zt¡ output the mantissa in mod-16 and mod-15 respectively,
while the PROM (23) gives the value of exponent.
The exponent "t * may be of any value of -L, -2 and
The residue form of those values are shown in Table 5.19
3
Table 5.19
Resj-due form of the exponent of
Exponent in Residue form
1
B
Exponentin
Decirnalform
-1
-2
-J
In Hex In Binarymod-16 noJ-15 nod- 16 ¡nod- 15
1i 10
1 101
1100
E
D
c
F
E
D
1111
1110
1 101
From Table 5.1-9 it is seen that two most significant bits of
the residues (in binary) in mod-16 and mod-l5 are same and
constant (11). Therefore in the formation of a look up table,
storÍng of these two bits is not necessary; only two least
significant bits of each residue are required.
only one (256x4) PRotl is needed.
139
Therefore
Two M.S.Bs are generated at the output cj-rcuit of the
RAU and this will be discussed in section \.7 .
The PROM(23) (rig 5.17) forms the look up rable forthe generation of the two least significant bits of each
residue of the exponent "t å
The Tables 5.20(a), 5.20(b) and 5.20(c) show the con-
tents of the pRoMs (L7) , (2I) and (23) respectively.
5.6(f) Delav in findinq the mantissa andexponent of 1
B
Delay 1 PROM delay (from FÍg 5.17)
70 ns (for PRoM, rntel 3601).
140
xt,x5X6
x7
x0xt
X2
X3
EEO
EEI
EE1
EE5
EMO
EMI
EM2
EM3
EM4
EM5
ËM6
EM7
ïw0EXP.
L. S.
IN
IW0 L. S.
EXP. IN
EEO
EEI
EE4
EE
EMO
EMI
EM4
EM5
BITS OF
MoD-15 ,
BITS OF
MOD - 16
rn
IÌto2
G)oaoao)o
3o)=.tnU¡oo
(p
xt'X5
X6
x7x0
X1
x2x3
E
E
x4
X5
X6
x7XO
X1
x2
X3
(o
I
!oE
E
E
+5v
Fig. 5.17 C ircu it f or o pProx imote f tootingnumber of 1/ B in the 16 -1 5
system -
pointresidue
5
6
7
1
3
2
ll
10
( zglI
15
P
R
0M
5
6
7
t,
3
2
P12Rt0M 10
l21l s
5
6
7
64
6
56
R 67
R
R41
5
6
7
I3
2
1
12
1t
10
$719
t5
P
R
oM
R ¿5
141
Table 5.20(a)
Look up table for the mantissa of Iin nod-16 B
0
Each hex digit represents the residue of B innod-16. (Lower 4 address bits)
t 4 B 6 3 8 4 B F I D 0 5 4 C E
01234s6789ABCDE
0 7 4 2 A E 13 s D F 2 6 E C 9
3Bt229E135DF26DB
AE D A 019 E 13 5 C E 15 C
c8A81F098135CE15
5 B 7 6 E 5 6 0 8 D t 3 5 4 2F
Eachhex digitrepresentsthe residueofVinnod-15.(Higher4 addressbits).
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
E
C
4
2
F
B
4
6
D
0
04
EO
CE
4C
24
F2
BF
4B
53
74
A
4
0
D
c
4
2
F
A
2
5
A
4
0
D
B
4
2
E
A
F
4
9
3
0
D
B
4
1
E
4
D
5
9
3
F
D
B
3
1
3
1
A
2
I
5
F
D
B
j
9
1
F
7
1
8
2
F
D
5
E
6
F
D
5
0
7
2
F
D
7
D
3
c
c
A
0
7
2
F
D
7
c
1
8
B
1
F
7
2
0
c
6
B
D
2
F
0
E
6
3
0
c
6
A
A
B
6
E
E
4C
24
02
c05C
95
68
32
F5
c9
L42
Table s .20 (b)
Look up table for the mantissa of Iin mod-15 '^ B
0
Each hex digit represents the residue of B innod-16. (Lorver 4 address bits)
8BAE07C024D057ED
0123456789A8CD8
0110 8 C 0 2 4 D 0 3 7 0 E E
Eachhex digitrepresentsthe residueofVinnod- 15 .(Higher4 addressbits) .
1
2
3
4
5
6
7
8
9
A
B
c
D
E
F
c
D
6
2
E
C
5
1
D
9
2
313C87C024C826D
AEA9BD7CO24CE26
c9AO44D6802431D
5C87937C68E23CE
15B73525858E23C
E 15 B 612 0 2 ^
5 A E 13
C E 15 A 5 D O D E 9 4 A E 1
3CD74A4ADAC84AE
tscD1.4938C6873A
Dl5BD()492880563
9 D 13 B D 0 312 4 6 51s
2L8C028D0380154
1ic8c024Ð0370EE
329D158D03815CEC
7
0
L43
Table 5.20(c)
Look up table for two least significant bits of each
residue (in nod-15 and nod-16) "f *
Each hex digit represents the residue of B innod-16. (Lower 4 address bits)
0
1
2
3
4
01234567894BCDEF0444444444444444
4844444444444444
4494444444444444
4449444444444444
4444994444444444
4444499444444444Eachhex digitrepresentsthe residueof/innod-15.(Higher4 addressbits) .
5
6
7
I
9
A
B
C
D
E
F
44444499 4
9
9
4
4
4
4
4
4
4
4444444
4444444
4444444
44
44
44
44
44
04
4
4
4
4
4
4
4
4
4
44449
44444
44444
44444
9444444
9944444
4994444
4 4 4 4 4 4 E
44 44444
44 44444
4499444
4444944
44 44444 4444494
44444
44444
r44
For ß = 11, t glr) = 5. The highest positive number
for the system under consideration is +119; and the highest
negative number is -I2O.
5.6.1(a) Error in Floatinq Point Addition/Subtracti-on
From (4.20) ,
numbers is
the maximum relative error for positive
| ø¡z)
5.6.1 Error in Floatinq Point AdditionSubtraction and Multiplication
(i) Max (¿) 5 .o42R 119
The maximum relatj-ve error for negative numbers is
.o42
5.6.1.(b) Error in Floatinq Point Multiplication
From (4.2t¡ ,
rs is
the maximum relative error for positive
(ii) Max (¿)
U (zo)ß/, ß/t
2 25+3 5
65L20 .54
5L20
n l,j + 3'max R
65119 .55119
The maximum relative error for neqatlve numbers i-s
U (¿olmax
5 .7 Outr¡ut Circu t of the RAU
The outputs from the RAU are the results of addition,
subtractl-on, multiptication, comparison, approximate quotient
for integer division, and mantissa and exponent of $ tot
floating division.
145
The sign of the result of addition, subtraction and
multiplication, overflow signal and the Exclusive OR of the
sJ-gn of the divisor and divj-dend are connected to the pins
4, 5 and 6 respectively of the RAU board (fig 5.8 and 5.10)
and are eventually" connected to the C-port (lower part
C0, Cl, C2) of the SDK-80 microcomputer (fi-g 5.4) .
The result cf addition, subtraction, multiplication,
comparison, approxi-mate quotient, and the mantissa and1exponent "f Ë are multiplexed by three least significant bits
of the operation codes (fig 5.18).
The pin 2
are connected to
most significant
of the multiplexers (24) , (25) , (28) and
+5V through 1.8 K reslstors to generate
bits for each residue of exponent of
(2e)
two
_lB
The pin 4 of the
and (28) are connected
5 MSB positj-ons of the
least significant bits
multiplexers (24) , (25) ,
to ground which generates
comparison sj-gnals; only
give the information of
(26) ,' (27)
zeros in the
the three
comparr_scn.
Table 5.2L shows the states of the selectj-on pins and
the selected inputs.
L46
87I
+5V
+5Y
|,1V7
7
EM7AD7SU7
MU5
EE5AP5
EM5AD5su5
Øzþtûo
U3
AP3
EM3AD3su3
+5vMU
AP6
EM6AD6su6
MU4
EE4AP4
EM4AD4SU4
BS13
2
QzþtØ
ôz$r6o
(2t,'
( 26 )
(2 8'
(32 )
(25)
B5 t
3Cr{1'mxm7
2
3
5
B4
Q7)
B3
oÉ.
C)co
3
É.
tro
tJ)É.oF(-)LUzzO(J
lrl(9êLTJ
I
2
9 101121
0
øþø 40
+5vAP2cþ2Ern2AD2su2
( 29)
B1
BO
39
ØzQtøo
ØzØtØo
MUIEElAPlc0lEMIADlsul
2
3
1
=c--{P5rrl
¡ìn
MUOEEOAPO
2
3
I
(33)
=ct-{'t->mxmvr0 1l
2
3
II
-!
cÉ0EMO
ADOsu0
72
314
9Øz
þtØo
ØzötØo
R6 2
3
2
3
1
I
3cJ.
}5m)<mv
10 11I 1011
1
2
3
L2
13
=cr-{T5-mxmÐ
1tI
2
3
1
2
3
t,
.SC
-tT'->mxrftn
61
3ct-1¡].mxmn
I2
5
I 1011
2
3l.
R60ct-
-o
mxm7l0 I
2
3
2
3
I9
5
Fig.5.18 Output circuit of the RAU
L47
Table 5.2L
States of selection pins and selected inputs
Statesþ2, þ1, 00
selection pinsbits of op. code) Selected inputs
of(¡
0
1
1
1
0
1
0
1
0
1
0
0
1
1
1
1
0
0
0
1
0
Addition
Subtraction
Multiplication
Approximate quotient
Compar j-son
Ma-ntissa of
Exponent of
The outputs from the multiplexers are connected to the
pins 37 through 44 of edge connectors of the RAU board. The
outputs are eventually connected to the B-port of SDK-80
microcomputer (fiq 5.4). The most significant 4 bits of the
outputs represent the residue in mod-16 and the least signif-
icant 4 bits represent the residue in rnod-l5. In case of
comparison, three least significant bits gives the information
of the results of comparison.
5.8 Conversion of Residue Numbers to Decimal Numbers
The 1-6-15 residue system is a three-digit <iecimal sys-
tem (ttre highest positive number is +119). The theory behind
the conversion has been described in secti-on 4.5.
1B1
B
Fig 5.19 shows the residue
one decimal diqit (residue form)
operations required to
of a positive number X.
find
1.48
IN (X}
i<-0
Is
23
t-fExtract O
lrom T . T+
END b <- T. 10
c<- x-b
fromExtract O
b
Yes
No
x<-i<-
T
i+t
Process of re sid u e to decimq t
conversion in the 16-15 res¡duesystem .
Fig . 5 .19
L49
Since 16 and 15 are greater than 10, the residue of the
decimal digit in mod-16 is equal to the residue in mod-15
and each residue is equal to the decimal digit. Only one
residue is needed to be extracted. Decimal numbers are
represented in signed magnitude form. Thcrefore if X is
negative, it is converted to its positive form by residue
subtraction from zero or by residue multiplication with -1.
Successive digits are found by taking T (ln Fig 5.19)
as a new value of X.
The first decimal digit is extracted by residue
multiplication with 01 and second digit by residue multip-
Ii-cation with 10. The residue addition of first and second
extracted digits gives two consecutive decimal digits which
are stored at an 8-bit-byte location. The third digit(t'l.S.O) is extracted by resj-due multiplication with 0l- and
is stored at another location. The contents of those locat-
ions, in proper order, give the decimal number of X.
(The program listings have been given in Appendix
-6 (c).)
5.9. How the Residue Arithmetic Compute r Works
The RAU together with the SDK-80 microcomputer forms
a real time residue arithmetic computer (nac). The communic-
ation between the RAC and outside is thus made through a
teletype or VDU using SDK-80 programmes.
With the starting command - G
return), the RAC undergoes the phases
the flow chart of Fig. 5.20.
Boo) ( ù= carriage
of operations shown by
150
START
G 80oJ
tnitialise the p0RTs
Give signat to get thetype of operation required.
Wait
operationavaitable
Is
,)
Give signat to getope rand s .
Wa it
Areoperandsaveitabte
7
Pe rf orm
disptay
opera t ion and
the resutt .
Yes
Yes
Fig . 5. 20 Prog rom e loops of the R AC
l_5 1
5.10 Ho$¡ to operate the RAC
with the teletype or vDU connected to sDK-80 micro-
computer and power on to the SDK-80 and RAU, the
'reset'. Then the procedures that are followed
(i) Key in c Boo )
The computer responds with
SDK-80 is
are
0
(ii) Key in any
operati-on.
= (for type of operation).
alphabet A through ,f for the requj-red
(see Table 5.4)
(iii )
( iv)
If the operation is an integer operation the
computer responds with
M = (for fi-rst operand X).
Key in two hex numbers (resj-due number) .
The computer responds with
M = (for second operand Y).
Key j-n two hex numbers (residue number) .
Thc computer displays Che result, first in
residue form and second in decimal form with
overflow (if anlr) and sign characters. (tt¡e
overf low character j-s '?' . ) If operat j-on is
a comparison one, the display is ) or = or <
to indicate X is greater than or équal to or
less than Y. The computer signals
0 = (for further operatlon).
If
responds
operation is a floating point one, the computer
with
M = (for the mantissa of X).
Key in two hex numbers (residue number).
The conìputer responds with
E = (for the exponent of X).
L52
form)
f orm).
(iiÍ )
(iv) Key in two hex numbers (residue number).
The computer responds with
M (for the mantissa of V).
(v) Key in two hex numbers.
The computer responds with
E (for the exponent of V).
(vi) Key in two hex numbers.
The computer displays the result as
EM (in residue
(in decimalM
(fne dash-line indicates the digits. The results are
displavs with proper sign and overflow (i-r any) characters.)
Then the computer responds with
0 = (for further operation).
153
5.11 Conclusi-ons
The delay in multiplicative overflow detection, acc-
ording to the proposed technique, is 230 ns; whereas deIay,
accordj-ng to conventj-onal fast technique [-.rsing PROMs of
70 ns access tlme (tntel Bipolar PROM, 3601)] would be
4.2.70 = 560 ns. Therefore multiplicative overflow detec-
tion is considerably faster, accordlng to Lhe proposed tech-
nique. In determination of the first approximation for
residue integer division, the proposed technique introduces
a delay of I57 nsi whereas conventional fast division tech-
nique would need 2.2.70 = 28O ns. Therefore determination
of first approximation is also faster in the proposed tech-
nique.
Until now there has been no residue computer which
performs floating point operations. The introduction of
floating point arithmetic in 16-15 moduli system reveals
the fact that floating point arithmetic operations are feas-
ible in residue system, and that these operations are cost-
effective. The maximum relative errors that are introduced
in addition and multiplJ-cation [section 5.6.1] are not really
significant and quite normal for a single precision macl-^1ne.
Therefore the proposed algoriuhms on floating point arith-
metic have great impli-caticn in the residue system.
In the residue-to-decimal conversion process, where
the moduli are 16 and 15,the conversion radix is 10 and
neither A(X) methodnor base
fore the proposed technique
there is no reason for not
extensj-on is applicable. There-
is the only choice. Moreover
using the proposed technique where
all- the integer arithmetic
can be allotted for output
154
operations exist and more time
translation.
CHAPTER VItttrr
CONCLUSIONS
This concluding chapter presents a comparative study
between residue and binary number systems, and puts forward
a suggestion on further study on residue number systems.
6
The bases of compari-son
consumption in performing the
cation, addition,/subtraction
are the speed, cost
basic operations
including overflow
and power
multiplic-
detection.
For the purpose of comparison'16-15 and 16-15-13-11
moduli systems have been considered and the fastest avail-able J-ogic components of both TTL and ECL technology have
been chosen when dealing with implementations.
The range of 16-15 moduli system (16x1-5=24O) is lëss
than 28, however, greater than 27; likewise the range
16-15-13-l-1 system (16x15x13x11 = 34320) 1s less than 2" ,
however, greater than 2rs . In this cornparison, however, a
16-15 residue system has been compared wj-th an B-bit binary
system,: while the 16-15-13-11 residue system has been com-
pared with a 16-bit binary system.
In multiplj-catj-on the 16-15-l-3-11- system needs four(256x4) pRO¡ls. The component requirement for multiplicativeoverflow detection (on the basis of Fig 4.L) has been shown
in Table 6. 1 (a) .
155
1s6
In the circuit of Fig 4.L the generation of the group
number of the operand X, g(X) has been shown. The generat-
ion of g (V) needs similar sorts of components as required
for S (X). Again for the generation of g (X) the information
of NZ(X) is required; and ñZ(X) can be formed with one B
input NAND gate and one inverter with two levels of gate
delay. Similar type of components are needed for NZ(V).
The sign detectioi: (by mixed radix conversion) of the product
(SZ) needs five (256x4) pRottts. The circuit configuration is
sj-mi1ar to the circuit used for SX, except that (256x8) pnOU
is replaced by a (256x4) Pnot"l.
The requirement when using ECL components is same as
that of TTL components, however, since (256x8), (512x8) and
(5L2x4) ECL PROMs are not available, those PROMs are to be
built from available (256x4) enot"ts. The (256x8) is a PRoM
with 8-bit address lines and 8-bit data li-nes. The function
of that PROM can be confì-gured by using two (256x4) enOus.
One is used for four J-east signi-ficant data outputs, and
other one is used for four most significant data outputs.
The (512x8) pno¡,t can be built from two (256x8) pRotqs (con-
structed by above method). The B-bit address lj-nes are used
to select any L:cation of (256x8) pnotq and the remaining
address bit selects one of two (256x8) pRO¡,1s. The outputs
from (256x8) pROt"ts are wire-ORed. Therefore four (256x4)
PROMs are needed to construct an equivalent (512x8) enot'ts.
construction of a (5I2x4) pno¡¿ needs tu/o (256x4) pRot"ts. The
8-bit address lines select any locatj-on of (256x4) PRO¡,1,
whilst the remaining address line selects one of two (256x4)
PROMs. The outputs of (256x4) pROt'ls are wire-ORed. Table
L57
6. 1 (b) shows ECL required f or multipS-ication and its over-
flow detection in 16-15-13-L1 moduli system. In place of a
4-bit ful1 adder (nCf,) which Ís not available, a 4-bitArithmetic Logic Unit (ef,U) has been chosen. Since an 8 in-put ECL NAND is not avaj-Iabl-e, 2 j-nput AND gates are to be
used for the generation of Nl(X) and liJZ (y) . A total of
fourteen 2-input AND gates are needed and the arrangement
has three level-s of gate delay using currently available
components.
In a 16-15 moduli system, multiplication needs two
(256x4) pRotvls. The components f or multiplicative overf low
detectj-on can be calculated f rom the cj-rcuits in Fig 5.l-0
anC 5.8. The circuit in Fig 5.8 has been used for sign SZ
of the result Z. Tabte 6.2(a) shows the TTL components
required for multi-plication and its overflow detection in
a 16-15 moduli system.
The ECL components needed are the same as the TTL com-
ponents, however, since ECL 3-input AND gates are not avail-able, 2-input AND gates are to be used. Therefore for three
3-input AND gates, six 2-input AND gates are substituted.
Tabl-e 6.2(b) shows the ECL components needed for nultiplic-
ation and overflow detectj-on j-n a L6-15 moduli system.
Of the TTL family Schottky TTL ISZ ] is rhe fasresr;therefore Schottky TTL components have been chosen. Of the
ECL family [Se ], EcL-Iff is the fastest,- however, ECL-IIT
has a limited number of functions, therefore ECL-10000 has
been chosen for the ECL components. Tables 6.9(.) and 6.3(b)
show the characteristics regarding delay, cost and power
158
consumption of TTL and ECL components respectively.
Table 6.1(a)
TTL cornponents required for nultiplication andits overflorv detection in a L6-15-15-1L modu1isystem. (Yaking into account of generation ofg(V) and SZ.)
Function ConponentRequired
Numberof
Conponents
Number ofPackages
TrpeNo.
Multiplication (256x4) PROM 82527
82527
825714
82S130
82S115
sN74S283
SN74S15B
SN74S86
SN74SO8
SN74S32
44
OverflowDetection:(According tothe circuit inFig 4.1,requirement forgeneration ofS(n and signdetection of7 i.e. SZ.)
(256x4) PROM
(25óx8) PROM
(512x4) PROM
(512x8) PROM
4-bit Ful1 Adder
2:1 Multiplexer
2-input Exclusive OR
2-input Al,{D
2-input 0R
2
4
4
t4
2
4
4
t4
6
2
1
1
1
6
2
2
2
3
I B-input ttANlInverter for
SN74S3OSN74SO4
2
2
a
IgeneraNZ (x) ,
ticn of
^/z (y) . l
42
(Totalpackage
count)
159
Table 6. 1(b)
ECL conponents required for multiplicationand its overflow detection in a 16-15-13-11noduli system.
Function Coml.ronentReqrrired
Nunberof
Conponents
Nunber ofPackages
TypeNo.
Multiplication (256^4) PROM 1014 9
10149
l_ 0181
t0L73
10L07
10104
IvlC 10103
4
42
6
2
1
3
(Hex AND)
1
4
6
OverflowDetection:(According tothe circuitin Fig 4.1,the require-nent forgenerationof g(V) andthe signdetectionof Z i. e. SZ)
(2s6xa) PRoM
4-bit Arithneti" MCLogic Unit
2:1 Multiplexer MC
2-input Exclusive OR lvfc
2-input AND MC
2-input 0R
42
2
2
16
3
59
(Totalpackage
count)
160
Table 6,2(a)
TTL conponents required for nultiplicationand its overflow detection in a 16-15 nodulisysten.
Functinn ConponentRequíred
Nunberof
Components
Number ofPackagesof gates
TypeNo.
Muttiplication(rig s.6 (c) )
OverflowDetection:(According tothe circuitsin Fig 5.8and 5. 10.)
(2s6x4) PROM
(2s6x4) PROM
4-bit Ful1 Adder
2-input Exclusive 0R
2-input 0R
2-input AND
Inverter4:1 MultiplexerS-input AND
82527
82527
sN74S285
SN74S86
SN74S32
SNT4SOB
SN74S04sN74S153SN74S1 1
22
3
1
2
2
1
3
1
5
5
4
L
41
343
L7
(Tota1package
count)
161
Table 6.2(b)
ECL conponents required for multiplicationand its overflow detection in a 16-15 modulisysten.
Function ComponentRequired
Nunberof
Components
Number ofPackagesof gates
TypeNo.
l4uttiplication (256x ) PROM 10149
1 0149
MC 10181
MC 10107
MC 10103
MC 10104
IvlC 10195MC 10174
22
OverflowDetection:(According tothe circuitsin Fig 5.8and 5.10.)
(2s6xa) PROM
4-bit ALU
2-input ExclusiveOR
2-input 0R
2-input AIttrD
Inverter4:1 Multiplexer
3
1
2
3
1
5
5 2
2
(Hex AND)
10
L
434
L7
(Totalpackage
count)
Table 6. 3 (a)
Characteristics of TTL components required forResidue Multiplication and its overflow detection
Components
(256x4) pno¡,t
(256x8) Pnou(51,2x4) pnou
(5i-2x8) pnou
4-Bit Adder3-input AND
Hex Inverter2-input AND
2-input OR
Quad Exclusive CR
2:1 Multiplexer8-input NAND
4: l- Multi-plexer
TypeNumber
82527
I2S 11_4
B25 1 30
825115
sN74s283SN74S1 1
SN74SO4
SN7 4S O8
SN7 4S3 2
SN74S86
sN74s158
sN74s30
sN74S15 3
Delayin ns Power
mwr/Bitpwlnitmw/eitlw/sitmw
mw/gatemw/gatemw/gatemw/gatemw
mlf
mw/gatem14r
Price*
25.2519.006.50
17.002.O0
.571 .08
.57
.57
.852.39
.862.39
Manufacturers
sisnetics [Ze ](i)(ii )
(iii)(iv)(v)
(vi )
(vii )
(viii )
(rx)(x)
(xi )
(xii )
(xiii )
40
60
BO
60
7
4.753
4.754
7
4
3
6
.6165
.3165
510
31
19
32
35
250
195
L9
225
il
I
ll
Texas Instrument ISZ ]il
il
il
il
ll
il
il
I
il
il
ll
il
il
il
It
il
79 -03POìN* All prices are i-n Australian dollars and sma1l quantity price.
Table 6. 3 (b)
Characterj-stics of ECL components required forResidue Multiplication and its overflow detection
Function
(256x4 ) pnopt
4-bir ALU
Hex fnverter
Hex 2-input AND
2:1 Multiplexer
Triple Exclusive OR
Quad 2-input OR
Dual 4zI Multiplexer
TypeNumber
LOL49
MC 10181
MC 10195
MC 10104
MC 1017 3
MC 1_01_07
MC 1010 3
MC 10174
DeIayin ns
20
7
2
2.7
2.5
2.5
2
3.5
Power
mwr/Bit
mw
mwlekg
mw/vkg
mw
mw,/ekg
mwlPkg
mw
Pri-ce*
22.32
35.24
1.31
.51
7.10
.55
.5 i-
7.06
7 4.56
Signetics
Motorola
Manufacturers
(i)
(ii)
(iii- )
(iv)
(v)
(vi )
(vii )
(viii)
.66
600
100
140
270
110
100
305
[ 78]
Ise]il
ll
* A1I prices are in Australian dollars and small quantiti price.POr(,
L64
Presently the MPY/HJ family [56] of binary multi-p1j-ers are the fastest. Table 6.4(a) shows comparj-sons
of a 16 x 16 multiplier Vs. 16-15-13-11 moduli multiplier
and an B x B bits multiplier Vs. 16-15 moduli multiplier
using TTL technology. The delay in overflow detection ina 16-15-13-11 moduli multiplj-cation has been calculated
using the expression (4.1)r whilst the expression (5.7)
and (5.7a) have been used for calculation of delay in over-
flow detection in the 16-15 moduli multiplication. Table
6.4(b) shows similar comparisons using ECL components.
From the examination of Table 6.¿ (.) and 6.4 (b) it
is clear that residue multlplj-cation is much faster and
more cost-effective, specially using ECL technology. How-
ever, when residue multiplication is associated with over-
flow detection, the system gets slower and more costly.
However, since the same piece of hardware, used for over-
flow detection, can be used for sign d.etection and generat-
ion of first approxi-mation for resj-due j-nteger dÍvision,
the cost is not as much of a concerning factor as would at
first appear.
Table 6.4 (a)
Comparison of (i) 16x16 binary multiplier Vs 16-15-13-11 mod muttiplierincluding its overflow detection
(ii) 8x8 binary multiplier Vs 16-15 mod multj-its overflow detection (TTL components.
lier includingp)
Function
(1) 16 x 16 bits multiplier
(2) Residue Multiplication(16-15-13-1l-mod)
(3) Overflow Detection
(4) 8 x 8 bits multj-plie::
(5) Residue Multiplication(16-15 mod)
ComponentRequired
rRw/, MPY-16 HJ
See Table6. 1 (a)
See Table6. 1 (a)
TRw/MPY-8 HJ-]-
See Table6 "2 (a)
Number ofComponents
See Table6. 1 (a)
See Tab1e6. 1 (a)
1
See Table6.2 (a)
See Table6. 2 (a)
Delay inNS
100
40
269
45
40
L29
Price*
$265.00
$101.00
$s06.21
$120
$ 5o.so
$ e3.00
Power
3w
2.56 W
18w
1W
1.78 vü
4W
1
(6) Overflow Detectlon See Table6.2 (a)
* All prices are in Australian dollars. POlC¡
Com,oari-son of (i)
(ii)
Table 6.4 (b)
16x16 binary multiplier Vs 16-L5-13-11 mod multipl-icationincluding overflot¡ detection8xB binary multiplication Vs 16-15 mod multiplicationincluding overflow detection. (Using ECL.)
Functi-on
(1) L6 x 16 binarymultiplication
(2) Residue Multiplication(16-1s-13-11)
(3) Overflow Detection
(4) SxSbinaryMultiplier
(5) Residue Multiplication( 16-15-mod)
ComponentRequired
Motorola /L0L83(2x4 multiplier)
See Table6. 1 (b)
See Tab1e6. 1- (b)
Motcrrola /I0Ig3
See Table6 .2 (b)
Number ofComponents
32
See Tab1e6. 1 (b)
See Table6. 1 (b)
See Table6 .2 (b)
See Table6 .2 (b)
Delay inNS
100
20
L26
50
Price*
@ 30.84ea986.88
89.28
1165.39
@ 30.84ea246.72
44.64
320.00
8
Power
25.6 w
2.7 W
33.16 W
6.4 w
1. 35 V{
5vù
20
65(6) Overflow Detec;ion See Table
6.2 (b)
* All prices are in Australian dollars. HOrOì
t67
A comparison of a 4-bit binary adder (fff, and ECL)
with a 4-bit residue PROM adder has been shown in Table 6.5.
From the table it is apparent that in TTL technology a
4-bit binary adder is six times faster than a 4-bit residue
PROM adder. Therefore in addition of equivalent 24 (=6x4)
bits or higher, residue PROM wil1 be faster, provided the
access time of the PRoMs used is 40 ns. However, since the
cost of one (256x4) pnO¡¿ (TTL) is twelve times higher than
that of a 4-bit binary adder (TTL), the residue adder isnot cost effective.
In ECL technology, a 4-bit binary adder is three times
faster than a -bj-t residue PROM adder. with ECL technology
addition of equi-valent L2 (=3x4) ¡its or higher will be
faster in a residue system assuming that the access time ofthe PROMs used is 20 ns. However, sign detection in 3
moduli (each module having 4 bits) system wilt need 40 ns
[ = (3-I)'2O; see Appendix-S]; whereas the sign detection ina 12 bì-t binary system will need 3x7 = 2L ns.
From what has been discussed above, it is clear thatpresent day technology still is not favourable towards the
impiementation of resÍdue j-n general purpose computers. The
binary system wil-1 maintain its p::edomillance. However, inspecial applications wÌrere there is no use of sion and over-
flow detection, residue multiplication will be the firstchoice and may also be a contender 1n very fast and large
systems where the carry free property is of great importance
in minimising the chip connections and inter chip delays.
Table 6.5
Comparison of a 4 bit binary adder(TTL and ECL) Vs. a 4 bit residuePR0M adder (TTL and ECL).
Function Technology ConponentsNunber ofConponents
Delay inns.
168
Price in $'.4.
A4bitbinaryadder
TTL
ECL
TTL
sN74S283
MC 10181
82527(256x4) PROM
1 7
7
2.00
35.20
25.25
1
1 40A4bitresiduePROM
adder 10149(2s6x4) PROM
ECL 1 20 22.32
As it has been discussed earli-er that the residue
floating point arithmetic can be performed in software prov-
ided all the residue integer arithmetic operations are avaj-1-
ab1e. In fast processors the residue floating point
operations will be fast. However, in comparison with binary
floatj-ng point arithmetic the residue floating point ¿rrith-
metic is sl-ower since (f ) the mantissa.s of the residue
floating point operands are to be broken down into two
co-efficients and (ii) in normalisation process the mul.ti-
plicative overflow information is required. However, at
least it has been shown that the floating point arithmetic
can be performed in the residue system, and the operations
are cost-effective, since the only requirements are PROMS
for generation of floating point numbers of the reciprocal
of the mantissa of divisor and memories to store the prog-
ramme required for resj-due floating point operations.
169
It is clear from the discussion above that the multi-plicative overflow detection is the speed limiting factor
in the residue system. Also sign detection is a problem.
Thêrefore more efficient algorithms for sign detection and
overflow detection should be investigated and also the
possibility of using logic gates or FPLAs (instead of PROMs)
should be looked at. In the near future VLSI circuit may
open the way to j-mplementation of overflow detectors with
combinational logic and a dj-fferent comparison between the
systems may then result.
The resj-due PROM adder,/subtractor is slow. The com-
binational logic -i s another possible \^/ay for implementing
resj-due addition,/subtraction and should be a matter of
f urther investigat j-on.
1
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81.
A1
APPENDIX - 1
Some Important Proofs
Apl (a) :
If 2rt <M< 2r^*', U= n+1, andg(X) andg(/l arethe
group numbers of X and V respectively, prove that
(i) if glxl+g(V) > U, overflow will occur-
(ii) if gl(l+glVl < U, overflow will not occur'
(iii) if g(xl+glvl = u, overflow may or may not occur.
If it occurs, the sign of the product will be
incorrect.
Proof:
The multiplication of the lor,/est numbers j-n two
groups is gj-ven by (from Table 4.1)
7=W
Z=W 2
z
2-^*glXl . v{ .2-^+glVl
2-Z^+glXl+slVl
(1)
( 1a)
Let glxl+TlV) = A+L- If A is an even number, W=(M
and ¿ = U/2+L. Therefore (1a) can be written as
z = M . 2 z(q/!+ll+¡tr+l = M/2 .""(2a)
If A is an odd number, W=
fore (1a) can be written as
Y!l¿2t and ¿ = lq+1)/2. There-
(M/2) . 2-2{(q+1 | I 2}+U+1 = M/2 (2b)
it
The equarions (2a) and (2b) indicate that overflow
will occur when the lowest positive numbers in two groups,r
sum of which is greater than U, is multiplied- | The
L
A2
equations (2a) and (2b) do not indicate overflow if one
of the lowest numbers is negati-ve, sínce M/2 is within
the range of negative half. However, in most cases @þ
or ëÌt is not an integer number. Therefore error will be
introduced in determination of W, and this error will make
7 ín equdtions (2a) and (2b) greater than M/2, and there-
fore the product of the lowest numbers one of whÍch is
negative will overflow" The method of determination of W
and construction of group tabre when @þ or ëlt is not
an integer number has been discussed in sectj-on 4.2.1)_t
Let g lxl +g lV I
can be written as
q. If. A is an even number, then (1a)
Z=M 2-2lql2+11+a = |11
o
2-¿ ( 3a)
If A is an odd number, (1a) becomes
(M/2) . 2 2{la+l1/2}+a = M.2 -2z ( 3b)
The equatj-ons (3a) and (3b) indicate overflow will not
occur.
The multiplicati-on of the highest numbers of two
groups glxl and g(/) is given by
z(
tw 2-^+gt,Xl+i -1 2-^*glVl+t l.
ì
[''
Z=w2 z-2^+g(Xl+SlV)+z _ hr . 2-^+glXl+1
-w.2-^+glVl+1 +1 ..... (4)
_1W
1-w
,'s-9(vl
z^ g (xl= !i[
2 2-2^+slxl+slvl+1 l,ìI
)+1
=w z-2o*g(Xl+g(V)+t
r.+r-fr.2^-s(vl
1+1
z^-s(xl
z^-s(xl
A3
(4b)
1!v
+1
(4a)
Since group 1 contains number L, overflow will
never occur on multiplication of number in group 1 with
the number in any other groups. Therefore overflow for
the groups greater than 1 will be consj-dered;
Let S lKl +S lY I A. The equation ( a) can be written
asZ=vtrZ.2-2d+ti+1 1
W
1
UIz^-slvl +1
( 4c)
ì
The minimum value of Z depends on the minimum value of
^-s(xl
The expression ( c)
to 2. Let glxl = 2.
slvl
From the value of M,
,nl z
2^
1-+ -2 1 .^-9 lV I-Ïl"
If tJ is an even number, then from (4c) and (4e)
is mj-nimised when SlXl or S(Yl is equal
Therefore
= r1-2 (4d)
W can be expressed as
n+l<w<2-v- ( e)
2s-a+2 < I _ 1
,nlz2Ul2+1-2
2U/2+l-ti+2,n/ z
-2 1vü
1-+
A4
2(n+1) /2+1-Z 2ln*1ll/2+1-ln+1l¡+2
n/2 2n/2
l-2n+1 | I 2+3
mtn
L-
= L-+-22
z
orZ >Mm1n
2
2-2lU/2+11+q+7
However, for n s 4, 2l-2n+f) l2+3 t t
Therefore the minimum value of ('ic) is a positive number
for n > 4.
In other words for n > 4
Z-2o* U* 12vl (4f)
1=Pt.2
The expression (5) indicates that when the sum of group
numbers is equal to {, multiplication of the highest numbers
in two groups will produce overflow-
In similar way the expressed (5) can be proved to be
valid for odd value of q. Again from (4)
2 -2^+g(Xl+SlVl+Z
(5)
Z<w 2 (6)
Therefore for glx)+g(yl : A an<.l evnn value of ti, (frcm (6))
Z<M ( 6a)
If glxl+glVl = A-!, and A is an even number then from (6)
z<w 2-2lU/2+ll+q+l+l
orZ<M.2 -1 (6b)
A5
The expressì-on (6) indicates, t^rhen the sum of two
groups is less than /, the product of the highest number
of two groups does not overflow. Similarly it can be
proved that expression (0U¡ is also valid for the odd
value of U.
if
Combining
slxl+s(Vl
Combining
(2a) ,
> U,
(3a),
(2b) and (5), it cêrr b€ written that
overflow must occur.
(3n¡ and (6b), it can be concluded
that
if glxl +glyl < U, overflow will not occur-
combining (3a), (3b), (5) and (6a), it can be
concluded that
if glXl+$lVl =
If overflow occurs, the
U, overflow may
product will be
or may not occur.
of incorrect sign.
4n-t, ....., &zt At Afe mixed radix digits
APl (b)
If d-nt
of a number
ffinr ffin-r t
dÍgits bnt
(negative
¡ lfl2 ¡ III ¡
bn-rt ....t
or positive
{ (mi 1)
(positive or negative) in system of moduli
the mixed radixrespectively,
br., br of the 'counterpart' n.mber
number) are given by
oi\ for oil 0 (i=n, nrl, k+l )
the
the
then
b.1
bn {m.kon] and
pfor l0andþ - 0 nPok
(p:k-l- , k-2, 2, 1).
0
A6
Proof:
The 'counterpart' number is formed by subtraction of
the number from zero i.e.
(or, orr-, ok*, ou ok-, o" or)
Since o"
by (*r o*.) .
propagates up
formed by
bk*, =
b\*, =
Example:
Ifm 2
(or, 4rr- i on*, ou ou-, o, o ,)
, to 4k-r are zeros, the kth digit is formed
This subtracti-on produces a borrow which
to nth digit. Therefore other digits are
(^k* t 4k* r -1)
(*k*. &k*, -1)
{ (m¡1 r -1) -a¡a , }
{ (mt+ z -L) -at*, }aIt
{(m -L)-a }.nnb (m a _1)n n
b 0 forp k-1, k-2,
n
2, 1.P
= 0,
given
,fr2
then
by
6s =
b-2
ô-I
= 7, R,
the MRDs
(2-1)-1
(7-5)
0.
and 4 1 5a33 3 2
O.t
is
of the 'counterpart' number
0
2
A7
APPENDIX - 2
AP2z Floating Point va.Iue "t å
For B > l- and positive,
(1)
Let (2)
where OB and rU are the quotient and remainder of the left
hand side division in (2).
+a2
å=ou
Case (i ) rf O
divided by B.
Let
g-2L=g'.BB
tBB
ßl-B
1 ß3BB
r p
B+
P
33.B
ß R then 7",) is added to r and thenBB
r + vt (s)
(3a)
( 3b)
(s)
(6)
t-.e.
r rBBB =O +r
The rounded Qu j-s given bY K where
K=Q oB
Hence K
Case (if) If QB ß < R, then
ß-3
+
2
r
o
is added to rp and then divided bY B
ttB
+r+
D
vlB
v^=Q t
(6a)
The rounded is given by H, where
+ t
AB
( 6b)
( 6c)
is the negative
The exponents
OP
0oHP
Hence
ff H > R, then H is taken to be equal to R
For B 1 B¡
ß-3
The floating point value of
form of mantissa of positive
å-H
*=ß
negative
1
Bof both positive and. negatj-ve are same.
1B
1B
Table 5.18: Table of nantissa and exponent offor B = 7 to I20. (11 is the base of exponen
DecinalNumbers
1
2
3
4
5
6
7
I9
10
11
T2
13
14
15
16
Residue NumbersMod-15 Mod-16
Mantissa inDecinal Fonn
11
61
40
30
24
20
L7
15
13
t2
11
111
102
95
89
83
Exponent inDecimal Forn
-1
-2
-2
-2
-2
-2
-2
-2
-2
-2
-2
-3
-3
-3
-3
-3
Mantissa in ResidueForm
Mod-15 Mod-16
Exponent inResidue Form
Mod-15 Mod-16
F
E
E
E
E
E
E
E
E
E
E
D
D
D
D
D
E
D
D
D
D
D
D
D
D
D
D
C
c
C
C
c
B
1
A
E
8
+
1
F
D
C
B
F
6
F
9
3
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1
B
D
8
0
9
5
2
0
D
c
B
6
72
5
E
8
'ÚtDzH
I
(r¡
Þ\c
c)or+
coo-
DecinalNunbers
L7
1B
19
20
2L
22
23
24
25
26
27
28
29
30
3T
32
33
Residue NunbersMod-15 Mod-16
lvlantissa inDecinal Fonn
Exponent inDecinal Form
Mantissa in ResidueForn
It{od- 15 Mcd- 16
Exponent inResidue Fonn
Mod-15 Mod-16
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
c
C
c
c
C
c
C
c
c
c
C
c
c
C
C
C
c
E
A
6
3
F
D
A
7
5
3
1
0
E
C
B
A
8
3
E
A
7
3
1
D
A
8
6
4
3
1
E
D
C
A
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
c
D
E
0
1
2
3
78
74
70
67
63
61
58
55
53
51
49
48
46
44
43
42
40
-3
-3
-3
-3
-3
-3
-5
-3
-3
-3
-3
-3
-5
-3
-3
-3
-3
ÞtsO
t)or+H.
oo.
DecinalNumbers
34
35
36
37
38
39
40
4t42
43
44
45
46
47
48
49
s0
Residue Nunberst{od-15 I'fod-16
Itfantissa inDecinal Forn
39
38
37
36
55
34
33
32
32
3L
30
50
29
28
2B
27
27
Exponent inDecinal Forn
I,.{antissa in ResidueForm
lvlo<i-lS Mod-16
Exponent inResidue Form
It{od-15 Mod-16
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
C
C
c
c
C
c
c
C
C
c
C
c
c
C
C
C
C
7
6
5
4
3
2
1
0
0
F
E
E
L.
c
C
B
B
9
8
7
6
5
4
3
2
2
1
0
0
E
D
D
C
C
2
3
4
5
6
7
8
9
A
L}
C
D
E
F
0
1
2
4
5
6
7
8
IA
B
c
D
E
0
1
2
3
4
5
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
tsH
a)oal
oÞ,
DecirnalNuinbers
51
52
53
s4
55
56
57
58
59
60
61
62
63
64
65
66
67
6B
Residue NunbersItfod- 15 Mod- 16
l4antissa inDecinal Forn
26
26
25
25
24
24
23
23
¿5
22
22
2t
27
2t
20
20
20
20
Exponent inDecinal Forn
-3
-5
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
Mantissa in ResidueForm
Mod- 15 Nlod- 16
Exponent inResidue Form
Mod-15 lvlod-16
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
C
c
C
c
c
C
C
C
C
c
C
c
c
c
C
C
C
C
A
A
9
9
8
B
7
7
7
6
6
5
5
5
4
4
4
4
B
B
A
A
9
9
8
8
8
7
7
6
6
6
5
5
5
5
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
6
7
8
9
A
B
c
D
E
0
1
2
J
4
rJ
6
7
8
tst\)
t)o(-lF.
oÊ,
DecinalNumbers
69
70
7l72
t5
74
t5
76
77
7B
79
80
81
82
83
84
B5
Residue Nt¡mbersMod-15 Mod-16
Mantissa inDecinal Forn
19
19
19
18
18
18
18
1B
T7
t7
t7
t7
16
76
16
16
16
Exponent inDecimal Forn
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
Nfantissa in ResidueForrn
Mod-15 N,cd-16
Exponent inResidue Fonn
l,lod-15 lvlod-16
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
C
c
c
c
c
c
C
c
c
c
c
c
C
C
C
c
c
ó
3
3
2
2
2
2
2
1
1
1
1
0
0
0
0
0
4
4
4
3
3
3
3
J
2
2
2
2
1
1
1
1
1
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
9
A
B
C
D
E
0
1
2
3
4
5
ó
7
8
9
A
ts(^
(-)oclts.
oÊ.
DecinalNumbers
B6
87
B8
B9
90
91
92
93
94
95
96
97
98
99
100
101
Residue NumbersMod-15 Mod-16
Mantissa inDecinal Forn
15
15
15
15
15
15
14
L4
t4
L4
74
T4
t4
L3
15
L3
Exponent inDecinal Form
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3z-.,
-3
-3
-3
Mantissa in P.esidueForn
Mod-16 Mod-16
Exponent inResidue Forn
l"lod-15 l"lod-16
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
C
C
c
c
C
C
c
c
C
c
c
c
C
c
C
c
F
F
F
F
F
F
E
E
E
E
E
E
E
D
D
D
0
0
0
0
0
0
E
E
E
E
E
E
E
D
D
D
6
7
B
9
A
B
C
D
E
F
0
1
2
3
4
5
B
C
D
E
0
1
2
3
4
5
6
7
8
9
A
B
Þè
cl
rlP.
oÈ
DecinalNu:nbers
t02
103
104
105
106
L07
108
109
110
111
Lt2
L73
rt411s
LL6
777
118
119
720
Residue NunbersMod- 15 Ilod- 16
Mantissa inDecinal Form
Exponent inDecinal Forn
-3
-3
-j
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
-3
Mantissa in ResidueFonn
Mod-15 Mod-16
Exponent inResidue Form
Mod-15 lvlod-16
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
c
c
c
c
c
c
c
c
c
c
C
C
c
c
c
c
C
C
C
D
D
D
D
D
C
c
C
C
C
c
c
c
C
B
B
B
B
5
D
D
D
D
D
c
c
c
C
C
C
C
C
C
B
B
B
B
4
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
ó
7
8
C
D
E
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
0
T3
73
L3
73
T3
72
L2
L2
l2t2
l2L2
72
T2
11
11
11
11
-11
ts(/r
A16
APPENDIX - 4
AP4: Error Analysis of Floating PointAddition and Multiplication Operations
In case of floating point additj-on/subtraction, and
multiplication, the errors are introduced during rounding
process in normal-ì.sation. In floating point division
error is introduced from two sources (i) error from
approximation of floating point, vafue of ] and (ii) theIJ
error from floating point multiplj-cation of FI(A.K).
However, errors only due to floating addition and multip-
lication will be evaluated, assuming the exponents of the
operands are zero.
aP4 (a) : Error in floatinq point additon
The actual value of Z is given bY
ß + cl
The positive error occurs if
z cz (from (4.11) ) .
(cz ß + "r)>R or c
2a Rß
and
if ß is odd.
if ß is even.
Under these condi-ti-ons the normalised rounded Z (Fig 4-6)
becomes
Z. = (cz + 1)ß
", ''V4
A17
Therefore positive error ø+ -- Z' z
ß -c (1)
(1a)
(2)
(3)
I
Case (i) If ß is odd, then
v^ ß-12
z .þl*tor
(c,). ='m1n
(c,) . j¡ mÌn
Ê
Under error condition since cr > vr, and cl is an
j-nteger, therefore the minimum value of cl can be given by
( 1b)
¿+ in equation (1), Ís maximj-sed,
9-l*'For cr =
therefore
(ø+¡m ax
Case (ii) If ß is even, then
V, = B/z
= ,.|9^orß
Under error condition since cl >
therefore the minimum value of ct,
(", )*i' v^For c. = (c.) . ,r ¡ ml-lr
therefore
vl and ct is an integer,
in this case, is gj-ven by
(4)
e+ in equation (1), is maxlmised,'
AlB
Therefore in both cases, positive maximum error is same.
The relative positive error U(ø+¡ is given by
?+crB+c,
(5)
)*r* and cz ß + cr
is given by
(6)
if ß is odd.
U (¿+)
and
lu- |
If ß is odd,
negative error, U(e
The U(ø+¡ is maximj-sed when Ø* = (¿+
Therefore the maximum value of U (¿+)
R
fs ^l( ø+¡U ( u*)*"* max
R
The negatj-ve error occurs if
(cz 3 + cr) > R or c2
R
Rß
c v^
cr < if ß is even.
Under those conditi-ons the normalised Z becomes
., =czß
Therefore the absolute value of negative error is given by
or
lz' -zl
V,'
is given by
v^
c
lu-l-)max
U ( ¿- )*r*R
(7)
A19
If ß iq even, lu-l v^
{ (cs
and maximum I u- | is siven by
(since lu-l is an integer.)
v^-'
v^
The maxi-mum relative negative error, when ß is even,
is given by
U { ø-)*.*
From (6), (7) and (B),
¡lax(¿) is given by (6)
Max(¿) = U(ø+) .*
ZR=c2ß+cr
R(B)
it is clear that the maximum error,
or (7) , therefore
(e)R
AP4 (b) : Error in .f_-I-e-ati_ng. point multip lication
Actua1 value of Z is given by
I - cg 92 + cz ß + cr (from 4.I4) .
Case (i) If c3 = 0, Z is reduced to Z whereR
(10)
In this case, maximum errgr is Same aS the maximum errgr
in floating point addition.
Case (ii) If ca and cr are nonzero, then positive error
will occur if
ß + "r) or ce
vl if ß is odd.
ß]>R
c2
or
and
c wl if ß is even.
A20
In this case the normalised rounded Z (Ffg 4.7) becomes
z (cs + 1)ß2
Therefore positive error 8-+ -- Z' Z
= g'-(cr.ß+cr) ( 11)
or e+ < g2 ""'9
Case (iii) If ca j-s nonzero and c, i" zeto, then positive
error will occur if
ca ' ß + cz > R or ca ' ß > R
c2>and
If ß is even t c2
if ß is od.d.
if ß is even.
(L2)
in this case
2c
v^ú,1
Under these conditions, the expresslon for positive error
can be derived from (11) as
ø'+ = 92 "r. ß ..... (13)
From (13) and (tZ), it is seen that ø' > ø- Therefore to
evaluate maximum positive error, the expression (13) will
be used.
Q.+ j-s maxj-mised if cz = ("rLir, .
If ß is odd cz , Vl (under the error conditions
Therefore the minimum value of c2 can begiven above).
written as
(", Li,, vl., (14)
V^, theref ore ( c2
is (under error condition)
(", ),ni' v4
m 1n
(rs¡
A2I
Therefore if ß is odd, the maximum positive error is
given by
(¿'+Lr* = ß2 (cz)*in' ß from (13)
s2 l\rl*rJ o rr.-om (ra¡
= lr.ú,^*'] ' IFzrl.'j l, Wù.')f ,:om ( 1a)
Therefore when ß is odd, (¿'*) "*
( ro¡
When ß is even, the maximum positive error is given by
{ (ce
and
Wr' [, 'V^)
ß from (13)
from (fS¡ß
from (3)
(12¡
The negative error occurs if
2c
c
ß + cz) or ca . ß ) > R
v^ if 3 is odd.
e,, if ß is even.2
(ror c and c are nonzero)3 t
Under these conditions, the normalised rounded Z becomes
c3
z g2
The absolute vafue of negative error I u- | is given
A22
(ro¡
by
lu-l = 17' zl
)max
3 + c, .....(18)
v^
c2
The maximum value of õ r , (", )*"* = ( 3-1)
If ß is odd, under the above condition,
cz <
Therefore the maxi-mum value of c can be !.'ritten as2
Therefore the maximum absolute value of negative error,
when ß is odd, is given by
c2
c2
vr (19a)
ß + (c,)¡ max
ß + (ß-1) from (19a) and (19)
. Frr].'] . [, .V^+1-1]
(ø-)max
(c" )- max
v^w^.v + 3.
I'
l'If ß is even , under the above condition
Therefore the maximum value of c can be wri-tten as2
w^
I (20)
(2L)c w^ -12 max
Theref ore the maximum abso.'l-ute value of negative error,
when ß is even, is given by
lu-L.* = l""l*.* . ß + l.rl*r*
vl-,wt-,
(ß-1) from (19) and (2L)] ß+
]. 2- W^ + 2'Wl-,from (3)
A:23
= ,[E ù)' 1 (22)
Comparing (16) and (2O') , the maximum error, when ß is odd
is given by (20), therefore
(ø (o) )
([ (øo) )*"* =
(U (¿¿) )o'"* =
v^ þ^max
(ø(ø) )*r* = 2
=2 +3
ì
2
2
2
(23)
Comparing (ZZ¡ and (tl¡, the maximum error, when ß is even,
is given by (]-7) , therefore
w^ (24)
by
V'lhen c is nonzero, the minimum value of Z is3
(z') =ft (zs¡m¡-n
The maximum relative error, when ß is odd, is given
(e(o))max
(z)m1n
2 2 +3. 2(26)
by
R
from (23) and (ZS¡
The maximum relative error, when ß is even-, is given
(ø(ø) )maxt) man
vr)(
(
t2
2
Rfrom (24) ; ,r::'.'
A24
APPENDIX - 5
AP5 Mixed Radix Conversion
For a set of moduli *i (i=L,2,3,
X can be expressed j-n mixed radix form
n) a number
Izs ] as
{=a n+a3m2mr+a2mr*4r..... (1)
where a. (i=L,2,3, .... Ì n) are the mixed radix digits. The1
digits can be found by
lxl*,
+n- I.'fi1= I
a
a
X-e.,n
Rr '
2
&3 m m2 3
In this h/ay, by successi-ve subtraction and divislon,
all the digÍts can be obtained. Conversion of a number X
(residue form) to mixed radi-x fcrm (shown in (1) ) is called
mixed radix conversion (MRC) -
Example:
For m, = 16, m2 = 15, mr = 13, find mixed radix
digits of X >
A25
Solution:
Residue of X
Subtract a"r
Moduli: 16 15 13
7 I 4r B
8 B
15 L2
denotes multiplicatj-ve inverse of 13
and 16
5
* Multiply by 5 7
11 9 &2=9
Subtract a2
* Multiply by t+1,, l-5L4 0.. g
From example, it can be shown that total paralleI
residue operations required are
(i) (n-1) subtractions and (if) (n-1) multiplication.
If these operations are carried out with PROMs (by look up
table) then subtractions and multiplication can be over-
lapped (since the multipliers are constant numbers). In
this case total operations are (n-1). In other words, delay
is (n-1) PRoM-delay (access time).
The decimal value (DV) of X = 14x15x13 + 9x13+8
= 2855
lrl| 13 lmt
92
* !1
151
L3 m. '1 16
and l-5 with respective to mí (rs and. 16)
respectirr"rv.J
A26
APPENDIX 6
PROGRAM LISTÏNGS
A-i
Appcndix-6 consists of the program listings for the
RAC and is divided into three parts AP6 (a) , AP6 (b) and
AP6 (c) . The AP6 (a) contains the program listings for
integer arj-thmetic operations together with initialisation
of the ports of the microcomputer, decoding of the operation
codes etc.; the AP6 (b) contains the program listings for
floating point arithmetic operations and the AP6 (c) contains
the program listings for the conversion of residue numbers
to deci.mal numbers.
The programs are the subroutines nested together. The
labe1s of the subroutines and routines, in alphabetical order,
are given belor^¡.
Labels Subroutines/Routines Paqe
AD
ADD
AP
AI2A30
BLN
S
R
R
R
R
s
S
R
S
R
S
S
S
S
R
R
A30
A33
A32
A33
A33
A29
A38
A54
A2B
A39
A62
A3l_
*
A30
A33
A33
CAD
CAP
CAR
CAT
CBCD
CCHR
CNVBN
CM
COMS
coMu
Labels
coR
COSI
COUS
COVER
CV
DAD
DIDIVDSV
Subrout
ECHO
EEQ
EPT
EQ
EXP
EXPO
EXT
FAD
FA
FBCD
FD
FDI
FEND
FFC
FINTS
FTXE
FM
FMT
FMU
FS
FSU
GAT
GET
GETCH
GGT
S ut Paqe
A31
A32
A32
A54
A30
A-ii
A38
A30
A34
A32
*
A32
A2B
A28
A54
A43
A57
A45
A32
A62
A32
A57
A41
A57
A40
A40
A32
A59
A49
A32
A48
A39
A29*
A31
Labels
GT
IBCD
TNI
JPM
KAT
KATCH
KATH
KATR
KKK
LLTLOAD
LT
MAD
MM
MNT
MU
MUL
NCHRT
NEG
NEGA
Nl"lOUT
NORL
NORM
oPc
OSIGN
OUÎPU
OVER
OVFL
ut
PASS
PEG
PEND
S utines
A-iii
Paqe
A2B
A6l_
A2B
A30
A36
A46
A36
A36
A58
A31
A29
A2B
A47
A32
À28
A30
A33
A65
A28
A41*
A52
A42
A2B
A31
A45
A44
A59
A36
A50
A40
Labels
PElPOS
POVER
PSÏ
QZERO
RRET
RSÏ
RZERO
Subroutines /Routines
R
s
R
R
A-iv
Paqe
A34
A28
A53
A31
A56
A60
A63
A56
A40
A32
A64
A34
A57
A39
A28
A37
A39
A65
A30
A33
A64
A34
A35
A35
A47
A31
A30
A38
A32
A64
A28
A56
SAT
SB
SCHRT
SDIV
SDK
SELE
SET
sscSSEP
SSSP
SU
SUB
SUM
TAB
TAC
TAD
TAD
TAG
TAKE
TAP
TEST
TOR
TTT
TZERO
R
R
R
R
R
R
s
S
R
s
R
R
S
S
S
R
S
R
R
R
s
R
S
s
R
R
R
S
SXTAR A29
Labels
ZRET
ZERO
Is
Subroutine s,/Routine s
A-v
Paqe
A60
A36
R
R
Subroutine : R Routine l
* Resides in the Monitor Prom of the SDK microcomputer.
A21
AP-6(a) : Li-stings .of fnteger Arithmetic operations
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