Research Challenges in Open Source HW

PULP PLATFORMOpen Source Hardware, the way it should be!

http://pulp-platform.org @pulp_platform

Research Challenges in Open Source HW

Luca Benini <[email protected], [email protected]>

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Open Source Hardware

Hardware whose design is made publicly available so that anyone can study, modify, distribute, make, and sell the design or hardware based on that design

(source: Open Source Hardware (OSHW) Statement of Principles 1.0)

Very wide definition – includes PCBs and makers’ stuff

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I will focus on Open Souce Computing Hardware (OSCHW)

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OSCHW Needs an Open Source ISA

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A modern, open, free ISA, extensible by constructionEndorsed by 1000+ Members & large SW ecosystemAn open ISA is a prerequisite!

Risc-V international moved to Zürich, CH for international neutrality, 1/3 of members from EU

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FoundriesFoundriesFoundries

Phy IP ProvidersPhy IP ProvidersPhy IP Providers

EDA CompaniesEDA CompaniesEDA Companies

Technically, what is “open” in OSCHW Today?

HDLNetlist GDSII ChipLogic

Synth. P&R FAB

PDK

OtherIP

Simu-lator

Sim.Models

Std.Cells

Only the first stage of the silicon production pipeline RTL source code (permissive*, e.g. Apache is key for industrial adoption)

Later stages contain closed IP of various actors not open source by default

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Cadence license for academic usage forbids permissive open sourcing of designs made with CDNS tools unless a reciprocal* license is used

“See: https://cern-ohl.web.cern.ch/ (CERN-OHL-S, -W, -P)

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What about End-to-End Open HW (pdk, tools)?

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Open Source ASIC EDA flowOpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. https://github.com/The-OpenROAD-Project/OpenLane

Open source process design kit for usage with SkyWater Foundry 130nm tech.https://github.com/google/skywater-pdk

40 submissions for the MPW-ONE shuttle: 60% submitted by first-time ASIC designers.

MPW-TWO (June 18th tapeout)

Most based on the Caravel harness

Raven 130nm mixed-signal SoC

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Not only cores – many IPs for a Platform

Platforms

RISC-V CoresRI5CY

32b

Ibex

32b

Snitch

32b

Ariane+ Ara64b

Interconnect

AXI4 – InterconnectAPB – Peripheral Bus

Logarithmic interconnectPeripherals

DMA GPIOI2SUART

SPIJTAG

Accelerators Neurostream(ML)

HWCrypt(crypto)

PULPO(1st ord. opt)

HWCE(convolution)

RV

MI

O

inte

rcon

nect

A

Single Core• PULPino• PULPissimo

IOT HPC

M

I

Ocluster

interconnect

A RVRVRV

M MMMin

terc

onne

ct

Multi-core• Open-PULP• PULP-PM

RV

cluster

interconnect

R5 RVR5R5

M MMM

cluster

interconnect

R5 RVR5R5

M MMM

cluster

interconnect

R5 RVR5R5

M MMM

cluster

interconnect

R5 RVR5R5

M MMM

cluster

interconnect

A RVRVRV

M MMM

cluster

interconnect

A RVRVRV

M MMMM

I

O inte

rcon

nect

Multi-cluster• Hero• Manticore

R5

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https://github.com/pulp‐platform/

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OSCHW to address key challenges

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Energy

Security

Safety

61-512.webp61-512.webp61-512-1.webp

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Research – XPULP ML extensions: RI5CY

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RISC‐V V1

V2V3HW loops. Post modified Load/Store, MACV2

SIMD 2/4 + DotProduct + Shuffling.Bit manipulation, Lightweight fixed pointV3

Baseline RISC-V RV32IMC (not good for ML)V1

XPULP extensions: 25 kGE 40 kGE (1.6x) but 10x ML perf!

ISA is extensible by construction

PULP RI5CY – An Open MCU-class RISC-V Core for EE-AI 3-cycle ALU-OP, 4-cyle MEM-OPIPC loss: LD-use, Branch

I, D mem IF tuned for low latency & time borrowing

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Product: GWT’s GAP8 IoT processor

175

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Energy efficient OSCHW based Products?

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✔✘ prototype (IO phy, MPW +2M$) ✘ product (+20M$)

Edge/Mobile

✘ prototype (core,IO phy, tech, MPW +$10M)

✘ product (+100M$)

HPC/Cloud

✔ prototype, ✔ product (+5M$)

IoT Near-sensor

arXiv:2009.00993v1 [cs.DC] 2020

FACT: prototype is prerequisite for product!

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Energy

Security

Safety

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Research – knowing how things “work” is vital

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From the “ZombieLoad” paperFrom section 3.2, emphasis added for this presentation

“While we identified some necessary building blocks to observe the leakage (cf. Section 5), we can only provide a hypothesis on why the interaction of the building blocks leads to the observed leakage. As we could only observe data leakage on Intel CPUs, we assume that this is indeed an implementation issue (such as Meltdown) and not an issue with the underlying design (as with Spectre).”

Closed implementations hide/abstract many secrets from users Being able to see inside and run experiments are vital for safety and security experts

M. Schwarz, M. Lipp, D. Moghimi, J. Van Bulck, J. Stecklina, T. Prescher, D. Gruss, “ZombieLoad: Cross-Privilege-Boundary Data Sampling”, arXiv:1905.05726

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Research Product OpenTitan is the first

open source silicon project building a transparent, high-quality reference design for silicon root of trust (RoT) chips.

Founding Partners

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Research Product OpenTitan is the first

open source silicon project building a transparent, high-quality reference design for silicon root of trust (RoT) chips.

Founding Partners

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Leakage resistant crypto

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Energy

Security

Safety

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PULP

Fabric Controller

CLUSTER

RISC-V core

I/O

L2 Mem

Inte

rcon

nect

L1 Mem (TCDM)

Interconnect

RISC-V coreRISC-V

coreRISC-V

coreRISC-V

coreRISC-V

core

DMA

icache

RISC-V coreHWPE Peripherals

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PULP in Space: Protecting PULP from SEU

ECC

ECC

Scrubbing

C-TCLSConfigurable Triple core lockstep

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Research Product

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OSHW for space and safety critical appls

Quantify failure rate due to soft errors processor designs (similar approach for automotive, servers, experimental instrumentation, by adapting the error models)

Detailed white-box analysis is possible only for open-source (IP) cores

OSCHW also helps with long-term maintainability and helps avoiding captivity

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Scaling up OSCHW industrial ambition

Platforms

RISC-V CoresRI5CY

32b

Ibex

32b

Snitch

32b

Ariane+ Ara64b

Interconnect

AXI4 – InterconnectAPB – Peripheral Bus

Logarithmic interconnectPeripherals

DMA GPIOI2SUART

SPIJTAG

RV

MI

O

inte

rcon

nect

A

Single Core• PULPino• PULPissimo

IOT HPC

M

I

Ocluster

interconnect

A RVRVRV

M MMMin

terc

onne

ct

Multi-core• Open-PULP• PULP-PM

RV

cluster

interconnect

R5 RVR5R5

M MMM

cluster

interconnect

R5 RVR5R5

M MMM

cluster

interconnect

R5 RVR5R5

M MMM

cluster

interconnect

R5 RVR5R5

M MMM

cluster

interconnect

A RVRVRV

M MMM

cluster

interconnect

A RVRVRV

M MMMM

I

O inte

rcon

nect

Multi-cluster• Hero• MANTICORE

R5

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Tens of active users, many use-cases HW, SW specialization, verification, documentation, training

Cannot be sustained by one University, or two…

Tens of active users, many use-cases HW, SW specialization, verification, documentation, training

Cannot be sustained by one University, or two…

Accelerators Neurostream(ML)

HWCrypt(crypto)

PULPO(1st ord. opt)

HWCE(convolution)

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Feel the momentum!Ibex RISC-V core, flash interface, communications ports, cryptography accelerators, and more.

Vibrant repository

Contributors35+

1300+

GitHub Issues

Contributions

470

Zero-Riscy Ibex

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Academic open source Industrial open source

OpenHW Group is a not-for-profit, global organization (EU,NA,Asia) where HW and SW designers collaborate in the development of open-source cores, related IP, tools and SW such as the Core-V family

OpenHW Group provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

RI5CY, ARIANE

Rick O’Connor (OpenHW CEO, former RISC-V foundation director)

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OpenHW Group Ecosystem

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Cloud Based Verification

RTL SimulationFormal Methods

Stimulus

CV32 & CV64 Cores

GCC / LLVM &

OS ports

MPW Layout

&Fab

SoC Protos

Eval Boards

Verification is Key!

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The role of public EU funding Facilitate prototyping of OSCHW (Europractice++) Tech. access and MPW cost (including substrate, packaging) Enablement (e.g. PLL) + IO/PHY (e.g. HBM) IPs cost Access to advanced EDA Tools + Expertise (e.g. advanced EDA cockpits) Design implementation support + Expertise (e.g. Backend, Packaging…)

Nurture & Support the ecosystem EU Supported OpenHWGroup around RISC-V Develop commercial EU IP ecosystem with facilitated access for EU companies EU EDA tooling: research and companies Education-centric initiatives (+Training)

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Big risk: Fragmentation!!

http://pulp-platform.org @pulp_platform

Luca Benini, Alessandro Capotondi, Alessandro Ottaviano, Alessio Burrello, Alfio Di Mauro, Andrea Borghesi, Andrea Cossettini, Andreas Kurth, Angelo Garofalo, Antonio Pullini, Arpan Prasad, Bjoern Forsberg, Corrado Bonfanti, Cristian Cioflan, Daniele Palossi, Davide Rossi, Fabio Montagna, Florian Glaser, Florian Zaruba, Francesco Conti, Georg Rutishauser, Germain Haugou, Gianna Paulin, Giuseppe Tagliavini, Hanna Müller, Luca Bertaccini, Luca Valente, Manuel Eggimann, Manuele Rusci, Marco Guermandi, Matheus Cavalcante, Matteo Perotti, Matteo Spallanzani, Michael Rogenmoser, Moritz Scherer, Moritz Schneider, Nazareno Bruschi, Nils Wistoff, Pasquale Davide Schiavone, Paul Scheffler, Philipp Mayer, Robert Balas, Samuel Riedel, SegioMazzola, Sergei Vostrikov, Simone Benatti, Stefan Mach, Thomas Benz, Thorir Ingolfsson, Tim Fischer, Victor Javier Kartsch Morinigo, Vlad Niculescu, Xiaying Wang, Yichao Zhang, Frank K. Gürkaynak, all our past collaborators and many more that we forgot to mention

Documents

Research Challenges in Open Source HW