Research Article Optimal ILP-Based Approach for …downloads.hindawi.com/journals/mse/2014/571374.pdfResearch Article Optimal ILP-Based Approach for Gate Location Assignment and Scheduling

Research ArticleOptimal ILP-Based Approach for Gate LocationAssignment and Scheduling in Quantum Circuits

Naser Mohammadzadeh1 Tayebeh Bahreini1 and Hossein Badri2

1 Computer Engineering Department Shahed University Tehran Iran2Department of Industrial Engineering Amirkabir University of Technology Tehran Iran

Correspondence should be addressed to Tayebeh Bahreini tbahreinishahedacir

Received 7 July 2013 Revised 18 November 2013 Accepted 19 November 2013 Published 4 February 2014

Academic Editor Azah Mohamed

Copyright copy 2014 Naser Mohammadzadeh et alThis is an open access article distributed under theCreative CommonsAttributionLicense which permits unrestricted use distribution and reproduction in anymedium provided the originalwork is properly cited

Physical design and synthesis are two key processes of quantum circuit design methodology The physical design process itselfdecomposes into scheduling mapping routing and placement In this paper a mathematical model is proposed for mappingrouting and scheduling in ion-trap technology in order to minimize latency of the circuit The proposed model which is a mixedinteger linear programming (MILP) model gives the optimal locations for gates and the best sequence of operations in terms oflatency Experimental results show that our scheme outperforms the other schemes for the attempted benchmarks

1 Introduction

Quantum effects have been a major concern in classical com-puters in metal-oxide-semiconductor technology (CMOS) asthe feature size shrinks into the 10 s of nanometers range[1] Quantum effects such as entanglement and superpositionare amplified in quantum computers They operate on theentangled superposition states and this is where the powerof quantum algorithms comes from

A quantum circuit is a model for quantum computationIn a large picture the quantum circuit design flow includestwo main tasks synthesis and physical design (Figure 1)The physical design consists of scheduling mapping andplacement processes In this paper an ILP-based approachis proposed for scheduling routing and mapping processesThe proposed approach takes an initial netlist and a layoutand maps and schedules the gates on the layout

A quantum circuit is defined as a sequence of quantumoperations acting on one ormultiple qubitsThese operationscould be categorized in two groups (1) single or multiqubitlogical gates and (2) single qubit measurement In thispaper only one- and two-qubit operations are considereddue to some practical limitations on many quantum circuittechnologies [2]

Ion-trap technology is a quantum technologywhere everyuniversal element for quantum computation has been real-ized with a clear scalable communicationmodel [3 4] In thistechnology an ion is the physical demonstration of a qubitand a gate location is a location wherein a gate is performedEach ion could be trapped or physically moved between trapsby applying pulse sequences to discrete electrodes (Figure 2)Each qubit is measured by stimulating the target ion with adifferent frequency laser pulse [5]

In this paper library of macroblocks which is defined in[6] (Figure 3) is used due to two major advantages The mainreason is that by using this library some low level detailscould be removed and it is not necessary to consider thevariations in ion types size of electrodes and precise voltagelevels needed for trapping and moving ions All of thesedetails are condensed within the macroblocks [7 8]

In this library a 3 times 3 structure of trap regions andelectrodes forms each macroblock Each structure has someports to allow qubits to move between the macroblocks Gatelocations are indicated by black squares Various orientationsof each macroblock could be used in a layout

The paper is continued as follows an overview of theprior work is presented in Section 2 followed by the detailsof the proposed model in Section 3 An illustrative example

Hindawi Publishing CorporationModelling and Simulation in EngineeringVolume 2014 Article ID 571374 8 pageshttpdxdoiorg1011552014571374

2 Modelling and Simulation in Engineering

High level description

Scheduled layout

Synthesis

Physical design

Technology-dependent netlist

Figure 1 Quantum circuit design flow [9]

Gate laserMEMS mirrors

Trap regions

Electrodes

Ion (qubit)

Figure 2 Simplified ion-trap technology view [5]

Dead end gate

Straight channel gate

Straight channel Turn

P1P1

P1P1 P1

P0 P0 P0 P0 P0P0P2 P2

P3

Three-wayintersection

Four-wayintersection

Figure 3 Library of basic macroblocks used in this paper [6]

is presented in Section 4 Section 5 shows the experimentalresults and Section 6 concludes the paper

2 Related Work

There are a lot of techniques proposed for optimization insynthesis process [6 10ndash14] but a few studies have been doneon optimization problems in the quantum physical stage

Metodi et al [15] presented a physical operations sched-uler (QPOS) which takes a description of a circuit and a def-inite physical layout and produces a sequence of operationswhich indicates the required communication and possibleparallelism in the circuit Dousti and Pedram [16] presented

an algorithm for scheduling placement and routing of aquantum circuit which decreases the circuit latency Theydeveloped a heuristic for placement called MVFB whichimproved the center placement used in the previous quantumCAD tool [17 18] Balensiefer et al [17 18] proposed a designflow and compilation technique to consider fault-toleranceand developed some tools to appraise layouts Whitney et al[9] proposed a computer-aided design flow for the layoutscheduling and control of ion-trap-based quantum circuitsThey proposed two heuristics for layout design The firstheuristic is a greedy algorithm that is appropriate for smallcircuits Dataflow-based algorithm was proposed for largercircuits aiming at placement and routing

Modelling and Simulation in Engineering 3

The proposed

modelA layout

A netlist (1) Optimum initial locations for qubits(2) Optimum gate location for each gate(3) Optimum sequence for operations

Figure 4 Inputs and outputs of the proposed model

Maslov et al [19] proposed heuristics for the mapping ofquantum circuits onto molecules used in liquid state NMRquantum computing technology Their algorithm starts withamolecule to be used for computationmodeled as aweightedgraph with edges representing atomic couplings within themolecule The dataflow graph of the circuit is mapped ontothe molecule graph with an effort to minimize overall circuitlatency

Mohammadzadeh et al [8] proposed an optimizationtechnique applying gate location changing (GLC) to reducethe latency of quantumcircuitsTheproposed technique findscritical paths by the use of layout and scheduling informationand reduces their latency by modifying locations of the gateson the critical path These authors gave an introduction tothe physical synthesis concept in quantum circuits [20ndash22]which includes techniques that change the netlist using layoutinformation to improve latency andor area as the mainperformance indicators of the circuits

Yazdani et al [23] presented a physical design flow forquantum circuits in ion-trap technology which consists oftwo parts First a scheduler takes a description of a circuitand finds the best order for the execution of its quantumgates using ILPThen a layout generator receives the scheduleproduced by the scheduler and generates a layout for thiscircuit using a graph-drawing algorithm [24] This work usesILP only to schedule quantum circuits

To the best of our knowledge there is no ILP model inthe literature in which mapping scheduling and routing areconsidered simultaneously Focusing on this issue in thispaper a model is proposed for them in the physical designstage The proposed model gives the optimal mapping (ielocations of the gates) as well as the optimal routing andscheduling in terms of latency

3 The Proposed Approach

In this section a mixed integer linear programming model ispresented for scheduling routing and mapping of quantumcircuits This model is proposed to minimize latency of aquantum circuit It takes an initial netlist and a layout asinputs and finds the optimum initial locations for qubitsoptimum gate location for each gate and the optimumsequence of operations in such way that the latency of thecircuit is minimized (Figure 4)

Suppose that each gate has a processing time (p119894) where

119894 isin 1 2 119899 For one-qubit gates the processing time is1 120583s and for two-qubit gate is 10 120583s as mentioned in Table 1Each gate has a starting time (S

119894) that is a variable Due

to qubit congestion and gate dependencies all gates cannot

Table 1 Latency values for various physical operations in ion-traptechnology [25]

Physical operation Latency (120583s)One-qubit gate 1Two-qubit gate 10Straight movement 1Turn 10

execute concurrently Obviously the finishing time for eachgate would be S

119894+ p119894

Let 119895 isin 1 2 119899 be a set of locations and eachgate is located at one place Parameter 119889

1198951198951015840 indicates the

distance between location 119895 and location 1198951015840 and is calculatedusing values mentioned in Table 1 Strict Manhattan distanceis not an accurate measure to calculate distance betweenlocations because preliminary studies in ion-trap technologyhave shown that turning corners and traversing intersectionswill be more time consuming than moving straight througha one-way channel [26] Therefore in this paper a modifiedversion of Manhattan distance is used that considers thelatencies of both straight movement and turn in calculatingthe distance between gate locations The value of variable 119909

119894119895

denotes location of each gate Variable119909119894119895is 1 if gate 119894 is located

at location 119895Each gate may have two kinds of dependencies to other

gates If gate 119894 must be executed before gate 1198941015840 and it changesthe value of qubit 119902 and gate 1198941015840 needs this qubit thereforegate 1198941015840 has to wait until execution of gate 119894 is finished In theproposed model set 119910

1198941198941015840 represents this type of dependency

The other kind of dependency which is represented by set 1198921198941198941015840

occurs when both gate 119894 and gate 1198941015840need qubit 119902 in this casedata congestion would occur The binary variable 119891

1198941198941015840 is used

to model the second type of dependency if 1198911198941198941015840 = 1 it means

that gate 119894 is executed at first and if1198911198941198941015840 = 0 it means that gate 1198941015840

is executed at first In the following formulation119872 indicatesa very big number The proposed model is summarized asfollows

MILP Model

Minimize 119905 (1)

subject to

119878119894+ 119875119894le 119905 forall119894 isin 1 119899 (2)

119878119894+ 119875119894+ 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

1198941015840

forall (119894 1198941015840) isin 119910 forall119895 119895

1015840isin 1 119899

(3)


G0 H Q0

G1 H Q1

G2 H Q2

G3 H Q3

G4 H Q4

G5 H Q5

G6 H Q6

G7 CX Q5 Q7

G8 CX Q5 Q8

G9 CX Q3 Q6

G10 CX Q3 Q8

G11 CX Q3 Q7

G12 CX Q2 Q6

G13 CX Q2 Q5

G14 CX Q2 Q8

G15 CX Q1 Q6

G16 CX Q1 Q5

G17 CX Q1 Q7

G18 CX Q0 Q4

(a)

[13|6]

GLC Proposedapproach

[0|17] [8|15]

[1|16]

[2|8]

[3|18]

[4|4]

[5|10]

[6|14]

[7|11]

[7|1]

[11|3]

[14|5]

[9|0] [10|9]

[15|12][12|13]

[16|2]

[18|7]

[X|Y]

(b)

Figure 5 (a) A circuit netlist (b) The gate locations assigned by GLC technique and the proposed approach

119878119894+ 119875119894+ 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

1198941015840 +119872 sdot 119891

1198941198941015840


1015840isin 1 119899

(4)

1198781198941015840 + 1198751198941015840 + 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

119894+119872 sdot (1 minus 119891

1198941198941015840)


1015840isin 1 119899

(5)119899

sum119895=1

119909119894119895= 1 forall119894 isin 1 119899 (6)

119899

sum119894=1

119909119894119895= 1 forall119895 isin 1 119899 (7)

119909119894119895isin 0 1 forall119894 119895 isin 1 119899 (8)

1198911198941198941015840 isin 0 1 forall119894 119894

1015840isin 1 119899 (9)

119878119894ge 0 forall119894 isin 1 119899 (10)

119905 ge 0 (11)

Formula (1) illustrates the objectivemdashthemaximum com-pletion time (critical path)mdashto be minimized Formula (2)defines the critical path as the maximum completion time ofgates Formula (3) illustrates priority dependencies Formulas(4) and (5) are used to prevent congestions Based on thesetwo constraints either gate 119894 would be started first and gate 1198941015840starts after finishing time of gate 119894 plus the transferring timeof the common qubit or gate 1198941015840 starts first and gate 119894 startsafter finishing time of gate 1198941015840 plus the transferring time of thecommon qubit Formula (6) ensures that each gate locationis only assigned to one gate and (7) ensures that each gate islocated in only one location Constraints (9)-(10) are relatedto definition of variables

4 An Example

To illustrate the idea of the proposed approach an exampleis presented in this section Figure 5(a) shows QASM [27]instruction sequence of circuit [9-1-3] [28] The examplehas been solved by GLC technique [8] and the proposedapproach Physical latencies shown in Table 1 have been


Table 2 Benchmarks used for evaluation of the proposed model

Benchmark Number of gate Number of qubit Number of extended variables Number of extended constraints[6-0-2] 6 6 5 199[4-2-2] 7 4 62 806[5-2-2] 8 5 78 1049[6-2-2] 10 6 116 1831[5-0-3] 11 5 145 4148[5-1-3] 12 5 156 5653[ham3-D1] 12 3 189 11413[ham3-D2] 13 3 203 16771[mod5-D4] 14 5 239 13959[1bitAdder-rd32] 16 4 274 35377[7-1-3] 18 7 351 25651[10-0-2] 18 10 342 17875[9-1-3] 19 9 381 22440[9-3-2] 20 9 408 28871[7-0-3] 20 7 472 50461[13-1-3] 39 13 1605 334738[11-1-5] 47 11 4479 880661

29

Root

G0 G1 G2 G4 G5 G6G3

G7 G9

3 293

G18

23

G11

23 27

G13

26

G12G8

3

G10

3

G15

3

57

G16

23

G17

2336

34

1 1111 1

14 40

129

3

23

27

24

7750

7363

142

96 102

3

G14

23

54

137

Figure 6 Dataflow graph of the example based on the proposedmodel

used to calculate operation latency In this example latencyobtained by the GLC technique is 189 120583s while for theproposed model it is 142 120583s Figure 5(b) depicts the locationsassigned to each gate by the GLC technique and the proposed

050

100150200250300350400450

Num

ber o

fex

tend

ed v

aria

bles

[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]

Figure 7 The number of extended variables in each class ofbenchmarks

model The dataflow graph of the circuit which is attained bythe proposed approach is shown in Figure 6

5 Experimental Results

The computational analysis presented in this section is toevaluate the proposed model Different benchmarks wereselected from [28 29] The proposed model was fed with thedata of these benchmarks and solved using the CPLEX MIPsolver in GAMS tool [30] The software was run on a Dualcore 226GHz processor with 2GB of RAM After solvingthe benchmarks numbers of extended variables number ofextended constraints and the latency were calculated Table 2shows structure of the benchmarks with the numbers ofextended variables and number of extended constraints

In MILP models size of the model is a function of totalnumber of extended variables and constraints By increasing


[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]0

510152025303540

Num

ber o

fex

tend

ed c

onstr

aint

stimes10

3

Figure 8 The number of extended constraints in each class ofbenchmarks

Table 3 The latency of the benchmark circuits achieved by theproposed approach compared with [8]

Benchmark Latency (120583s) Improvement ()GLC [8] The proposed model

[4-2-2] 108 108lowast 0[5-2-2] 96 76lowast 2083[5-0-3] 138 132lowast 434[ham3-D1] 286 185 3531[ham3-D2] 323 230 2879[mod5-D4] 228 162 2894[1bitAdder-rd32] 310 277 1064[10-0-2] 283 175 3816[7-0-3] 288 252 1250[13-1-3] 417 314 2470lowastOptimal solution

the number of gates as well as complexity of data flow graphthe number of extended variables (Figure 7) and constraints(Figure 8) are increased The number of extended variablesvaries from 5 to 4479 while total number of extendedconstraints is between 199 and 880661

To evaluate the proposed model the latency of eachbenchmark is compared to results of the GLC technique [8]that is the best in the literature Table 3 shows the compu-tational results

Experimental results show that the proposedmodel couldfind the minimum latency for small circuits and improve thelatency of benchmarks up to 38 For larger circuits becauseof the exponential increase in the size of the problem MILPsolver cannot find the optimum solution but it still improvesthe latency Figure 9 depicts a comparable view on the resultsof the GLC algorithm and those of the proposed model foreach benchmark

As mentioned in Section 2 Yazdani et al [23] proposedan ILP-based approach that uses ILP to schedule a circuitTo evaluate the effectiveness of our approach over theirs acomparison has been done between the results obtained from

[4-2-2]

[5-2-2]

[5-0-3]

[ham3-D1]

[ham3-D2]

[mod5-D4]

[1bitAdder-rd32]

[7-0-3]

[10-0-2]

[13-1-3]

GLCThe proposed model

0

05

1

Figure 9 Improvement in the latency (120583s) of the benchmarksachieved by the proposed model

the proposed model the ILP-based approach [23] and GLCmethod [8] The computational results in Table 4 show theapproach proposed in this paper that improves the averagelatency by about 255 and 361 compared with GLC andprevious ILP-based approach respectively Figure 10 presentsa comparable view on the results of the proposedmodel GLCalgorithm [8 23]

In sum the proposed model adopts an integrated app-roach in which gate location problem routing and schedul-ing are optimized simultaneously The GLC technique [8]and the ILP-based model proposed in [23] are dominated bythe proposed model in all attempted benchmarks The GLCtechnique follows a hierarchal approach for gate locationrouting and scheduling of the circuits while in [23] anILP-based model is used to schedule a circuit and then theplacement procedure is done on the scheduled circuit

6 Conclusion

In this paper a mathematical model for mapping routingand scheduling in ion-trap technology was proposed forminimizing the latency of the quantum circuit The pro-posed model follows an integrated approach in which gatelocation assigning routing and scheduling are optimizedsimultaneously An example was analyzed to illustrate theapplication of the proposed model Moreover some analysiswas done on different size of benchmarks to evaluate theefficiency of the proposed model in comparison to the bestwork reported in the literature The proposed model couldoffer a considerable amount of improvement in all attemptedcircuits The results showed that it is possible to obtainoptimal or near optimal solutionswithin a reasonable amountof time for small sizes instances However when the size of


Table 4 The latency of the benchmark circuits achieved by the proposed approach compared with [8 23]

Benchmark Latency (120583s) Improvement ()The proposed model GLC [8] Yazdani et al [23] Over GLC [8] Over Yazdani et al [23]

[6-0-2] 14 38 23 6315 3913[6-2-2] 76 121 121 3719 3719[5-1-3] 152 191 239 2041 3640[7-1-3] 155 205 263 2439 4106[9-1-3] 142 170 383 1647 6292[9-3-2] 192 202 259 495 2586[11-1-5] 595 677 659 1211 971Average 255 361

0

05

1[6-0-2]

[6-2-2]

[5-1-3]

[7-1-3][9-1-3]

[9-3-2]

[11-1-5]

The proposed modelGLCYazdani et al (2013)


benchmarks was larger more time and space are required toachieve the optimal solution The future work is to developsome heuristic solution methods for optimization of largebenchmarks

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] R P Feynman ldquoQuantummechanical computersrdquo Foundationsof Physics vol 16 no 6 pp 507ndash531 1986

[2] A Barenco C H Bennett R Cleve et al ldquoElementary gatesfor quantum computationrdquo Physical Review A vol 52 no 5 pp3457ndash3467 1995

[3] H Haffner C F Roos and R Blatt ldquoQuantum computing withtrapped ionsrdquo Physics Reports vol 469 no 4 pp 155ndash203 2008

[4] D Kielpinski C Monroe and D J Wineland ldquoArchitecture fora large-scale ion-trap quantum computerrdquo Nature vol 417 no6890 pp 709ndash711 2002

[5] T SMetodi and F T ChongQuantumComputing for ComputerArchitects vol 1 of Synthesis Lectures in Computer Architecture2006

[6] MWhitney Practical fault tolerance for quantum circuits [PhDthesis] University of California Berkeley Calif USA 2009

[7] S B Bravyi and A Y Kitaev ldquoQuantum codes on a lattice withboundaryrdquoQuantum Computers and Computing vol 2 pp 43ndash48 2001

[8] N Mohammadzadeh M S Zamani and M Sedighi ldquoGatelocation changing an optimization technique for quantumcircuitsrdquo World Scientific International Journal of QuantumInformation vol 10 no 3 Article ID 1250037 20 pages 2012

[9] M Whitney N Isailovic Y Patel and J Kubiatowicz ldquoAuto-mated generation of layout and control for quantum circuitsrdquoin Proceedings of the 4th Conference on Computing Frontiers pp83ndash94 May 2007

[10] DMaslov C Young DMMiller and GW Dueck ldquoQuantumcircuit simplification using templatesrdquo in Proceedings of theDesign Automation and Test in Europe (DATE rsquo05) pp 1208ndash1213 March 2005

[11] D Maslov G W Dueck and D M Miller ldquoSimplificationof toffoli networks via templatesrdquo in Proceedings of the 16thSymposium on Integrated Circuits and System Design pp 53ndash582003

[12] V V Shende A K Prasad K N Pate I L Markov andJ P Hayes ldquoScalable simplification of reversible circuitsrdquo inProceedings of the 12th International Workshop on Logic andSynthesis (IWLS rsquo03) 2003

[13] M Sedlak and M Plesch ldquoTowards optimization of quantumcircuitsrdquo Central European Journal of Physics vol 6 no 1 pp128ndash134 2008

[14] A Aho and K Svore ldquoThe design and optimization of quantumcircuits using the palindrome transformrdquo in Proceedings of theERATO Conference on Quantum Information Sciences (EQISrsquo03) pp 4ndash6 2003

[15] T S Metodi D S Thaker A Cross and F T Chong ldquoSchedul-ing physical operations in a quantum information processorrdquoin Defense and Security Symposium vol 6244 of Proceedingsof SPIE International Society for Optics and Photonics 200662440T

[16] M J Dousti and M Pedram ldquoMinimizing the latency ofquantum circuits during mapping to the ion trap circuit fabricrdquoin Proceedings of the Design Automation amp Test in EuropeConference amp Exhibition (DATE rsquo12) pp 840ndash843 2012


[17] S Balensiefer L Kreger-Stickles andMOskin ldquoQUALE quan-tum architecture layout evaluatorrdquo inQuantum Information andComputation III vol 5815 of Proceedings of SPIE pp 103ndash114March 2005

[18] S Balensiefer L Kregor-Stickles and M Oskin ldquoAn evaluationframework and instruction set architecture for ion-trap basedquantum micro-architecturesrdquo in Proceedings of the IEEE 32ndInterntional Symposium on Computer Architecture (ISCA rsquo05)pp 186ndash196 June 2005

[19] D Maslov S M Falconer and M Mosca ldquoQuantum cir-cuit placement optimizing qubit-to-qubit interactions throughmapping quantum circuits into a physical experimentrdquo in Pro-ceedings of the 44th ACMIEEE Design Automation Conference(DAC rsquo07) pp 962ndash965 San Diego Calif USA June 2007

[20] NMohammadzadehM Sedighi andM S Zamani ldquoQuantumphysical synthesis improving physical design by netlist modi-ficationsrdquo Microelectronics Journal vol 41 no 4 pp 219ndash2302010

[21] N Mohammadzadeh M S Zamani andM Sedighi ldquoAuxiliaryqubit selection a physical synthesis technique for quantumcircuitsrdquo Quantum Information Processing vol 10 no 2 pp139ndash154 2011

[22] N Mohammadzadeh M S Zamani and M Sedighi ldquoImprov-ing latency of quantum circuits by gate exchangingrdquo in Proceed-ings of the IEEE 12th Euromicro Conference on Digital SystemDesign (DSD rsquo09) pp 67ndash73 Patras Greece August 2009

[23] M YazdaniM S Zamani andM Sedighi ldquoA quantumphysicaldesign flowusing ilp and graph drawingrdquoQuantum InformationProcessing vol 12 no 10 pp 3239ndash3264 2013

[24] ldquoGDToolkitrdquo 2013 httpwwwdiauniroma3itsimgdtgdt4indexphp

[25] N Isailovic An investigation into the realities of a quantumdatapath [PhD thesis] University of California 2010

[26] C E Pearson D R Leibrandt W S Bakr W J Mallard K RBrown and I L Chuang ldquoExperimental investigation of planarion trapsrdquo Physical Review A vol 73 no 3 Article ID 03230712 pages 2006

[27] A Cross Synthesis and evaluation of fault-tolerant quantumcomputer architectures [PhD thesis] Massachusetts Institute ofTechnology 2005

[28] M Grassl ldquoCircuits for quantum error-correcting codesrdquo 2013httpiaks-wwwiraukadehomegrasslQECCindexhtml

[29] D Maslov G Dueck and N Scott ldquoReversible logic synthesisbenchmarks pagerdquo 2013 httpwwwcsuviccasimdmaslov

[30] ldquoGAMSrdquo 2013 httpwwwgamscom

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Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks



High level description

Scheduled layout

Synthesis

Physical design

Technology-dependent netlist

Figure 1 Quantum circuit design flow [9]

Gate laserMEMS mirrors

Trap regions

Electrodes

Ion (qubit)

Figure 2 Simplified ion-trap technology view [5]

Dead end gate

Straight channel gate

Straight channel Turn

P1P1

P1P1 P1

P0 P0 P0 P0 P0P0P2 P2

P3

Three-wayintersection

Four-wayintersection

Figure 3 Library of basic macroblocks used in this paper [6]

is presented in Section 4 Section 5 shows the experimentalresults and Section 6 concludes the paper

2 Related Work

There are a lot of techniques proposed for optimization insynthesis process [6 10ndash14] but a few studies have been doneon optimization problems in the quantum physical stage

Metodi et al [15] presented a physical operations sched-uler (QPOS) which takes a description of a circuit and a def-inite physical layout and produces a sequence of operationswhich indicates the required communication and possibleparallelism in the circuit Dousti and Pedram [16] presented

an algorithm for scheduling placement and routing of aquantum circuit which decreases the circuit latency Theydeveloped a heuristic for placement called MVFB whichimproved the center placement used in the previous quantumCAD tool [17 18] Balensiefer et al [17 18] proposed a designflow and compilation technique to consider fault-toleranceand developed some tools to appraise layouts Whitney et al[9] proposed a computer-aided design flow for the layoutscheduling and control of ion-trap-based quantum circuitsThey proposed two heuristics for layout design The firstheuristic is a greedy algorithm that is appropriate for smallcircuits Dataflow-based algorithm was proposed for largercircuits aiming at placement and routing


The proposed

modelA layout
















119894+ p119894


1198951198951015840 indicates the


119894119895







1198941198941015840 is used




MILP Model

Minimize 119905 (1)

subject to

119878119894+ 119875119894le 119905 forall119894 isin 1 119899 (2)

119878119894+ 119875119894+ 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

1198941015840


1015840isin 1 119899

(3)


G0 H Q0

G1 H Q1

G2 H Q2

G3 H Q3

G4 H Q4

G5 H Q5

G6 H Q6

G7 CX Q5 Q7

G8 CX Q5 Q8

G9 CX Q3 Q6

G10 CX Q3 Q8

G11 CX Q3 Q7

G12 CX Q2 Q6

G13 CX Q2 Q5

G14 CX Q2 Q8

G15 CX Q1 Q6

G16 CX Q1 Q5

G17 CX Q1 Q7

G18 CX Q0 Q4

(a)

[13|6]


[0|17] [8|15]

[1|16]

[2|8]

[3|18]

[4|4]

[5|10]

[6|14]

[7|11]

[7|1]

[11|3]

[14|5]

[9|0] [10|9]

[15|12][12|13]

[16|2]

[18|7]

[X|Y]

(b)


119878119894+ 119875119894+ 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

1198941015840 +119872 sdot 119891

1198941198941015840


1015840isin 1 119899

(4)

1198781198941015840 + 1198751198941015840 + 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

119894+119872 sdot (1 minus 119891

1198941198941015840)


1015840isin 1 119899

(5)119899

sum119895=1

119909119894119895= 1 forall119894 isin 1 119899 (6)

119899

sum119894=1

119909119894119895= 1 forall119895 isin 1 119899 (7)

119909119894119895isin 0 1 forall119894 119895 isin 1 119899 (8)

1198911198941198941015840 isin 0 1 forall119894 119894

1015840isin 1 119899 (9)

119878119894ge 0 forall119894 isin 1 119899 (10)

119905 ge 0 (11)


4 An Example





29

Root

G0 G1 G2 G4 G5 G6G3

G7 G9

3 293

G18

23

G11

23 27

G13

26

G12G8

3

G10

3

G15

3

57

G16

23

G17

2336

34

1 1111 1

14 40

129

3

23

27

24

7750

7363

142

96 102

3

G14

23

54

137



050

100150200250300350400450

Num

ber o

fex

tend

ed v

aria

bles

[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]







[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]0

510152025303540

Num

ber o

fex

tend

ed c

onstr

aint

stimes10

3









[4-2-2]

[5-2-2]

[5-0-3]

[ham3-D1]

[ham3-D2]

[mod5-D4]

[1bitAdder-rd32]

[7-0-3]

[10-0-2]

[13-1-3]


0

05

1




6 Conclusion





[6-0-2] 14 38 23 6315 3913[6-2-2] 76 121 121 3719 3719[5-1-3] 152 191 239 2041 3640[7-1-3] 155 205 263 2439 4106[9-1-3] 142 170 383 1647 6292[9-3-2] 192 202 259 495 2586[11-1-5] 595 677 659 1211 971Average 255 361

0

05

1[6-0-2]

[6-2-2]

[5-1-3]

[7-1-3][9-1-3]

[9-3-2]

[11-1-5]






References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










The proposed

modelA layout
















119894+ p119894


1198951198951015840 indicates the


119894119895







1198941198941015840 is used




MILP Model

Minimize 119905 (1)

subject to

119878119894+ 119875119894le 119905 forall119894 isin 1 119899 (2)

119878119894+ 119875119894+ 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

1198941015840


1015840isin 1 119899

(3)


G0 H Q0

G1 H Q1

G2 H Q2

G3 H Q3

G4 H Q4

G5 H Q5

G6 H Q6

G7 CX Q5 Q7

G8 CX Q5 Q8

G9 CX Q3 Q6

G10 CX Q3 Q8

G11 CX Q3 Q7

G12 CX Q2 Q6

G13 CX Q2 Q5

G14 CX Q2 Q8

G15 CX Q1 Q6

G16 CX Q1 Q5

G17 CX Q1 Q7

G18 CX Q0 Q4

(a)

[13|6]


[0|17] [8|15]

[1|16]

[2|8]

[3|18]

[4|4]

[5|10]

[6|14]

[7|11]

[7|1]

[11|3]

[14|5]

[9|0] [10|9]

[15|12][12|13]

[16|2]

[18|7]

[X|Y]

(b)


119878119894+ 119875119894+ 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

1198941015840 +119872 sdot 119891

1198941198941015840


1015840isin 1 119899

(4)

1198781198941015840 + 1198751198941015840 + 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

119894+119872 sdot (1 minus 119891

1198941198941015840)


1015840isin 1 119899

(5)119899

sum119895=1

119909119894119895= 1 forall119894 isin 1 119899 (6)

119899

sum119894=1

119909119894119895= 1 forall119895 isin 1 119899 (7)

119909119894119895isin 0 1 forall119894 119895 isin 1 119899 (8)

1198911198941198941015840 isin 0 1 forall119894 119894

1015840isin 1 119899 (9)

119878119894ge 0 forall119894 isin 1 119899 (10)

119905 ge 0 (11)


4 An Example





29

Root

G0 G1 G2 G4 G5 G6G3

G7 G9

3 293

G18

23

G11

23 27

G13

26

G12G8

3

G10

3

G15

3

57

G16

23

G17

2336

34

1 1111 1

14 40

129

3

23

27

24

7750

7363

142

96 102

3

G14

23

54

137



050

100150200250300350400450

Num

ber o

fex

tend

ed v

aria

bles

[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]







[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]0

510152025303540

Num

ber o

fex

tend

ed c

onstr

aint

stimes10

3









[4-2-2]

[5-2-2]

[5-0-3]

[ham3-D1]

[ham3-D2]

[mod5-D4]

[1bitAdder-rd32]

[7-0-3]

[10-0-2]

[13-1-3]


0

05

1




6 Conclusion





[6-0-2] 14 38 23 6315 3913[6-2-2] 76 121 121 3719 3719[5-1-3] 152 191 239 2041 3640[7-1-3] 155 205 263 2439 4106[9-1-3] 142 170 383 1647 6292[9-3-2] 192 202 259 495 2586[11-1-5] 595 677 659 1211 971Average 255 361

0

05

1[6-0-2]

[6-2-2]

[5-1-3]

[7-1-3][9-1-3]

[9-3-2]

[11-1-5]






References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










G0 H Q0

G1 H Q1

G2 H Q2

G3 H Q3

G4 H Q4

G5 H Q5

G6 H Q6

G7 CX Q5 Q7

G8 CX Q5 Q8

G9 CX Q3 Q6

G10 CX Q3 Q8

G11 CX Q3 Q7

G12 CX Q2 Q6

G13 CX Q2 Q5

G14 CX Q2 Q8

G15 CX Q1 Q6

G16 CX Q1 Q5

G17 CX Q1 Q7

G18 CX Q0 Q4

(a)

[13|6]


[0|17] [8|15]

[1|16]

[2|8]

[3|18]

[4|4]

[5|10]

[6|14]

[7|11]

[7|1]

[11|3]

[14|5]

[9|0] [10|9]

[15|12][12|13]

[16|2]

[18|7]

[X|Y]

(b)


119878119894+ 119875119894+ 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

1198941015840 +119872 sdot 119891

1198941198941015840


1015840isin 1 119899

(4)

1198781198941015840 + 1198751198941015840 + 1198891198951198951015840 + (119909

119894119895+ 11990911989410158401198951015840 minus 2) sdot 119872 le 119878

119894+119872 sdot (1 minus 119891

1198941198941015840)


1015840isin 1 119899

(5)119899

sum119895=1

119909119894119895= 1 forall119894 isin 1 119899 (6)

119899

sum119894=1

119909119894119895= 1 forall119895 isin 1 119899 (7)

119909119894119895isin 0 1 forall119894 119895 isin 1 119899 (8)

1198911198941198941015840 isin 0 1 forall119894 119894

1015840isin 1 119899 (9)

119878119894ge 0 forall119894 isin 1 119899 (10)

119905 ge 0 (11)


4 An Example





29

Root

G0 G1 G2 G4 G5 G6G3

G7 G9

3 293

G18

23

G11

23 27

G13

26

G12G8

3

G10

3

G15

3

57

G16

23

G17

2336

34

1 1111 1

14 40

129

3

23

27

24

7750

7363

142

96 102

3

G14

23

54

137



050

100150200250300350400450

Num

ber o

fex

tend

ed v

aria

bles

[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]







[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]0

510152025303540

Num

ber o

fex

tend

ed c

onstr

aint

stimes10

3









[4-2-2]

[5-2-2]

[5-0-3]

[ham3-D1]

[ham3-D2]

[mod5-D4]

[1bitAdder-rd32]

[7-0-3]

[10-0-2]

[13-1-3]


0

05

1




6 Conclusion





[6-0-2] 14 38 23 6315 3913[6-2-2] 76 121 121 3719 3719[5-1-3] 152 191 239 2041 3640[7-1-3] 155 205 263 2439 4106[9-1-3] 142 170 383 1647 6292[9-3-2] 192 202 259 495 2586[11-1-5] 595 677 659 1211 971Average 255 361

0

05

1[6-0-2]

[6-2-2]

[5-1-3]

[7-1-3][9-1-3]

[9-3-2]

[11-1-5]






References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation












29

Root

G0 G1 G2 G4 G5 G6G3

G7 G9

3 293

G18

23

G11

23 27

G13

26

G12G8

3

G10

3

G15

3

57

G16

23

G17

2336

34

1 1111 1

14 40

129

3

23

27

24

7750

7363

142

96 102

3

G14

23

54

137



050

100150200250300350400450

Num

ber o

fex

tend

ed v

aria

bles

[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]







[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]0

510152025303540

Num

ber o

fex

tend

ed c

onstr

aint

stimes10

3









[4-2-2]

[5-2-2]

[5-0-3]

[ham3-D1]

[ham3-D2]

[mod5-D4]

[1bitAdder-rd32]

[7-0-3]

[10-0-2]

[13-1-3]


0

05

1




6 Conclusion





[6-0-2] 14 38 23 6315 3913[6-2-2] 76 121 121 3719 3719[5-1-3] 152 191 239 2041 3640[7-1-3] 155 205 263 2439 4106[9-1-3] 142 170 383 1647 6292[9-3-2] 192 202 259 495 2586[11-1-5] 595 677 659 1211 971Average 255 361

0

05

1[6-0-2]

[6-2-2]

[5-1-3]

[7-1-3][9-1-3]

[9-3-2]

[11-1-5]






References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










[6-0

-2]

[4-2

-2]

[5-2

-2]

[6-2

-2]

[5-0

-3]

[5-1

-3]

[ham

3-D

1]

[ham

3-D

2]

[mod

5-D

4]

[1bi

tAdd

er-r

d32

]

[7-1

-3]

[10

-0-2

]

[9-1

-3]

[9-3

-2]0

510152025303540

Num

ber o

fex

tend

ed c

onstr

aint

stimes10

3









[4-2-2]

[5-2-2]

[5-0-3]

[ham3-D1]

[ham3-D2]

[mod5-D4]

[1bitAdder-rd32]

[7-0-3]

[10-0-2]

[13-1-3]


0

05

1




6 Conclusion





[6-0-2] 14 38 23 6315 3913[6-2-2] 76 121 121 3719 3719[5-1-3] 152 191 239 2041 3640[7-1-3] 155 205 263 2439 4106[9-1-3] 142 170 383 1647 6292[9-3-2] 192 202 259 495 2586[11-1-5] 595 677 659 1211 971Average 255 361

0

05

1[6-0-2]

[6-2-2]

[5-1-3]

[7-1-3][9-1-3]

[9-3-2]

[11-1-5]






References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation












[6-0-2] 14 38 23 6315 3913[6-2-2] 76 121 121 3719 3719[5-1-3] 152 191 239 2041 3640[7-1-3] 155 205 263 2439 4106[9-1-3] 142 170 383 1647 6292[9-3-2] 192 202 259 495 2586[11-1-5] 595 677 659 1211 971Average 255 361

0

05

1[6-0-2]

[6-2-2]

[5-1-3]

[7-1-3][9-1-3]

[9-3-2]

[11-1-5]






References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation


























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









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Research Article Optimal ILP-Based Approach for …downloads.hindawi.com/journals/mse/2014/571374.pdfResearch Article Optimal ILP-Based Approach for Gate Location Assignment and Scheduling