Research ArticleHardware Implementation of 32-Bit High-Speed DirectDigital Frequency Synthesizer

Salah Hasan Ibrahim12 Sawal Hamid Md Ali2 and Md Shabiul Islam3

1 Department of Electronics College of Engineering Diyala University Baqubah Diyala 32001 Iraq2Department of Electrical Electronics amp System Engineering Faculty of Engineering Universiti KebangsaanMalaysia (UKM) 43600 Bangi Malaysia

3 Institute of Microengineering and Nanoelectronics (IMEN) Universiti Kebangsaan Malaysia (UKM) 43600 Bangi Malaysia

Correspondence should be addressed to Salah Hasan Ibrahim mrsalah65yahoocom

Received 4 February 2014 Revised 13 March 2014 Accepted 29 April 2014 Published 2 June 2014

Academic Editor Robert Adams

Copyright copy 2014 Salah Hasan Ibrahim et al This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

The design and implementation of a high-speed direct digital frequency synthesizer are presented A modified Brent-Kung paralleladder is combined with pipelining technique to improve the speed of the system A gated clock technique is proposed to reducethe number of registers in the phase accumulator designThe quarter wave symmetry technique is used to store only one quarter ofthe sine wave The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition techniqueand trigonometric identity Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates one sub-ROM block can be removed from the design These techniques compressed the ROM into 368 bits The ROM compressed ratio is5342 1 with only two adders two multipliers and XOR-gates with high frequency resolution of 0029HzThese techniques makethe direct digital frequency synthesizer an attractive candidate for wireless communication applications

1 Introduction

Direct digital frequency synthesis (DDFS) systems with high-speed frequency hopping function low power consumptionhigh frequency resolution and small chip area are in agreat demand for DDFS applications especially in wirelesscommunications and radar systems DDFS systems have lownoise and high frequency resolution compared with phaselock loop [1] The DDFS output frequency (119865out) is given by

119865out = (FCW2119873

) lowast 119865clk (1)

where 119865clk is clock frequency FCW is a frequency controlword and 119873 is the phase accumulator width Pipeliningtechnique is defined as a technique that partitioned the giventask into a number of subtasks that need to be performedin a sequence The pipelining technique is used in [2ndash4] toincrease the throughput of the output frequency Howeverthis technique also increases the power consumption andchip area The gated clock technique was applied to the

pipeline phase accumulator (PA) in [5] to reduce the numberof registers without performance degradation A paralleladder based on progression-of-states technique was com-bined with the pipelining technique in [6 7] for high-speedlow power pipelined parallel PA The pipelined accumulatorwith parallel adder technique was proposed in [8] In thispaper two blocks of parallel 16-bit ripple carry adder (RCA)are designed based on the progression-of-states techniquewith two pipelining stages

DDFS spectral purity depends on the number of thephase output bits used for addressing the ROM Thereforethe higher spectral purity required the bigger ROM sizeneeded The quarter wave symmetry in [9 10] was appliedas a simple technique to reduce the ROM size storing onlyquarter (0 1205872) of the sine wave bits and using thetwo most significant bits (MSB) to generate the full sinewave (2120587) Quarter wave symmetry together with an angulardecomposition method based on trigonometric identity wasused in [11ndash13] to compress the ROM size by partitioningthe ROM into three sub-ROMs This technique was also

Hindawi Publishing Corporatione Scientific World JournalVolume 2014 Article ID 131568 9 pageshttpdxdoiorg1011552014131568

2 The Scientific World Journal

8

8

8

8

+

+

+

+

8-bit reg

8-bit reg

8-bit reg

8-bit reg 8-bit reg

8-bit reg 8-bit reg

8-bit reg 8-bit reg 8-bit reg 8-bit reg

8-bit reg 8-bit reg 8-bit reg8-bit reg

Figure 1 The conventional 32-bit pipelining phase accumulator

used in [14] where the ROM is partitioned into two ROMsnamely coarse and fine ROMs to obtain the quadratureoutputs sine and cosine values The author suggested severalDDFS systems implemented with different types of FPGA kitboards and compared them with an ASIC based approach

The polynomial approximation method was used inDDFS design to optimize the spurious-free dynamic range(SFDR) This method was used by Ashrafi and Adhamiin [15] to determine the upper bound of the SFDR usingpiecewise polynomial interpolation Fourier series was usedto establish a linear relationship between the coefficients ofthe interpolating polynomials and the frequency spectrumThis method can be used in any kind of DDFS to maximizethe SFDR

De Caro et al proposed a dual-slope technique in [16]to optimize the piecewise linear approximation for the phaseto sine mapping This technique improves the spectral purityand ROM size The stored values of the two quarters (1205874)sine and cosine sub-ROMs with 3MSB bits and mapper arerequired to accomplish the quarter phase to sinemapping andproduce quadrature output from the DDFS In [17] De Caroet al proposed another DDFS architecture which is based onpiecewise linear approximation technique with nonuniformsegment length to the input of three groups of multiplexerThis technique can maximize the SFDR and reduce the sizeof the coefficients ROM

This paper presents a high-speed DDFS system withpipelined PA based on modified parallel BK adder andgated clock technique The ROM was resized by applyingthe quarter-wave symmetry technique in one quarter of thesine wave and an angular decomposition technique basedon trigonometric identity has been applied to compress thequarter ROM LUT Based on these techniques the quarterROM LUT was partitioned into three sub-ROMs (119860 119861 and

119862) The proposed architecture improves the speed of theDDFS and reduces the size of the ROMs

2 The Gated Clock and Parallel PipeliningTechnique for Phase Accumulator

Themodified parallel BK adder based on the progression-of-states technique combined with gated clock technique wasused in the proposed design of the PA The frequency reso-lution (119865Res) of DDFS is determined by the clock frequency(119865clk) and the number of119873 input bit of the PA as depicted by

119865Res =119865clk2119873

(2)

For high frequency resolution it is preferable to design aPA with large FCW bits input However a large ROM size isrequired to implement all the 2119873 bits of phase accumulatoroutput Due to this reason a part of the MSB phase outputis used to address the phase to amplitude converter or ROMlookup table while maintaining high frequency resolutionThe pipeline technique was used to increase the throughputof the accumulator and this throughput will double with thenumber of pipeline stages as shown in Figure 1

The number of registers increases with the number ofpipeline stages which leads to high power consumptionTherefore in this design a gated clock technique was used toreduce the number of preskewing registers while preservinghigh-speed operation In this technique D flip-flops (DFFs)were used to connect each row of the pipeline stages withFCW input These registers are clocked by the pipelinedpulses with one clock cycle based on the shifted clockpulses as shown in Figure 2(a) Considering that the phaseaccumulator input bits are 119873 the PA was partitioned into 119871

The Scientific World Journal 3

FclkK

DFF DFF DFF DFFSet

Clk

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8 9

1 Td 2 Td 3 Td

A

A

B

B

C

C

Vcc

(a)

+

+

+

+

8-DFF

OUT X(T + 3)OUT X(T + 4)

OUT X(T + 2)

OUT X(T + 1)

IN [7 2]LOW [1 0]

IN [7 0]LOW [1 0]

IN [7 1]LOW [0]

[7 0][7 0]

[7 0]

[7 0]

(b)

Parallel adder

Pipelined PA outputMultiplexer

X1

X2

X3

X4

1 2 3 4 Clk4 Clk

(c)

Figure 2 (a) The gated clock technique (b) parallel adder based on progression-of-states technique and (c) pipelined PA output

stages with B DFFs in each stageThe number of the DFFs119870for preskewing registers is given by

119870 =(119873 lowast (119871 + 1))

2 (3)

By applying the gated clock technique on the proposeddesign the number of DFFs is given by

119870 = 119873 + 119871 (4)

As a result with the gated clock technique the numbersof preskewing registers have been reduced from 80 to 36corresponding to 537 reduction

Figure 2(b) shows the operation of the parallel adderFour adders calculate the holding constant of 8-bit inputwordwithin four clock cycles Holding the FCW for four clockcycles limits the update rate of the frequency input wordbut does not cause any glitch because the four adders willsteadily increase the accumulator output four times Assumethat FCW is 119873 and the parallel adder output is 119883 at the 119879thclock time The parallel adderrsquos outputs are given as follows

119883 (119879 + 1) = 119873 + 119883 (119879)

119883 (119879 + 2)

= 119883 (119879 + 1) + 119883 (119879) = 119873 + 119883 (119879) + 119883 (119879) = 119873 + 2119883 (119879)

119883 (119879 + 3) = 119883 (119879 + 2) + 119883 (119879) = 119873 + 3 119883 (119879)

119883 (119879 + 4) = 119883 (119879 + 3) + 119883 (119879) = 119873 + 4119883 (119879)

(5)

The result of the fourth adder is set as a feedback to the secondinput for all the four adders To generate the second output[119883(119879+2)] and fourth output [119883(119879+4)] the119873 bit is shifted upby removing one and two bits of the FCW input and replacingthem with the one and two bits from the lower pipeliningstage respectively before they are addedThe119883(119879+2) outputand119883(119879) output are used to generate119883(119879 + 3)

This operationmade the frequency tuningword held con-stant for four clock cycles without causing any imperfectionsin the PA output The partitioned clock cycles (1198621198971198964) makethe multiplexers choose one of the results at the output of thePA to overcome the holding time on the parallel adders asillustrated in Figure 2(c)

3 Phase Accumulator Architecture

The proposed phase accumulator architecture based on themodified parallel BK adder and the gated clock techniquewith pipelining stages is shown in Figure 3 The output of thePA is a truncated 14-bit value that is achieved from the 8 and6 bits of the top and second pipelining stages respectively

The 32-bit FCW input is sufficient to obtain 0029Hzfrequency resolution from the 125MHz clock frequency ofCyclone III FPGA kit board (119865Res = 125 times 106232 =

0029Hz)

31Modifying Brent-KungAdder TheBKadder is fast and allcarries are computed simultaneously through a binary tree ofldquoBKrdquo cells as shown in Figure 4(a)

4 The Scientific World Journal

+

+

+

+

+

+

+

+

+

+

+

+

8-DFF

4-DFF

4-DFF

8-DFF 6-DFF

6-DFF

6-DFF

6-DFF

8-DFF

8-DFF

8-DFF

8-DFF

8 OUT X4

8 OUT X3

8 OUT X2

8 OUT X1

6 OUT X4

6 OUT X3

6 OUT X2

6 OUT X1

32

8 8

248

8

8

8

8

8

Clk4 Clk4

DFF

DFF

DFF

DFFDFF

MUX

MU

X

MUX

K

Set

Clk

Clk Clk

Clk

14

8

6

IN [7 2]

IN [7 0]

IN [7 0]

LOW [1 0]IN [7 2]

LOW [1 0]

LOW [1 0]IN [7 0]

LOW [1 0]IN [7 1]LOW [0]

IN [7 1]LOW [0]

IN [31 24]

IN [23 16]

IN [15 8]

[1 0

][9

8]

[17

16] 4 times 1

4 times 1

OUT [31 18]

8-bit reg 8-bit reg

8-bit reg

8-bit reg

8-bit reg

8-bit reg 6-bit reg8-bit reg

8-bit reg

8-bit reg

24-bit reg

24-bit reg

32-bit reg

18-bit reg

Figure 3 Pipelined phase accumulator with parallel adder based on modifying Bren-Kung adder and gated clocking technique

BK cells compute the carry for two or more of full adder(FA) cells and they are calculated as a sum of 119866 and 119875 cells[23 24] The arithmetic operation is given by

BK = 119866 + 119875

119866 = 11989210158401015840+ 11990110158401015840sdot 1198921015840

119875 = 11990110158401015840sdot 1199011015840

(6)

where 119892101584010158401198921015840 119901101584010158401199011015840 are higher and lower generate and prop-agate functions respectively The 119901 is a propagate function(119901119894= 119909119894oplus 119910119894) and 119892 is a generate function (119892

119894= 119909119894sdot 119910119894)

The general prefix addition algorithm is explained byZimmermann in [25] By adding the carry input 119862in in theprefix structure with somemodifications the prefix structurecan be used in pipelining-based adder design This approachis used in BK adder fast carry computation However inthis paper a modification is proposed to the BK adder sothat it can be used in pipelining architecture The proposedmodification is by removing the operation of the 119892

0 and

the carry out of the first bit 1198621can be achieved by a 2-1

multiplexer The input to this multiplexer is 1199090and 119862in while

1199010is the select input and the output is 119862

1 The operation of

the multiplexer is given by

1198621= (1199010 119888in) + (119909

0 1199010) (7)

where 1198621is the carry out 119901

0is the propagate function 119862in

is the carry input and 1199090is the first bit input The proposed

modification of the 8-bit BK adder is shown in Figure 4(b)The sum and carry out of the modified 8-bit BK adder areshown in

1198780= 1199010oplus 119888in

119878119873sdotsdotsdot1

= 119901((119873minus1)sdotsdotsdot1)

oplus 119862((119873minus1)sdotsdotsdot1)

119862out = 119892119873+ 119901119873sdot 119862119873

(8)

311 Comparison of Different Adder Architecture An adderis a key element of the pipelining PA design and a fastadder improves PA performance Parallel-prefix adder treestructures such as Sklansky [26] Kogge-Stone adder [27] BK[23] and Beaumont-Smith [28] have been used in pipeliningaccumulator design for high-speed operation

A comparison has been made between conventionaladder and several parallel-prefix adders for 12-bit 18-bit 24-bit and 32-bit operations The PA designs were coded inVerilog HDL and verified in Cyclone III FPGA kit boardPrior to that all the designs were simulated by usingALTERAQuartus IIThe comparison result is shown in Figure 5 Fromthe figure it can be seen that BK adder performs relativelyfaster especially for high number of bits

4 ROM Lookup Table Design

ROM LUT or phase-to-amplitude converter (PAC) is amemory storage address for DDFS which is used to convert

The Scientific World Journal 5

P0P1P2P3P4P5P6P7

x0x1x7 y0y1y7

P middot gP middot gP middot gP middot gP middot gP middot gP middot g p g

S0S1S2S3S4S5S6S7

SSSSSSSS

BK

BK

BK

BK BK

BK

BK

BKBK

BK

BK

Criticalpath

g0g1g2g3g4g5g6g7 p0p1p2p3p4p5p6P7

middot middot middot

middot middot middot middot middot middot middot

(a)

P2P3P4P5P6P7

x0x1 y0y1x7 y7

P middot g P middot g P middot g P middot g P middot g P middot g P middot g

S0S1S2S3S4S5S6S7

S S S S S S S S

BK

BK

BK

BK

BK BK BK

BK

BK

BK BK

Criticalpath

p

Cin

Cin

C1

C1

g1g2g3g4g5g6g7 p1p2p3p4p5p6P7 middotp

middot middot middot

middot middot middot middot middot middot middot

MU

X

(b)

Figure 4 Block circuit diagram of conventional Brent-Kung adder (a) and (b) modifying Brent-Kung adder

450

400

350

300

250

200

150

100

Max

imum

ope

ratio

n fre

quen

cy (M

Hz)

10 15 20 25 30 35

Number of bits

CLARCABrent-Kung

Kogge-StoneSklanskyBeaumont Smith

Figure 5 Comparison result of maximum operating frequency(119865Max) for phase accumulator design with CLA Brent-Kung Kogge-Stone Sklansky Beaumont-Smith and RCA adders

the phase signal into an amplitude sine wave signal High-accuracy output signal for DDFS requires a large number ofLUT The ROM size exponentially increases with increasingnumber of bit inputs The designerrsquos challenge is a tradeoffbetween reducing the ROM size while maintaining highperformance (high resolution high speed) Quarter-wavesymmetry technique is used to resize the ROM in theproposed DDFS design to store only one quarter (0 1205872) of

+

+

24 times 11Bit ROM

Bit ROM

Bit ROM

28 times 4

24 times 4

times

times

11

11

11

11

11

4

4

4

B

C

C

P-2 sineB

sineC

sineA cosA

cosA

cosA

cosA

cosA

sineA

sinB

sinB

sinC

sinC

sinout

Figure 6 Architecture of compressed ROM LUT design

the sine waveform and two most significant bits (MSB) fromthe phase accumulator are used to reconstruct the full sinewave From these twoMSBs one of them is used to determineif the sine amplitude is increasing or decreasing and the otherone is used to determine its sign

The phase output is directly used in the first and thirdquarter while the inverse values of the phase output areused in the second and fourth quarters This requires 2rsquoscomplement when the phase is between (120587 2120587) and isachieved by adding full adder at the output gate to accomplishthe full sine wave value To save power and achieve a smallerarea design the 12 LSB offset is added to the stored memoryaddress of sub-ROMs This offset removes the full addercomponent from the 2rsquos complement of the proposed design

The angular decomposition technique based on trigono-metric identity is one of the best techniques to reducethe quarter ROM LUT size The quarter ROM LUT waspartitioned into three (119860 119861 and 119862) such that 119860 lt (1205872)

6 The Scientific World Journal

MSB1

MSB2

PFout

Frequency control

word

Fclk

Adder Register comp1st

comp1st

RegNP-2

P-2

DDF

bit ROM

bit ROM

bit ROM

24 times 11 = 176

24 times 8 = 128

24 times 5 = 80

+

+DACLPF

sineA cosA

sineB

sineC

sinB

sinA

sinC

cosA

cosA

Figure 7 The block diagram of the final design of high-speed DDFS

Figure 8 Signal tap logic analyzer of FCW input (in hexadecimal) the sawtooth PA output and half and full amplitude waveform

119861 lt (1205872) lowast (12119860) and 119862 lt (1205872) lowast (12119860+119861) with the sameapproximations based on trigonometric identity

According to the trigonometric relation the sine wavefunction is given in

sin (119860 + 119861 + 119862)

= sin (119860 + 119861) cos119862 + cos119860 cos119861 sin119862

minus sin119860 sin119861 sin119862

(9)

where

sin (119860 + 119861) = sin119860 cos119861 + cos119860 sin119861 (10)

Equation (10) indicates the presence of four split sub-ROMstwo (2119860 and 2119861) for sin and cos119860 and119861The calculated resultsof (sin-cos119860) show that they are inversely symmetrical Basedon this cos(119860) can be obtained by complementing the sin(119860)

values and this is achieved by connecting the sin(119860) outputand the high 119881

119888119888to the XOR logic gate inputs In this way

only one addressing sub-ROM is needed for sin119860 and cos119860values The equation for cos119861 calculation is given by

cos119861 = cos((120587

2times

[0 (2119861 minus 1)]

2119861) times (

1

2119861)) (11)

The formula shows that the cos119861 values with 4-bit inputare fed into the sub-ROM 119861 (119861 = 4) therefore cos119861 =

cos(0046019) = 0999999677 cong 1 Thus the (cos119861) blockROMwas also removed from the proposed designTherefore(10) can be reduced as given by

sin (119860 + 119861) = sin119860 + cos119860 sin119861 (12)

With three values of 119860 119861 and 119862 (9) may be rewritten as

sin (119860 + 119861 + 119862) = sin119860 + cos119860 sin119861 + cos119860 sin119862 (13)

The change in the proposed ROMLUT design after hardwarereduction is shown in Figure 6

The error that results from the approximation in (9) is(2120587214) which is approximately 383 times 10minus4 The requiredROM size for 12-bit input is 214 times 12 = 196608 bits Applyingthe sine wave approximation based on trigonometric identitywith three 4-bit ROM requires only 368 bits [(24 times 11 =

176) + (24 times 8 = 128) + (24 times 4 = 64)] for ROM 119860 ROM 119861and ROM119862 respectivelyThe compressed ratio (196608368)is 5342 1 with only two adders two multiplayer adders andXOR gate as additional hardware equipment

The final design of the high-speed DDFS which consistsof parallel pipelining PA and compressed ROMLUT by usingthe wave symmetry technique is shown in Figure 7

The Scientific World Journal 7

Table 1 Comparison between Rom size with previous DDFS works

Phaseaccumulator

(bit)

Truncatedphase (bit)

Amplitudephase (bit)

ROM size(bit)

Truncationratio SFDR (dB)

Sunderland et al 1984 [11] 20 14 12 3328 591 1 72Nicholas et al 1988 [12] 31 15 14 3072 1493 1 90Curticapean and Niittylahti 2001 [18] 28 14 12 832 236 1 84De Caro and Strollo 2005 [19] 24 14 12 480 4096 1 836Yang et al 2004 [8] 32 14 12 2176 9035 1 NAChimakurthy et al 2006 [20] 15 15 15 1216 404 1 903Babak and Keshavarzi 2009 [21] 32 16 14 1664 5513 1 853De Caro et al 2008 [22] 24 14 12 672 2925 1 80This work 32 14 12 368 5342 1 68Note in this work the measured DDFS output waveform is in signal-to-noise ratio (SNR)

Figure 9 The sine wave signal of the high-speed DDFS

5 Hardware Implementation ofHigh-Speed DDFS

The proposed design of the high-speed DDFS with 0029Hzfrequency resolution was coded in Verilog HDL successfullysimulated in ALTERAQuartus II software and implementedwith a Cyclone III FPGA kit board

The proposed DDFS has been verified using a spec-trum analyzer The measured results are consistent with thesimulated results The DDFS design accumulates the FCWinput into the sawtooth PA output and the PA output feedsinto the phase-to-amplitude converter (ROM LUT) The fullamplitude waveform at the output of the ROM lookup tableis shown using the Signal Tap logic analyzer in Figure 8

6 Result and Discussion

The 32-bit DDFS has been implemented on the CycloneIII FPGA kit board The 32-bit phase accumulator outputwas truncated into 14 bits Approximately 196608 (214 times

12) bits were required to draw the full sine wave signalwith 12-bit output Quarter-wave symmetry and an angular

decomposition technique based on trigonometric identitywere appliedTheROMwas compressed to only 368 bits with5342 1 ratio The measured DDFS output waveforms andspectra for different clock frequencies illustrate the purityof the sine wave output as shown in Figure 9 for frequencytuning word = (1FFFFFFF) in hexadecimal format and 119865clk =125MHz (Cyclone III kit board clock frequency) The outputfrequency that was calculated is 119865out = (FCW2119873) times 119865clk =

(229 minus 1232) times 125 lowast 106 = 15624999MHz The measuredoutput frequency from oscilloscope is 1563MHz and this isclosely matched with the calculation result

The signal-to-noise ratio (SNR) was approximated basedon

SNR = minus 602119872 minus 176 dB (14)

(see [29]) where119872 represents the number of bits used to feedthe digital-to-analog converter For the proposedDDFS119872 =

12 and the calculated SNR is 74 dBThe measured DDFS output from the spectrum analyzer

shows SNR of approximately 68 dB as shown in Figures 10(a)and 10(b) The result is about 6 dB less than the calculatedresult and this is due to the noise from wire connections

Table 1 shows the comparison of the ROM size used inthe proposed design with some other parameters The tableshows that the proposed design has the smallest ROM size

7 Conclusion

A 32-bit high-speed DDFS system was designed with0029Hz frequency resolution The system was successfullysimulated in ALTERA Quartus II software The phase accu-mulator together with the ROM lookup table has beenimplemented on the Cyclone III FPGA kit and verified witha Signal Tap logic analyzer and the complete DDFS systemwith digital to analog convertor has been implemented on theCyclone III FPGA kit board and the performance has beenmeasured using oscilloscope and spectrum analyzer Parallelpipelining with clock gating has been applied on a modifiedBK adder for the proposed phase accumulator design Wavesymmetry and an angular decomposition technique based on

8 The Scientific World Journal

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Marker1563MHz

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

minus1308dBm

Thu 16 Jan 2014

(a)

3113MHz

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

Marker

Thu 16 Jan 2014

minus1339dBm

(b)

Figure 10 The measured signal-to-noise ratio for the DDFS waveform output (a and b)

trigonometric identity were used to reduce the ROMsizeTheROM was compressed to only 368 bits with a 5342 1 ratioThe proposed design has demonstrated attractive resultsthat improve the operation speed and reduce the ROM sizesignificantly

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Tierney C M Rader and B Gold ldquoA digital frequency syn-thesizerrdquo IEEE Transactions on Audio and Electroacoustics vol19 pp 48ndash57 1971

[2] XGeng F FDai J D Irwin andR C Jaeger ldquoAn 11-bit 86GHzdirect digital synthesizer MMIC with 10-bit segmented sine-weighted DACrdquo IEEE Journal of Solid-State Circuits vol 45 no2 pp 300ndash313 2010

[3] B S Jensen M M Khafaji T K Johansen V Krozer and J CScheytt ldquoTwelve-bit 20-GHz reduced size pipeline accumulatorin 025 120583m SiGeC technology for direct digital synthesiserapplicationsrdquo IET Circuits Devices and Systems vol 6 no 1 pp19ndash27 2012

[4] S H Ibrahim S H M Ali and M S Islam ldquoDesign a 24-bits pipeline phase accumulator for direct digital frequencysynthesizerrdquo in Proceedings of the International Symposiumon Instrumentation and Measurement Sensor Network andAutomation (IMSNA rsquo12) pp 393ndash397 August 2012

[5] J Chen D Wu L Zhou J Wu Z Jin and X Liu ldquoA 53-GHz 32-bit accumulator designed for direct digital frequencysynthesizerrdquo Chinese Science Bulletin vol 57 no 19 pp 2480ndash2487 2012

[6] B-D Yang L-S Kim and H-K Yu ldquoA high speed directdigital frequency synthesizer using a low power pipelinedparallel accumulatorrdquo in Proceedings of the IEEE International

Symposium on Circuits and Systems vol 5 pp 373ndash376 May2002

[7] M Chappell and A McEwan ldquoA low power high speedaccumulator for DDFS applicationsrdquo in Proceedings of the IEEEInternational Symposium on Cirquits and Systems vol 2 pp797ndash800 May 2004

[8] B-D Yang J-H Choi S-H Han L-S Kim and H-K Yu ldquoAn800-MHz low-power direct digital frequency synthesizer withan on-chip DA converterrdquo IEEE Journal of Solid-State Circuitsvol 39 no 5 pp 761ndash774 2004

[9] K R Rekha B S Nagabushan and K R Nataraj ldquoFPGAimplementation of low power digital frequency synthesizerrdquoInternational Journal of Engineering Science and Technology vol2 no 10 pp 5385ndash5394 2010

[10] J M P Langlois and D Al-Khalili ldquoLow power direct digitalfrequency synthesizers in 018 120583m CMOSrdquo in Proceedings ofthe IEEE Custom Integrated Circuits Conference pp 283ndash286September 2003

[11] D A Sunderland R A Strauch S S Wharfield H T Petersonand C R Cole ldquoCMOSSOS frequency synthesizer LSI circuitfor spread spectrum communicationsrdquo IEEE Journal of Solid-State Circuits vol 19 no 4 pp 497ndash506 1984

[12] H T Nicholas H Samueli and B Kim ldquoOptimization of directdigital frequency synthesizer performance in the presence offinite word length effectsrdquo in Proceedings of the 42nd AnnualFrequency Control Symposium pp 357ndash363 June 1988

[13] M N Khan M S Imran M Rehan and U Hai ldquoHighspeed direct digital frequency synthesizer(DDFS) architecturewith reduced ROM structurerdquo in Proceedings of the StudentConference on Engineering Sciences and Technology (SCONESTrsquo05) pp 1ndash5 August 2005

[14] E N Mariangela Genovese D De Caro N Petra and AG M Strollo ldquoAnalysis and comparison of direct digitalfrequency synthesizers implementedon FPGArdquo Integration theVLSI Journal vol 47 pp 261ndash271 2014

[15] A Ashrafi and R Adhami ldquoTheoretical upperbound of thespurious-free dynamic range in direct digital frequency syn-thesizers realized by polynomial interpolation methodsrdquo IEEE

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

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RotatingMachinery

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Submit your manuscripts athttpwwwhindawicom

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Shock and Vibration

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Acoustics and VibrationAdvances in

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Electrical and Computer Engineering

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Advances inOptoElectronics

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Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

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Chemical EngineeringInternational Journal of Antennas and

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Navigation and Observation

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DistributedSensor Networks

International Journal of

2 The Scientific World Journal

8

8

8

8

+

+

+

+

8-bit reg

8-bit reg

8-bit reg

8-bit reg 8-bit reg

8-bit reg 8-bit reg

8-bit reg 8-bit reg 8-bit reg 8-bit reg

8-bit reg 8-bit reg 8-bit reg8-bit reg

Figure 1 The conventional 32-bit pipelining phase accumulator

used in [14] where the ROM is partitioned into two ROMsnamely coarse and fine ROMs to obtain the quadratureoutputs sine and cosine values The author suggested severalDDFS systems implemented with different types of FPGA kitboards and compared them with an ASIC based approach

The polynomial approximation method was used inDDFS design to optimize the spurious-free dynamic range(SFDR) This method was used by Ashrafi and Adhamiin [15] to determine the upper bound of the SFDR usingpiecewise polynomial interpolation Fourier series was usedto establish a linear relationship between the coefficients ofthe interpolating polynomials and the frequency spectrumThis method can be used in any kind of DDFS to maximizethe SFDR

De Caro et al proposed a dual-slope technique in [16]to optimize the piecewise linear approximation for the phaseto sine mapping This technique improves the spectral purityand ROM size The stored values of the two quarters (1205874)sine and cosine sub-ROMs with 3MSB bits and mapper arerequired to accomplish the quarter phase to sinemapping andproduce quadrature output from the DDFS In [17] De Caroet al proposed another DDFS architecture which is based onpiecewise linear approximation technique with nonuniformsegment length to the input of three groups of multiplexerThis technique can maximize the SFDR and reduce the sizeof the coefficients ROM

This paper presents a high-speed DDFS system withpipelined PA based on modified parallel BK adder andgated clock technique The ROM was resized by applyingthe quarter-wave symmetry technique in one quarter of thesine wave and an angular decomposition technique basedon trigonometric identity has been applied to compress thequarter ROM LUT Based on these techniques the quarterROM LUT was partitioned into three sub-ROMs (119860 119861 and

119862) The proposed architecture improves the speed of theDDFS and reduces the size of the ROMs

2 The Gated Clock and Parallel PipeliningTechnique for Phase Accumulator

Themodified parallel BK adder based on the progression-of-states technique combined with gated clock technique wasused in the proposed design of the PA The frequency reso-lution (119865Res) of DDFS is determined by the clock frequency(119865clk) and the number of119873 input bit of the PA as depicted by

119865Res =119865clk2119873

(2)

For high frequency resolution it is preferable to design aPA with large FCW bits input However a large ROM size isrequired to implement all the 2119873 bits of phase accumulatoroutput Due to this reason a part of the MSB phase outputis used to address the phase to amplitude converter or ROMlookup table while maintaining high frequency resolutionThe pipeline technique was used to increase the throughputof the accumulator and this throughput will double with thenumber of pipeline stages as shown in Figure 1

The number of registers increases with the number ofpipeline stages which leads to high power consumptionTherefore in this design a gated clock technique was used toreduce the number of preskewing registers while preservinghigh-speed operation In this technique D flip-flops (DFFs)were used to connect each row of the pipeline stages withFCW input These registers are clocked by the pipelinedpulses with one clock cycle based on the shifted clockpulses as shown in Figure 2(a) Considering that the phaseaccumulator input bits are 119873 the PA was partitioned into 119871

The Scientific World Journal 3

FclkK

DFF DFF DFF DFFSet

Clk

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8 9

1 Td 2 Td 3 Td

A

A

B

B

C

C

Vcc

(a)

+

+

+

+

8-DFF

OUT X(T + 3)OUT X(T + 4)

OUT X(T + 2)

OUT X(T + 1)

IN [7 2]LOW [1 0]

IN [7 0]LOW [1 0]

IN [7 1]LOW [0]

[7 0][7 0]

[7 0]

[7 0]

(b)

Parallel adder

Pipelined PA outputMultiplexer

X1

X2

X3

X4

1 2 3 4 Clk4 Clk

(c)

Figure 2 (a) The gated clock technique (b) parallel adder based on progression-of-states technique and (c) pipelined PA output

stages with B DFFs in each stageThe number of the DFFs119870for preskewing registers is given by

119870 =(119873 lowast (119871 + 1))

2 (3)

By applying the gated clock technique on the proposeddesign the number of DFFs is given by

119870 = 119873 + 119871 (4)

As a result with the gated clock technique the numbersof preskewing registers have been reduced from 80 to 36corresponding to 537 reduction

Figure 2(b) shows the operation of the parallel adderFour adders calculate the holding constant of 8-bit inputwordwithin four clock cycles Holding the FCW for four clockcycles limits the update rate of the frequency input wordbut does not cause any glitch because the four adders willsteadily increase the accumulator output four times Assumethat FCW is 119873 and the parallel adder output is 119883 at the 119879thclock time The parallel adderrsquos outputs are given as follows

119883 (119879 + 1) = 119873 + 119883 (119879)

119883 (119879 + 2)

= 119883 (119879 + 1) + 119883 (119879) = 119873 + 119883 (119879) + 119883 (119879) = 119873 + 2119883 (119879)

119883 (119879 + 3) = 119883 (119879 + 2) + 119883 (119879) = 119873 + 3 119883 (119879)

119883 (119879 + 4) = 119883 (119879 + 3) + 119883 (119879) = 119873 + 4119883 (119879)

(5)

The result of the fourth adder is set as a feedback to the secondinput for all the four adders To generate the second output[119883(119879+2)] and fourth output [119883(119879+4)] the119873 bit is shifted upby removing one and two bits of the FCW input and replacingthem with the one and two bits from the lower pipeliningstage respectively before they are addedThe119883(119879+2) outputand119883(119879) output are used to generate119883(119879 + 3)

This operationmade the frequency tuningword held con-stant for four clock cycles without causing any imperfectionsin the PA output The partitioned clock cycles (1198621198971198964) makethe multiplexers choose one of the results at the output of thePA to overcome the holding time on the parallel adders asillustrated in Figure 2(c)

3 Phase Accumulator Architecture

The proposed phase accumulator architecture based on themodified parallel BK adder and the gated clock techniquewith pipelining stages is shown in Figure 3 The output of thePA is a truncated 14-bit value that is achieved from the 8 and6 bits of the top and second pipelining stages respectively

The 32-bit FCW input is sufficient to obtain 0029Hzfrequency resolution from the 125MHz clock frequency ofCyclone III FPGA kit board (119865Res = 125 times 106232 =

0029Hz)

31Modifying Brent-KungAdder TheBKadder is fast and allcarries are computed simultaneously through a binary tree ofldquoBKrdquo cells as shown in Figure 4(a)

4 The Scientific World Journal

+

+

+

+

+

+

+

+

+

+

+

+

8-DFF

4-DFF

4-DFF

8-DFF 6-DFF

6-DFF

6-DFF

6-DFF

8-DFF

8-DFF

8-DFF

8-DFF

8 OUT X4

8 OUT X3

8 OUT X2

8 OUT X1

6 OUT X4

6 OUT X3

6 OUT X2

6 OUT X1

32

8 8

248

8

8

8

8

8

Clk4 Clk4

DFF

DFF

DFF

DFFDFF

MUX

MU

X

MUX

K

Set

Clk

Clk Clk

Clk

14

8

6

IN [7 2]

IN [7 0]

IN [7 0]

LOW [1 0]IN [7 2]

LOW [1 0]

LOW [1 0]IN [7 0]

LOW [1 0]IN [7 1]LOW [0]

IN [7 1]LOW [0]

IN [31 24]

IN [23 16]

IN [15 8]

[1 0

][9

8]

[17

16] 4 times 1

4 times 1

OUT [31 18]

8-bit reg 8-bit reg

8-bit reg

8-bit reg

8-bit reg

8-bit reg 6-bit reg8-bit reg

8-bit reg

8-bit reg

24-bit reg

24-bit reg

32-bit reg

18-bit reg

Figure 3 Pipelined phase accumulator with parallel adder based on modifying Bren-Kung adder and gated clocking technique

BK cells compute the carry for two or more of full adder(FA) cells and they are calculated as a sum of 119866 and 119875 cells[23 24] The arithmetic operation is given by

BK = 119866 + 119875

119866 = 11989210158401015840+ 11990110158401015840sdot 1198921015840

119875 = 11990110158401015840sdot 1199011015840

(6)

where 119892101584010158401198921015840 119901101584010158401199011015840 are higher and lower generate and prop-agate functions respectively The 119901 is a propagate function(119901119894= 119909119894oplus 119910119894) and 119892 is a generate function (119892

119894= 119909119894sdot 119910119894)

The general prefix addition algorithm is explained byZimmermann in [25] By adding the carry input 119862in in theprefix structure with somemodifications the prefix structurecan be used in pipelining-based adder design This approachis used in BK adder fast carry computation However inthis paper a modification is proposed to the BK adder sothat it can be used in pipelining architecture The proposedmodification is by removing the operation of the 119892

0 and

the carry out of the first bit 1198621can be achieved by a 2-1

multiplexer The input to this multiplexer is 1199090and 119862in while

1199010is the select input and the output is 119862

1 The operation of

the multiplexer is given by

1198621= (1199010 119888in) + (119909

0 1199010) (7)

where 1198621is the carry out 119901

0is the propagate function 119862in

is the carry input and 1199090is the first bit input The proposed

modification of the 8-bit BK adder is shown in Figure 4(b)The sum and carry out of the modified 8-bit BK adder areshown in

1198780= 1199010oplus 119888in

119878119873sdotsdotsdot1

= 119901((119873minus1)sdotsdotsdot1)

oplus 119862((119873minus1)sdotsdotsdot1)

119862out = 119892119873+ 119901119873sdot 119862119873

(8)

311 Comparison of Different Adder Architecture An adderis a key element of the pipelining PA design and a fastadder improves PA performance Parallel-prefix adder treestructures such as Sklansky [26] Kogge-Stone adder [27] BK[23] and Beaumont-Smith [28] have been used in pipeliningaccumulator design for high-speed operation

A comparison has been made between conventionaladder and several parallel-prefix adders for 12-bit 18-bit 24-bit and 32-bit operations The PA designs were coded inVerilog HDL and verified in Cyclone III FPGA kit boardPrior to that all the designs were simulated by usingALTERAQuartus IIThe comparison result is shown in Figure 5 Fromthe figure it can be seen that BK adder performs relativelyfaster especially for high number of bits

4 ROM Lookup Table Design

ROM LUT or phase-to-amplitude converter (PAC) is amemory storage address for DDFS which is used to convert

The Scientific World Journal 5

P0P1P2P3P4P5P6P7

x0x1x7 y0y1y7

P middot gP middot gP middot gP middot gP middot gP middot gP middot g p g

S0S1S2S3S4S5S6S7

SSSSSSSS

BK

BK

BK

BK BK

BK

BK

BKBK

BK

BK

Criticalpath

g0g1g2g3g4g5g6g7 p0p1p2p3p4p5p6P7

middot middot middot

middot middot middot middot middot middot middot

(a)

P2P3P4P5P6P7

x0x1 y0y1x7 y7

P middot g P middot g P middot g P middot g P middot g P middot g P middot g

S0S1S2S3S4S5S6S7

S S S S S S S S

BK

BK

BK

BK

BK BK BK

BK

BK

BK BK

Criticalpath

p

Cin

Cin

C1

C1

g1g2g3g4g5g6g7 p1p2p3p4p5p6P7 middotp

middot middot middot

middot middot middot middot middot middot middot

MU

X

(b)

Figure 4 Block circuit diagram of conventional Brent-Kung adder (a) and (b) modifying Brent-Kung adder

450

400

350

300

250

200

150

100

Max

imum

ope

ratio

n fre

quen

cy (M

Hz)

10 15 20 25 30 35

Number of bits

CLARCABrent-Kung

Kogge-StoneSklanskyBeaumont Smith

Figure 5 Comparison result of maximum operating frequency(119865Max) for phase accumulator design with CLA Brent-Kung Kogge-Stone Sklansky Beaumont-Smith and RCA adders

the phase signal into an amplitude sine wave signal High-accuracy output signal for DDFS requires a large number ofLUT The ROM size exponentially increases with increasingnumber of bit inputs The designerrsquos challenge is a tradeoffbetween reducing the ROM size while maintaining highperformance (high resolution high speed) Quarter-wavesymmetry technique is used to resize the ROM in theproposed DDFS design to store only one quarter (0 1205872) of

+

+

24 times 11Bit ROM

Bit ROM

Bit ROM

28 times 4

24 times 4

times

times

11

11

11

11

11

4

4

4

B

C

C

P-2 sineB

sineC

sineA cosA

cosA

cosA

cosA

cosA

sineA

sinB

sinB

sinC

sinC

sinout

Figure 6 Architecture of compressed ROM LUT design

the sine waveform and two most significant bits (MSB) fromthe phase accumulator are used to reconstruct the full sinewave From these twoMSBs one of them is used to determineif the sine amplitude is increasing or decreasing and the otherone is used to determine its sign

The phase output is directly used in the first and thirdquarter while the inverse values of the phase output areused in the second and fourth quarters This requires 2rsquoscomplement when the phase is between (120587 2120587) and isachieved by adding full adder at the output gate to accomplishthe full sine wave value To save power and achieve a smallerarea design the 12 LSB offset is added to the stored memoryaddress of sub-ROMs This offset removes the full addercomponent from the 2rsquos complement of the proposed design

The angular decomposition technique based on trigono-metric identity is one of the best techniques to reducethe quarter ROM LUT size The quarter ROM LUT waspartitioned into three (119860 119861 and 119862) such that 119860 lt (1205872)

6 The Scientific World Journal

MSB1

MSB2

PFout

Frequency control

word

Fclk

Adder Register comp1st

comp1st

RegNP-2

P-2

DDF

bit ROM

bit ROM

bit ROM

24 times 11 = 176

24 times 8 = 128

24 times 5 = 80

+

+DACLPF

sineA cosA

sineB

sineC

sinB

sinA

sinC

cosA

cosA

Figure 7 The block diagram of the final design of high-speed DDFS

Figure 8 Signal tap logic analyzer of FCW input (in hexadecimal) the sawtooth PA output and half and full amplitude waveform

119861 lt (1205872) lowast (12119860) and 119862 lt (1205872) lowast (12119860+119861) with the sameapproximations based on trigonometric identity

According to the trigonometric relation the sine wavefunction is given in

sin (119860 + 119861 + 119862)

= sin (119860 + 119861) cos119862 + cos119860 cos119861 sin119862

minus sin119860 sin119861 sin119862

(9)

where

sin (119860 + 119861) = sin119860 cos119861 + cos119860 sin119861 (10)

Equation (10) indicates the presence of four split sub-ROMstwo (2119860 and 2119861) for sin and cos119860 and119861The calculated resultsof (sin-cos119860) show that they are inversely symmetrical Basedon this cos(119860) can be obtained by complementing the sin(119860)

values and this is achieved by connecting the sin(119860) outputand the high 119881

119888119888to the XOR logic gate inputs In this way

only one addressing sub-ROM is needed for sin119860 and cos119860values The equation for cos119861 calculation is given by

cos119861 = cos((120587

2times

[0 (2119861 minus 1)]

2119861) times (

1

2119861)) (11)

The formula shows that the cos119861 values with 4-bit inputare fed into the sub-ROM 119861 (119861 = 4) therefore cos119861 =

cos(0046019) = 0999999677 cong 1 Thus the (cos119861) blockROMwas also removed from the proposed designTherefore(10) can be reduced as given by

sin (119860 + 119861) = sin119860 + cos119860 sin119861 (12)

With three values of 119860 119861 and 119862 (9) may be rewritten as

sin (119860 + 119861 + 119862) = sin119860 + cos119860 sin119861 + cos119860 sin119862 (13)

The change in the proposed ROMLUT design after hardwarereduction is shown in Figure 6

The error that results from the approximation in (9) is(2120587214) which is approximately 383 times 10minus4 The requiredROM size for 12-bit input is 214 times 12 = 196608 bits Applyingthe sine wave approximation based on trigonometric identitywith three 4-bit ROM requires only 368 bits [(24 times 11 =

176) + (24 times 8 = 128) + (24 times 4 = 64)] for ROM 119860 ROM 119861and ROM119862 respectivelyThe compressed ratio (196608368)is 5342 1 with only two adders two multiplayer adders andXOR gate as additional hardware equipment

The final design of the high-speed DDFS which consistsof parallel pipelining PA and compressed ROMLUT by usingthe wave symmetry technique is shown in Figure 7

The Scientific World Journal 7

Table 1 Comparison between Rom size with previous DDFS works

Phaseaccumulator

(bit)

Truncatedphase (bit)

Amplitudephase (bit)

ROM size(bit)

Truncationratio SFDR (dB)

Sunderland et al 1984 [11] 20 14 12 3328 591 1 72Nicholas et al 1988 [12] 31 15 14 3072 1493 1 90Curticapean and Niittylahti 2001 [18] 28 14 12 832 236 1 84De Caro and Strollo 2005 [19] 24 14 12 480 4096 1 836Yang et al 2004 [8] 32 14 12 2176 9035 1 NAChimakurthy et al 2006 [20] 15 15 15 1216 404 1 903Babak and Keshavarzi 2009 [21] 32 16 14 1664 5513 1 853De Caro et al 2008 [22] 24 14 12 672 2925 1 80This work 32 14 12 368 5342 1 68Note in this work the measured DDFS output waveform is in signal-to-noise ratio (SNR)

Figure 9 The sine wave signal of the high-speed DDFS

5 Hardware Implementation ofHigh-Speed DDFS

The proposed design of the high-speed DDFS with 0029Hzfrequency resolution was coded in Verilog HDL successfullysimulated in ALTERAQuartus II software and implementedwith a Cyclone III FPGA kit board

The proposed DDFS has been verified using a spec-trum analyzer The measured results are consistent with thesimulated results The DDFS design accumulates the FCWinput into the sawtooth PA output and the PA output feedsinto the phase-to-amplitude converter (ROM LUT) The fullamplitude waveform at the output of the ROM lookup tableis shown using the Signal Tap logic analyzer in Figure 8

6 Result and Discussion

The 32-bit DDFS has been implemented on the CycloneIII FPGA kit board The 32-bit phase accumulator outputwas truncated into 14 bits Approximately 196608 (214 times

12) bits were required to draw the full sine wave signalwith 12-bit output Quarter-wave symmetry and an angular

decomposition technique based on trigonometric identitywere appliedTheROMwas compressed to only 368 bits with5342 1 ratio The measured DDFS output waveforms andspectra for different clock frequencies illustrate the purityof the sine wave output as shown in Figure 9 for frequencytuning word = (1FFFFFFF) in hexadecimal format and 119865clk =125MHz (Cyclone III kit board clock frequency) The outputfrequency that was calculated is 119865out = (FCW2119873) times 119865clk =

(229 minus 1232) times 125 lowast 106 = 15624999MHz The measuredoutput frequency from oscilloscope is 1563MHz and this isclosely matched with the calculation result

The signal-to-noise ratio (SNR) was approximated basedon

SNR = minus 602119872 minus 176 dB (14)

(see [29]) where119872 represents the number of bits used to feedthe digital-to-analog converter For the proposedDDFS119872 =

12 and the calculated SNR is 74 dBThe measured DDFS output from the spectrum analyzer

shows SNR of approximately 68 dB as shown in Figures 10(a)and 10(b) The result is about 6 dB less than the calculatedresult and this is due to the noise from wire connections

Table 1 shows the comparison of the ROM size used inthe proposed design with some other parameters The tableshows that the proposed design has the smallest ROM size

7 Conclusion

A 32-bit high-speed DDFS system was designed with0029Hz frequency resolution The system was successfullysimulated in ALTERA Quartus II software The phase accu-mulator together with the ROM lookup table has beenimplemented on the Cyclone III FPGA kit and verified witha Signal Tap logic analyzer and the complete DDFS systemwith digital to analog convertor has been implemented on theCyclone III FPGA kit board and the performance has beenmeasured using oscilloscope and spectrum analyzer Parallelpipelining with clock gating has been applied on a modifiedBK adder for the proposed phase accumulator design Wavesymmetry and an angular decomposition technique based on

8 The Scientific World Journal

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Marker1563MHz

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

minus1308dBm

Thu 16 Jan 2014

(a)

3113MHz

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

Marker

Thu 16 Jan 2014

minus1339dBm

(b)

Figure 10 The measured signal-to-noise ratio for the DDFS waveform output (a and b)

trigonometric identity were used to reduce the ROMsizeTheROM was compressed to only 368 bits with a 5342 1 ratioThe proposed design has demonstrated attractive resultsthat improve the operation speed and reduce the ROM sizesignificantly

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Tierney C M Rader and B Gold ldquoA digital frequency syn-thesizerrdquo IEEE Transactions on Audio and Electroacoustics vol19 pp 48ndash57 1971

[2] XGeng F FDai J D Irwin andR C Jaeger ldquoAn 11-bit 86GHzdirect digital synthesizer MMIC with 10-bit segmented sine-weighted DACrdquo IEEE Journal of Solid-State Circuits vol 45 no2 pp 300ndash313 2010

[3] B S Jensen M M Khafaji T K Johansen V Krozer and J CScheytt ldquoTwelve-bit 20-GHz reduced size pipeline accumulatorin 025 120583m SiGeC technology for direct digital synthesiserapplicationsrdquo IET Circuits Devices and Systems vol 6 no 1 pp19ndash27 2012

[4] S H Ibrahim S H M Ali and M S Islam ldquoDesign a 24-bits pipeline phase accumulator for direct digital frequencysynthesizerrdquo in Proceedings of the International Symposiumon Instrumentation and Measurement Sensor Network andAutomation (IMSNA rsquo12) pp 393ndash397 August 2012

[5] J Chen D Wu L Zhou J Wu Z Jin and X Liu ldquoA 53-GHz 32-bit accumulator designed for direct digital frequencysynthesizerrdquo Chinese Science Bulletin vol 57 no 19 pp 2480ndash2487 2012

[6] B-D Yang L-S Kim and H-K Yu ldquoA high speed directdigital frequency synthesizer using a low power pipelinedparallel accumulatorrdquo in Proceedings of the IEEE International

Symposium on Circuits and Systems vol 5 pp 373ndash376 May2002

[7] M Chappell and A McEwan ldquoA low power high speedaccumulator for DDFS applicationsrdquo in Proceedings of the IEEEInternational Symposium on Cirquits and Systems vol 2 pp797ndash800 May 2004

[8] B-D Yang J-H Choi S-H Han L-S Kim and H-K Yu ldquoAn800-MHz low-power direct digital frequency synthesizer withan on-chip DA converterrdquo IEEE Journal of Solid-State Circuitsvol 39 no 5 pp 761ndash774 2004

[9] K R Rekha B S Nagabushan and K R Nataraj ldquoFPGAimplementation of low power digital frequency synthesizerrdquoInternational Journal of Engineering Science and Technology vol2 no 10 pp 5385ndash5394 2010

[10] J M P Langlois and D Al-Khalili ldquoLow power direct digitalfrequency synthesizers in 018 120583m CMOSrdquo in Proceedings ofthe IEEE Custom Integrated Circuits Conference pp 283ndash286September 2003

[11] D A Sunderland R A Strauch S S Wharfield H T Petersonand C R Cole ldquoCMOSSOS frequency synthesizer LSI circuitfor spread spectrum communicationsrdquo IEEE Journal of Solid-State Circuits vol 19 no 4 pp 497ndash506 1984

[12] H T Nicholas H Samueli and B Kim ldquoOptimization of directdigital frequency synthesizer performance in the presence offinite word length effectsrdquo in Proceedings of the 42nd AnnualFrequency Control Symposium pp 357ndash363 June 1988

[13] M N Khan M S Imran M Rehan and U Hai ldquoHighspeed direct digital frequency synthesizer(DDFS) architecturewith reduced ROM structurerdquo in Proceedings of the StudentConference on Engineering Sciences and Technology (SCONESTrsquo05) pp 1ndash5 August 2005

[14] E N Mariangela Genovese D De Caro N Petra and AG M Strollo ldquoAnalysis and comparison of direct digitalfrequency synthesizers implementedon FPGArdquo Integration theVLSI Journal vol 47 pp 261ndash271 2014

[15] A Ashrafi and R Adhami ldquoTheoretical upperbound of thespurious-free dynamic range in direct digital frequency syn-thesizers realized by polynomial interpolation methodsrdquo IEEE

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

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Submit your manuscripts athttpwwwhindawicom

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DistributedSensor Networks

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The Scientific World Journal 3

FclkK

DFF DFF DFF DFFSet

Clk

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8 9

1 Td 2 Td 3 Td

A

A

B

B

C

C

Vcc

(a)

+

+

+

+

8-DFF

OUT X(T + 3)OUT X(T + 4)

OUT X(T + 2)

OUT X(T + 1)

IN [7 2]LOW [1 0]

IN [7 0]LOW [1 0]

IN [7 1]LOW [0]

[7 0][7 0]

[7 0]

[7 0]

(b)

Parallel adder

Pipelined PA outputMultiplexer

X1

X2

X3

X4

1 2 3 4 Clk4 Clk

(c)

Figure 2 (a) The gated clock technique (b) parallel adder based on progression-of-states technique and (c) pipelined PA output

stages with B DFFs in each stageThe number of the DFFs119870for preskewing registers is given by

119870 =(119873 lowast (119871 + 1))

2 (3)

By applying the gated clock technique on the proposeddesign the number of DFFs is given by

119870 = 119873 + 119871 (4)

As a result with the gated clock technique the numbersof preskewing registers have been reduced from 80 to 36corresponding to 537 reduction

Figure 2(b) shows the operation of the parallel adderFour adders calculate the holding constant of 8-bit inputwordwithin four clock cycles Holding the FCW for four clockcycles limits the update rate of the frequency input wordbut does not cause any glitch because the four adders willsteadily increase the accumulator output four times Assumethat FCW is 119873 and the parallel adder output is 119883 at the 119879thclock time The parallel adderrsquos outputs are given as follows

119883 (119879 + 1) = 119873 + 119883 (119879)

119883 (119879 + 2)

= 119883 (119879 + 1) + 119883 (119879) = 119873 + 119883 (119879) + 119883 (119879) = 119873 + 2119883 (119879)

119883 (119879 + 3) = 119883 (119879 + 2) + 119883 (119879) = 119873 + 3 119883 (119879)

119883 (119879 + 4) = 119883 (119879 + 3) + 119883 (119879) = 119873 + 4119883 (119879)

(5)

The result of the fourth adder is set as a feedback to the secondinput for all the four adders To generate the second output[119883(119879+2)] and fourth output [119883(119879+4)] the119873 bit is shifted upby removing one and two bits of the FCW input and replacingthem with the one and two bits from the lower pipeliningstage respectively before they are addedThe119883(119879+2) outputand119883(119879) output are used to generate119883(119879 + 3)

This operationmade the frequency tuningword held con-stant for four clock cycles without causing any imperfectionsin the PA output The partitioned clock cycles (1198621198971198964) makethe multiplexers choose one of the results at the output of thePA to overcome the holding time on the parallel adders asillustrated in Figure 2(c)

3 Phase Accumulator Architecture

The proposed phase accumulator architecture based on themodified parallel BK adder and the gated clock techniquewith pipelining stages is shown in Figure 3 The output of thePA is a truncated 14-bit value that is achieved from the 8 and6 bits of the top and second pipelining stages respectively

The 32-bit FCW input is sufficient to obtain 0029Hzfrequency resolution from the 125MHz clock frequency ofCyclone III FPGA kit board (119865Res = 125 times 106232 =

0029Hz)

31Modifying Brent-KungAdder TheBKadder is fast and allcarries are computed simultaneously through a binary tree ofldquoBKrdquo cells as shown in Figure 4(a)

4 The Scientific World Journal

+

+

+

+

+

+

+

+

+

+

+

+

8-DFF

4-DFF

4-DFF

8-DFF 6-DFF

6-DFF

6-DFF

6-DFF

8-DFF

8-DFF

8-DFF

8-DFF

8 OUT X4

8 OUT X3

8 OUT X2

8 OUT X1

6 OUT X4

6 OUT X3

6 OUT X2

6 OUT X1

32

8 8

248

8

8

8

8

8

Clk4 Clk4

DFF

DFF

DFF

DFFDFF

MUX

MU

X

MUX

K

Set

Clk

Clk Clk

Clk

14

8

6

IN [7 2]

IN [7 0]

IN [7 0]

LOW [1 0]IN [7 2]

LOW [1 0]

LOW [1 0]IN [7 0]

LOW [1 0]IN [7 1]LOW [0]

IN [7 1]LOW [0]

IN [31 24]

IN [23 16]

IN [15 8]

[1 0

][9

8]

[17

16] 4 times 1

4 times 1

OUT [31 18]

8-bit reg 8-bit reg

8-bit reg

8-bit reg

8-bit reg

8-bit reg 6-bit reg8-bit reg

8-bit reg

8-bit reg

24-bit reg

24-bit reg

32-bit reg

18-bit reg

Figure 3 Pipelined phase accumulator with parallel adder based on modifying Bren-Kung adder and gated clocking technique

BK cells compute the carry for two or more of full adder(FA) cells and they are calculated as a sum of 119866 and 119875 cells[23 24] The arithmetic operation is given by

BK = 119866 + 119875

119866 = 11989210158401015840+ 11990110158401015840sdot 1198921015840

119875 = 11990110158401015840sdot 1199011015840

(6)

where 119892101584010158401198921015840 119901101584010158401199011015840 are higher and lower generate and prop-agate functions respectively The 119901 is a propagate function(119901119894= 119909119894oplus 119910119894) and 119892 is a generate function (119892

119894= 119909119894sdot 119910119894)

The general prefix addition algorithm is explained byZimmermann in [25] By adding the carry input 119862in in theprefix structure with somemodifications the prefix structurecan be used in pipelining-based adder design This approachis used in BK adder fast carry computation However inthis paper a modification is proposed to the BK adder sothat it can be used in pipelining architecture The proposedmodification is by removing the operation of the 119892

0 and

the carry out of the first bit 1198621can be achieved by a 2-1

multiplexer The input to this multiplexer is 1199090and 119862in while

1199010is the select input and the output is 119862

1 The operation of

the multiplexer is given by

1198621= (1199010 119888in) + (119909

0 1199010) (7)

where 1198621is the carry out 119901

0is the propagate function 119862in

is the carry input and 1199090is the first bit input The proposed

modification of the 8-bit BK adder is shown in Figure 4(b)The sum and carry out of the modified 8-bit BK adder areshown in

1198780= 1199010oplus 119888in

119878119873sdotsdotsdot1

= 119901((119873minus1)sdotsdotsdot1)

oplus 119862((119873minus1)sdotsdotsdot1)

119862out = 119892119873+ 119901119873sdot 119862119873

(8)

311 Comparison of Different Adder Architecture An adderis a key element of the pipelining PA design and a fastadder improves PA performance Parallel-prefix adder treestructures such as Sklansky [26] Kogge-Stone adder [27] BK[23] and Beaumont-Smith [28] have been used in pipeliningaccumulator design for high-speed operation

A comparison has been made between conventionaladder and several parallel-prefix adders for 12-bit 18-bit 24-bit and 32-bit operations The PA designs were coded inVerilog HDL and verified in Cyclone III FPGA kit boardPrior to that all the designs were simulated by usingALTERAQuartus IIThe comparison result is shown in Figure 5 Fromthe figure it can be seen that BK adder performs relativelyfaster especially for high number of bits

4 ROM Lookup Table Design

ROM LUT or phase-to-amplitude converter (PAC) is amemory storage address for DDFS which is used to convert

The Scientific World Journal 5

P0P1P2P3P4P5P6P7

x0x1x7 y0y1y7

P middot gP middot gP middot gP middot gP middot gP middot gP middot g p g

S0S1S2S3S4S5S6S7

SSSSSSSS

BK

BK

BK

BK BK

BK

BK

BKBK

BK

BK

Criticalpath

g0g1g2g3g4g5g6g7 p0p1p2p3p4p5p6P7

middot middot middot

middot middot middot middot middot middot middot

(a)

P2P3P4P5P6P7

x0x1 y0y1x7 y7

P middot g P middot g P middot g P middot g P middot g P middot g P middot g

S0S1S2S3S4S5S6S7

S S S S S S S S

BK

BK

BK

BK

BK BK BK

BK

BK

BK BK

Criticalpath

p

Cin

Cin

C1

C1

g1g2g3g4g5g6g7 p1p2p3p4p5p6P7 middotp

middot middot middot

middot middot middot middot middot middot middot

MU

X

(b)

Figure 4 Block circuit diagram of conventional Brent-Kung adder (a) and (b) modifying Brent-Kung adder

450

400

350

300

250

200

150

100

Max

imum

ope

ratio

n fre

quen

cy (M

Hz)

10 15 20 25 30 35

Number of bits

CLARCABrent-Kung

Kogge-StoneSklanskyBeaumont Smith

Figure 5 Comparison result of maximum operating frequency(119865Max) for phase accumulator design with CLA Brent-Kung Kogge-Stone Sklansky Beaumont-Smith and RCA adders

the phase signal into an amplitude sine wave signal High-accuracy output signal for DDFS requires a large number ofLUT The ROM size exponentially increases with increasingnumber of bit inputs The designerrsquos challenge is a tradeoffbetween reducing the ROM size while maintaining highperformance (high resolution high speed) Quarter-wavesymmetry technique is used to resize the ROM in theproposed DDFS design to store only one quarter (0 1205872) of

+

+

24 times 11Bit ROM

Bit ROM

Bit ROM

28 times 4

24 times 4

times

times

11

11

11

11

11

4

4

4

B

C

C

P-2 sineB

sineC

sineA cosA

cosA

cosA

cosA

cosA

sineA

sinB

sinB

sinC

sinC

sinout

Figure 6 Architecture of compressed ROM LUT design

the sine waveform and two most significant bits (MSB) fromthe phase accumulator are used to reconstruct the full sinewave From these twoMSBs one of them is used to determineif the sine amplitude is increasing or decreasing and the otherone is used to determine its sign

The phase output is directly used in the first and thirdquarter while the inverse values of the phase output areused in the second and fourth quarters This requires 2rsquoscomplement when the phase is between (120587 2120587) and isachieved by adding full adder at the output gate to accomplishthe full sine wave value To save power and achieve a smallerarea design the 12 LSB offset is added to the stored memoryaddress of sub-ROMs This offset removes the full addercomponent from the 2rsquos complement of the proposed design

The angular decomposition technique based on trigono-metric identity is one of the best techniques to reducethe quarter ROM LUT size The quarter ROM LUT waspartitioned into three (119860 119861 and 119862) such that 119860 lt (1205872)

6 The Scientific World Journal

MSB1

MSB2

PFout

Frequency control

word

Fclk

Adder Register comp1st

comp1st

RegNP-2

P-2

DDF

bit ROM

bit ROM

bit ROM

24 times 11 = 176

24 times 8 = 128

24 times 5 = 80

+

+DACLPF

sineA cosA

sineB

sineC

sinB

sinA

sinC

cosA

cosA

Figure 7 The block diagram of the final design of high-speed DDFS

Figure 8 Signal tap logic analyzer of FCW input (in hexadecimal) the sawtooth PA output and half and full amplitude waveform

119861 lt (1205872) lowast (12119860) and 119862 lt (1205872) lowast (12119860+119861) with the sameapproximations based on trigonometric identity

According to the trigonometric relation the sine wavefunction is given in

sin (119860 + 119861 + 119862)

= sin (119860 + 119861) cos119862 + cos119860 cos119861 sin119862

minus sin119860 sin119861 sin119862

(9)

where

sin (119860 + 119861) = sin119860 cos119861 + cos119860 sin119861 (10)

Equation (10) indicates the presence of four split sub-ROMstwo (2119860 and 2119861) for sin and cos119860 and119861The calculated resultsof (sin-cos119860) show that they are inversely symmetrical Basedon this cos(119860) can be obtained by complementing the sin(119860)

values and this is achieved by connecting the sin(119860) outputand the high 119881

119888119888to the XOR logic gate inputs In this way

only one addressing sub-ROM is needed for sin119860 and cos119860values The equation for cos119861 calculation is given by

cos119861 = cos((120587

2times

[0 (2119861 minus 1)]

2119861) times (

1

2119861)) (11)

The formula shows that the cos119861 values with 4-bit inputare fed into the sub-ROM 119861 (119861 = 4) therefore cos119861 =

cos(0046019) = 0999999677 cong 1 Thus the (cos119861) blockROMwas also removed from the proposed designTherefore(10) can be reduced as given by

sin (119860 + 119861) = sin119860 + cos119860 sin119861 (12)

With three values of 119860 119861 and 119862 (9) may be rewritten as

sin (119860 + 119861 + 119862) = sin119860 + cos119860 sin119861 + cos119860 sin119862 (13)

The change in the proposed ROMLUT design after hardwarereduction is shown in Figure 6

The error that results from the approximation in (9) is(2120587214) which is approximately 383 times 10minus4 The requiredROM size for 12-bit input is 214 times 12 = 196608 bits Applyingthe sine wave approximation based on trigonometric identitywith three 4-bit ROM requires only 368 bits [(24 times 11 =

176) + (24 times 8 = 128) + (24 times 4 = 64)] for ROM 119860 ROM 119861and ROM119862 respectivelyThe compressed ratio (196608368)is 5342 1 with only two adders two multiplayer adders andXOR gate as additional hardware equipment

The final design of the high-speed DDFS which consistsof parallel pipelining PA and compressed ROMLUT by usingthe wave symmetry technique is shown in Figure 7

The Scientific World Journal 7

Table 1 Comparison between Rom size with previous DDFS works

Phaseaccumulator

(bit)

Truncatedphase (bit)

Amplitudephase (bit)

ROM size(bit)

Truncationratio SFDR (dB)

Sunderland et al 1984 [11] 20 14 12 3328 591 1 72Nicholas et al 1988 [12] 31 15 14 3072 1493 1 90Curticapean and Niittylahti 2001 [18] 28 14 12 832 236 1 84De Caro and Strollo 2005 [19] 24 14 12 480 4096 1 836Yang et al 2004 [8] 32 14 12 2176 9035 1 NAChimakurthy et al 2006 [20] 15 15 15 1216 404 1 903Babak and Keshavarzi 2009 [21] 32 16 14 1664 5513 1 853De Caro et al 2008 [22] 24 14 12 672 2925 1 80This work 32 14 12 368 5342 1 68Note in this work the measured DDFS output waveform is in signal-to-noise ratio (SNR)

Figure 9 The sine wave signal of the high-speed DDFS

5 Hardware Implementation ofHigh-Speed DDFS

The proposed design of the high-speed DDFS with 0029Hzfrequency resolution was coded in Verilog HDL successfullysimulated in ALTERAQuartus II software and implementedwith a Cyclone III FPGA kit board

The proposed DDFS has been verified using a spec-trum analyzer The measured results are consistent with thesimulated results The DDFS design accumulates the FCWinput into the sawtooth PA output and the PA output feedsinto the phase-to-amplitude converter (ROM LUT) The fullamplitude waveform at the output of the ROM lookup tableis shown using the Signal Tap logic analyzer in Figure 8

6 Result and Discussion

The 32-bit DDFS has been implemented on the CycloneIII FPGA kit board The 32-bit phase accumulator outputwas truncated into 14 bits Approximately 196608 (214 times

12) bits were required to draw the full sine wave signalwith 12-bit output Quarter-wave symmetry and an angular

decomposition technique based on trigonometric identitywere appliedTheROMwas compressed to only 368 bits with5342 1 ratio The measured DDFS output waveforms andspectra for different clock frequencies illustrate the purityof the sine wave output as shown in Figure 9 for frequencytuning word = (1FFFFFFF) in hexadecimal format and 119865clk =125MHz (Cyclone III kit board clock frequency) The outputfrequency that was calculated is 119865out = (FCW2119873) times 119865clk =

(229 minus 1232) times 125 lowast 106 = 15624999MHz The measuredoutput frequency from oscilloscope is 1563MHz and this isclosely matched with the calculation result

The signal-to-noise ratio (SNR) was approximated basedon

SNR = minus 602119872 minus 176 dB (14)

(see [29]) where119872 represents the number of bits used to feedthe digital-to-analog converter For the proposedDDFS119872 =

12 and the calculated SNR is 74 dBThe measured DDFS output from the spectrum analyzer

shows SNR of approximately 68 dB as shown in Figures 10(a)and 10(b) The result is about 6 dB less than the calculatedresult and this is due to the noise from wire connections

Table 1 shows the comparison of the ROM size used inthe proposed design with some other parameters The tableshows that the proposed design has the smallest ROM size

7 Conclusion

A 32-bit high-speed DDFS system was designed with0029Hz frequency resolution The system was successfullysimulated in ALTERA Quartus II software The phase accu-mulator together with the ROM lookup table has beenimplemented on the Cyclone III FPGA kit and verified witha Signal Tap logic analyzer and the complete DDFS systemwith digital to analog convertor has been implemented on theCyclone III FPGA kit board and the performance has beenmeasured using oscilloscope and spectrum analyzer Parallelpipelining with clock gating has been applied on a modifiedBK adder for the proposed phase accumulator design Wavesymmetry and an angular decomposition technique based on

8 The Scientific World Journal

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Marker1563MHz

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

minus1308dBm

Thu 16 Jan 2014

(a)

3113MHz

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

Marker

Thu 16 Jan 2014

minus1339dBm

(b)

Figure 10 The measured signal-to-noise ratio for the DDFS waveform output (a and b)

trigonometric identity were used to reduce the ROMsizeTheROM was compressed to only 368 bits with a 5342 1 ratioThe proposed design has demonstrated attractive resultsthat improve the operation speed and reduce the ROM sizesignificantly

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Tierney C M Rader and B Gold ldquoA digital frequency syn-thesizerrdquo IEEE Transactions on Audio and Electroacoustics vol19 pp 48ndash57 1971

[2] XGeng F FDai J D Irwin andR C Jaeger ldquoAn 11-bit 86GHzdirect digital synthesizer MMIC with 10-bit segmented sine-weighted DACrdquo IEEE Journal of Solid-State Circuits vol 45 no2 pp 300ndash313 2010

[3] B S Jensen M M Khafaji T K Johansen V Krozer and J CScheytt ldquoTwelve-bit 20-GHz reduced size pipeline accumulatorin 025 120583m SiGeC technology for direct digital synthesiserapplicationsrdquo IET Circuits Devices and Systems vol 6 no 1 pp19ndash27 2012

[4] S H Ibrahim S H M Ali and M S Islam ldquoDesign a 24-bits pipeline phase accumulator for direct digital frequencysynthesizerrdquo in Proceedings of the International Symposiumon Instrumentation and Measurement Sensor Network andAutomation (IMSNA rsquo12) pp 393ndash397 August 2012

[5] J Chen D Wu L Zhou J Wu Z Jin and X Liu ldquoA 53-GHz 32-bit accumulator designed for direct digital frequencysynthesizerrdquo Chinese Science Bulletin vol 57 no 19 pp 2480ndash2487 2012

[6] B-D Yang L-S Kim and H-K Yu ldquoA high speed directdigital frequency synthesizer using a low power pipelinedparallel accumulatorrdquo in Proceedings of the IEEE International

Symposium on Circuits and Systems vol 5 pp 373ndash376 May2002

[7] M Chappell and A McEwan ldquoA low power high speedaccumulator for DDFS applicationsrdquo in Proceedings of the IEEEInternational Symposium on Cirquits and Systems vol 2 pp797ndash800 May 2004

[8] B-D Yang J-H Choi S-H Han L-S Kim and H-K Yu ldquoAn800-MHz low-power direct digital frequency synthesizer withan on-chip DA converterrdquo IEEE Journal of Solid-State Circuitsvol 39 no 5 pp 761ndash774 2004

[9] K R Rekha B S Nagabushan and K R Nataraj ldquoFPGAimplementation of low power digital frequency synthesizerrdquoInternational Journal of Engineering Science and Technology vol2 no 10 pp 5385ndash5394 2010

[10] J M P Langlois and D Al-Khalili ldquoLow power direct digitalfrequency synthesizers in 018 120583m CMOSrdquo in Proceedings ofthe IEEE Custom Integrated Circuits Conference pp 283ndash286September 2003

[11] D A Sunderland R A Strauch S S Wharfield H T Petersonand C R Cole ldquoCMOSSOS frequency synthesizer LSI circuitfor spread spectrum communicationsrdquo IEEE Journal of Solid-State Circuits vol 19 no 4 pp 497ndash506 1984

[12] H T Nicholas H Samueli and B Kim ldquoOptimization of directdigital frequency synthesizer performance in the presence offinite word length effectsrdquo in Proceedings of the 42nd AnnualFrequency Control Symposium pp 357ndash363 June 1988

[13] M N Khan M S Imran M Rehan and U Hai ldquoHighspeed direct digital frequency synthesizer(DDFS) architecturewith reduced ROM structurerdquo in Proceedings of the StudentConference on Engineering Sciences and Technology (SCONESTrsquo05) pp 1ndash5 August 2005

[14] E N Mariangela Genovese D De Caro N Petra and AG M Strollo ldquoAnalysis and comparison of direct digitalfrequency synthesizers implementedon FPGArdquo Integration theVLSI Journal vol 47 pp 261ndash271 2014

[15] A Ashrafi and R Adhami ldquoTheoretical upperbound of thespurious-free dynamic range in direct digital frequency syn-thesizers realized by polynomial interpolation methodsrdquo IEEE

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

4 The Scientific World Journal

+

+

+

+

+

+

+

+

+

+

+

+

8-DFF

4-DFF

4-DFF

8-DFF 6-DFF

6-DFF

6-DFF

6-DFF

8-DFF

8-DFF

8-DFF

8-DFF

8 OUT X4

8 OUT X3

8 OUT X2

8 OUT X1

6 OUT X4

6 OUT X3

6 OUT X2

6 OUT X1

32

8 8

248

8

8

8

8

8

Clk4 Clk4

DFF

DFF

DFF

DFFDFF

MUX

MU

X

MUX

K

Set

Clk

Clk Clk

Clk

14

8

6

IN [7 2]

IN [7 0]

IN [7 0]

LOW [1 0]IN [7 2]

LOW [1 0]

LOW [1 0]IN [7 0]

LOW [1 0]IN [7 1]LOW [0]

IN [7 1]LOW [0]

IN [31 24]

IN [23 16]

IN [15 8]

[1 0

][9

8]

[17

16] 4 times 1

4 times 1

OUT [31 18]

8-bit reg 8-bit reg

8-bit reg

8-bit reg

8-bit reg

8-bit reg 6-bit reg8-bit reg

8-bit reg

8-bit reg

24-bit reg

24-bit reg

32-bit reg

18-bit reg

Figure 3 Pipelined phase accumulator with parallel adder based on modifying Bren-Kung adder and gated clocking technique

BK cells compute the carry for two or more of full adder(FA) cells and they are calculated as a sum of 119866 and 119875 cells[23 24] The arithmetic operation is given by

BK = 119866 + 119875

119866 = 11989210158401015840+ 11990110158401015840sdot 1198921015840

119875 = 11990110158401015840sdot 1199011015840

(6)

where 119892101584010158401198921015840 119901101584010158401199011015840 are higher and lower generate and prop-agate functions respectively The 119901 is a propagate function(119901119894= 119909119894oplus 119910119894) and 119892 is a generate function (119892

119894= 119909119894sdot 119910119894)

The general prefix addition algorithm is explained byZimmermann in [25] By adding the carry input 119862in in theprefix structure with somemodifications the prefix structurecan be used in pipelining-based adder design This approachis used in BK adder fast carry computation However inthis paper a modification is proposed to the BK adder sothat it can be used in pipelining architecture The proposedmodification is by removing the operation of the 119892

0 and

the carry out of the first bit 1198621can be achieved by a 2-1

multiplexer The input to this multiplexer is 1199090and 119862in while

1199010is the select input and the output is 119862

1 The operation of

the multiplexer is given by

1198621= (1199010 119888in) + (119909

0 1199010) (7)

where 1198621is the carry out 119901

0is the propagate function 119862in

is the carry input and 1199090is the first bit input The proposed

modification of the 8-bit BK adder is shown in Figure 4(b)The sum and carry out of the modified 8-bit BK adder areshown in

1198780= 1199010oplus 119888in

119878119873sdotsdotsdot1

= 119901((119873minus1)sdotsdotsdot1)

oplus 119862((119873minus1)sdotsdotsdot1)

119862out = 119892119873+ 119901119873sdot 119862119873

(8)

311 Comparison of Different Adder Architecture An adderis a key element of the pipelining PA design and a fastadder improves PA performance Parallel-prefix adder treestructures such as Sklansky [26] Kogge-Stone adder [27] BK[23] and Beaumont-Smith [28] have been used in pipeliningaccumulator design for high-speed operation

A comparison has been made between conventionaladder and several parallel-prefix adders for 12-bit 18-bit 24-bit and 32-bit operations The PA designs were coded inVerilog HDL and verified in Cyclone III FPGA kit boardPrior to that all the designs were simulated by usingALTERAQuartus IIThe comparison result is shown in Figure 5 Fromthe figure it can be seen that BK adder performs relativelyfaster especially for high number of bits

4 ROM Lookup Table Design

ROM LUT or phase-to-amplitude converter (PAC) is amemory storage address for DDFS which is used to convert

The Scientific World Journal 5

P0P1P2P3P4P5P6P7

x0x1x7 y0y1y7

P middot gP middot gP middot gP middot gP middot gP middot gP middot g p g

S0S1S2S3S4S5S6S7

SSSSSSSS

BK

BK

BK

BK BK

BK

BK

BKBK

BK

BK

Criticalpath

g0g1g2g3g4g5g6g7 p0p1p2p3p4p5p6P7

middot middot middot

middot middot middot middot middot middot middot

(a)

P2P3P4P5P6P7

x0x1 y0y1x7 y7

P middot g P middot g P middot g P middot g P middot g P middot g P middot g

S0S1S2S3S4S5S6S7

S S S S S S S S

BK

BK

BK

BK

BK BK BK

BK

BK

BK BK

Criticalpath

p

Cin

Cin

C1

C1

g1g2g3g4g5g6g7 p1p2p3p4p5p6P7 middotp

middot middot middot

middot middot middot middot middot middot middot

MU

X

(b)

Figure 4 Block circuit diagram of conventional Brent-Kung adder (a) and (b) modifying Brent-Kung adder

450

400

350

300

250

200

150

100

Max

imum

ope

ratio

n fre

quen

cy (M

Hz)

10 15 20 25 30 35

Number of bits

CLARCABrent-Kung

Kogge-StoneSklanskyBeaumont Smith

Figure 5 Comparison result of maximum operating frequency(119865Max) for phase accumulator design with CLA Brent-Kung Kogge-Stone Sklansky Beaumont-Smith and RCA adders

the phase signal into an amplitude sine wave signal High-accuracy output signal for DDFS requires a large number ofLUT The ROM size exponentially increases with increasingnumber of bit inputs The designerrsquos challenge is a tradeoffbetween reducing the ROM size while maintaining highperformance (high resolution high speed) Quarter-wavesymmetry technique is used to resize the ROM in theproposed DDFS design to store only one quarter (0 1205872) of

+

+

24 times 11Bit ROM

Bit ROM

Bit ROM

28 times 4

24 times 4

times

times

11

11

11

11

11

4

4

4

B

C

C

P-2 sineB

sineC

sineA cosA

cosA

cosA

cosA

cosA

sineA

sinB

sinB

sinC

sinC

sinout

Figure 6 Architecture of compressed ROM LUT design

the sine waveform and two most significant bits (MSB) fromthe phase accumulator are used to reconstruct the full sinewave From these twoMSBs one of them is used to determineif the sine amplitude is increasing or decreasing and the otherone is used to determine its sign

The phase output is directly used in the first and thirdquarter while the inverse values of the phase output areused in the second and fourth quarters This requires 2rsquoscomplement when the phase is between (120587 2120587) and isachieved by adding full adder at the output gate to accomplishthe full sine wave value To save power and achieve a smallerarea design the 12 LSB offset is added to the stored memoryaddress of sub-ROMs This offset removes the full addercomponent from the 2rsquos complement of the proposed design

The angular decomposition technique based on trigono-metric identity is one of the best techniques to reducethe quarter ROM LUT size The quarter ROM LUT waspartitioned into three (119860 119861 and 119862) such that 119860 lt (1205872)

6 The Scientific World Journal

MSB1

MSB2

PFout

Frequency control

word

Fclk

Adder Register comp1st

comp1st

RegNP-2

P-2

DDF

bit ROM

bit ROM

bit ROM

24 times 11 = 176

24 times 8 = 128

24 times 5 = 80

+

+DACLPF

sineA cosA

sineB

sineC

sinB

sinA

sinC

cosA

cosA

Figure 7 The block diagram of the final design of high-speed DDFS

Figure 8 Signal tap logic analyzer of FCW input (in hexadecimal) the sawtooth PA output and half and full amplitude waveform

119861 lt (1205872) lowast (12119860) and 119862 lt (1205872) lowast (12119860+119861) with the sameapproximations based on trigonometric identity

According to the trigonometric relation the sine wavefunction is given in

sin (119860 + 119861 + 119862)

= sin (119860 + 119861) cos119862 + cos119860 cos119861 sin119862

minus sin119860 sin119861 sin119862

(9)

where

sin (119860 + 119861) = sin119860 cos119861 + cos119860 sin119861 (10)

Equation (10) indicates the presence of four split sub-ROMstwo (2119860 and 2119861) for sin and cos119860 and119861The calculated resultsof (sin-cos119860) show that they are inversely symmetrical Basedon this cos(119860) can be obtained by complementing the sin(119860)

values and this is achieved by connecting the sin(119860) outputand the high 119881

119888119888to the XOR logic gate inputs In this way

only one addressing sub-ROM is needed for sin119860 and cos119860values The equation for cos119861 calculation is given by

cos119861 = cos((120587

2times

[0 (2119861 minus 1)]

2119861) times (

1

2119861)) (11)

The formula shows that the cos119861 values with 4-bit inputare fed into the sub-ROM 119861 (119861 = 4) therefore cos119861 =

cos(0046019) = 0999999677 cong 1 Thus the (cos119861) blockROMwas also removed from the proposed designTherefore(10) can be reduced as given by

sin (119860 + 119861) = sin119860 + cos119860 sin119861 (12)

With three values of 119860 119861 and 119862 (9) may be rewritten as

sin (119860 + 119861 + 119862) = sin119860 + cos119860 sin119861 + cos119860 sin119862 (13)

The change in the proposed ROMLUT design after hardwarereduction is shown in Figure 6

The error that results from the approximation in (9) is(2120587214) which is approximately 383 times 10minus4 The requiredROM size for 12-bit input is 214 times 12 = 196608 bits Applyingthe sine wave approximation based on trigonometric identitywith three 4-bit ROM requires only 368 bits [(24 times 11 =

176) + (24 times 8 = 128) + (24 times 4 = 64)] for ROM 119860 ROM 119861and ROM119862 respectivelyThe compressed ratio (196608368)is 5342 1 with only two adders two multiplayer adders andXOR gate as additional hardware equipment

The final design of the high-speed DDFS which consistsof parallel pipelining PA and compressed ROMLUT by usingthe wave symmetry technique is shown in Figure 7

The Scientific World Journal 7

Table 1 Comparison between Rom size with previous DDFS works

Phaseaccumulator

(bit)

Truncatedphase (bit)

Amplitudephase (bit)

ROM size(bit)

Truncationratio SFDR (dB)

Sunderland et al 1984 [11] 20 14 12 3328 591 1 72Nicholas et al 1988 [12] 31 15 14 3072 1493 1 90Curticapean and Niittylahti 2001 [18] 28 14 12 832 236 1 84De Caro and Strollo 2005 [19] 24 14 12 480 4096 1 836Yang et al 2004 [8] 32 14 12 2176 9035 1 NAChimakurthy et al 2006 [20] 15 15 15 1216 404 1 903Babak and Keshavarzi 2009 [21] 32 16 14 1664 5513 1 853De Caro et al 2008 [22] 24 14 12 672 2925 1 80This work 32 14 12 368 5342 1 68Note in this work the measured DDFS output waveform is in signal-to-noise ratio (SNR)

Figure 9 The sine wave signal of the high-speed DDFS

5 Hardware Implementation ofHigh-Speed DDFS

The proposed design of the high-speed DDFS with 0029Hzfrequency resolution was coded in Verilog HDL successfullysimulated in ALTERAQuartus II software and implementedwith a Cyclone III FPGA kit board

The proposed DDFS has been verified using a spec-trum analyzer The measured results are consistent with thesimulated results The DDFS design accumulates the FCWinput into the sawtooth PA output and the PA output feedsinto the phase-to-amplitude converter (ROM LUT) The fullamplitude waveform at the output of the ROM lookup tableis shown using the Signal Tap logic analyzer in Figure 8

6 Result and Discussion

The 32-bit DDFS has been implemented on the CycloneIII FPGA kit board The 32-bit phase accumulator outputwas truncated into 14 bits Approximately 196608 (214 times

12) bits were required to draw the full sine wave signalwith 12-bit output Quarter-wave symmetry and an angular

decomposition technique based on trigonometric identitywere appliedTheROMwas compressed to only 368 bits with5342 1 ratio The measured DDFS output waveforms andspectra for different clock frequencies illustrate the purityof the sine wave output as shown in Figure 9 for frequencytuning word = (1FFFFFFF) in hexadecimal format and 119865clk =125MHz (Cyclone III kit board clock frequency) The outputfrequency that was calculated is 119865out = (FCW2119873) times 119865clk =

(229 minus 1232) times 125 lowast 106 = 15624999MHz The measuredoutput frequency from oscilloscope is 1563MHz and this isclosely matched with the calculation result

The signal-to-noise ratio (SNR) was approximated basedon

SNR = minus 602119872 minus 176 dB (14)

(see [29]) where119872 represents the number of bits used to feedthe digital-to-analog converter For the proposedDDFS119872 =

12 and the calculated SNR is 74 dBThe measured DDFS output from the spectrum analyzer

shows SNR of approximately 68 dB as shown in Figures 10(a)and 10(b) The result is about 6 dB less than the calculatedresult and this is due to the noise from wire connections

Table 1 shows the comparison of the ROM size used inthe proposed design with some other parameters The tableshows that the proposed design has the smallest ROM size

7 Conclusion

A 32-bit high-speed DDFS system was designed with0029Hz frequency resolution The system was successfullysimulated in ALTERA Quartus II software The phase accu-mulator together with the ROM lookup table has beenimplemented on the Cyclone III FPGA kit and verified witha Signal Tap logic analyzer and the complete DDFS systemwith digital to analog convertor has been implemented on theCyclone III FPGA kit board and the performance has beenmeasured using oscilloscope and spectrum analyzer Parallelpipelining with clock gating has been applied on a modifiedBK adder for the proposed phase accumulator design Wavesymmetry and an angular decomposition technique based on

8 The Scientific World Journal

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Marker1563MHz

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

minus1308dBm

Thu 16 Jan 2014

(a)

3113MHz

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

Marker

Thu 16 Jan 2014

minus1339dBm

(b)

Figure 10 The measured signal-to-noise ratio for the DDFS waveform output (a and b)

trigonometric identity were used to reduce the ROMsizeTheROM was compressed to only 368 bits with a 5342 1 ratioThe proposed design has demonstrated attractive resultsthat improve the operation speed and reduce the ROM sizesignificantly

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Tierney C M Rader and B Gold ldquoA digital frequency syn-thesizerrdquo IEEE Transactions on Audio and Electroacoustics vol19 pp 48ndash57 1971

[2] XGeng F FDai J D Irwin andR C Jaeger ldquoAn 11-bit 86GHzdirect digital synthesizer MMIC with 10-bit segmented sine-weighted DACrdquo IEEE Journal of Solid-State Circuits vol 45 no2 pp 300ndash313 2010

[3] B S Jensen M M Khafaji T K Johansen V Krozer and J CScheytt ldquoTwelve-bit 20-GHz reduced size pipeline accumulatorin 025 120583m SiGeC technology for direct digital synthesiserapplicationsrdquo IET Circuits Devices and Systems vol 6 no 1 pp19ndash27 2012

[4] S H Ibrahim S H M Ali and M S Islam ldquoDesign a 24-bits pipeline phase accumulator for direct digital frequencysynthesizerrdquo in Proceedings of the International Symposiumon Instrumentation and Measurement Sensor Network andAutomation (IMSNA rsquo12) pp 393ndash397 August 2012

[5] J Chen D Wu L Zhou J Wu Z Jin and X Liu ldquoA 53-GHz 32-bit accumulator designed for direct digital frequencysynthesizerrdquo Chinese Science Bulletin vol 57 no 19 pp 2480ndash2487 2012

[6] B-D Yang L-S Kim and H-K Yu ldquoA high speed directdigital frequency synthesizer using a low power pipelinedparallel accumulatorrdquo in Proceedings of the IEEE International

Symposium on Circuits and Systems vol 5 pp 373ndash376 May2002

[7] M Chappell and A McEwan ldquoA low power high speedaccumulator for DDFS applicationsrdquo in Proceedings of the IEEEInternational Symposium on Cirquits and Systems vol 2 pp797ndash800 May 2004

[8] B-D Yang J-H Choi S-H Han L-S Kim and H-K Yu ldquoAn800-MHz low-power direct digital frequency synthesizer withan on-chip DA converterrdquo IEEE Journal of Solid-State Circuitsvol 39 no 5 pp 761ndash774 2004

[9] K R Rekha B S Nagabushan and K R Nataraj ldquoFPGAimplementation of low power digital frequency synthesizerrdquoInternational Journal of Engineering Science and Technology vol2 no 10 pp 5385ndash5394 2010

[10] J M P Langlois and D Al-Khalili ldquoLow power direct digitalfrequency synthesizers in 018 120583m CMOSrdquo in Proceedings ofthe IEEE Custom Integrated Circuits Conference pp 283ndash286September 2003

[11] D A Sunderland R A Strauch S S Wharfield H T Petersonand C R Cole ldquoCMOSSOS frequency synthesizer LSI circuitfor spread spectrum communicationsrdquo IEEE Journal of Solid-State Circuits vol 19 no 4 pp 497ndash506 1984

[12] H T Nicholas H Samueli and B Kim ldquoOptimization of directdigital frequency synthesizer performance in the presence offinite word length effectsrdquo in Proceedings of the 42nd AnnualFrequency Control Symposium pp 357ndash363 June 1988

[13] M N Khan M S Imran M Rehan and U Hai ldquoHighspeed direct digital frequency synthesizer(DDFS) architecturewith reduced ROM structurerdquo in Proceedings of the StudentConference on Engineering Sciences and Technology (SCONESTrsquo05) pp 1ndash5 August 2005

[14] E N Mariangela Genovese D De Caro N Petra and AG M Strollo ldquoAnalysis and comparison of direct digitalfrequency synthesizers implementedon FPGArdquo Integration theVLSI Journal vol 47 pp 261ndash271 2014

[15] A Ashrafi and R Adhami ldquoTheoretical upperbound of thespurious-free dynamic range in direct digital frequency syn-thesizers realized by polynomial interpolation methodsrdquo IEEE

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

The Scientific World Journal 5

P0P1P2P3P4P5P6P7

x0x1x7 y0y1y7

P middot gP middot gP middot gP middot gP middot gP middot gP middot g p g

S0S1S2S3S4S5S6S7

SSSSSSSS

BK

BK

BK

BK BK

BK

BK

BKBK

BK

BK

Criticalpath

g0g1g2g3g4g5g6g7 p0p1p2p3p4p5p6P7

middot middot middot

middot middot middot middot middot middot middot

(a)

P2P3P4P5P6P7

x0x1 y0y1x7 y7

P middot g P middot g P middot g P middot g P middot g P middot g P middot g

S0S1S2S3S4S5S6S7

S S S S S S S S

BK

BK

BK

BK

BK BK BK

BK

BK

BK BK

Criticalpath

p

Cin

Cin

C1

C1

g1g2g3g4g5g6g7 p1p2p3p4p5p6P7 middotp

middot middot middot

middot middot middot middot middot middot middot

MU

X

(b)

Figure 4 Block circuit diagram of conventional Brent-Kung adder (a) and (b) modifying Brent-Kung adder

450

400

350

300

250

200

150

100

Max

imum

ope

ratio

n fre

quen

cy (M

Hz)

10 15 20 25 30 35

Number of bits

CLARCABrent-Kung

Kogge-StoneSklanskyBeaumont Smith

Figure 5 Comparison result of maximum operating frequency(119865Max) for phase accumulator design with CLA Brent-Kung Kogge-Stone Sklansky Beaumont-Smith and RCA adders

the phase signal into an amplitude sine wave signal High-accuracy output signal for DDFS requires a large number ofLUT The ROM size exponentially increases with increasingnumber of bit inputs The designerrsquos challenge is a tradeoffbetween reducing the ROM size while maintaining highperformance (high resolution high speed) Quarter-wavesymmetry technique is used to resize the ROM in theproposed DDFS design to store only one quarter (0 1205872) of

+

+

24 times 11Bit ROM

Bit ROM

Bit ROM

28 times 4

24 times 4

times

times

11

11

11

11

11

4

4

4

B

C

C

P-2 sineB

sineC

sineA cosA

cosA

cosA

cosA

cosA

sineA

sinB

sinB

sinC

sinC

sinout

Figure 6 Architecture of compressed ROM LUT design

the sine waveform and two most significant bits (MSB) fromthe phase accumulator are used to reconstruct the full sinewave From these twoMSBs one of them is used to determineif the sine amplitude is increasing or decreasing and the otherone is used to determine its sign

The phase output is directly used in the first and thirdquarter while the inverse values of the phase output areused in the second and fourth quarters This requires 2rsquoscomplement when the phase is between (120587 2120587) and isachieved by adding full adder at the output gate to accomplishthe full sine wave value To save power and achieve a smallerarea design the 12 LSB offset is added to the stored memoryaddress of sub-ROMs This offset removes the full addercomponent from the 2rsquos complement of the proposed design

The angular decomposition technique based on trigono-metric identity is one of the best techniques to reducethe quarter ROM LUT size The quarter ROM LUT waspartitioned into three (119860 119861 and 119862) such that 119860 lt (1205872)

6 The Scientific World Journal

MSB1

MSB2

PFout

Frequency control

word

Fclk

Adder Register comp1st

comp1st

RegNP-2

P-2

DDF

bit ROM

bit ROM

bit ROM

24 times 11 = 176

24 times 8 = 128

24 times 5 = 80

+

+DACLPF

sineA cosA

sineB

sineC

sinB

sinA

sinC

cosA

cosA

Figure 7 The block diagram of the final design of high-speed DDFS

Figure 8 Signal tap logic analyzer of FCW input (in hexadecimal) the sawtooth PA output and half and full amplitude waveform

119861 lt (1205872) lowast (12119860) and 119862 lt (1205872) lowast (12119860+119861) with the sameapproximations based on trigonometric identity

According to the trigonometric relation the sine wavefunction is given in

sin (119860 + 119861 + 119862)

= sin (119860 + 119861) cos119862 + cos119860 cos119861 sin119862

minus sin119860 sin119861 sin119862

(9)

where

sin (119860 + 119861) = sin119860 cos119861 + cos119860 sin119861 (10)

Equation (10) indicates the presence of four split sub-ROMstwo (2119860 and 2119861) for sin and cos119860 and119861The calculated resultsof (sin-cos119860) show that they are inversely symmetrical Basedon this cos(119860) can be obtained by complementing the sin(119860)

values and this is achieved by connecting the sin(119860) outputand the high 119881

119888119888to the XOR logic gate inputs In this way

only one addressing sub-ROM is needed for sin119860 and cos119860values The equation for cos119861 calculation is given by

cos119861 = cos((120587

2times

[0 (2119861 minus 1)]

2119861) times (

1

2119861)) (11)

The formula shows that the cos119861 values with 4-bit inputare fed into the sub-ROM 119861 (119861 = 4) therefore cos119861 =

cos(0046019) = 0999999677 cong 1 Thus the (cos119861) blockROMwas also removed from the proposed designTherefore(10) can be reduced as given by

sin (119860 + 119861) = sin119860 + cos119860 sin119861 (12)

With three values of 119860 119861 and 119862 (9) may be rewritten as

sin (119860 + 119861 + 119862) = sin119860 + cos119860 sin119861 + cos119860 sin119862 (13)

The change in the proposed ROMLUT design after hardwarereduction is shown in Figure 6

The error that results from the approximation in (9) is(2120587214) which is approximately 383 times 10minus4 The requiredROM size for 12-bit input is 214 times 12 = 196608 bits Applyingthe sine wave approximation based on trigonometric identitywith three 4-bit ROM requires only 368 bits [(24 times 11 =

176) + (24 times 8 = 128) + (24 times 4 = 64)] for ROM 119860 ROM 119861and ROM119862 respectivelyThe compressed ratio (196608368)is 5342 1 with only two adders two multiplayer adders andXOR gate as additional hardware equipment

The final design of the high-speed DDFS which consistsof parallel pipelining PA and compressed ROMLUT by usingthe wave symmetry technique is shown in Figure 7

The Scientific World Journal 7

Table 1 Comparison between Rom size with previous DDFS works

Phaseaccumulator

(bit)

Truncatedphase (bit)

Amplitudephase (bit)

ROM size(bit)

Truncationratio SFDR (dB)

Sunderland et al 1984 [11] 20 14 12 3328 591 1 72Nicholas et al 1988 [12] 31 15 14 3072 1493 1 90Curticapean and Niittylahti 2001 [18] 28 14 12 832 236 1 84De Caro and Strollo 2005 [19] 24 14 12 480 4096 1 836Yang et al 2004 [8] 32 14 12 2176 9035 1 NAChimakurthy et al 2006 [20] 15 15 15 1216 404 1 903Babak and Keshavarzi 2009 [21] 32 16 14 1664 5513 1 853De Caro et al 2008 [22] 24 14 12 672 2925 1 80This work 32 14 12 368 5342 1 68Note in this work the measured DDFS output waveform is in signal-to-noise ratio (SNR)

Figure 9 The sine wave signal of the high-speed DDFS

5 Hardware Implementation ofHigh-Speed DDFS

The proposed design of the high-speed DDFS with 0029Hzfrequency resolution was coded in Verilog HDL successfullysimulated in ALTERAQuartus II software and implementedwith a Cyclone III FPGA kit board

The proposed DDFS has been verified using a spec-trum analyzer The measured results are consistent with thesimulated results The DDFS design accumulates the FCWinput into the sawtooth PA output and the PA output feedsinto the phase-to-amplitude converter (ROM LUT) The fullamplitude waveform at the output of the ROM lookup tableis shown using the Signal Tap logic analyzer in Figure 8

6 Result and Discussion

The 32-bit DDFS has been implemented on the CycloneIII FPGA kit board The 32-bit phase accumulator outputwas truncated into 14 bits Approximately 196608 (214 times

12) bits were required to draw the full sine wave signalwith 12-bit output Quarter-wave symmetry and an angular

decomposition technique based on trigonometric identitywere appliedTheROMwas compressed to only 368 bits with5342 1 ratio The measured DDFS output waveforms andspectra for different clock frequencies illustrate the purityof the sine wave output as shown in Figure 9 for frequencytuning word = (1FFFFFFF) in hexadecimal format and 119865clk =125MHz (Cyclone III kit board clock frequency) The outputfrequency that was calculated is 119865out = (FCW2119873) times 119865clk =

(229 minus 1232) times 125 lowast 106 = 15624999MHz The measuredoutput frequency from oscilloscope is 1563MHz and this isclosely matched with the calculation result

The signal-to-noise ratio (SNR) was approximated basedon

SNR = minus 602119872 minus 176 dB (14)

(see [29]) where119872 represents the number of bits used to feedthe digital-to-analog converter For the proposedDDFS119872 =

12 and the calculated SNR is 74 dBThe measured DDFS output from the spectrum analyzer

shows SNR of approximately 68 dB as shown in Figures 10(a)and 10(b) The result is about 6 dB less than the calculatedresult and this is due to the noise from wire connections

Table 1 shows the comparison of the ROM size used inthe proposed design with some other parameters The tableshows that the proposed design has the smallest ROM size

7 Conclusion

A 32-bit high-speed DDFS system was designed with0029Hz frequency resolution The system was successfullysimulated in ALTERA Quartus II software The phase accu-mulator together with the ROM lookup table has beenimplemented on the Cyclone III FPGA kit and verified witha Signal Tap logic analyzer and the complete DDFS systemwith digital to analog convertor has been implemented on theCyclone III FPGA kit board and the performance has beenmeasured using oscilloscope and spectrum analyzer Parallelpipelining with clock gating has been applied on a modifiedBK adder for the proposed phase accumulator design Wavesymmetry and an angular decomposition technique based on

8 The Scientific World Journal

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Marker1563MHz

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

minus1308dBm

Thu 16 Jan 2014

(a)

3113MHz

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

Marker

Thu 16 Jan 2014

minus1339dBm

(b)

Figure 10 The measured signal-to-noise ratio for the DDFS waveform output (a and b)

trigonometric identity were used to reduce the ROMsizeTheROM was compressed to only 368 bits with a 5342 1 ratioThe proposed design has demonstrated attractive resultsthat improve the operation speed and reduce the ROM sizesignificantly

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Tierney C M Rader and B Gold ldquoA digital frequency syn-thesizerrdquo IEEE Transactions on Audio and Electroacoustics vol19 pp 48ndash57 1971

[2] XGeng F FDai J D Irwin andR C Jaeger ldquoAn 11-bit 86GHzdirect digital synthesizer MMIC with 10-bit segmented sine-weighted DACrdquo IEEE Journal of Solid-State Circuits vol 45 no2 pp 300ndash313 2010

[3] B S Jensen M M Khafaji T K Johansen V Krozer and J CScheytt ldquoTwelve-bit 20-GHz reduced size pipeline accumulatorin 025 120583m SiGeC technology for direct digital synthesiserapplicationsrdquo IET Circuits Devices and Systems vol 6 no 1 pp19ndash27 2012

[4] S H Ibrahim S H M Ali and M S Islam ldquoDesign a 24-bits pipeline phase accumulator for direct digital frequencysynthesizerrdquo in Proceedings of the International Symposiumon Instrumentation and Measurement Sensor Network andAutomation (IMSNA rsquo12) pp 393ndash397 August 2012

[5] J Chen D Wu L Zhou J Wu Z Jin and X Liu ldquoA 53-GHz 32-bit accumulator designed for direct digital frequencysynthesizerrdquo Chinese Science Bulletin vol 57 no 19 pp 2480ndash2487 2012

[6] B-D Yang L-S Kim and H-K Yu ldquoA high speed directdigital frequency synthesizer using a low power pipelinedparallel accumulatorrdquo in Proceedings of the IEEE International

Symposium on Circuits and Systems vol 5 pp 373ndash376 May2002

[7] M Chappell and A McEwan ldquoA low power high speedaccumulator for DDFS applicationsrdquo in Proceedings of the IEEEInternational Symposium on Cirquits and Systems vol 2 pp797ndash800 May 2004

[8] B-D Yang J-H Choi S-H Han L-S Kim and H-K Yu ldquoAn800-MHz low-power direct digital frequency synthesizer withan on-chip DA converterrdquo IEEE Journal of Solid-State Circuitsvol 39 no 5 pp 761ndash774 2004

[9] K R Rekha B S Nagabushan and K R Nataraj ldquoFPGAimplementation of low power digital frequency synthesizerrdquoInternational Journal of Engineering Science and Technology vol2 no 10 pp 5385ndash5394 2010

[10] J M P Langlois and D Al-Khalili ldquoLow power direct digitalfrequency synthesizers in 018 120583m CMOSrdquo in Proceedings ofthe IEEE Custom Integrated Circuits Conference pp 283ndash286September 2003

[11] D A Sunderland R A Strauch S S Wharfield H T Petersonand C R Cole ldquoCMOSSOS frequency synthesizer LSI circuitfor spread spectrum communicationsrdquo IEEE Journal of Solid-State Circuits vol 19 no 4 pp 497ndash506 1984

[12] H T Nicholas H Samueli and B Kim ldquoOptimization of directdigital frequency synthesizer performance in the presence offinite word length effectsrdquo in Proceedings of the 42nd AnnualFrequency Control Symposium pp 357ndash363 June 1988

[13] M N Khan M S Imran M Rehan and U Hai ldquoHighspeed direct digital frequency synthesizer(DDFS) architecturewith reduced ROM structurerdquo in Proceedings of the StudentConference on Engineering Sciences and Technology (SCONESTrsquo05) pp 1ndash5 August 2005

[14] E N Mariangela Genovese D De Caro N Petra and AG M Strollo ldquoAnalysis and comparison of direct digitalfrequency synthesizers implementedon FPGArdquo Integration theVLSI Journal vol 47 pp 261ndash271 2014

[15] A Ashrafi and R Adhami ldquoTheoretical upperbound of thespurious-free dynamic range in direct digital frequency syn-thesizers realized by polynomial interpolation methodsrdquo IEEE

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

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Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

6 The Scientific World Journal

MSB1

MSB2

PFout

Frequency control

word

Fclk

Adder Register comp1st

comp1st

RegNP-2

P-2

DDF

bit ROM

bit ROM

bit ROM

24 times 11 = 176

24 times 8 = 128

24 times 5 = 80

+

+DACLPF

sineA cosA

sineB

sineC

sinB

sinA

sinC

cosA

cosA

Figure 7 The block diagram of the final design of high-speed DDFS

Figure 8 Signal tap logic analyzer of FCW input (in hexadecimal) the sawtooth PA output and half and full amplitude waveform

119861 lt (1205872) lowast (12119860) and 119862 lt (1205872) lowast (12119860+119861) with the sameapproximations based on trigonometric identity

According to the trigonometric relation the sine wavefunction is given in

sin (119860 + 119861 + 119862)

= sin (119860 + 119861) cos119862 + cos119860 cos119861 sin119862

minus sin119860 sin119861 sin119862

(9)

where

sin (119860 + 119861) = sin119860 cos119861 + cos119860 sin119861 (10)

Equation (10) indicates the presence of four split sub-ROMstwo (2119860 and 2119861) for sin and cos119860 and119861The calculated resultsof (sin-cos119860) show that they are inversely symmetrical Basedon this cos(119860) can be obtained by complementing the sin(119860)

values and this is achieved by connecting the sin(119860) outputand the high 119881

119888119888to the XOR logic gate inputs In this way

only one addressing sub-ROM is needed for sin119860 and cos119860values The equation for cos119861 calculation is given by

cos119861 = cos((120587

2times

[0 (2119861 minus 1)]

2119861) times (

1

2119861)) (11)

The formula shows that the cos119861 values with 4-bit inputare fed into the sub-ROM 119861 (119861 = 4) therefore cos119861 =

cos(0046019) = 0999999677 cong 1 Thus the (cos119861) blockROMwas also removed from the proposed designTherefore(10) can be reduced as given by

sin (119860 + 119861) = sin119860 + cos119860 sin119861 (12)

With three values of 119860 119861 and 119862 (9) may be rewritten as

sin (119860 + 119861 + 119862) = sin119860 + cos119860 sin119861 + cos119860 sin119862 (13)

The change in the proposed ROMLUT design after hardwarereduction is shown in Figure 6

The error that results from the approximation in (9) is(2120587214) which is approximately 383 times 10minus4 The requiredROM size for 12-bit input is 214 times 12 = 196608 bits Applyingthe sine wave approximation based on trigonometric identitywith three 4-bit ROM requires only 368 bits [(24 times 11 =

176) + (24 times 8 = 128) + (24 times 4 = 64)] for ROM 119860 ROM 119861and ROM119862 respectivelyThe compressed ratio (196608368)is 5342 1 with only two adders two multiplayer adders andXOR gate as additional hardware equipment

The final design of the high-speed DDFS which consistsof parallel pipelining PA and compressed ROMLUT by usingthe wave symmetry technique is shown in Figure 7

The Scientific World Journal 7

Table 1 Comparison between Rom size with previous DDFS works

Phaseaccumulator

(bit)

Truncatedphase (bit)

Amplitudephase (bit)

ROM size(bit)

Truncationratio SFDR (dB)

Sunderland et al 1984 [11] 20 14 12 3328 591 1 72Nicholas et al 1988 [12] 31 15 14 3072 1493 1 90Curticapean and Niittylahti 2001 [18] 28 14 12 832 236 1 84De Caro and Strollo 2005 [19] 24 14 12 480 4096 1 836Yang et al 2004 [8] 32 14 12 2176 9035 1 NAChimakurthy et al 2006 [20] 15 15 15 1216 404 1 903Babak and Keshavarzi 2009 [21] 32 16 14 1664 5513 1 853De Caro et al 2008 [22] 24 14 12 672 2925 1 80This work 32 14 12 368 5342 1 68Note in this work the measured DDFS output waveform is in signal-to-noise ratio (SNR)

Figure 9 The sine wave signal of the high-speed DDFS

5 Hardware Implementation ofHigh-Speed DDFS

The proposed design of the high-speed DDFS with 0029Hzfrequency resolution was coded in Verilog HDL successfullysimulated in ALTERAQuartus II software and implementedwith a Cyclone III FPGA kit board

The proposed DDFS has been verified using a spec-trum analyzer The measured results are consistent with thesimulated results The DDFS design accumulates the FCWinput into the sawtooth PA output and the PA output feedsinto the phase-to-amplitude converter (ROM LUT) The fullamplitude waveform at the output of the ROM lookup tableis shown using the Signal Tap logic analyzer in Figure 8

6 Result and Discussion

The 32-bit DDFS has been implemented on the CycloneIII FPGA kit board The 32-bit phase accumulator outputwas truncated into 14 bits Approximately 196608 (214 times

12) bits were required to draw the full sine wave signalwith 12-bit output Quarter-wave symmetry and an angular

decomposition technique based on trigonometric identitywere appliedTheROMwas compressed to only 368 bits with5342 1 ratio The measured DDFS output waveforms andspectra for different clock frequencies illustrate the purityof the sine wave output as shown in Figure 9 for frequencytuning word = (1FFFFFFF) in hexadecimal format and 119865clk =125MHz (Cyclone III kit board clock frequency) The outputfrequency that was calculated is 119865out = (FCW2119873) times 119865clk =

(229 minus 1232) times 125 lowast 106 = 15624999MHz The measuredoutput frequency from oscilloscope is 1563MHz and this isclosely matched with the calculation result

The signal-to-noise ratio (SNR) was approximated basedon

SNR = minus 602119872 minus 176 dB (14)

(see [29]) where119872 represents the number of bits used to feedthe digital-to-analog converter For the proposedDDFS119872 =

12 and the calculated SNR is 74 dBThe measured DDFS output from the spectrum analyzer

shows SNR of approximately 68 dB as shown in Figures 10(a)and 10(b) The result is about 6 dB less than the calculatedresult and this is due to the noise from wire connections

Table 1 shows the comparison of the ROM size used inthe proposed design with some other parameters The tableshows that the proposed design has the smallest ROM size

7 Conclusion

A 32-bit high-speed DDFS system was designed with0029Hz frequency resolution The system was successfullysimulated in ALTERA Quartus II software The phase accu-mulator together with the ROM lookup table has beenimplemented on the Cyclone III FPGA kit and verified witha Signal Tap logic analyzer and the complete DDFS systemwith digital to analog convertor has been implemented on theCyclone III FPGA kit board and the performance has beenmeasured using oscilloscope and spectrum analyzer Parallelpipelining with clock gating has been applied on a modifiedBK adder for the proposed phase accumulator design Wavesymmetry and an angular decomposition technique based on

8 The Scientific World Journal

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Marker1563MHz

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

minus1308dBm

Thu 16 Jan 2014

(a)

3113MHz

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

Marker

Thu 16 Jan 2014

minus1339dBm

(b)

Figure 10 The measured signal-to-noise ratio for the DDFS waveform output (a and b)

trigonometric identity were used to reduce the ROMsizeTheROM was compressed to only 368 bits with a 5342 1 ratioThe proposed design has demonstrated attractive resultsthat improve the operation speed and reduce the ROM sizesignificantly

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Tierney C M Rader and B Gold ldquoA digital frequency syn-thesizerrdquo IEEE Transactions on Audio and Electroacoustics vol19 pp 48ndash57 1971

[2] XGeng F FDai J D Irwin andR C Jaeger ldquoAn 11-bit 86GHzdirect digital synthesizer MMIC with 10-bit segmented sine-weighted DACrdquo IEEE Journal of Solid-State Circuits vol 45 no2 pp 300ndash313 2010

[3] B S Jensen M M Khafaji T K Johansen V Krozer and J CScheytt ldquoTwelve-bit 20-GHz reduced size pipeline accumulatorin 025 120583m SiGeC technology for direct digital synthesiserapplicationsrdquo IET Circuits Devices and Systems vol 6 no 1 pp19ndash27 2012

[4] S H Ibrahim S H M Ali and M S Islam ldquoDesign a 24-bits pipeline phase accumulator for direct digital frequencysynthesizerrdquo in Proceedings of the International Symposiumon Instrumentation and Measurement Sensor Network andAutomation (IMSNA rsquo12) pp 393ndash397 August 2012

[5] J Chen D Wu L Zhou J Wu Z Jin and X Liu ldquoA 53-GHz 32-bit accumulator designed for direct digital frequencysynthesizerrdquo Chinese Science Bulletin vol 57 no 19 pp 2480ndash2487 2012

[6] B-D Yang L-S Kim and H-K Yu ldquoA high speed directdigital frequency synthesizer using a low power pipelinedparallel accumulatorrdquo in Proceedings of the IEEE International

Symposium on Circuits and Systems vol 5 pp 373ndash376 May2002

[7] M Chappell and A McEwan ldquoA low power high speedaccumulator for DDFS applicationsrdquo in Proceedings of the IEEEInternational Symposium on Cirquits and Systems vol 2 pp797ndash800 May 2004

[8] B-D Yang J-H Choi S-H Han L-S Kim and H-K Yu ldquoAn800-MHz low-power direct digital frequency synthesizer withan on-chip DA converterrdquo IEEE Journal of Solid-State Circuitsvol 39 no 5 pp 761ndash774 2004

[9] K R Rekha B S Nagabushan and K R Nataraj ldquoFPGAimplementation of low power digital frequency synthesizerrdquoInternational Journal of Engineering Science and Technology vol2 no 10 pp 5385ndash5394 2010

[10] J M P Langlois and D Al-Khalili ldquoLow power direct digitalfrequency synthesizers in 018 120583m CMOSrdquo in Proceedings ofthe IEEE Custom Integrated Circuits Conference pp 283ndash286September 2003

[11] D A Sunderland R A Strauch S S Wharfield H T Petersonand C R Cole ldquoCMOSSOS frequency synthesizer LSI circuitfor spread spectrum communicationsrdquo IEEE Journal of Solid-State Circuits vol 19 no 4 pp 497ndash506 1984

[12] H T Nicholas H Samueli and B Kim ldquoOptimization of directdigital frequency synthesizer performance in the presence offinite word length effectsrdquo in Proceedings of the 42nd AnnualFrequency Control Symposium pp 357ndash363 June 1988

[13] M N Khan M S Imran M Rehan and U Hai ldquoHighspeed direct digital frequency synthesizer(DDFS) architecturewith reduced ROM structurerdquo in Proceedings of the StudentConference on Engineering Sciences and Technology (SCONESTrsquo05) pp 1ndash5 August 2005

[14] E N Mariangela Genovese D De Caro N Petra and AG M Strollo ldquoAnalysis and comparison of direct digitalfrequency synthesizers implementedon FPGArdquo Integration theVLSI Journal vol 47 pp 261ndash271 2014

[15] A Ashrafi and R Adhami ldquoTheoretical upperbound of thespurious-free dynamic range in direct digital frequency syn-thesizers realized by polynomial interpolation methodsrdquo IEEE

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

The Scientific World Journal 7

Table 1 Comparison between Rom size with previous DDFS works

Phaseaccumulator

(bit)

Truncatedphase (bit)

Amplitudephase (bit)

ROM size(bit)

Truncationratio SFDR (dB)

Sunderland et al 1984 [11] 20 14 12 3328 591 1 72Nicholas et al 1988 [12] 31 15 14 3072 1493 1 90Curticapean and Niittylahti 2001 [18] 28 14 12 832 236 1 84De Caro and Strollo 2005 [19] 24 14 12 480 4096 1 836Yang et al 2004 [8] 32 14 12 2176 9035 1 NAChimakurthy et al 2006 [20] 15 15 15 1216 404 1 903Babak and Keshavarzi 2009 [21] 32 16 14 1664 5513 1 853De Caro et al 2008 [22] 24 14 12 672 2925 1 80This work 32 14 12 368 5342 1 68Note in this work the measured DDFS output waveform is in signal-to-noise ratio (SNR)

Figure 9 The sine wave signal of the high-speed DDFS

5 Hardware Implementation ofHigh-Speed DDFS

The proposed design of the high-speed DDFS with 0029Hzfrequency resolution was coded in Verilog HDL successfullysimulated in ALTERAQuartus II software and implementedwith a Cyclone III FPGA kit board

The proposed DDFS has been verified using a spec-trum analyzer The measured results are consistent with thesimulated results The DDFS design accumulates the FCWinput into the sawtooth PA output and the PA output feedsinto the phase-to-amplitude converter (ROM LUT) The fullamplitude waveform at the output of the ROM lookup tableis shown using the Signal Tap logic analyzer in Figure 8

6 Result and Discussion

The 32-bit DDFS has been implemented on the CycloneIII FPGA kit board The 32-bit phase accumulator outputwas truncated into 14 bits Approximately 196608 (214 times

12) bits were required to draw the full sine wave signalwith 12-bit output Quarter-wave symmetry and an angular

decomposition technique based on trigonometric identitywere appliedTheROMwas compressed to only 368 bits with5342 1 ratio The measured DDFS output waveforms andspectra for different clock frequencies illustrate the purityof the sine wave output as shown in Figure 9 for frequencytuning word = (1FFFFFFF) in hexadecimal format and 119865clk =125MHz (Cyclone III kit board clock frequency) The outputfrequency that was calculated is 119865out = (FCW2119873) times 119865clk =

(229 minus 1232) times 125 lowast 106 = 15624999MHz The measuredoutput frequency from oscilloscope is 1563MHz and this isclosely matched with the calculation result

The signal-to-noise ratio (SNR) was approximated basedon

SNR = minus 602119872 minus 176 dB (14)

(see [29]) where119872 represents the number of bits used to feedthe digital-to-analog converter For the proposedDDFS119872 =

12 and the calculated SNR is 74 dBThe measured DDFS output from the spectrum analyzer

shows SNR of approximately 68 dB as shown in Figures 10(a)and 10(b) The result is about 6 dB less than the calculatedresult and this is due to the noise from wire connections

Table 1 shows the comparison of the ROM size used inthe proposed design with some other parameters The tableshows that the proposed design has the smallest ROM size

7 Conclusion

A 32-bit high-speed DDFS system was designed with0029Hz frequency resolution The system was successfullysimulated in ALTERA Quartus II software The phase accu-mulator together with the ROM lookup table has beenimplemented on the Cyclone III FPGA kit and verified witha Signal Tap logic analyzer and the complete DDFS systemwith digital to analog convertor has been implemented on theCyclone III FPGA kit board and the performance has beenmeasured using oscilloscope and spectrum analyzer Parallelpipelining with clock gating has been applied on a modifiedBK adder for the proposed phase accumulator design Wavesymmetry and an angular decomposition technique based on

8 The Scientific World Journal

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Marker1563MHz

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

minus1308dBm

Thu 16 Jan 2014

(a)

3113MHz

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

Marker

Thu 16 Jan 2014

minus1339dBm

(b)

Figure 10 The measured signal-to-noise ratio for the DDFS waveform output (a and b)

trigonometric identity were used to reduce the ROMsizeTheROM was compressed to only 368 bits with a 5342 1 ratioThe proposed design has demonstrated attractive resultsthat improve the operation speed and reduce the ROM sizesignificantly

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Tierney C M Rader and B Gold ldquoA digital frequency syn-thesizerrdquo IEEE Transactions on Audio and Electroacoustics vol19 pp 48ndash57 1971

[2] XGeng F FDai J D Irwin andR C Jaeger ldquoAn 11-bit 86GHzdirect digital synthesizer MMIC with 10-bit segmented sine-weighted DACrdquo IEEE Journal of Solid-State Circuits vol 45 no2 pp 300ndash313 2010

[3] B S Jensen M M Khafaji T K Johansen V Krozer and J CScheytt ldquoTwelve-bit 20-GHz reduced size pipeline accumulatorin 025 120583m SiGeC technology for direct digital synthesiserapplicationsrdquo IET Circuits Devices and Systems vol 6 no 1 pp19ndash27 2012

[4] S H Ibrahim S H M Ali and M S Islam ldquoDesign a 24-bits pipeline phase accumulator for direct digital frequencysynthesizerrdquo in Proceedings of the International Symposiumon Instrumentation and Measurement Sensor Network andAutomation (IMSNA rsquo12) pp 393ndash397 August 2012

[5] J Chen D Wu L Zhou J Wu Z Jin and X Liu ldquoA 53-GHz 32-bit accumulator designed for direct digital frequencysynthesizerrdquo Chinese Science Bulletin vol 57 no 19 pp 2480ndash2487 2012

[6] B-D Yang L-S Kim and H-K Yu ldquoA high speed directdigital frequency synthesizer using a low power pipelinedparallel accumulatorrdquo in Proceedings of the IEEE International

Symposium on Circuits and Systems vol 5 pp 373ndash376 May2002

[7] M Chappell and A McEwan ldquoA low power high speedaccumulator for DDFS applicationsrdquo in Proceedings of the IEEEInternational Symposium on Cirquits and Systems vol 2 pp797ndash800 May 2004

[8] B-D Yang J-H Choi S-H Han L-S Kim and H-K Yu ldquoAn800-MHz low-power direct digital frequency synthesizer withan on-chip DA converterrdquo IEEE Journal of Solid-State Circuitsvol 39 no 5 pp 761ndash774 2004

[9] K R Rekha B S Nagabushan and K R Nataraj ldquoFPGAimplementation of low power digital frequency synthesizerrdquoInternational Journal of Engineering Science and Technology vol2 no 10 pp 5385ndash5394 2010

[10] J M P Langlois and D Al-Khalili ldquoLow power direct digitalfrequency synthesizers in 018 120583m CMOSrdquo in Proceedings ofthe IEEE Custom Integrated Circuits Conference pp 283ndash286September 2003

[11] D A Sunderland R A Strauch S S Wharfield H T Petersonand C R Cole ldquoCMOSSOS frequency synthesizer LSI circuitfor spread spectrum communicationsrdquo IEEE Journal of Solid-State Circuits vol 19 no 4 pp 497ndash506 1984

[12] H T Nicholas H Samueli and B Kim ldquoOptimization of directdigital frequency synthesizer performance in the presence offinite word length effectsrdquo in Proceedings of the 42nd AnnualFrequency Control Symposium pp 357ndash363 June 1988

[13] M N Khan M S Imran M Rehan and U Hai ldquoHighspeed direct digital frequency synthesizer(DDFS) architecturewith reduced ROM structurerdquo in Proceedings of the StudentConference on Engineering Sciences and Technology (SCONESTrsquo05) pp 1ndash5 August 2005

[14] E N Mariangela Genovese D De Caro N Petra and AG M Strollo ldquoAnalysis and comparison of direct digitalfrequency synthesizers implementedon FPGArdquo Integration theVLSI Journal vol 47 pp 261ndash271 2014

[15] A Ashrafi and R Adhami ldquoTheoretical upperbound of thespurious-free dynamic range in direct digital frequency syn-thesizers realized by polynomial interpolation methodsrdquo IEEE

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

8 The Scientific World Journal

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Marker1563MHz

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

minus1308dBm

Thu 16 Jan 2014

(a)

3113MHz

REF 00dBm10dB

ATT 10dB A wrtNorm Norm

B blnk

Center 3125MHz Span 625MHzlowastRBW 10kHz lowastVBW 10kHz SWP 13 s

Marker

Thu 16 Jan 2014

minus1339dBm

(b)

Figure 10 The measured signal-to-noise ratio for the DDFS waveform output (a and b)

trigonometric identity were used to reduce the ROMsizeTheROM was compressed to only 368 bits with a 5342 1 ratioThe proposed design has demonstrated attractive resultsthat improve the operation speed and reduce the ROM sizesignificantly

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Tierney C M Rader and B Gold ldquoA digital frequency syn-thesizerrdquo IEEE Transactions on Audio and Electroacoustics vol19 pp 48ndash57 1971

[2] XGeng F FDai J D Irwin andR C Jaeger ldquoAn 11-bit 86GHzdirect digital synthesizer MMIC with 10-bit segmented sine-weighted DACrdquo IEEE Journal of Solid-State Circuits vol 45 no2 pp 300ndash313 2010

[3] B S Jensen M M Khafaji T K Johansen V Krozer and J CScheytt ldquoTwelve-bit 20-GHz reduced size pipeline accumulatorin 025 120583m SiGeC technology for direct digital synthesiserapplicationsrdquo IET Circuits Devices and Systems vol 6 no 1 pp19ndash27 2012

[4] S H Ibrahim S H M Ali and M S Islam ldquoDesign a 24-bits pipeline phase accumulator for direct digital frequencysynthesizerrdquo in Proceedings of the International Symposiumon Instrumentation and Measurement Sensor Network andAutomation (IMSNA rsquo12) pp 393ndash397 August 2012

[5] J Chen D Wu L Zhou J Wu Z Jin and X Liu ldquoA 53-GHz 32-bit accumulator designed for direct digital frequencysynthesizerrdquo Chinese Science Bulletin vol 57 no 19 pp 2480ndash2487 2012

[6] B-D Yang L-S Kim and H-K Yu ldquoA high speed directdigital frequency synthesizer using a low power pipelinedparallel accumulatorrdquo in Proceedings of the IEEE International

Symposium on Circuits and Systems vol 5 pp 373ndash376 May2002

[7] M Chappell and A McEwan ldquoA low power high speedaccumulator for DDFS applicationsrdquo in Proceedings of the IEEEInternational Symposium on Cirquits and Systems vol 2 pp797ndash800 May 2004

[8] B-D Yang J-H Choi S-H Han L-S Kim and H-K Yu ldquoAn800-MHz low-power direct digital frequency synthesizer withan on-chip DA converterrdquo IEEE Journal of Solid-State Circuitsvol 39 no 5 pp 761ndash774 2004

[9] K R Rekha B S Nagabushan and K R Nataraj ldquoFPGAimplementation of low power digital frequency synthesizerrdquoInternational Journal of Engineering Science and Technology vol2 no 10 pp 5385ndash5394 2010

[10] J M P Langlois and D Al-Khalili ldquoLow power direct digitalfrequency synthesizers in 018 120583m CMOSrdquo in Proceedings ofthe IEEE Custom Integrated Circuits Conference pp 283ndash286September 2003

[11] D A Sunderland R A Strauch S S Wharfield H T Petersonand C R Cole ldquoCMOSSOS frequency synthesizer LSI circuitfor spread spectrum communicationsrdquo IEEE Journal of Solid-State Circuits vol 19 no 4 pp 497ndash506 1984

[12] H T Nicholas H Samueli and B Kim ldquoOptimization of directdigital frequency synthesizer performance in the presence offinite word length effectsrdquo in Proceedings of the 42nd AnnualFrequency Control Symposium pp 357ndash363 June 1988

[13] M N Khan M S Imran M Rehan and U Hai ldquoHighspeed direct digital frequency synthesizer(DDFS) architecturewith reduced ROM structurerdquo in Proceedings of the StudentConference on Engineering Sciences and Technology (SCONESTrsquo05) pp 1ndash5 August 2005

[14] E N Mariangela Genovese D De Caro N Petra and AG M Strollo ldquoAnalysis and comparison of direct digitalfrequency synthesizers implementedon FPGArdquo Integration theVLSI Journal vol 47 pp 261ndash271 2014

[15] A Ashrafi and R Adhami ldquoTheoretical upperbound of thespurious-free dynamic range in direct digital frequency syn-thesizers realized by polynomial interpolation methodsrdquo IEEE

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

The Scientific World Journal 9

Transactions on Circuits and Systems I vol 54 no 10 pp 2252ndash2261 2007

[16] D De Caro and A G M Strollo ldquoHigh-performance directdigital frequency synthesizers in 025 120583m CMOS using dual-slope approximationrdquo IEEE Journal of Solid-State Circuits vol40 no 11 pp 2220ndash2227 2005

[17] D De Caro N Petra and A G M Strollo ldquoDirect digi-tal frequency synthesizer using nonuniform piecewise-linearapproximationrdquo IEEE Transactions on Circuits and Systems Ivol 58 no 10 pp 2409ndash2419 2011

[18] F Curticapean and J Niittylahti ldquoA hardware efficient directdigital frequency synthesizerrdquo in Proceedings of the 8th IEEEInternational Conference on Electronics Circuits and Systems(ICECS rsquo01) pp 51ndash54 September 2001

[19] D De Caro andA GM Strollo ldquoHigh-performance direct dig-ital frequency synthesizers using piecewise-polynomial approx-imationrdquo IEEE Transactions on Circuits and Systems I vol 52no 2 pp 324ndash337 2005

[20] L S J Chimakurthy M Ghosh F F Dai and R C Jaeger ldquoAnovel DDS using nonlinear ROM addressing with improvedcompression ratio and quantization noiserdquo IEEE Transactionson Ultrasonics Ferroelectrics and Frequency Control vol 53 pp274ndash283 2006

[21] F Babak and P Keshavarzi ldquoA novel DDFS based on trigono-metric approximationwith a scaling blockrdquo inProceedings of the6th International Conference on Information Technology NewGenerations (ITNG rsquo09) pp 102ndash106 2009

[22] D De Caro N Petra and A G M Strollo ldquoReducing lookup-table size in direct digital frequency synthesizers using opti-mizedmultipartite tablemethodrdquo IEEE Transactions on Circuitsand Systems I vol 55 no 7 pp 2116ndash2127 2008

[23] R P Brent and H T Kung ldquoRegular layout for parallel addersrdquoIEEE Transactions on Computers vol 31 no 3 pp 260ndash2641982

[24] K Bazargan EE 5324mdashVLSI Design II Adders University ofMinnesota 2006

[25] R Zimmermann Binary adder architectures for cell-based VLSIand their synthesis [Doctor of technical sciences] Swiss FederalInstitute of Technology in Zurich 1997

[26] J Sklansky ldquoConditional-sum addition logicrdquo IRE Transactionson Electronic Computers vol EC-9 pp 226ndash231 1960

[27] P M Kogge and H S Stone ldquoA parallel algorithm for theefficient solution of a general class of recurrence equationsrdquoIEEE Transactions on Computers vol 22 no 8 pp 786ndash7931973

[28] A Beaumont-Smith and C-C Lim ldquoParallel prefix adderdesignrdquo in Proceedings of the 15th IEEE Symposium onComputerArithmetic pp 218ndash225 June 2001

[29] P OLeary and F Maloberti ldquoA direct-digital synthesizer withimproved spectral performancerdquo IEEE Transactions on Com-munications vol 39 no 7 pp 1046ndash1048 1991

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of