Research Article Design a Bioamplifier with High CMRR · 2019. 7. 31. · OS OUT =0 = OV 2 TH 2 + ( / ) ( / ) 2 + OV /2 2. ... and circuit for the rst and second stages were designed

Hindawi Publishing CorporationVLSI DesignVolume 2013 Article ID 210265 5 pageshttpdxdoiorg1011552013210265

Research ArticleDesign a Bioamplifier with High CMRR

Yu-Ming Hsiao Miin-Shyue Shiau Kuen-Han Li Jing-Jhong Hou Heng-Shou HsuHong-Chong Wu and Don-Gey Liu

Department of Electronic Engineering Feng Chia University Taichung 40724 Taiwan

Correspondence should be addressed to Don-Gey Liu dgliufcuedutw

Received 23 December 2012 Accepted 5 April 2013

Academic Editor Yeong-Lin Lai

Copyright copy 2013 Yu-Ming Hsiao et alThis is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and lowoffset This design was implemented by the 035 120583m CMOS technology provided by TSMC With three stages of amplification andby balanced self-bias a voltage gain of 80 dB with a CMRR of 130 dB was achieved The related input offset was as low as 06 120583VIn addition the bias circuits were designed to be less sensitive to the power supply It was expected that the whole amplifier wasthen more independent of process variations This fact was confirmed in this study by simulation With the simulation results it ispromising to exhibit an amplifier with high performances for biomedical applications

1 Introduction

For biomedical applications a voltage amplifier with a gainof 80 dB and a high CMRR is required as a building blockin front-end subsystems [1 2] Since the voltage level ofphysiologic signals at the front-end subsystem is very weakprocesses for analog signals usually include several steps ofamplification filtering offset adjustment and electrical con-ditioning After suitable processing the signal will then belarge enough and effectively suitable for analog-to-digitalconversion at later stages [3ndash5]

In considering the physiological signals extracted fromhuman bodies the amplitude of an electrocardiographic(ECG) signal is usually less than 100 120583V Such value is veryweak as compared to the noise floor and imperfection of thecommonly used operational amplifiers (OPAs) An instru-mentation amplifier (IA) is usually employed to achieve therequired performances

In addition to the requirement of high voltage gain in con-structing the amplifiers for an IA another important require-ment for the amplifiers is CMRR According to the recom-mendations of Association of the Advancement of MedicalInstrumentation (AAMI) CMRR is required to be higherthan 90 dBwith the open-loop voltage gain higher than 80 dB

In this study the 035 120583mCMOS technology of TSMCwasemployed in designing a high performance amplifier

In our study a high-voltage-gain amplifier was tried witha self-biasing technique to have a high CMRR and low inputoffset and to be less sensitive to process variations Thesimulation was performed based on the models supported byChip Implementation Center (CIC) The related results willbe illustrated

2 Design Details

21 Design of the Differential Amplifier For the purposesof high CMRR and low offset at the input differentialconfigurationwith a symmetrical floor planning in layoutwillbe preferred in the design of an amplifier

Figure 1 shows the schematic of an amplifier with thedifferential configuration both at the input and at the outputIn this circuit transistors 119872

1and 119872

2are the differential

pair for amplification The block with 119868119879and 119877

119879forms a tail

current biasThe resistors 1198771198631 1198771198632 1198771198711 and 119877

1198712are taken as

the loadsFigure 2 shows an alternative representation of the ampli-

fier in Figure 1 The input and output signals can be decom-posed into the common and the differential modes Withthis decomposition the performance of the amplifier in thecommon mode and the differential mode can be discussedseparately

2 VLSI Design

119881DD

1198771198631 11987711986321198811199001 1198811199002

11987711987121198771198711

1198721 1198722

119881IN1 119881IN2

minus119881ss

119877119879119868119879

Figure 1 Schematic of the differential amplifier

DA

1198811199001

1198811199002

1198771198712

1198771198711

119881IN1

119881IN2119881cm

1198811198892

minus1198811198892+minus

+

+

+minusminus minus

Figure 2 Representation of the amplifier in the common and thedifferential modes

In the commonmode the two output voltages will be thesame if the circuit is ideal in a form of total symmetry Thisrequires that the branches for 119868

1198631and 1198681198632

are matched with1198771198711= 1198771198712

and 1198771198631

= 1198771198632

For the current bias as the tail a current mirror witha stable reference current 119868REF can be employed in theintegrated circuits to give a high output resistance 119877

119879

Other techniques to improve the performance of thisamplifier will be discussed in detail in the following

For practical design there exist variations in the deviceseven with the integrated circuit technology The outputvoltage will not be zero for the common input condition Forexample the imperfections in the threshold voltage and thetransconductance of the MOS transistors and the variationin 119877119863are uncorrelated The resulted input offset voltage can

be expressed as

119881OS equiv119881OUT

1003816100381610038161003816119881119889=0

119860119889

=119881OV2

radic(Δ119877119863

119877119863

)

2

+ (Δ (119882119871)

(119882119871))

2

+ (Δ119881TH

(119881OV) 2)

2

(1)

According to the analysis in the common mode and thedifferential mode the output voltage can be expressed as the

sum of the amplification of the signals of both modes Therelations for the outputs can be written at follows

1198811198741

=119860119889

2times V119889+ 119860cm times Vcm (2a)

1198811198742

= minus119860119889

2times V119889+ 119860cm times Vcm (2b)

where V119889equiv Vin1 minus Vin2 Vcm equiv (Vin1 + Vin2)2 119860119889 is the

differential-mode voltage gain and 119860cm is the common-mode gain It is similar for the expression for 119881

1198742 The

common-mode rejection ratio (CMRR) is then defined as

CMRR equiv

10038161003816100381610038161003816100381610038161003816

119860119889

119860cm

10038161003816100381610038161003816100381610038161003816 (3)

A good amplifier is required to have a high 119860119889with a nearly

zero 119860cm Due to the variations in the fabrication processit is a big challenge to achieve a high CMRR with a lowinput offset In this study a balanced bias technique wasemployed to reduce the sensitivity to the process variationGood properties of this amplifier have been confirmed in thepostlayout simulation

22 Tristage Amplifier In this design three stages of ampli-fication were employed to achieve the required voltage gainand CMRR at the same time for weak biosignals Figure 3shows the detailed circuit in this design Table 1 gives thespecifications for this design

As seen in Figure 3 the first stage is composed of1198721ndash1198725

The second stage includes 1198726ndash11987212 These two stages can

be used as an operational transconductance amplifier (OTA)[6 7] or a folded cascade amplifier [8] The third stagecomprising 119872

13and 119872

14forms a type 119860 common-source

(CS) amplifier to drive loadsTransistors119872

1198781ndash1198721198786provide a bias current for the first-

stage amplifier The source of biasing for the second-stageamplifier comes from the balanced self-bias current mirror1198728ndash11987211 in Figure 3 In this part the biasing currents were

less sensitive to the level of the power supply In additionthe complementary arrangement of the loads at the first-stageand the second-stage amplifiers would reduce the variationof the amplification if there are changes in the NMOS andPMOSThe bias voltage for the third stage comes from119872

9in

the second stage Since the bias currents in1198729and119872

11were

constant the gate bias for11987213would be constant Therefore

the properties of the whole amplifier would be less affected bythe uncertainties in fabrication

For the design strategy the first stage was designed toachieve a high CMRR rather than a high voltage gain Theoverall voltage gain was boosted at the second and thethird stages Since this amplifier was designed for biomedicalapplications the voltage gain was tried to be as high aspossible with a moderate small bandwidth around 100Hz Atthe third stage a clamping circuit can keep dynamic trackingof the output gain such that the voltage gain would be lessaffected by variations in the transistors

In addition to the electrical considerations the layoutand circuit for the first and second stages were designed as

VLSI Design 3

Stage 1 Stage 2 Stage 3

119881DD

1198721 1198722

119881IN2

minus119881ss

119881IN1

119881out

11987214

119862119862

119877119885

11987213

11987212

11987210 11987211

1198726 1198727

1198728 1198729

11987241198601198723119860

11987241198611198723119861

11987211987821198721198781

1198721198783 1198721198784

11987211987861198721198785

119877119878

Self-bias

119881119861

Figure 3 Structure of the tristage amplifier

Table 1 Specifications for the bioamplifier

Parameter Spec Value119881119900119881119894

≧ 20 kVV119860VO ≧ 80 dBPM ≧ 60∘

UGF ≦ 2MHzCMRR ≧ 90 dBPD ≦ 1mW

symmetrical as possible In this way the common signalswould be cancelled out in the differential structureThereforethe equivalent input offset would be suppressed effectively

With the above techniques an amplifier with high voltagegain high CMRR low offset and low drift voltage can beachieved and confirmed in the simulation

For our circuit the level of the power supply was set at33 V by setting 119881DD at 165V and minus119881SS at minus165V In themeanwhile the power dissipation was specified below 1mWfor portable operations With this constraint as explained by(4) the total current consumed in this circuit cannot bemorethan 0303mA

119868Supply le119875119863Spec

119881Supply= 0303mA (4)

As for the stability consideration the phase margin (PM)of this amplifier was tuned to be 60∘ in our simulation [9]In this design we select 119866

1198983ge 10119866

1198982 And the second

pole was set as 1205961198752

ge 22 times 120596119879 Therefore the Miller

compensation capacitor 119862119862 was selected to be 18 pF by the

following calculation

119862119862ge 22 times

1198661198981

1198661198982

times 1198621198742

= 0221198621198742 (5)

23 Transistor Dimensions In general the tail current wasrequired to be higher than the product of the screw rate and119862119862 In this study this product was 10 120583A for the second stage

Since the screw rate for the case of light loads is not requiredstrictly the tail current at stage 2 was selected as 15 120583A

The bias currents for the two branches through 1198726and

1198727equally divide the tail current into 119868

1198636= 1198681198638

= 11986811986310

=

1198681198637

= 1198681198639

= 11986811986311

= 75 120583AWith this bias current the transconductance 119892

119898 and the

gate-to-source voltage 119881GS can be designed by a suitabledimension ratio119882119871 by the following relations

119868119863=1

2sdot 120583119899sdot 119862119900119909sdot (

119882

119871) sdot (119881OV)

2

sdot (1 + 120582119881DS) (6)

119892119898= (120583119899sdot 119862119900119909) sdot (

119882

119871) sdot (119881OV) sdot (1 + 120582119881DS)

= radic2120583119899sdot 119862119900119909sdot (

119882

119871) sdot 119868119863sdot (1 + 120582119881DS)

=2 times 119868119863

119881OV

(7)

where the overdrive voltage 119881OV equiv 119881GS minus 119881thFor the third stage its transconductance gain 119866

1198983 is the

same as 11989211989813

of11987213 We chose 119866

1198983ge 10119866

1198982 that is 119866

1198983ge

590 120583AV and 11989211989813

= 1198661198983

= 600 120583AV In addition theoverdrive voltage for119872

13was selected as 119881OV13 = 02V that

is 119881GS13 equiv 119881OV13 + 119881tn = 085V Therefore 119881DS13 = 119881DS14 =165V The dimension ratio for (119882119871)

13can be determined

by (6)In this design we used 119872

1198781sim 1198721198786

and a resistor 119877119878

to form a self-bias circuit with a boot-strapping positive

4 VLSI Design

Table 2 Variations of the simulated properties of the bio-amplifier with 5 fabrication corners

Items SS SF TT FS FF119881119900119881119894

minus331 k minus297 k minus293 k minus277 k minus226 k119860VO (dB) 904 895 893 889 871PM 888∘ 898∘ 897∘ 897∘ 910∘

119891H3db (Hz) 630 631 794 631 82UGF (Hz) 141119864 + 06 147119864 + 06 146119864 + 06 144119864 + 06 152119864 + 06

CMRR (dB) 1364351 1362238 1367342 1365733 135778PD (120583W) 357 332 328 324 316119881os (120583V) 108 101 52 0033 208

feedback The current controlled by 119868REF can be expressedas

119868REF times 119877119878 = 119881GS1198786 minus 119881GS1198785 = radic119868REF1198701198786

minus radic119868REF1198701198785

(8)

By (8) we selected the dimension ratio of1198721198785to be 14 of that

of1198721198786 that is

(119882

119871)1198785

=1

4(119882

119871)1198786

(9)

The resistance can be obtained as follows

119877119878=

1

119868REFradic119868REF1198701198785

(10)

The reference current was set as 119868REF = 5 120583A The dimensionratio for119872

1198781sim 1198721198784can also be derived by (6)

3 Simulation and Verification beforeFabrication

In this study HSPICE with the device models for 035 120583mCMOS technology from TSMC was employed for the simu-lation and analysisThe performance of the whole circuit wasverified first in the prelayout simulation Then the physicallayout was implemented and the related parameters wereextracted With the obtained information of the physicallayout the postlayout simulation was performed to checkthe feasibility of our layout Corner simulations were alsoperformed to check the effect of the process variation on theperformance of our amplifier

Figures 4ndash7 illustrate the related performances with 5 cor-ner conditions in fabrication Table 2 lists other performanceitems with the 5 corners With these results we can find thatthe voltage gain in Figure 6 can be kept higher than 80 dBAnd the variation of the obtained gains due to the uncertaintyin fabrication can be smaller than 5 dB It can also be foundin Figures 4 and 5 that the phase margin is much larger than60∘ In Figure 5 we can confirm that the variation of phasesis insignificant As shown in Figure 7 the obtained CMRR isas high as 130 dB for frequency up to 10 kHzThe variation ofCMRR due to the fabrication is also insignificant With theseresults a bio-amplifier both with a very high CMRR and ahigh voltage gain at the same time can be expected for thefabricated chips

Frequency (Hz)

0102030405060708090

100

0306090120150180

Phas

e (de

g)

minus10minus20minus30minus40minus50

Volta

ge g

ain

(dB)

minus30

minus60

minus90

minus1201119864minus01 1119864+01 1119864+03 1119864+05 1119864+07

Figure 4 Frequency response for the bio-amplifier in the typicalfabrication condition (TT)

SSSFTT

FSFF

FF

SS

180

150

120

Phas

e (de

g)

90

60

30

Frequency (Hz)1119864minus01 1119864+01 1119864+03 1119864+05 1119864+07

Figure 5 Simulated phases for the bio-amplifier in 5 cornerconditions

4 Conclusion

A bio-amplifier with high gain and high CMRRwas designedand verified in this study According to the obtained perfor-mance properties in Table 2 it is promising that a processindependent performance can be obtained for this amplifier

VLSI Design 5

0102030405060708090

100

Volta

ge g

ain

(dB)


minus10minus20

minus30

minus40minus50

SSSFTT

FSFF

Figure 6 Simulated gains for the bio-amplifier in 5 corner condi-tions

40

60

80

100

120

140

CMRR

(dB)


SSSFTT

FSFF

Figure 7 Simulated CMRRs for the bio-amplifier in 5 cornerconditions

Acknowledgments

The authors acknowledge the support from Chip Implemen-tation Center (CIC) and Chang Bin Show Chwan MemorialHospital with the research resources Partial financial supportfrom National Science Council (NSC) republic of china isalso acknowledged

References

[1] K A Ng and P K Chan ldquoA CMOS analog front-end IC forportable EEGECG monitoring applicationsrdquo IEEE Transac-tions on Circuits and Systems I vol 52 no 11 pp 2335ndash23472005

[2] B Wang H Ji Z Huang and H Li ldquoA high-speed dataacquisition system for ECT based on the differential sampling

methodrdquo IEEE Sensors Journal vol 5 no 2 pp 308ndash3112005

[3] C H Chan J Wills J LaCoss J J Granacki and J ChomaJr ldquoA novel variable-gain micro-power band-pass auto-zeroingCMOS amplifierrdquo in Proceedings of the IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo07) pp 337ndash340May 2007

[4] B Premanode N Silawan and C Toumazou ldquoDrift reductionin ion-sensitive FETs using correlated double samplingrdquo Elec-tronics Letters vol 43 no 16 pp 857ndash859 2007

[5] J Wu G K Fedder and L R Carley ldquoA low-noise low-offsetchopper-stabilized capacitive-readout amplifier for CMOSMEMS accelerometersrdquo in Proceedings of the IEEE InternationalSolid-State Circuits Conference (ISSCC rsquo02) pp 428ndash425 Febru-ary 2002

[6] G Nicollini and C Guardiani ldquo33-V 800-nV rms noise gain-programmable CMOS microphone preamplifier design usingyield modeling techniquerdquo IEEE Journal of Solid-State Circuitsvol 28 no 8 pp 915ndash921 1993

[7] V Ivanov J Zhou and I M Filanovsky ldquoA 100-dB CMRRCMOS operational amplifier with single-supply capabilityrdquoIEEE Transactions on Circuits and Systems II vol 54 no 5 pp397ndash401 2007

[8] P C de Jong G C M Meijer and A H M van RoermundldquoA 300∘C dynamic-feedback instrumentation amplifierrdquo IEEEJournal of Solid-State Circuits vol 33 no 12 pp 1999ndash20081998

[9] K N Leung and P K T Mok ldquoAnalysis of multistage amplifier-frequency compensationrdquo IEEE Transactions on Circuits andSystems I vol 48 no 9 pp 1041ndash1056 2001

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Submit your manuscripts athttpwwwhindawicom

VLSI Design



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Navigation and Observation



DistributedSensor Networks


2 VLSI Design

119881DD

1198771198631 11987711986321198811199001 1198811199002

11987711987121198771198711

1198721 1198722

119881IN1 119881IN2

minus119881ss

119877119879119868119879

Figure 1 Schematic of the differential amplifier

DA

1198811199001

1198811199002

1198771198712

1198771198711

119881IN1

119881IN2119881cm

1198811198892

minus1198811198892+minus

+

+

+minusminus minus

Figure 2 Representation of the amplifier in the common and thedifferential modes

In the commonmode the two output voltages will be thesame if the circuit is ideal in a form of total symmetry Thisrequires that the branches for 119868

1198631and 1198681198632

are matched with1198771198711= 1198771198712

and 1198771198631

= 1198771198632

For the current bias as the tail a current mirror witha stable reference current 119868REF can be employed in theintegrated circuits to give a high output resistance 119877

119879

Other techniques to improve the performance of thisamplifier will be discussed in detail in the following

For practical design there exist variations in the deviceseven with the integrated circuit technology The outputvoltage will not be zero for the common input condition Forexample the imperfections in the threshold voltage and thetransconductance of the MOS transistors and the variationin 119877119863are uncorrelated The resulted input offset voltage can

be expressed as

119881OS equiv119881OUT

1003816100381610038161003816119881119889=0

119860119889

=119881OV2

radic(Δ119877119863

119877119863

)

2

+ (Δ (119882119871)

(119882119871))

2

+ (Δ119881TH

(119881OV) 2)

2

(1)

According to the analysis in the common mode and thedifferential mode the output voltage can be expressed as the

sum of the amplification of the signals of both modes Therelations for the outputs can be written at follows

1198811198741

=119860119889

2times V119889+ 119860cm times Vcm (2a)

1198811198742

= minus119860119889

2times V119889+ 119860cm times Vcm (2b)

where V119889equiv Vin1 minus Vin2 Vcm equiv (Vin1 + Vin2)2 119860119889 is the

differential-mode voltage gain and 119860cm is the common-mode gain It is similar for the expression for 119881

1198742 The

common-mode rejection ratio (CMRR) is then defined as

CMRR equiv

10038161003816100381610038161003816100381610038161003816

119860119889

119860cm

10038161003816100381610038161003816100381610038161003816 (3)

A good amplifier is required to have a high 119860119889with a nearly

zero 119860cm Due to the variations in the fabrication processit is a big challenge to achieve a high CMRR with a lowinput offset In this study a balanced bias technique wasemployed to reduce the sensitivity to the process variationGood properties of this amplifier have been confirmed in thepostlayout simulation

22 Tristage Amplifier In this design three stages of ampli-fication were employed to achieve the required voltage gainand CMRR at the same time for weak biosignals Figure 3shows the detailed circuit in this design Table 1 gives thespecifications for this design

As seen in Figure 3 the first stage is composed of1198721ndash1198725

The second stage includes 1198726ndash11987212 These two stages can

be used as an operational transconductance amplifier (OTA)[6 7] or a folded cascade amplifier [8] The third stagecomprising 119872

13and 119872

14forms a type 119860 common-source

(CS) amplifier to drive loadsTransistors119872

1198781ndash1198721198786provide a bias current for the first-

stage amplifier The source of biasing for the second-stageamplifier comes from the balanced self-bias current mirror1198728ndash11987211 in Figure 3 In this part the biasing currents were

less sensitive to the level of the power supply In additionthe complementary arrangement of the loads at the first-stageand the second-stage amplifiers would reduce the variationof the amplification if there are changes in the NMOS andPMOSThe bias voltage for the third stage comes from119872

9in

the second stage Since the bias currents in1198729and119872

11were

constant the gate bias for11987213would be constant Therefore

the properties of the whole amplifier would be less affected bythe uncertainties in fabrication

For the design strategy the first stage was designed toachieve a high CMRR rather than a high voltage gain Theoverall voltage gain was boosted at the second and thethird stages Since this amplifier was designed for biomedicalapplications the voltage gain was tried to be as high aspossible with a moderate small bandwidth around 100Hz Atthe third stage a clamping circuit can keep dynamic trackingof the output gain such that the voltage gain would be lessaffected by variations in the transistors

In addition to the electrical considerations the layoutand circuit for the first and second stages were designed as

VLSI Design 3


119881DD

1198721 1198722

119881IN2

minus119881ss

119881IN1

119881out

11987214

119862119862

119877119885

11987213

11987212

11987210 11987211

1198726 1198727

1198728 1198729

11987241198601198723119860

11987241198611198723119861

11987211987821198721198781

1198721198783 1198721198784

11987211987861198721198785

119877119878

Self-bias

119881119861




≧ 20 kVV119860VO ≧ 80 dBPM ≧ 60∘





119868Supply le119875119863Spec

119881Supply= 0303mA (4)


1198983ge 10119866






119862119862ge 22 times

1198661198981

1198661198982

times 1198621198742

= 0221198621198742 (5)





1198636= 1198681198638

= 11986811986310

=

1198681198637

= 1198681198639

= 11986811986311


119898 and the


119868119863=1

2sdot 120583119899sdot 119862119900119909sdot (

119882

119871) sdot (119881OV)

2

sdot (1 + 120582119881DS) (6)

119892119898= (120583119899sdot 119862119900119909) sdot (

119882

119871) sdot (119881OV) sdot (1 + 120582119881DS)

= radic2120583119899sdot 119862119900119909sdot (

119882

119871) sdot 119868119863sdot (1 + 120582119881DS)

=2 times 119868119863

119881OV

(7)


1198983 is the

same as 11989211989813

of11987213 We chose 119866

1198983ge 10119866

1198982 that is 119866

1198983ge

590 120583AV and 11989211989813

= 1198661198983




13can be determined


1198781sim 1198721198786



4 VLSI Design




119891H3db (Hz) 630 631 794 631 82UGF (Hz) 141119864 + 06 147119864 + 06 146119864 + 06 144119864 + 06 152119864 + 06

CMRR (dB) 1364351 1362238 1367342 1365733 135778PD (120583W) 357 332 328 324 316119881os (120583V) 108 101 52 0033 208



minus radic119868REF1198701198785

(8)


of1198721198786 that is

(119882

119871)1198785

=1

4(119882

119871)1198786

(9)


119877119878=

1

119868REFradic119868REF1198701198785

(10)






Frequency (Hz)

0102030405060708090

100

0306090120150180

Phas

e (de

g)


Volta

ge g

ain

(dB)

minus30

minus60

minus90

minus1201119864minus01 1119864+01 1119864+03 1119864+05 1119864+07


SSSFTT

FSFF

FF

SS

180

150

120

Phas

e (de

g)

90

60

30



4 Conclusion


VLSI Design 5

0102030405060708090

100

Volta

ge g

ain

(dB)


minus10minus20

minus30

minus40minus50

SSSFTT

FSFF


40

60

80

100

120

140

CMRR

(dB)


SSSFTT

FSFF


Acknowledgments


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 3


119881DD

1198721 1198722

119881IN2

minus119881ss

119881IN1

119881out

11987214

119862119862

119877119885

11987213

11987212

11987210 11987211

1198726 1198727

1198728 1198729

11987241198601198723119860

11987241198611198723119861

11987211987821198721198781

1198721198783 1198721198784

11987211987861198721198785

119877119878

Self-bias

119881119861




≧ 20 kVV119860VO ≧ 80 dBPM ≧ 60∘





119868Supply le119875119863Spec

119881Supply= 0303mA (4)


1198983ge 10119866






119862119862ge 22 times

1198661198981

1198661198982

times 1198621198742

= 0221198621198742 (5)





1198636= 1198681198638

= 11986811986310

=

1198681198637

= 1198681198639

= 11986811986311


119898 and the


119868119863=1

2sdot 120583119899sdot 119862119900119909sdot (

119882

119871) sdot (119881OV)

2

sdot (1 + 120582119881DS) (6)

119892119898= (120583119899sdot 119862119900119909) sdot (

119882

119871) sdot (119881OV) sdot (1 + 120582119881DS)

= radic2120583119899sdot 119862119900119909sdot (

119882

119871) sdot 119868119863sdot (1 + 120582119881DS)

=2 times 119868119863

119881OV

(7)


1198983 is the

same as 11989211989813

of11987213 We chose 119866

1198983ge 10119866

1198982 that is 119866

1198983ge

590 120583AV and 11989211989813

= 1198661198983




13can be determined


1198781sim 1198721198786



4 VLSI Design




119891H3db (Hz) 630 631 794 631 82UGF (Hz) 141119864 + 06 147119864 + 06 146119864 + 06 144119864 + 06 152119864 + 06

CMRR (dB) 1364351 1362238 1367342 1365733 135778PD (120583W) 357 332 328 324 316119881os (120583V) 108 101 52 0033 208



minus radic119868REF1198701198785

(8)


of1198721198786 that is

(119882

119871)1198785

=1

4(119882

119871)1198786

(9)


119877119878=

1

119868REFradic119868REF1198701198785

(10)






Frequency (Hz)

0102030405060708090

100

0306090120150180

Phas

e (de

g)


Volta

ge g

ain

(dB)

minus30

minus60

minus90

minus1201119864minus01 1119864+01 1119864+03 1119864+05 1119864+07


SSSFTT

FSFF

FF

SS

180

150

120

Phas

e (de

g)

90

60

30



4 Conclusion


VLSI Design 5

0102030405060708090

100

Volta

ge g

ain

(dB)


minus10minus20

minus30

minus40minus50

SSSFTT

FSFF


40

60

80

100

120

140

CMRR

(dB)


SSSFTT

FSFF


Acknowledgments


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









4 VLSI Design




119891H3db (Hz) 630 631 794 631 82UGF (Hz) 141119864 + 06 147119864 + 06 146119864 + 06 144119864 + 06 152119864 + 06

CMRR (dB) 1364351 1362238 1367342 1365733 135778PD (120583W) 357 332 328 324 316119881os (120583V) 108 101 52 0033 208



minus radic119868REF1198701198785

(8)


of1198721198786 that is

(119882

119871)1198785

=1

4(119882

119871)1198786

(9)


119877119878=

1

119868REFradic119868REF1198701198785

(10)






Frequency (Hz)

0102030405060708090

100

0306090120150180

Phas

e (de

g)


Volta

ge g

ain

(dB)

minus30

minus60

minus90

minus1201119864minus01 1119864+01 1119864+03 1119864+05 1119864+07


SSSFTT

FSFF

FF

SS

180

150

120

Phas

e (de

g)

90

60

30



4 Conclusion


VLSI Design 5

0102030405060708090

100

Volta

ge g

ain

(dB)


minus10minus20

minus30

minus40minus50

SSSFTT

FSFF


40

60

80

100

120

140

CMRR

(dB)


SSSFTT

FSFF


Acknowledgments


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 5

0102030405060708090

100

Volta

ge g

ain

(dB)


minus10minus20

minus30

minus40minus50

SSSFTT

FSFF


40

60

80

100

120

140

CMRR

(dB)


SSSFTT

FSFF


Acknowledgments


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









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