Research Article An Improved Control Strategy for a Four-Leg Grid …downloads.hindawi.com/archive/2016/9123747.pdf · 2019. 7. 30. · Research Article An Improved Control Strategy

Research ArticleAn Improved Control Strategy for a Four-Leg Grid-FormingPower Converter under Unbalanced Load Conditions

Mohammad Reza Miveh,1 Mohd Fadli Rahmat,1 Mohd Wazir Mustafa,1

Ali Asghar Ghadimi,2 and Alireza Rezvani3

1Faculty of Electrical Engineering, Universiti Teknologi Malaysia (UTM), 81310 Skudai, Johor, Malaysia2Department of Electrical Engineering, Faculty of Engineering, Arak University, Arak, Iran3Young Researchers and Elite Club, Islamic Azad University, Saveh Branch, Saveh, Iran

Correspondence should be addressed to Mohammad Reza Miveh; [email protected]

Received 6 March 2016; Revised 14 June 2016; Accepted 30 June 2016

Academic Editor: Don Mahinda Vilathgamuwa

Copyright © 2016 Mohammad Reza Miveh et al.This is an open access article distributed under theCreativeCommonsAttributionLicense, which permits unrestricted use, distribution, and reproduction in anymedium, provided the originalwork is properly cited.

This paper proposes an improved multiloop control strategy for a three-phase four-leg voltage source inverter (VSI) operatingwith highly unbalanced loads in an autonomous distribution network. The main objective is to balance the output voltages of thefour-leg inverter under unbalanced load conditions. The proposed control strategy consists of a proportional-integral (PI) voltagecontroller and a proportional current loop in each phase.The voltage controller and the current control loop are, respectively, used toregulate the instantaneous output voltage and generate the pulse widthmodulation (PWM) voltage commandwith zero steady-statetracking error and fast transient response. A voltage decoupling feedforward path is also used to enhance the system robustness.Since the outer voltage loop operates in the synchronous reference frame, tuning and stability analysis of the PI controller is farfrom being straightforward. In order to cope with this challenge, the stationary reference frame equivalent of the voltage controllerin the rotating frame is derived. Subsequently, a systematic design based on a frequency response approach is provided. Simulationresults are also carried out using the DIgSILENT PowerFactory software to verify the effectiveness of the suggested control strategy.

1. Introduction

Poor operational efficiency, gradual depletion of fossil-fuelresources, and environmental pollution are the main prob-lems associated with traditional power systems [1–3]. Theseserious issues have led to a considerable attempt to generatepower using renewable energy sources (RES) at the lowvoltage level [4, 5]. For applications in renewable energy anddistributed generation (DG), there is a need to use powerelectronic inverters to convertDCpower into a controlledACpower [6]. Conventionally, the inverters used in distributionnetworks behave like voltage sources when they operateindependently [7]. On the other hand, they behave as currentsources, when they are directly connected to the utilitygrid [8]. The change of operational mode from autonomousmode to grid-connected mode or vice versa may cause thechange of their controllers’ scheme. The most importantdistinguishing feature of a voltage source inverter (VSI) is that

there is no need to change its controller, when the operationmode is changed [7]. Therefore, it is commonly used indistribution networks, due to its proper capability to operatein both grid-connected and islanded modes [8]. Here, theautonomous operation of VSIs is considered. However, toachieve a stable and secure operation, a number of technicaland regulatory issues have to be resolved before VSIs canbecome commonplace in distribution networks.

Since most traditional six-switch inverters are designedfor three-phase three-wire systems, their controllers arequite suitable for balanced three-phase loads. In many lowvoltage distribution systems, the loads can be a mixture ofsingle-phase and three-phase ones, resulting in unbalancedvoltage problems [9]. Unbalance voltage conditions can leadto adverse effects on equipment and the electric distribu-tion system [10]. Malfunction of protection devices, powerelectronic converters, and adjustable speed drives are themain challenges caused by unbalanced loads in distribution

Hindawi Publishing CorporationAdvances in Power ElectronicsVolume 2016, Article ID 9123747, 14 pageshttp://dx.doi.org/10.1155/2016/9123747

2 Advances in Power Electronics

networks [9, 10]. To cope with this challenge, a neutral lineis needed to provide a current path for unbalanced loads ina three-phase four-wire system. Hence, it is important to usea proper inverter topology to balance the output voltages ofcritical loads.

So far, various VSI topologies are introduced for properoperation in a three-phase four-wire distribution network.The use of a three-leg inverter topology in three-phase four-wire systems with a costly and bulky Δ-Y transformer ispopular due to trapping zero sequence currents in the Δwinding. In this topology, the control of the inverter is onlyresponsible for compensating the voltage drops caused bypositive and negative sequence currents on the output filter ofthe inverter in the Δ side of the transformer. Nonetheless, thezero sequence currents may cause voltage drops in the Y-sideof the transformer that the three-leg inverter cannot handlethis challenge [11]. The three-leg inverter with a split DC-link capacitor has also been extensively used in the literaturebecause of its simple structure [12, 13]. However, it needsan expensive and a large capacitor to achieve equal voltagesharing between the split capacitors. Moreover, capacitorvoltage balancing is another challenge with this topology[14]. The three-phase four-leg VSI plays an important rolein the proper operation of three-phase four-wire distributionnetworks because of its superior performance characteristicsin handling unbalanced conditions. The provision of thefourth leg in four-leg VSIs can result in controlling the phasevoltages independently. Indeed, the independently controlledphase voltages allow four-leg inverters to provide balancedoutput voltages even under unbalance load conditions.

To date, various control methods have been proposedin the literature to balance the output voltage of a three-phase four-leg VSI in autonomous mode. The proportional-resonant (PR) controller in the stationary reference framehas been commonly used for balancing the output voltageof the four-leg inverter due to its superior performance ineliminating the steady-state error, while regulating sinusoidalsignals [17]. However, it is sensitive to frequency variationsand the phase shift of current sensors. The proportional-integral (PI) controller in the 𝑑𝑞 frame is also widely usedand works well with pure DC signals [15, 16, 18, 19]. Thisapproach operates based on the extraction of the symmetricalcomponents of the unbalanced signals in the 𝑑𝑞 frame.Nonetheless, the use of filters to obtain the symmetricalcomponents of the unbalanced signals leads to low crossoverfrequency, which may cause a slow dynamic response. Inanother approach, a combination of the 𝑑𝑞 frame and thestationary reference frame is utilized to compensate distort-ing effects of nonlinear and unbalanced loads in a stand-alone distribution system [20]. The integral controllers inthe 𝑑𝑞 frame are responsible for compensating the positiveand negative sequence distortions, while a zero-dampingbandpass filter is employed in the stationary reference frameto compensate the zero sequence distortion. However, theeffectiveness of the proposed scheme is only presented for thesteady-state condition, and the zero steady-state error for thezero sequence component is not truly achieved.

In this paper, an improved per-phase control scheme fora three-phase four-leg VSI operating with highly unbalanced

loads in an autonomous distribution network is presented.Themain objective is to effectively balance the output voltagesof the four-leg inverter under extremely unbalanced loadconditions.The proposed control strategy consists of an outervoltage loop and an inner current loop in each phase. Theouter voltage controller and the inner capacitor loop are,respectively, utilized to regulate the instantaneous outputvoltage and currents. A voltage decoupling feedforward isalso used to improve the system robustness. The mainadvantages of the method are the simplicity, low steady-statevoltage tracking error, and fast transient response.

The rest of this paper is organized as follows. Section 2describes the model of the four-leg inverter. Section 3presents the proposed per-phase multiloop control of thefour-leg inverter in the 𝑑𝑞 frame. The stationary referenceframe equivalent model of the PI controller in the 𝑑𝑞 syn-chronous reference frame is derived in Section 4. The designof the current loop and the voltage control are presented inSections 5 and 6, respectively. The carrier-based pulse widthmodulation (PWM)method for the generation of the inverteroutput voltages is also explained in Section 7. Simulationresults are provided in Section 8. Finally, the conclusion givesa brief summary and critique of the findings.

2. System Modeling

Figure 1 shows the power stage of a four-leg grid-forminginverter and its LC output filter connected to unbalancedloads in an autonomous three-phase four-wire distributionnetwork [21]. Since the LC filter yields better performancethan the L filter and is less complicated than the LCL filter,the LC filter represents a suitable compromise for the systemintended for use in this paper. The LC filter parameters arechosen such that the unwanted components in the four-leg inverter output voltage are attenuated effectively andthe inverter current ripple is reduced admissibly using themethod presented in [17]. The loads can be placed either inline-to-line or line-to-neutral connection. It is worth notingthat the neutral line of the autonomous four-wire system isprovided by connecting the fourth legs of the four-leg inverterto the neutral point of loads. The additional leg regulates theload zero sequence voltage [22]. To minimize the switchingfrequency ripple imposed on the neutral current inverter (𝐼

𝑛),

a neutral inductor (𝐿𝑛) is also used.

The carrier-based pulse width modulation (PWM) tech-nique is selected to produce three output voltages indepen-dently because of its simplicity and ease of implementation[23]. Since the four-leg inverter is assumed to be powered byan ideal constant DC voltage source, no controller is neededto regulate the DC-link voltage, and it is possible to considerthat theDC-link voltage is constant throughout this study [5].Table 1 presents the parameters of the four-leg VSI.

To describe the behavior of the circuit depicted inFigure 1, the following quantities for voltages and currents canbe defined:

𝑉pwm = [𝑉𝐴𝑓 𝑉𝐵𝑓 𝑉𝐶𝑓]𝑇

, (1)

Advances in Power Electronics 3

f AB

C

Unb

alan

ced

load

s

Vdc

Sf1

Sf2

ILA

ILB

ILC

VA

VB

VG

Cf

RfLf

Rn

RA

RB

RC

Ln

In

Iload-B

Iload-A

Iload-C

SA1 SB1

SA2 SB2

SC1

SC2

VC

IcA

Figure 1: Power stage of a three-phase four-leg VSI.

Table 1: System parameters.

Parameter Description Value𝑓𝑠

Switching frequency 5 kHz𝑤𝑓

Fundamental frequency 2𝜋60 rad/s𝐿𝑓and 𝐿

𝑛Filter inductance 0.1mH

𝐶𝑓

Filter capacitance 300𝜇F𝑅𝑓and 𝑅

𝑛Resistor of the filter inductance 10mΩ

𝑉dc DC-link voltage 300V

where 𝑉pwm is the vector of three-phase inverter output line-to-neutral PWM voltages.

𝐼inv = [𝐼𝑙𝐴 𝐼𝑙𝐵𝐼𝑙𝐶]𝑇

,

𝐼load = [𝐼load-𝐴 𝐼load-𝐵 𝐼load-𝐶]𝑇

,

𝑉load = [𝑉𝐴 𝑉𝐵𝑉𝐶]𝑇

.

(2)

By applying Kirchhoff voltage and current laws to the powerstage of the three-phase four-leg VSI, the following equationscan be obtained [21].

𝑉load = 𝑅𝑓𝐼inv + 𝐿𝑓𝑑𝐼inv𝑑𝑡

+ 𝑉pwm − 𝑅𝑛𝐼𝑛 − 𝐿𝑛𝑑𝐼𝑛

𝑑𝑡.

𝐼inv = 𝐼load + 𝐶𝑓𝑑𝑉load𝑑𝑡

.

(3)

The control system tuning and stability analysis of the four-leg inverter can be performed on a per-phase basis [7].Hence, the power stage of the four-leg inverter is modeledaccording to the principles of the per-phase basis so thatonly a single-phase representation of the inverter is used forthe analysis and design [9]. Figure 2 illustrates the per-phaserepresentation of the four-leg inverter for one phase to neutralconnection [2, 9]. As can be seen, the fundamental compo-nent of the switched voltage of each phase and the connectedload to that phase are modeled as an ideal controlled voltagesource (𝑢𝑉dc, which 𝑢 is the control variable) and a currentsource (𝐼

𝑜), respectively. In this figure, 𝐼

𝐿and 𝑉

𝑐are also

L

C

R

uVdc

Io+

−

+

−

IL

Vc

Figure 2: Basic per-phase representation of the four-leg inverter ineach phase.

v

iomVdc 1

CS

1

Ls + rIL

Figure 3:Average switchingmodel of the four-legVSI in each phase.

the respective phase inductor current and capacitor voltage,respectively.

For implementation of a single-phase system in thesynchronous reference frame, it is necessary to generatea pseudo-two-phase system [2]. In this two-phase system,one component is obtained from the original single-phasesystem (𝛼) and an orthogonal signal (𝛽) must be createdfrom the original single-phase signal. Based on Figure 2, thedifferential equations representing the model of the single-phase system in the 𝛼𝛽 frame can be written as

𝐿

𝑑𝑖𝑙,𝛼𝛽

𝑑𝑡= 𝑢𝑉dc,𝛼𝛽 − V

𝑐,𝛼𝛽− 𝑅𝑖𝑙,𝛼𝛽,

𝐶

𝑑V𝑐,𝛼𝛽

𝑑𝑡= 𝑖𝑙,𝛼𝛽

− 𝑖𝑜,𝛼𝛽.

(4)

The average switchingmodel of the four-legVSI in each phaseis depicted in Figure 3. This is obtained by assuming that theswitching frequency is much higher than the fundamentalfrequency. As can be seen from Figure 3, �� (the functionof modulating signal) is used instead of the control variable,


which represents the average value of 𝑢 over one cycle ofswitching frequency.

3. Per-Phase Control Scheme

The independently controlled phase voltages allow the four-leg inverter to provide balanced output voltages under highlyunbalanced load conditions. The per-phase control schemeis used in this paper due to its superior performance inproviding balanced output voltages under extremely unbal-anced load conditions. In this control scheme, three legs areswitched independently from each other so that voltages canbe regulated in their output filter capacitors. The fourth legof the inverter provides a zero voltage at the neutral point ofthe inverter using the proposed controller and carrier-basedPWM technique [23].

The implementation of the independent control of thesingle-phase system in the 𝑑𝑞 frame needs to create asecondary orthogonal signal from each original phase signalthrough a complex orthogonal signal generation (OSG) tech-nique [5]. Several attempts have been made in the literatureto generate an orthogonal signal from an original single-phase signal such as second-order generalized integrator,Kalman filter, and first-order all-pass filter (APF) methods[24–27]. In this paper, the orthogonal signal is generatedbased on the reference values of the 𝑑- and 𝑞-axes [28, 29].The proposed method exhibits improved steady-state anddynamic performances in comparison with the invertersequipped with the conventional orthogonal signal generationtechniques.

The structure of the suggested control scheme for phase“𝐴” is presented in Figure 4. The control system consistsof an inner current loop and an outer voltage loop in eachphase. The main function of the external voltage loop is tocontrol the instantaneous output voltages within the standardlimits. The inner current loop is also adopted to generatethe switching states of the PWM modulator. In addition, itimproves the transient and steady-state performances of theproposed control scheme. A voltage decoupling feedforward(V∗) is also used to enhance the control system robustness[2]. It is noteworthy that the capacitor current is employedas the feedback signal in the inner loop due to its superiorperformance in rejecting disturbances rather than the induc-tor current. Furthermore, the use of the capacitor currentis much easier and more cost-effective than the inductorcurrent. According to the basic principles of control theory ofcascaded control, these loops can be designed independentlyas long as the dynamics of the voltage loop is designed to beslower than the internal current controller [2].

The voltage loop operates in the synchronous referenceframe, whereas the inner current loop functions in thestationary coordinate system. In the outer loop, 𝑉

𝑐𝐴is the

𝐴-phase output voltage of the filter capacitor to the neutralline. 𝑉

𝛼and 𝑉

𝛽are the real and the orthogonal components

of 𝑉𝑐𝐴

in the stationary reference frame, respectively. The𝑑𝑞 components of the 𝐴-phase output voltage of the filtercapacitor can be generated by applying the Park transforma-tion, after creating the pseudo-two-phase system. A simple

phase locked loop (PLL) is used to obtain the sin 𝜃 andcos 𝜃 terms [30]. The PI controllers are utilized in the voltageloop to regulate the instantaneous output voltages in the𝑑𝑞 frame. The reference voltages for the three phases haveequal amplitudes but are separated from the other voltagesby a phase angle of 120∘. The 𝑞-component of the referencevoltages in each phase (𝑉∗

𝑞) is set at 0, whereas the 𝑑-

component (𝑉∗𝑑) is set at the peak value of the reference phase

voltage.The reference signal of the internal current loop is

provided by employing the inverse Park transformation tothe output signals of the output voltage controller. As shownin Figure 4, only the 𝛼-axis quantity generated by the outervoltage loop is fed to the internal current controller forcompensation. It is the real signal of the two-phase system.Afterwards, the inner loop generates the switching states ofthe PWM using a simple proportional controller. The designapproach of the proposed control strategy is discussed indetail in the following sections.

4. Stationary Reference Frame Representationof the PI Controller in the 𝑑𝑞 Frame

In the proposed control strategy, the PI controller regulatesthe instantaneous output voltages of the inverter in the syn-chronous reference frame, whereas the simple proportionalcontroller regulates the current in the stationary referenceframe. Hence, the stability analysis and design of the wholeclosed-loop system is not straightforward. To successfullycope with this challenge, the stationary frame equivalentmodel of the PI controller is derived in this section [26,27]. The equivalent model of the used PI controller in thestationary reference frame is depicted in Figure 5. In thisblock, 𝑖∗

𝑐,𝛼𝛽stands for outputs, whereas 𝐸

𝛼𝛽stands for inputs.

The𝐺𝑃is the transfer function of the proportional gain (𝐾

𝑃),

and 𝐺𝐼is the transfer function of the integral controller (𝐾

𝐼).

The equivalent model of the PI controller depicted inFigure 5 can be considered as a two-input-two-output system.It can be explained in the time domain as

[

𝑖∗

𝑐,𝛼(𝑡)

𝑖∗

𝑐,𝛽(𝑡)]

= [

[

cos (𝑤𝑓𝑡) − sin (𝑤

𝑓𝑡)

sin (𝑤𝑓𝑡) cos (𝑤

𝑓𝑡)

]

]

{

{

{

[

𝐺𝑃𝐼(𝑡) 0

0 𝐺𝑃𝐼(𝑡)]

∗{

{

{

[

[

cos (𝑤𝑓𝑡) sin (𝑤

𝑓𝑡)

− sin (𝑤𝑓𝑡) cos (𝑤

𝑓𝑡)

]

]

[

𝐸𝛼(𝑡)

𝐸𝛽(𝑡)]}

}

}

}

}

}

,

(5)

where ∗ is the convolution operator.The Laplace transformation is used for both sides of (5).

After some mathematical manipulation it can be written as


a

dq

+

+

PI

PIdq

+P+

+

Outer voltage controller

Inner currentcontroller

i∗c,𝛽

i∗c,𝛼 = i∗c

cos 𝜃 sin 𝜃

cos 𝜃

sin 𝜃

𝛼𝛽

𝛼𝛽

𝛼𝛽

i∗c,q

i∗c,d

Eq

Ed

Vq Vd

V𝛽V𝛼

V∗d

V∗q

∗ = ∗𝛼 = ∗d cos (wft) − ∗q sin (wft)

−

−

−

iCaVCa

VAf

Figure 4: Per-phase cascaded controller for the four-leg inverter in phase “𝐴.”

[

𝑖∗

𝑐,𝛼(𝑠)

𝑖∗

𝑐,𝛽(𝑠)] =

1

2

[

[

𝐺𝑃𝐼(𝑠 + 𝑗𝑤

𝑓) + 𝐺𝑃𝐼(𝑠 − 𝑗𝑤

𝑓) −𝑗𝐺

𝑃𝐼(𝑠 + 𝑗𝑤

𝑓) + 𝑗𝐺

𝑃𝐼(𝑠 − 𝑗𝑤

𝑓)

+𝑗𝐺𝑃𝐼(𝑠 + 𝑗𝑤

𝑓) − 𝑗𝐺

𝑃𝐼(𝑠 − 𝑗𝑤

𝑓) 𝐺

𝑃𝐼(𝑠 + 𝑗𝑤

𝑓) + 𝐺𝑃𝐼(𝑠 − 𝑗𝑤

𝑓)

]

]

[

𝐸𝛼(𝑠)

𝐸𝛽(𝑠)] . (6)

In (6), 𝐺𝑃𝐼

can be replaced by 𝐾𝑃+ 𝐾𝐼/𝑠. After performing

some mathematical manipulation this yields

[

𝑖∗

𝑐,𝛼(𝑠)

𝑖∗

𝑐,𝛽(𝑠)]

=

[[[[

[

𝐾𝑃+

𝐾𝐼𝑠

𝑠2 + 𝑤2

𝑓

−

𝐾𝐼𝑤𝑓

𝑠2 + 𝑤2

𝑓

𝐾𝐼𝑤𝑓

𝑠2 + 𝑤2

𝑓

𝐾𝑃+

𝐾𝐼𝑠

𝑠2 + 𝑤2

𝑓

]]]]

]

[

𝐸𝛼(𝑠)

𝐸𝛽(𝑠)] .

(7)

Lastly, the transfer function of the real reference current 𝑖∗𝑐,𝛼

tothe real voltage error 𝐸

𝛼by replacing 𝐸

𝛽(𝑠) = ((𝑤

𝑓−𝑠)/(𝑤

𝑓+

𝑠))𝐸𝛼(𝑠) can be obtained as

𝑖∗

𝑐,𝛼(𝑠) =

𝑎3𝑠3

+ 𝑎2𝑠2

+ 𝑎1𝑠 + 𝑎0

𝑠3 + 𝑤𝑓𝑠2 + 𝑤

2

𝑓𝑠 + 𝑤3

𝑓

𝐸𝛼(𝑠) = 𝐻 (𝑠) 𝐸

𝛼(𝑠) , (8)

where 𝑎3= 𝐾𝑃, 𝑎2= 𝐾𝑃𝑤𝑓+ 𝐾𝐼, 𝑎1= 𝐾𝑃𝑤2

𝑓+ 2𝑤𝑓𝐾𝐼, and

𝑎0= 𝐾𝑃𝑤3

𝑓− 𝐾𝐼𝑤2

𝑓.

𝐻(𝑠) is the stationary reference frame representation ofthe PI controller in the 𝑑𝑞 frame. Figure 6 shows the Bodeplot of transfer function 𝐻(𝑠) for a typical controller in𝑤𝑓= 2𝜋60 rad/s. From this figure, it can be concluded

that for fundamental frequency, the phase and amplitudecharacteristics of the PI controller in the 𝑑𝑞 frame areequivalent to the PR controller in the stationary referenceframe. The use of this technique considerably simplifies thestability analysis and control parameter design.

5. Design of the Current Controller

The block diagram of the inner current loop is presented inFigure 7. A simple proportional controller is used for inject-ing clean current to the PWM[28, 29]. In spite of the complexstructure of the PI compensator, the proportional controllerprovides more simplicity for the stability analysis and controlparameter design. Moreover, it can prevent unwanted phasedelays from the reference signal [5]. However, the use ofthe proportional controller in the internal loop requires ahigh proportional gain to eliminate the steady-state error. Tosuccessfully overcome this challenge, a feedforward path isadopted to simultaneously improve the performance of theinner loop and reduce the required control effort.

Since it can be assumed that 𝑍 is the load impedance and𝑖𝑜= V/𝑍, the closed-loop transfer function of the inner loop

can be written as

𝐺 (𝑠) =𝑖𝑐

𝑖∗𝑐

=𝐶𝑍𝐾𝑠

𝐿𝐶𝑍𝑠2 + (𝐶𝑍 (𝑟 + 𝐾) + 𝐿) 𝑠 + (𝑟 + 𝑍). (9)

It is obvious that the performance of the internal controllersignificantly depends on the load impedance and controllerparameters. The Bode plot of the corresponding transferfunction with a typical value for the proportional compen-sator in different loading conditions is shown in Figure 8.

It can be seen that the minimum bandwidth can beachieved at the nominal load. Hence, the proportional gain ofthe current controller must be tuned under nominal loadingconditions to ensure the expected bandwidth in the innerloop. The proportional gain value of the current loop can


dqdq +

E𝛼𝛽 EdqGP

GI

i∗c,dqi∗c,𝛼𝛽

𝛼𝛽𝛼𝛽

Figure 5: Equivalent control block.

101 102 103100

Frequency (Hz)

101 102 103100

Frequency (Hz)

050

100150

Mag

nitu

de (d

B)

−90−45

04590

Phas

e (de

g)

Figure 6: Bode plot of transfer function𝐻(𝑠) for𝐾𝑃= 0.1 and𝐾

𝐼=

10.

be calculated using |𝐺(𝑗𝑤𝑏𝑖)|2

= 1/2 and assuming that𝑤𝑏𝑖is the required bandwidth of the inner loop. Hence, the

proportional gain can be obtained as

𝐾

=

𝐿 + 𝑟𝐶𝑍 + √2𝑟𝐶𝑍 (𝑟𝐶𝑍 + 𝐿) + 𝐿2 (2 + 𝐶2𝑍2𝑤

2

𝑏𝑖)

𝐶𝑍.

(10)

Basically, the required bandwidthmust be selected lower thanthe switching frequency to put a limit on the inner loop

response to the switching noise. Hence, it is chosen as one-fourth of the switching frequency. From (10) and with 𝑤

𝑏𝑖=

2𝜋(0.25 × (𝑓𝑠= 5 kHz)) kHz ≅ 8 krad/s, the proportional

gain of the inner current loop is set on 1.

6. Design of the Voltage Controller

The next step after determining the gain of the inner loopis to design the outer voltage loop. The block diagram ofthe cascaded controller and its simplified block diagram areillustrated in Figure 9. In this figure, the internal controllerand the external loop are, respectively, replaced by 𝐺(𝑠) and𝐻(𝑠). Moreover, V∗ = V∗

𝛼= V∗𝑑cos(𝑤

𝑓𝑡) − V∗

𝑞sin(𝑤𝑓𝑡) is

the voltage decoupling feedforward to enhance the systemrobustness.TheBode plots of the open-loop transfer functionof the simplified block diagram for 𝐾 = 1, 𝐾

𝑃= 0.1, and

𝐾𝐼= 0 under different loading conditions are depicted in

Figure 10. The effect of various loading conditions on theouter loop performance can be investigated from this figure.It can be observed that the stability of the closed-loop systemand the phase margin under light-load or no-load conditionsare moderately decreased.

To guarantee the proper performance of the inverter inall load conditions, the PI regulator is designed under light-load conditions. Since, under light-load conditions, the loadimpedance tends to infinity (𝑍 → ∞), the transfer functionof (9) can be approximated as

𝑖𝑐

𝑖∗𝑐

≅𝐾

𝐿𝑠 + 𝑟 + 𝐾. (11)

Additionally, by assuming that the inverter operates under thelight-load condition, the open-loop and closed-loop transferfunctions of the control system can be written as (12) and (13),respectively:

VV∗ − V

=

𝐾 (𝑎3𝑠3

+ 𝑎2𝑠2

+ 𝑎1𝑠 + 𝑎0)

𝐿𝐶𝑠5 + 𝑏𝑠4

+ 𝑏𝑤𝑓𝑠3

+ 𝑏𝑤2

𝑓𝑠2

+ (𝑟 + 𝐾)𝐶𝑤3

𝑓𝑠

. (12)

VV∗=

𝐾 (𝑎3𝑠3

+ 𝑎2𝑠2

+ 𝑎1𝑠 + 𝑎0)

𝐿𝐶𝑠5 + 𝑏𝑠4

+ (𝑏𝑤𝑓+ 𝐾𝑎3) 𝑠3 + (𝑏𝑤

2

𝑓+ 𝐾𝑎2) 𝑠2 + ((𝑟 + 𝐾)𝐶𝑤

3

𝑓+ 𝐾𝑎1) 𝑠 + 𝐾𝑎

0

. (13)

In the PI controller, the proportional gain and the integralparameter should be accurately selected to ensure a fasttransient response and zero tracking steady-state error. Theselection of the proportional gain is a compromise betweenthe stability of the controller and the desired voltage regula-tion bandwidth. In this study, the proportional gain is chosenso that the required bandwidth (𝑤

𝑏V) can be achieved for(13). On the other hand, the integral gain is chosen so thatthe minimum steady-state error for the outer loop can beensured. In this case, the selection of the proportional param-eter is performed based on this assumption that the dynamic

of the voltage loop is unaffected by the integral gain. In otherwords, the proportional gain is responsible for the transientresponse, whereas the steady-state response is determined bythe integral parameter at the fundamental frequency. Hence,it can be assumed that𝐾

𝐼= 0, during tuning the proportional

parameter. Based on this assumption, the transfer function ofthe closed-loop system in the frequency domain and underlight-load condition can be rewritten as

VV∗=

𝐾𝑃𝐾

𝐾𝑃𝐾 − 𝐿𝐶𝑤2 + 𝑗 (𝑟 + 𝐾)𝐶𝑤

. (14)


i∗cic

il

ic

io

1/Vdc

m

Vdck+−

++++ −

−

1

Ls + r1

CS

∗

Figure 7: Block diagram of inner current control loop.

−60−50−40−30−20−10

0

Mag

nitu

de (d

B)

−90−45

04590

Phas

e (de

g)

103101 102 104 10510010−1

Frequency (Hz)

103101 102 104 10510010−1

Frequency (Hz)

Figure 8: Bode plots of 𝐺(𝑠) for 𝐾 = 1, under (solid line) nominalload, (dashed line) one-fifth of nominal load, and (dotted line) one-tenth of nominal load.

Assuming that the expected bandwidth is 𝑤𝑏V, 𝐾𝑃 can be

obtained as

𝐾𝑃=

𝐶𝑤𝑏V [√2𝐿

2𝑤2

𝑏V + 𝐾2 − 𝐿𝑤

𝑏V]

𝐾.

(15)

In practice, in order to achieve a satisfactory tradeoff betweenthe disturbance rejection and the proper transient response ininverter applications, the system bandwidth must be selectedbetween ten times of the fundamental frequency and one-tenth of the switching frequency. In this study, it is chosenas 550Hz, which is a value between 600Hz and 500Hz.Consequently, the system bandwidth and the proportionalgain can be determined as 𝑤

𝑏V = 2𝜋 × 550Hz ≃ 3 krad/sand 0.15, respectively. The next step is to determine theintegrator gain of the PI controller. The stability analysis isused to achieve an accurate value for integral parameter.The use of the Routh-Hurwitz criterion can be satisfied bythe integrator objectives in the voltage loop. The systemcharacteristic polynomial can be written as

𝐿𝐶𝑠5

+ 𝑏𝑠4

+ (𝑏𝑤𝑓+ 𝐾𝑎3) 𝑠3

+ (𝑏𝑤2

𝑓+ 𝐾𝑎2) 𝑠2

+ ((𝑟 + 𝐾)𝐶𝑤3

𝑓+ 𝐾𝑎1) 𝑠 + 𝐾𝑎

0= 0.

(16)

By applying the Routh-Hurwitz criterion, the system stabilityanalysis can discriminate as

𝐾 > 0,

𝐾𝑃> 0,

𝐾𝐼< 𝐾𝑃× 𝑤𝑓.

(17)

The proportional gain of the PI controller has been alreadydetermined.Therefore, the value of𝐾

𝑃×𝑤𝑓can be calculated

equal to 55. To evaluate the performance of the system sta-bility, the open-loop Bode plots of𝐻(𝑠)𝐺(𝑠)/𝐶𝑠 for differentvalues of 𝐾

𝐼are depicted in Figure 11. What is interesting in

this figure is that 𝐾𝐼has no effect on the phase margin. It is

noteworthy that an infinitive magnitude at the fundamentalfrequency provides a zero steady-state error. However, it hasa considerable influence on the operation of the controller inthe area near the fundamental frequency. Additionally, basedon the stationary reference frame equivalent of the integralterm in Figure 6, which affects the system performancein vicinity of the fundamental frequency, the integral gainshould beminimized to ensure that the integral termdoes notaffect other frequencies. Indeed, this gain should be selectedenough lower than the stability criterion in applicationswhere variations of the fundamental frequency are expected,which may happen in the case of autonomous grids. Hence,the choice of 𝐾

𝐼should be done based on a tradeoff between

eliminating the steady-state error and not affecting otherfrequencies. Based on this compromise and the Routh-Hurwitz criterion,𝐾

𝐼is chosen to be 42.

7. The Carrier-Based PWM Method for theGeneration of the Inverter Output Voltage

Kim and Sul [23] propose a voltage modulation technique onthe basis of a triangular carrier wave for three-phase four-leg VSIs to make three lines to neutral output voltages usingan additional leg. In this modulation method, the conceptof offset voltage is implemented using a single carrier. Themethod has a strong performance and can be implementedeasily. Therefore, it is used in this study to generate theinverter output voltage.

The block diagram of the used PWM scheme is shown inFigure 12. In this figure, 𝑉

𝐴𝑓, 𝑉𝐵𝑓, 𝑉𝐶𝑓

are the “𝛼” componentgenerated by the proposed cascaded controller. 𝑁 stands forthe fictive midpoint of the DC link, and 𝑉

𝑓𝑁is the offset

voltage, which is calculated quite different from three-phasethree-leg VSI using (18). The output voltages of the four-leg


i∗c ic

ilic

io

1/Vdc

m

VdckE

1

CS+−

++++ −

−

+−

H(s)

∗

∗ 1

Ls + r

(a)

vv

E+G(s)

i∗c ic−

H(s)

∗1

CS

(b)

Figure 9: (a) Block diagram of the suggested control scheme. (b) Its simplified representation.

10010−1 102101

Frequency (Hz)

10010−1 102101

Frequency (Hz)

−100

1020304050

Mag

nitu

de (d

B)

−135

−90

−45

0

Phas

e (de

g)

PM = 86 degPM = 90 degPM = 93 deg

Figure 10: Bode plots of 𝐻(𝑠)𝐺(𝑠)/𝐶𝑠, for 𝐾 = 1, 𝐾𝑃= 0.1, and

𝐾𝐼= 0, under (solid line) nominal load, (dashed line) one-fifth of

nominal load, and (dotted line) one-tenth of nominal load.

−405−315−225−135−45

Phas

e (de

g)

020406080

Mag

nitu

de (d

B)

102 103 104101

Frequency (Hz)

102 103 104101

Frequency (Hz)

Figure 11: Open-loop Bode plots of 𝐻(𝑠)𝐺(𝑠)/𝐶𝑠, for 𝐾 = 1, 𝐾𝑃=

0.15, and 𝐾𝐼= 10 (solid line), for 𝐾 = 1, 𝐾

𝑃= 0.15, and 𝐾

𝐼= 20

(dashed line).

Offsetvoltage

calculation

++

++

++

+

+

+

+

a+

b+

c+

f+

Carrier

VfN

Vdc/2

−Vdc/2

−

−

−

−

VAf

VCf

VBf

VAN

VBN

VCN

Figure 12: Block diagram of the used PWM scheme for the four-leginverter.

inverter (𝑉𝐴𝑁, 𝑉𝐵𝑁, 𝑉𝐶𝑁

) and pertaining constraint can beobtained by (19) and (20). Moreover, the ON-times of theupper switch of respective legs can be obtained as (21):

𝑉𝑓𝑁= mid(−

𝑉max2, −𝑉min2, −𝑉max + 𝑉min

2) . (18)

𝑉𝐴𝑁

= 𝑉𝐴𝑓+ 𝑉𝑓𝑁,

𝑉𝐵𝑁= 𝑉𝐵𝑓+ 𝑉𝑓𝑁,

𝑉𝐶𝑁

= 𝑉𝐶𝑓+ 𝑉𝑓𝑁,

(19)

−𝑉dc ≤ 𝑉𝐴𝑓, 𝑉𝐵𝑓, 𝑉𝐶𝑓 ≤ 𝑉dc, (20)

𝑇𝐴=𝑇𝑠

2+𝑉𝐴𝑁

𝑉dc𝑇𝑠,

𝑇𝐵=𝑇𝑠

2+𝑉𝐵𝑁

𝑉dc𝑇𝑠,

𝑇𝐶=𝑇𝑠

2+𝑉𝐶𝑁

𝑉dc𝑇𝑠,

𝑇𝐹=𝑇𝑠

2+

𝑉𝑓𝑁

𝑉dc𝑇𝑠,

(21)

where 𝑇𝑠is the period of the triangular carrier.


Table 2: System parameters for the simulation study.

Load voltage 155.56V/phase (peak)Frequency 60HzCurrent controller parameter 𝐾 = 1

PI voltage controller parameters 𝐾𝑃= 0.15, 𝐾

𝐼= 42

Balanced load 𝑅𝐴= 𝑅𝐵= 𝑅𝐶= 8Ω

Unbalanced loads(1) 𝑅𝐴= 10Ω, 𝑅

𝐵= 7Ω, 𝑅

𝐶= 8Ω

(2) 𝑅𝐴= 𝑅𝐵= 8Ω, 𝑅

𝐶=∞

(3) 𝑅𝐵= 8Ω, 𝑅

𝐴= 𝑅𝐶=∞

−1.5000−0.9000−0.3000

0.30000.90001.5000

Volta

ge re

fere

nces

(p.u

.)

40.00 50.00 60.00 70.00 80.0030.00Time (ms)

Gate drive: VfN

Gate drive: VAN

Gate drive: VBN

Gate drive: VCN

Figure 13:Three-phase pole voltage references and the offset voltagereference.

8. Simulation Results

To validate the performance of the proposed control strategy,the test system of Figure 1 has been simulated in the DIgSI-LENT PowerFactory software. The four-leg VSI is equippedwith the suggested control scheme. The types of loads areresistive, and other parameters of the system are presented inTable 2. Different simulation case studies under various loadscenarios are carried out to determinate the effectiveness ofboth the steady-state and the transient performances of thesuggested control scheme.

8.1. Steady-State Performance. The evaluation of the steady-state behavior of the proposed control strategy is made fora three-phase balanced load (𝑅

𝐴= 𝑅𝐵= 𝑅𝐶= 8Ω) and

three various unbalanced load cases, including (𝑅𝐴= 10Ω,

𝑅𝐵= 7Ω, 𝑅

𝐶= 8Ω), (𝑅

𝐴= 𝑅𝐵= 8Ω, 𝑅

𝐶= ∞), and

(𝑅𝐵= 8Ω, 𝑅

𝐴= 𝑅𝐶= ∞).

8.1.1. With a Three-Phase Balanced Load. The purpose ofthis part is to investigate the steady-state performance of thesuggested controller strategy when a three-phase balancedload is connected to the four-leg VSI. The balanced loadincludes a resistor of 8Ω for each phase. The three-phasepole voltage references (𝑉

𝐴𝑁, 𝑉𝐵𝑁, 𝑉𝐶𝑁) and the offset voltage

reference (𝑉𝑓𝑁) are shown in Figure 13. It can be seen

from this figure that the three-phase four-leg VSI has theconsiderable ability to provide desired pole voltage referenceswith the expected amplitude for the three-phase balancedload.

The output waveforms of load voltages, load currents,and neutral current for the four-leg VSI for the balanced

VA

VB

VC

−30.00−18.00−6.00

6.0018.0030.00

Load

curr

ent (

A)

−200.0−120.0−40.00

40.00120.0200.0

Phas

e vol

tage

(V)

32.00 44.00 56.00 68.00 80.0020.00Time (ms)

32.00 44.00 56.00 68.00 80.0020.00Time (ms)

Line A: Iload-ALine B: Iload-B

Line C: Iload-CLine N: In

Figure 14: Steady-state load voltages, load currents, and neutralcurrent for the balanced load.

VA

VB

VC

−30.00−18.00−6.00

6.0018.0030.00

Load

curr

ent (

A)

−200.0−120.0−40.00

40.00120.0200.0

Phas

e vol

tage

(V)

32.00 44.00 56.00 68.00 80.0020.00Time (ms)

32.00 44.00 56.00 68.00 80.0020.00Time (ms)



Figure 15: Steady-state load voltages and currents for the unbal-anced load (𝑅

𝐴= 10Ω, 𝑅

𝐵= 7Ω, and 𝑅

𝐶= 8Ω).

load are also depicted in Figure 14. The results indicate thatthe proposed control strategy is capable of regulating thefundamental component of the load voltage close to thedesired peak for the balanced load.

8.1.2. With Single-Phase and Three-Phase Unbalanced Loads.In this part, the steady-state performance of the proposedcontrol strategy for various unbalanced load cases, including(𝑅𝐴= 10Ω, 𝑅

𝐵= 7Ω, 𝑅

𝐶= 8Ω), (𝑅

𝐴= 𝑅𝐵= 8Ω,

𝑅𝐶= ∞), and (𝑅

𝐵= 8Ω, 𝑅

𝐴= 𝑅𝐶= ∞) are investigated.

The simulation results of load voltages and currents for thesedifferent unbalanced load scenarios are depicted in Figures15–17. Since the control structure adopts separate controllerfor each phase, the unbalanced loads have no influence on the


Table 3: Comparison of two control strategies in steady-state.

Load typeConventional control scheme Proposed control strategy

Load peak voltages (V) PVUR (%) Load peak voltages (V) PVUR (%)Phase 𝐴 Phase 𝐵 Phase 𝐶 Phase 𝐴 Phase 𝐵 Phase 𝐶

Balanced 155.32 155.55 155.54 0.096 155.50 155.54 155.56 0.021Unb. 1 155.25 155.52 155.58 0.128 155.38 155.49 155.56 0.062Unb. 2 155.15 155.56 155.6 0.184 155.23 155.52 155.75 0.173Unb. 3 155.55 155.65 155.15 0.192 155.79 155.25 155.45 0.188

VA

VB

VC

−30.00−18.00−6.00

6.0018.0030.00

Load

curr

ent (

A)

−200.0−120.0−40.00

40.00120.0200.0

Phas

e vol

tage

(V)

32.00 44.00 56.00 68.00 80.0020.00Time (ms)

32.00 44.00 56.00 68.00 80.0020.00Time (ms)




𝐴= 𝑅𝐵= 8Ω, and 𝑅

𝐶= ∞).

voltage controller performance, and the load voltages remainbalanced. From these figures, it is apparent that the proposedcontrol technique has a significant ability to provide balancedoutput voltages for the four-leg VSI even under extremelyunbalanced load condition containing a single-phase loadbetween the phase and neutral.

According to the IEEE standards, the voltage imbalanceneeds to be maintained low, below 2% for sensitive loads[30, 31]. The performance of the suggested multiloop controlstrategy has been compared with the conventional controlscheme [15, 16], with the same specification for the innerand outer control loops. In order to evaluate the value ofphase voltage unbalance rate (PVUR), the magnitudes of thefundamental components of the three-phase voltages andthe PVUR of all tested scenarios for both the conventionaland the suggested control schemes are presented in Table 3.The results show that the load voltages can remain balancedin steady-state for both the conventional and the proposedcontrol scheme at all tested conditions. Moreover, the valueof the PVUR is maintained below 2% at all tested conditionsfor both control strategies. However, the steady-state perfor-mance of the suggested per-phase control scheme is improvedbecause of avoiding the use of slow filter-based symmetricalcomponents calculators.

VA

VB

VC

−30.00−18.00−6.00

6.0018.0030.00

Load

curr

ent (

A)

−200.0−120.0−40.00

40.00120.0200.0

Phas

e vol

tage

(V)

32.00 44.00 56.00 68.00 80.0020.00Time (ms)

32.00 44.00 56.00 68.00 80.0020.00Time (ms)




𝐵= 8Ω, 𝑅

𝐴= 𝑅𝐶= ∞).

8.2. Transient Performance. In this part, the evaluation of thetransient behavior of the proposed control strategy is madefor a three-phase unbalanced load (𝑅

𝐴= 10Ω, 𝑅

𝐵= 7Ω,

and 𝑅𝐶= 8Ω). To verify the transient performance of the

proposed voltage control strategy a step change in the 𝑑-components of voltage references (𝑉

𝑑ref ) in all phases of thefour-leg inverter is applied and then returns to its initialvoltage value (while keeping 𝑉

𝑞ref = 0).For the 𝐴-phase a step change from 155.56 to 75V (peak)

at 26ms is applied and then returns to its initial voltage valueat 79ms. The transient behaviors of the voltage reference(𝑉𝐴,𝑑ref ) and the actual voltage (𝑉

𝐴,𝑑) of the respective phase

are shown in Figure 18. The 𝑑-reference voltage (peak)value in phase “𝐵” (𝑉

𝐵,𝑑ref ) is step changed from 155.56 to140V (peak) at 39ms, afterwards back to 155.56V at 79ms.Figure 19 also depicts the transient response of the voltage(𝑉𝐵,𝑑ref ) reference and the actual voltage (𝑉𝐵,𝑑) of the 𝑏-phase.For the 𝐶-phase also a step change from 155.56 to 135V

(peak) at 46ms is applied and then returns to its initial voltagevalue at 79ms. Figure 20 illustrates the waveforms of thevoltage (𝑉

𝐶,𝑑ref ) reference and actual voltage (𝑉𝐶,𝑑) of the

pertaining phase. As can be seen, the voltage controllers ineach phase demonstrate very fast dynamic, and the actualvoltages are capable of following closely their references. The


SRFPI controller: VAdref

SRFPI controller: VAd

0.000

40.00

80.00

120.0

160.0

200.0

Phas

e A (V

)

30.00 50.00 70.00 90.00 110.0010.00Time (ms)

Figure 18: Transient response of the PI controller to step changes inphase “𝐴.”

SRFPI controller: VBdref

SRFPI controller: VBd

100.0

120.0

160.0

140.0

180.0

200.0

Phas

e B (V

)

38.00 56.00 74.00 92.00 110.0020.00Time (ms)

Figure 19: Transient response of the PI controller to step changes inphase “𝐵.”

PI controllers take about 1 cycle to track reference voltage ineach phase. It is apparent that the proposed controller canchange the load voltages close to their references with veryfast dynamic.

8.2.1. Comparison between the Conventional and the ProposedControl Scheme. In this part, the transient performanceof the proposed control strategy has been compared withthe conventional control scheme [15, 16], with the samespecification for the voltage and current controller. In thissimulation, while the three-phase four-leg grid-forming unitis initially supplying a balanced load (8Ω/ph), a single-phaseinductive load (𝑅 = 20Ω and 𝐿 = 2mH) is added betweenphases “𝐴” and “𝐶” at 0.3 s. After 0.2 s, the connected loadbetween phase “𝐶” and neutral is changed from the nominalload to pure resistance of 5.7Ω. Lastly, the nominal loadbetween phase “𝐴” and neutral is disconnected at 0.7 s.

SRFPI controller: VCdref

SRFPI controller: VCd

100.0

120.0

160.0

140.0

180.0

200.0

Phas

e C (V

)

50.00 65.00 80.00 95.00 110.0035.00Time (ms)

Figure 20: Transient response of the PI controller to step changesin phase “𝐶.”

The output waveforms of load voltages under varyingunbalanced load conditions are depicted in Figure 21, forboth the conventional and the suggested control schemes.As can be seen, both control strategies can keep the loadvoltages balanced in steady-state under varying unbalancedload conditions. To compare the speed of response of twocontrol schemes, the transient load voltages for both controlstrategies are provided with zoomed Figures. It can be seenthat the load voltage waveforms are unaffected by the loadtransients in the proposed scheme. Comparing the tworesults, it can be seen that no significant changes in theload voltages can be observed with the proposed scheme.While there exist at least three line cycles transient with theconventional approach, the results show that the suggestedcontroller has a significant ability to balance the outputvoltages under severe unbalanced load conditions with zerosteady-state error and fast dynamic response.

9. Conclusion

In this study, a new per-phase cascaded voltage-currentcontrol strategy for a three-phase four-leg VSI operatingwith highly unbalanced loads in an autonomous distributionnetwork is presented.The suggested control scheme providesbalanced output voltages for the four-leg inverter even underextremely unbalanced loading conditions. It consists of anouter voltage loop in each phase to regulate the instantaneousoutput voltages and an inner current loop in each phase toimprove both the steady-state and transient behaviors of thecontrol system. The frequency response approach is usedfor tuning and stability analysis. The transient and steady-state performances of the suggested control scheme areinvestigated using simulation studies. The simulation resultsshow that the suggested controller has a significant abilityto balance the output voltages under severe unbalanced loadconditions with zero steady-state error and fast dynamicresponse.


200.0

120.0

40.00

−40.00

−120.0

−200.00.290 0.304 0.318 0.332 0.346 0.360

(s)

200.0

120.0

40.00

−40.00

−120.0

−200.0

(s)

0.490 0.504 0.518 0.532 0.546 0.560

200.0

120.0

40.00

−40.00

−120.0

−200.0

(s)

0.690 0.704 0.718 0.732 0.746 0.760

350.0

210.0

70.00

−70.00

−210.0

−350.0

Load

vol

tage

(V)

Time (s)0.200 0.360 0.520 0.680 0.840 1.000

VA

VB

VC

(a)200.0

120.0

40.00

−40.00

−120.0

−200.0

200.0

120.0

40.00

−40.00

−120.0

−200.0

250.0

150.0

50.00

−50.00

−150.0

−250.00.290 0.304 0.318 0.332 0.346 0.360

(s) (s) (s)

0.490 0.504 0.518 0.532 0.546 0.560 0.690 0.704 0.718 0.732 0.746 0.760

350.0

210.0

70.00

−70.00

−210.0

−350.0

Load

vol

tage

(V)

Time (s)0.200 0.360 0.520 0.680 0.840 1.000

VA

VB

VC

(b)

Figure 21: Waveforms of output voltages of the four-leg inverter for different load condition. (a) Proposed control scheme. (b) Conventionalscheme [15, 16].


Competing Interests

The authors declare that they have no competing interests.

References

[1] M. R. Miveh, M. F. Rahmat, M.W.Mustafa, and A. A. Ghadimi,“Progress in controlling autonomous microgrids,” ElectronicsWorld, vol. 122, pp. 20–23, 1957.

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