Research Article A Low-Complexity Euclidean Orthogonal LDPC Architecture …downloads.hindawi.com/journals/tswj/2015/327357.pdf · 2019-07-31 · Research Article A Low-Complexity

Research ArticleA Low-Complexity Euclidean Orthogonal LDPC Architecture forLow Power Applications

M. Revathy1 and R. Saravanan2

1Department of Electronics and Communication Engineering, PSNA College of Engineering and Technology, Dindigul 624622, India2Department of Computer Science and Engineering, RVS Educational Trust Group of Institutions, Dindigul 624005, India

Correspondence should be addressed to M. Revathy; [email protected]

Received 19 October 2014; Revised 17 March 2015; Accepted 19 March 2015

Academic Editor: Yo-Sheng Lin

Copyright © 2015 M. Revathy and R. Saravanan.This is an open access article distributed under theCreative CommonsAttributionLicense, which permits unrestricted use, distribution, and reproduction in anymedium, provided the originalwork is properly cited.

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access(WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-checkcode (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check nodeand variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generatoris used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable nodearchitecture.This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targetedto 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardwareutilizations on comparing with different conventional architectures.

1. Introduction

Low-density parity-check (LDPC) codes, introduced byGallager [1] during the 1960s, are a class of linear blockLDPC codes. The excellent error correction properties oflow-density parity- check (LDPC) codes have gained greatsignificance in the research fields. Among various errorcorrection codes, LDPC codes are chosen as better codes,closer to the Shannon limit. LDPC codes achieve 0.04 dB ofShannon’s limit. Compared to other codes, LDPC codes withiterative decoding are easy to implement. These codes havean enhanced error correcting capability. The name “LDPC”comes from the characteristic of their parity-check matrixwhich contains only a few 1s in comparison to the amount of0s. Their main advantage is that they provide a performancewhich is very close to the capacity for a lot of differentchannels and linear time complex algorithms for decoding.

LDPC codes have certain advantages over turbo codes(the best codes with BER closer to Shannon capacity, sofar). The first merit is that the decoding of LDPC codesfully follows parallelism which performs at a higher speed.Secondly, very low-complexity decoders are more enough

and suitable for these codes. Thirdly, LDPC decoding isverifiable; that is, decoding to a correct code word can beverified for accuracy.

Moreover, LDPC codes are more suitable for implemen-tation in applications that employ parallelism. Therefore,these codes can be employed in several standards includingWiMax (IEEE 802.16) and different high speed applicationsin which iterative message-passing algorithms are mostlyimplemented in parallel. LDPC implements parallelism inthe decoding process thereby achieving high decodingthroughput. LDPC codes consecutively decode both rowsand columns and therefore these codes are more suitable foriterative decoding, hence referred to as iterative decoders.

LDPC codes can be represented in two ways. The firstmethod is in the form of matrices, similar to all other linearblock codes, and the second way of representation is in theform of graphs. There are several algorithms proposed todecode LDPC codes and each algorithm has been designedautonomously and comes under different names as a matterof fact. Some of the widespread LDPC decoders used com-monly are the sum-product algorithm, belief propagationalgorithm, and message-passing algorithm.

Hindawi Publishing Corporatione Scientific World JournalVolume 2015, Article ID 327357, 8 pageshttp://dx.doi.org/10.1155/2015/327357

2 The Scientific World Journal

In this paper, a low-complexity Euclidean orthogonalLDPC architecture has been proposed for low power appli-cations. Section 2 reviews some of the related LDPC baseddecoding techniques. Section 3 explains the proposed LDPCdecoder, algorithm, and internal modules design in detail.The results and discussion are placed in Section 4 andSection 5 concludes our work.

2. Related Works

Darabiha et al. [2] investigated the VLSI architectures forlow-density parity-check (LDPC) decoders amenable to low-voltage and low power operation. They designed a highlyparallel decoder architecture with low routing overhead.Secondly, they proposed an efficient method to detect earlyconvergence of the iterative decoder and terminate the com-putations, thereby reducing dynamic power. A bit-serial fullyparallel LDPC decoder fabricated in a 0.13 𝜇mCMOS processwas reported and the above techniques were implementedto show the effect of power consumption. With early ter-mination, the prototype decoded 10.4 pJ/bit/iteration, whileperforming within 3 dB of the Shannon limit at a BER of10−5 and a throughput of 3.3 Gbps. If operated from a 0.6Vsupply, the energy consumption can be further reduced to2.7 pJ/bit/iteration with a total throughput of 648Mbps, dueto the highly parallel architecture.

Mansour and Shanbhag [3] proposed high-throughputmemory-efficient decoder architecture for LDPC codes basedon turbo decoding algorithm. A new merged-schedulemerge-passing algorithm was also proposed to reduce thememory overhead of their algorithm for low to moderate-throughput decoders. Moreover, a parallel soft-input soft-output (SISO) message update mechanism was proposed.Simulation results showed that their algorithm attained athroughput of 1.92Gbps for a frame length of 2304 bits, powersaving of 89.13%, and 69.83% reduction in silicon area with areduced interconnect length of 60.5%.

Reviriego et al. [10] proposed a majority logic decoderusing simple hardware. In this method, during the firstiteration of majority logic decoding, a word is detected forerrors and suppose if it is without any errors, the remainingiterations get stopped and hence the decoding process iscomplete. The average decoding time decreases as most ofthe words of a memory do not possess any errors. This onestep majority logic decodable method was also implementedover a similar technique called Euclidean geometry low-density parity-check (EG-LDPC) codes.Their results showedthat the method estimated the probability of error detectionfor various code sizes and different error counts with moreaccuracy and was proved to be suitable for EG-LDPC codes.

Torrieri et al. [11] proposed a double iterative LDPC basedCDMA (code division multiple access) receiver withoutthe use of any training or pilot symbols. An expectation-maximization channel-estimation algorithm for the fad-ing amplitude and interference-plus-noise power spectraldensity (PSD) is proposed for CDMA systems with low-density parity-check codes. The elimination of pilot symbolssimplifies the system design and enhances either informa-tion throughput or spectral efficiency by increasing the

information-symbol duration. After initial estimates of thefading amplitude and noise PSD are obtained, succeedingvalues of these parameters are iteratively updated from thechannel decoder.These updated estimates are then combinedwith the received symbols and iteratively passed to thedecoder. Experimental results show that this system hashigher throughput but bit error rates greater than othersystems.

The low-density parity-check codes for turbo multiuserdetection inmultipath CDMA channel are designed byWanget al. [12]. They developed a technique for computing theprobability density function (pdf) of the output extrinsicmessages as a function of the pdf of input extrinsic messages.In case of additive white Gaussian noise channels and asyn-chronous multipath fading channels, the extrinsic messagescan be considered symmetric Gaussian distributed. Simula-tion results are significant with the computed thresholds andirregular LDPC codes designed outperform the regular ones.

The nonbinary mixed domain LDPC decoders and theirfinite precision effects were studied by Kim and Sobelman[5]. They used proper scaling techniques and offset-basedmethods to improve the decoding performance. Besides, anovel Fast Fourier Transform (FFT)-based belief propagation(BP) decoder architecture was proposed to balance theoperational load among various processing units. The exper-imental outcomes demonstrated that their method reducedthe number of field programmable gate array slices to 47%compared with other standard FFT-based BP decoders.

Spagnol et al. [4] proposed a modified belief propagationalgorithm for Galois Field-GF(2𝑚) LDPC codes. The algo-rithm has been implemented with low hardware utilizationsin VLSI. Their decoding algorithm used a serial architecturefor GF(2𝑚) are implemented on FPGA. Their results showedthat their algorithm was suitable for short to medium lengthcodes.

The serial GF (64)-LDPC decoder proposed by Boutillonet al. [13] was based on Extended Min-Sum algorithm. Thealgorithmwas applied for different code rates and lengths andobtained a performance at less than 0.7 dB from the beliefpropagation algorithm. Their decoder easily gets adaptedfor very high Galois Field orders, such as GF(4096) andeven higher. Their experimentation results proved that theirdecoder used less than 20% of decoder area than that ofVirtex-4 FPGA at a throughput rate of 2.95Mbps.

Hwang and Lee [14] studied and discussed various meth-ods used in the construction of Block-Circulant (BC) ReedSolomon based low-density parity-check (RS-LDPC) codes.Their system resulted in a BC form from a random parity-check matrix for RS-LDPC codes. Based on the obtained BCparity-check matrix, switch network and decoder architec-ture has been built for BC-RS-LDPC codes.The designed BC-RS-LDPC decoder possesses high performance to prove theefficiency of their system.Their experimentation showed thatthe decoder utilized 1.3M gates at an operating frequency of450MHz with 8 iterations at a throughput rate of 41 Gbps.

The conventional methods in [15–21] stated variousdesign techniques for check node and variable node unit ofLDPC decoder. All these techniques focused on error rate

The Scientific World Journal 3

Check node unit

(CNU)

Variable node unit

(VNU)

Euclidean orthogonal generator

Data storage

elements (memory)

Internal address

generator

24

re im

Address 1

Address 2

8 8

P 1

P 2

MDGU(minimum

data generator

unit )

ComparatorMin 1

Min 2

Decoding sequence

Data received in

channel6

6

24

yk1

y |ADD||SUB|

Figure 1: Proposed architecture of decoder.

reduction and low power consumption by reducing the over-head and area reduction. The proposed methodology statedin this paper is based on Euclidean orthogonal architecture,which determines the severity level of the noises from thereceived signals in check node unit. If the noise severity on thereceived data is high (determined by Euclidean orthogonalgenerator), then it will make the variable node unit unableto decode the received signals. If the noise severity on thereceived data is high, then it will enable the variable node unitto decode the received signals.

3. Architecture of Proposed Decoder

The proposed method of decoder design comprises severalprocessing elements—variable node unit (VNU), check nodeunit (CNU), address generator, minimum data generator,and several other modules as shown in Figure 1. The inter-connections between CNUs and VNUs are provided by therouting networks. The connectivity provided by the parity-check matrix creates the label for input and output edgesof the CNU. After the completion of required number ofiterations, the VNU produces the final outputs.

Algorithm of proposed decoding is described in thefollowing.

(1) Data with noise is received from the channel and fedinto the check node unit of the LDPC decoder.

(2) Euclidean orthogonal generator gets the sequencefrom the check node unit and enable/disable thevariable node unit based on the severity level of thenoises on the received sequences.

(3) The output from variable node unit is stored in thedata storage elements which received the addresssequence from the address generator module.

(4) Minimum data generator unit generates the mini-mum 1 and minimum 2 data which are then given tothe comparator unit.

(5) The response from comparator is added with theresponse from the subtractor unit to produce thedecoded signals.

3.1. Check Node Unit. The architecture of the check node unitof LDPC decoder is shown in Figure 2. The CNU helps inthe determination of the strength of the received signal in thechannel.TheCNUconsists of twelve subtractor (|SUB|) units,four adder (|ADD|) units, and four sorter and concatenatormodules which are used in estimating the four directionaldifference vectors, fromwhich the smallest value of differenceis decided. In the proposed design, |ADD| and |SUB| units arerequired for the design of check node.

The gate count of a single multiplier or division moduleis much more than the gate count of one adder or subtractorunit; hence only adders and subtractors are fully utilized inour design instead of multipliers and division units, therebyreducing the hardware complexity and cost.

3.2. Architecture of Variable Node Unit (VNU). The variablenode unit (VNU) as shown in Figure 3 is used in computingthe hard decision vector “𝑥”. The hard decision vector “𝑥” isrouted to the check node unit or block (CNB) through therouting network, whose size is smaller than the network sizeof sum-product algorithm. A single-bit value exists for rout-ing between two nodes. The VNU comprises a flip-detectioncircuit, line buffer, multiplexed adder, and concatenator. Atfirst, the received signal “𝑦” from check node unit passesthrough a register-feedback assembly to enter the variablenode block (VNB). The received values are 6-bit signed-magnitude (SM) values. Let [𝑠𝑛 :𝑚𝑛] be 𝑛th 4-bit valueprovided to the 𝑛th VNB, where 𝑠𝑛 denotes hard decisionvalue and 𝑚𝑛 denotes the magnitude of 𝑠𝑛. The correlationcalculation is made simpler by SM for implementation andthe correlator circuit consists of an inverter followed by a 1-bit multiplexer. The block data received from CNU unit havefour subblocks, out of which the first three submodule blocksare processed by adder module and last submodule block isprocessed directly by multiplexer unit.


Sorter andconcatenator




3

3

3

3

3

3

3

3CB 1

CB 2

CB 3

CB 4

6

6

6

6

3

33

3

3

3

3

3

a

d

h

g

b

f

c

e |SUB|

|SUB|

|SUB|

|SUB|

|SUB|

|SUB|

|SUB|

|SUB|

|SUB|

|SUB|

|SUB|

|SUB|

|ADD|

|ADD|

|ADD|

|ADD|

Figure 2: Architecture of check node unit.

{ }

Initialise

6

6

6CNB 4

VNU input

6

66

66

66

6

MU

X

MU

X

CNB 1

CNB 2CNB 3

6

246

6

6

y

Σ

+

xk

Line buffer

yk1

Figure 3: Variable node architecture.


Positive edge

checker

Negative edge

checker0

1

qc

0

1

0

1

k1

Min 2

k3

Min 1

k4

Min 1 update

k2

Min 1

Min 2 new

Min 2 update

qc1

8

8

new

≥

≥

Figure 4: Minimum data generator unit.

3.3.MDGU. Avalue “qc” is produced at every clock cycle andfed to the minimum data generator unit (MDGU) depictedin Figure 4. Then, “qc” is compared to the updated first andsecond minimum (min 1 and min 2), that are initialized asthe maximum allowed value at the beginning of each checknode phase. The minimum of both comparisons (min 1 newand min 2 new) is passed on and sampled on the rising edgeof the clock signal, together with the previous first minimumand a flag signaling if min 1 = min 1 new. If min 1 update =0, then min 2 new is substituted with previous value of min1. Finally, min 1 and min 2 are updated on the falling edge ofthe clock, ready, and stable for the next “qc”. Once min 1 andmin 2 are produced, they are compared to all the “qc” of theCN, which are delayed by a number of clock cycles equal tothe degree of the CN (deg).

3.4. Internal Address Generator. Figure 5 shows the blockdiagram of the internal address generator (IAG) for theinput and the output. The instruction memory provides theinitial address and SKIP, STEP, and SUBSET fields to addressgenerator. After every cycle is executed, the current addressis processed by the IAG for calculating the address of thenext set of operands.Theoutput address generatorworks verysimilar to that of input address generator, but at the oppositephase of the clock compared to the input address generator.Therefore, the reconfigurable cells (RCs) guarantee the inputdata to be read in a single clock cycle and write back theoutput in the opposite phase of the clock. Hence, the RC isensured to performone complete computationwithin a singleclock cycle.

3.5. Euclidean Orthogonal Generator. It is used to determinethe level of noise on the received signal as shown in Figure 6.The output from CNU is fed into the Euclidean orthogonalgenerator, which consists of adder/subtractor, shifter, and

0 1

0 1

Magnitude checker

Subset

Default address

Address register

Skip Step

Adder

Incrementer

Address 1 Address 2

Figure 5: Internal address generator.

multiplexers. It will produce the real and imaginary part ofthe received signal from CNU. If the real term is greater thanthe imaginary term, then the signal from CNU is passedthrough the VNU in order to decode the signals; else it isdiscarded due to the high severity of noise on the receivedsequences.

4. Results and Discussion

The architecture of LDPC decoder designed in this work ismore suitable for low power applications and is verified using


CNU

CSA CSA

re

CSA CSA

im

++ + +

≫1 ≫2 ≫3 ≫4 ≫1 ≫2 ≫3 ≫4

A | SA | S

A | S A | S A | S A | S

C0 C1 C2 C3 C4 C5 C6 C7

S4

S0 S1 S2 S3

S5

f0f1

Figure 6: Euclidean orthogonal generator.

Xilinx 9.2i andModelsim 5.8 on several Virtex family devices.The proposed decoder is simulated on various FPGA devicesfor its performance analysis. The input for proposed decoderis taken from the real time mobile environment with noises.The clock frequency for the simulation is 200MHzwith 50-50on-off clock period as initial simulation setup. The designeddecoder made use of 100 LUTs and 51 slices with an operatingfrequency of 200MHz at themaximum.The results show thatthis proposed decoder consumes very low power in terms ofLookUpTables, FPGA slices, and gate counts.The power andcurrent consumptions are verified for different devices of theVirtex family and tabulated in Table 1. The performances ofthe proposed decoder have been analyzed in terms of numberof Look Up Tables (LUTs), number of Slices (S), gate counts(GC), Current Consumption (CC), and Power Consumption(PC). Table 2 explains the performance evaluation of thedecoder in terms of hardware used and Table 3 compares thedecoding latency of other decoding methods with proposeddecoder.

The operation of our proposed decoder is illustrated inFigure 7, which shows the RTL and technology schematicviews of the proposed technique are presented.

We have simulated the proposed code and then theproposed LDPC code is downloaded in to the FPGA devicefor its performancemeasurement.The power consumption of

Table 1: Performance analysis of power and current consumptionsof Virtex processors.

Family Devicespecifications

Powerconsumption

(mW)

Currentconsumption

(mA)Virtex-E XCV50E 151 82Virtex5 XC5VLX30 267 208Virtex4 XC4VLX15 253 127Virtex XCV50 27 10

Table 2: Performance evaluation of hardware utilizaions.

Hardware utilization parameters Hardware consumptionSlices 51LUTs 100Gate counts 3330

the proposed LDPC architecture is measured using xprimeror power analyzer tool available in the Xilinx tool. The inputto the FPGA unit is given from the real time mobile signalreceived from the channel with noises. The LDPC decoderproposed in this paper has been compared in terms of powerutilizations by evaluating it over different Virtex devices. The


(a)

(b) (c)

Figure 7: (a) simulation screenshot indicating decoded sequence, (b) RTL schematic of proposed design, and (c) technology schematic ofproposed design.

Table 3: Analysis of decoding latency.

Methodology Decoding latency (ns) CMOS technology Frequency (MHz)Proposed 22.02 45 nm 200Spagnol et al. (2009) [4] 50.05 65 nm 300Kim and Sobelman (2013) [5] 56.36 180 nm 450

LDPC decoder in this work was mainly designed for the pur-pose of reducing the power levels during operation. Table 1already discussed the power utilizations of different Virtexdevices and it has been shown that power consumptions ofsuch devices are at lower levels.

Several performance assessment parameters and resourceutilization parameters were determined for the proposedLDPC decoder. The current study mainly focuses on lowpower applications and hence the pipelined LDPC decoderis being designed and developed for this purpose. Theproposed LDPC decoding architecture is synthesized usingXilinx project navigator version 9.2i tool. The decodinglatency obtained for both check node and variable nodeunit implementations in the proposed architecture is about28 ns, whereas the decoding latencies obtained by Kim andSobelman [5] and Spagnol et al. [4] were about 56.36 nsand 50.05 ns, respectively, thereby proving that this proposedLDPC decoder design performs better than conventionaldecoding methods.

The proposed architecture consumed 4-input LUTs ofabout 100, which provides a low hardware complexity com-pared to Kim and Sobelman [5] and Spagnol et al. [4], whichconsumed 6422 LUTs and 12924 LUTs, respectively. Thepower consumptions of variousmethodologies are comparedin Table 4.

5. Conclusion

We have proposed the design of high efficient LDPC decoderarchitecture for implementations in low power applica-tions. The design of Euclidean orthogonal generator hasbeen proposed in this paper, which is a part of LDPCdecoder architecture. The Euclidean orthogonal generatorproposed in this work reduces the error rate of the proposedLDPC architecture. The design discussed produced betterresults than other conventional decoder architectures withlesser hardware consumption and power utilization of about


Table 4: Comparison of power consumptions of conventional methods.

Methodology Power consumption (mW)** CMOS technology Energy consumption (nJ)*

Proposed method 27 45 nm 104.7Ismail et al. (2013) [6] 33.14 65 nm 144.9Blanksby and Howland (2002) [7] 690 90 nm 256.1Mansour and Shanbhag (2006) [8] 787 65 nm 320.0Mohsenin et al. (2010) [9] 1359 180 nm 389.9*Energy consumption of one clock period. This comparison is only for the energy in one clock cycle, which maps to the power consumption.**Code rate is 0.96 and word length is 7 bits with 8 iterations.

27mW, which is more suitable for most of the low powerapplications.

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper.

References

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Research Article A Low-Complexity Euclidean Orthogonal LDPC Architecture …downloads.hindawi.com/journals/tswj/2015/327357.pdf · 2019-07-31 · Research Article A Low-Complexity