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A CASCADE BOOST CONVERTER DESIGN, DEMONSTRATION, AND SCALING FOR FUTURE HIGH VOLTAGE POWER CONDITIONING SYSTEMS
A Thesis presented to the faculty of the Graduate School
University of Missouri—Columbia
In Partial Fulfillment
Of the Requirements for the Degree
Master of Science
by
SCOTT CASTAGNO
Dr. Randy Curry, Thesis Supervisor
MAY 2006
© Copyright by Scott Castagno 2006
All Rights Reserved
ii
ACKNOWLEDGEMENTS
I would like to thank Dr. Randy Curry for his assistance, guidance, and support
with the research and writing of this thesis. All of his help and dedication is greatly
appreciated. Additionally, I would like to recognize Dr. Kenneth McDonald for his
willingness to provide technical support for the work. Also, student colleagues Josh
Leckbee, Peter Norgard, Laura Heffernan, Keith Lechien, and Matt Aubuchon provided
valuable collaboration and assistance throughout my graduate studies.
iii
TABLE OF CONTENTS
ACKNOWLEDGEMENTS................................................................................................ ii
TABLE OF CONTENTS................................................................................................... iii
LIST OF TABLES............................................................................................................ vii
LIST FIGURES .................................................................................................................. x
CHAPTER 1.0 INTRODUCTION ..................................................................................... 1
REFERENCES FOR CHAPTER 1.0 ................................................................................. 9
CHAPTER 2.0 THEORETICAL CASCADE BOOST DESIGN .................................... 11
2.1 SWITCH-MODE CONVERTERS................................................................. 11
2.2 THE BOOST CONVERTER.......................................................................... 13
2.3 DISCONTINUOUS MODE ........................................................................... 17
2.4 CASCADE BOOST CONVERTER DESIGN ............................................... 21
2.4.1 VOLTAGE GAIN AND INDUCTOR DERIVATION................... 22
2.4.2 FILTER CAPACITORS .................................................................. 27
2.5 ASYMMETRICAL SWITCHING ................................................................. 29
iv
2.6 INITIAL DESIGN VALUES AND SIMULATION RESULTS OF AN
IDEALIZED MODEL .......................................................................................... 31
REFERENCES FOR CHAPTER 2.0 ............................................................................... 37
CHAPTER 3.0 CASCADE BOOST CONVERTER PROTOTYPE DESIGN................ 38
3.1 IGBT SWITCHING DESIGN THEORY....................................................... 39
3.1.1 IGBT CAPACITANCE ................................................................... 41
3.1.2 THE TURN-OFF TRANSIENT OF IGBTS ................................... 44
3.1.3 IGBT SWITCHING THEORY CONCLUSION............................. 56
3.2 FIRST STAGE DETAIL ................................................................................ 57
3.3 SECOND STAGE DETAIL ........................................................................... 62
3.4 SECOND STAGE SWITCH DESIGN OPTIMIZATION............................. 68
REFERENCE FOR CHAPTER 3.0.................................................................................. 73
CHAPTER 4.0 DIAGNOSTICS OF THE CASCADE BOOST CONVERTER
PROTOTYPE ................................................................................................................... 75
4.1 VOLTAGE DIAGNOSTICS.......................................................................... 75
4.2 CURRENT DIAGNOSTICS .......................................................................... 77
4.3 OSCILLOSCOPE ........................................................................................... 78
v
CHAPTER 5.0 CASCADE BOOST CONVERTER PROTOTYPE RESULTS ............. 79
5.1 CASCADE BOOST CONVERTER OUTPUT AND EFFICIENCY ............ 80
5.2 COMPONENT LOSS ANALYSIS ................................................................ 88
5.2.1 MEASUREMENT OF THE FIRST STAGE IGBT LOSS ............. 88
5.2.2 MEASUREMENT OF THE SECOND STAGE IGBT LOSS ........ 92
5.2.3 MEASUREMENT OF DIODE LOSSES ........................................ 94
5.2.4 TOTAL COMPONENT LOSS CALCULATION .......................... 98
5.3 OPTIMIZATION OF THE PROTOTYPE CONVERTER............................ 99
REFERENCES FOR CHAPTER 5.0 ............................................................................. 101
CHAPTER 6.0 CASCADE BOOST CONVERTER SCALING TO HIGHER POWER
LEVELS.......................................................................................................................... 102
6.1 NEAR-TERM TECHNOLOGY BASED SCALING .................................. 103
6.2 FIVE & TEN-YEAR FUTURE TECHNOLOGY SCALING ..................... 112
REFERENCE FOR CHAPTER 6.0................................................................................ 123
CHAPTER 7.0 CONCLUSION...................................................................................... 125
APPENDIX A................................................................................................................. 128
vi
APPENDIX B ................................................................................................................. 131
APPENDIX C ................................................................................................................. 132
APPENDIX D................................................................................................................. 134
vii
LIST OF TABLES
Table
2.1 Comparison of voltage gain and inductor values over a range of duty ratios and voltage gain ratios. DCM inductor held at 3.3 mH; CCM Lmin adjusted to keep boost converter in CCM. .................................................................................................... 19
3.1 Cascade boost converter prototype design goals. ...................................................... 39 3.2 Caddell-Burns inductor specifications. Incremental current is the minimum current
at which the inductance will be decreased by 5% from the initial (zero-DC) value. 60 3.3 Volume and mass of first stage components using COTS components. ................... 61 3.4 Volume and mass of the second stage components. .................................................. 67 3.5 Total cascade boost converter prototype volume and mass....................................... 68 3.6 Turn-off loss comparison of the two IGBT designs. ................................................. 71 3.7 Cascade boost converter parameter comparison of 3.3 kV and 1200 V IGBTs. ....... 72 4.1 Voltage probes for circuit diagnostics including attenuation factor and bandwidth. 76 4.2 Measurement and diagnostic equipment implemented.............................................. 77 4.3 Current monitors for circuit diagnostics including output voltage per amp, peak
current, max continuous current, usable rise time. ................................................... 78 5.1 Cascade boost converter prototype design goals. ...................................................... 79 5.2 Average value data of the system operated at 5 kV output........................................ 84 5.3 Efficiency and loss for the first and second stages operated at 5 kV output. ............ 84
viii
5.4 First stage and second stage voltage data of the cascade boost converter prototype as input voltage is varied from 0 V to 100 V. ............................................................... 84
5.5 Cascade boost converter operating conditions for the component loss analysis ....... 88 5.6 Summary of the first stage IGBT data. ...................................................................... 92 5.7 Summary of second stage IGBT data. ....................................................................... 94 5.8 Breakdown of average component power loss. ......................................................... 99 6.1 Cascade boost converter specifications for a 60 kV, 300 kW module. ................... 102 6.2 Ideal parameters calculated for a 60 kV, 300 kW cascade boost converter. ........... 104 6.3 Switching parameters adjusted, corresponding to 90% efficiency. ......................... 104 6.4 Number of IGBT modules in series and parallel for assembly of S1 and S2............ 106 6.5 Expected voltage and current per IGBT, and total average turn-off loss. ............... 106 6.6 First stage components volume and mass for the near-term 60 kV, 300 kW converter.
................................................................................................................................. 110 6.7 Second stage components volume and mass for the near-term 60 kV, 300 kW
converter. ................................................................................................................ 110 6.8 Estimated volume and mass of components of the near-term 60 kV, 300 kW
converter. ................................................................................................................ 111 6.9 Total near-term projected component volume and mass and complete system volume
and mass of a 300 kW converter. The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter................ 111
6.10 Properties of SiC that will enhance power semiconductor devices. ...................... 113 6.11 Summary of the key parameter estimates for SiC devices in 5 and 10 years. ....... 116 6.12 Number of devices to be placed in series and parallel for the 5 and 10-year time
frames for the 300 kW converter’s first and second stage switches. ...................... 116 6.13 First stage component projected volume and mass for the 5 & 10-year trend in a 60
kV, 300 kW converter module................................................................................ 119
ix
6.14 Second stage component projected volume and mass for the 5 & 10-year trend in a 60 kV, 300 kW converter module........................................................................... 119
6.15 Estimated total volume and mass of each component category in a 60 kV, 300 kW
converter module. ................................................................................................... 119 6.16 5-year total projected component and complete system volume and mass for a 60
kV, 300 kW converter module. The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter............................. 119
6.17 10-year total projected component and total system volume and mass for a 60 kV,
300 kW converter module. The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter. .................................. 120
x
LIST OF FIGURES
Figure
1.1 Schematic of a simplified cascade boost converter. .................................................... 4 1.2 CPI gyrotron cross section. .......................................................................................... 6 1.3 CPI depressed collector configuration. ........................................................................ 7 2.1 General diagram of a generic DC-DC switch-mode converter.................................. 12 2.2 Single Stage Boost Converter .................................................................................... 14 2.3 Discontinuous Inductor Current. D is the switch duty ratio and ∆1 is the diode duty
ratio or the fall time of the inductor current.............................................................. 15 2.4 Continuous Inductor Current. During the fall time of the inductor current, the current
remains greater than zero. ......................................................................................... 15 2.5 Comparison of DCM to CCM (R=25 kΩ, f=10 kHz, L=3.3 mH)............................. 19 2.6 The CCM diode and inductor currents. High dif/dt occurring at diode turn-off....... 21 2.7 The DCM diode and inductor currents ...................................................................... 21 2.8 Simplified Cascade boost converter schematic.......................................................... 22 2.9 Example of the current waveforms of L1 (red), L2 (blue), and C1 (black). D is the
switch duty ratio, and ∆1 and ∆2 are the duty ratios of the diodes and fall time of the inductor current......................................................................................................... 23
2.10 Idealized Pspice circuit model using derived component values. Resistors R1, R2,
R3 were inserted into the model to avoid convergence problems. ........................... 33 2.11 Simulated output voltage of the second stage/converter. ∆V = 47.7 V, which
correlates to a voltage ripple of less than ± 0.5%..................................................... 34
xi
2.12 Simulated voltage across C1 and current through L1.............................................. 35 2.13 Simulated current through L2 with the second stage output voltage across C2. ..... 35 3.1 Bench top cascade boost converter prototype............................................................ 39 3.2 The IGBT equivalent circuit including, internal MOSFET and BJT, switch
capacitance, and drift region resistance, Rdrift. .......................................................... 42 3.3 The IGBT turn-off waveforms in a clamped inductive load. td(off): dealy time; tvr:
voltage rise-time; tf1: 1st current fall-time; tf2: 2nd current fall-time.......................... 42 3.4 Cross-section of the NPT IGBT................................................................................. 47 3.5 PNP transistor layers in the IGBT: Epeak occurs at the junction J2, and the depletion
region width, Wd, extends primarily into the n- drift region due to high doping concentration of the p+ body region. The x axis is the distance along the pnp layers, where the zero occurs at junction J2. ........................................................................ 47
3.6 Schematic of first stage components......................................................................... 57 3.7 Thermaflo E3045 heat sink profile. ........................................................................... 59 3.8 Schematic of second stage components..................................................................... 62 3.9 The IGBT stack with six IGBTs in series, operating as the second stage switch...... 64 3.10 The output Load with 10 series Ohmite, wire wound resistors for dissipation of the
1 kW output of the prototype. ................................................................................... 67 3.11 Voltage and current waveforms of two 3.3 kV IGBTs in series as the second stage
switch of the cascade boost converter with and output of 5 kV and 1 kW............... 70 3.12 Power loss waveform of the two 3.3 kV IGBTs in series. The integrated energy
loss is 126.5 mJ per pulse, which results in an average power loss of 1139 W........ 70 5.1 First stage DC output voltage; the average output voltage is displayed at 503 V, for a
voltage gain slightly of 5 from the 100 V input........................................................ 81 5.2 Cascade boost DC converter output voltage; the average output voltage is displayed
at 5010 V, for a voltage gain of approximately 10 from the 503 V first stage output.................................................................................................................................... 82
xii
5.3 First stage and second stage output voltages as input voltage is varied from 0 to 100 V, with constant switching duty ratios of .614 and .513 for the first and second stages respectively. ................................................................................................... 85
5.4 Efficiency of the individual stages and the overall converter.................................... 85 5.5 First stage experimental and simulated input currents when the converter is operated
with a 100 V input and 5 kVoutput........................................................................... 87 5.6 Second stage experimental and simulated input currents when the converter is
operated with a 100 V input and 5 kV output. .......................................................... 87 5.7 Turn-off voltage and collector current waveforms of the first stage IGBTs in parallel.
................................................................................................................................... 91 5.8 First stage turn-off power loss. The integrated turn-off loss = 4.83 mJ at 20 kHz for
98.57 W average loss. ............................................................................................... 91 5.9 Turn-off voltage and current waveforms of the second stage IGBT stack. ............... 93 5.10 Second stage IGBT stack turn-off power loss. The integrated turn-off energy loss =
11.6 mJ at 9 kHz for 104.7 W average loss. ............................................................. 93 5.11 First stage diode voltage and current waveforms. ................................................... 95 5.12 First stage diode power loss waveform. Integrated energy loss is 0.82 mJ per pulse
and average power loss is 1.67 W............................................................................. 96 5.13 Second stage diode voltage and current waveforms. ............................................... 97 5.14 Second stage diode power loss waveform. Integrated energy loss is 0.457 mJ per
pulse and average power loss is 4.13 W. .................................................................. 97 6.1 300 kW converter volume scaling from estimated technology trends..................... 121 6.2 300 kW converter mass scaling from estimated technology trends......................... 121 6.3 1.2 and 2.4 MW converter volume scaling using parallel 300 kW converter modules.
................................................................................................................................. 122 6.4 1.2 and 2.4 MW converter mass scaling using parallel 300 kW converter modules.
................................................................................................................................. 122 A.1 IGBT trigger module........................................................................................................129
xiii
A.2 Power oscillator....................................................................................................... 129 A.3 IGBT gate driver circuit.......................................................................................... 130 C.1 Experimental on-state forward conduction voltage and trend line of the International Rectifier IRGP30B120KD-E 1200 V, 60 A rated, Non-Punch Through (NPT),IGBT; Vg = 12.5 V. ........................................................................................................................ 133
1
CHAPTER 1 .0 INTRODUCTION
The demand for compact electrical systems has motivated size and weight
reduction of power conditioning architecture sub-systems. For military applications, the
government has funded the development of compact high voltage electrical systems for
combat vehicles that require large scale power conditioning. These systems include
electromagnetic launchers, electromagnetic armor, and electronic weapon systems [1-2].
These technologies have the potential for revolutionizing military engagement. However,
they face engineering challenges to meet the size and weight requirements for integration
on mobile platforms, in addition to technical risk mitigation and adhering to the stringent
reliability requirements for operation in military environments. The power conditioning
becomes a significant factor of the total size and weight of these systems, where new
technologies and innovation must develop highly compact and lightweight conditioning
architectures in order for such emerging military technologies to move forward.
The development of power conditioning technology has led to advancements in
the area of switch-mode power converters [3-4]. Switch-mode power conversion
topologies are highly common among electronic devices and power conditioning designs.
A switch-mode converter circuit topology familiar to the subject of power electronics is
the step-up, or boost converter [5-7]. The boost converter is a DC to DC converter that
simply steps-up, or boosts, the input voltage to a higher output voltage. Utilizing the
same circuit operation, AC to DC boost converters are used as power factor correction
(PFC) circuits for the front end of power conditioning systems requiring a unity power
2
factor interface with AC power sources. Generally, commercial boost converter circuits
are implemented in systems requiring power conditioning levels ranging from less than
10 W to multi-kilowatt, and have output DC voltages in the hundreds of volts range or
less, with step-up ratios on the order of 10. Converter designs in this regime have the
ability to exceed 90% efficiency [8-10]. The general operation principles of switch-mode
converters and typical boost converter design equations are discussed in this thesis, as a
background to the design of the cascade boost converter.
In converter designs for high voltage applications, high voltage switching is a
significant design challenge. Solid-state components rated higher than 1 kV can limit
switching frequency and efficiency due to typically higher switching loss, which impacts
component size, thermal management, and total power density. Fortunately, for solid-
state switch technology the capability of high voltage solid-state devices is advancing.
The pulsed power industry also has taken advantage of this technology as solid-state
switching provides advantages such as increased reliability, lifetime, control, and
provides the ability to create more compact system designs. For example, high voltage
thyratrons and spark gaps have been replaced by solid-state switches, and high voltage
power modulator designs have taken advantage of the solid-state technology [11-14].
Similarly, switch-mode converters and high voltage power conditioning systems benefit
with higher switching frequencies, greater power densities, and higher efficiencies from
improved, emerging solid-state switch technology. For instance, wide band-gap
semiconductor materials like silicon carbide (SiC) offer advantages, over existing silicon
(Si) devices, such as higher electric field breakdown strength, faster switching, and lower
3
switching loss. Already, 1200 V SiC diodes exhibit lower loss and can allow converters
to operate at higher frequencies. High voltage diodes with a voltage rating of 10 kV or
higher are anticipated to emerge as the first generation of high voltage SiC devices with
5-10 kV rated transistors subsequently available. A semiconductor paradigm shift of
mature wide band-gap devices for high voltage switching may occur within a 10-year
time frame. In addition to semiconductors, developing high voltage capacitor dielectrics
are enabling capacitive energy storage in smaller volumes, and nanocrystalline magnetic
core materials have already shown improvements in transformer and inductor core
reduction.
The circuit topology investigated in this research project is a high voltage
transformerless DC-DC switching converter, which has a significant potential for
reduction in size and weight through advances in the aforementioned SiC, capacitor, and
nanocrystalline technologies. The anticipated SiC technology will allow the converter to
operate at higher switching frequencies, thus shrinking passive components. Also,
expanded voltage capability will reduce the number of series devices in stacked assembly
designs. This converter is composed of two series arranged boost converters and
develops a high input to output DC-DC voltage step-up gain from the two stages. The
topology will suitably be referred to as the cascade boost converter, and a simplified
schematic is shown below in Figure 1.1.
4
R L
D 2 L 2 L 1 D 1
C 2 S 2 C 1 S 1 V s
Figure 1.1 Schematic of a simplified cascade boost converter.
A particular application for which the cascade boost converter is designed is the
power conditioning for high power microwave tubes. The Department of Defense
(DOD) has developed microwave architectures for integration onto airborne, sea, and
land vehicles. The Air Force has accelerated research and development of Directed
Energy systems using high-power microwave and laser technology, and this effort is
expected to continue well into the twenty-first century [15]. These Directed Energy
weapon systems can provide non-lethal tactical solutions for the military such as remote
disruption or destruction of enemy electronic systems and even physically stunning
enemy combatants with applied radiation on the subjects. Directed Energy weaponry
provides the United States with means for tactical advantage over the country’s
adversaries where casualty mitigation is an objective. The cascade boost topology is a
potential enabling technology for systems for mobile platforms by fulfilling power
conditioning size requirements. However, this converter is certainly not limited to high-
power microwave systems. The output can be tailored to meet the needs of a wide
variety of applications.
A typical high power microwave source is the gyrotron microwave tube.
Gyrotrons, originally developed in the 1960’s, were utilized for electron cyclotron
resonance heating of plasmas in fusion experiments [15]. Since the inception of the
5
Gyrotron, consortiums in Russia, France, Japan, and United States have developed
megawatt continuous power class tubes [15]. In a Gyrotron, a cathode at modest 40-85
kV voltage levels injects an electron beam into a 2-3 cavity structure [16]. The
continuous electron beam, after passing through the first cavity, produces a periodically
bunched beam [16]. An external magnetic field is also applied, imparting a helical
motion to the electron beam [16]. This helical motion allows the coupling of the electron
beam to a fast wave structure for extraction of the microwave power [16]. Gyrotron
tubes generate high power and high frequency microwave radiation that is applicable for
Directed Energy systems.
The predominant manufacturer of Gyrotrons in the United States, Communication
and Power Industries (CPI), has manufactured Gyrotrons up to 1 MW power levels at
efficiencies of 20-45% [17]. The typical efficiency of a single extraction cavity Gyrotron
is 20%, while multiple extraction cavities exhibit efficiencies of 40-45%. Gyrotrons with
an extraction efficiency of 40-45% and megawatt power levels are under development
[17].
The Gyrotron consists of a cathode, a ceramic metal housing, superconducting
magnets, a vacuum pump (VacIon) and a collector. A cross section of a CPI gyrotron is
shown in Figure 1.2. A 60 kV, 40A power supply is utilized to power the megawatt
output Gyrotron. In general, mega-watt class gyrotron tubes require the electron gun
cathode power supply to deliver 20 A or greater [18]. The body of the tube is biased at
+20 kV in the depressed collector mode of operation, where the collector is grounded
(depressed in voltage relative to the body) as shown in Figure 1.3. The 20 kV body
6
supply is a 50mA, highly regulated power supply. The 20 kV power supply is typically
regulated to +/- 0.1%. The efficiency of the Gyrotron is somewhat determined by the
regulation of the power supply according to CPI. Thus, the 60 kV supply must also have
a minimum regulation of +/- 0.5%.
Figure 1.2 CPI gyrotron cross section.
7
Figure 1.3 CPI depressed collector configuration.
The cascade boost converter has been selected to operate at 60 kV and 300 kW at
full power, based on the high current gyrotron power supply requirements, with the
ability to be modularized for higher power conditioning output by paralleling modules.
This modular approach extends the flexibility for many applications and provides
redundancy for increased reliability. Power regulation (+/- 0.5%) is achieved with
appropriate output filtering and a precise boost converter control system. The input for
the design of the converter has been selected at 1 kV, which requires a 60 times step-up
ratio for a 60 kV converter output.
Boost converter theory, an idealized converter design, an experimental cascade
boost converter prototype for design validation, and theoretical system scaling to mulit-
megawatt output levels is presented in the following chapters. The prototype converter
has demonstrated an output of 5 kV at 1 kW, stepped up from a 100 V input, for a total
step-up ratio of 50. The load utilized in the tests is a resistive load, and the converter was
designed for analysis and circuit demonstration in the laboratory environment, where the
(2) + 60 kV 40 A
_ Voltage Divider
for Sensing
(1) - 20 kV 50 mA
+
Collector
Body
1– Low current, highly regulated supply (+/- 0.1% regulation) 2– High current, moderately regulated supply (+/- 0.5% regulation)
Gyrotron
8
converter was operated at a constant input and output voltage. The scope of the prototype
converter analysis is centered on the main boost circuit components. This analysis
includes individual component power loss and performance in relation to the system
performance, namely the switches, diodes, inductors, and capacitors of the converter.
This research project also includes the review of high voltage solid-state switching theory
and switching designs of the cascade boost converter. Finally, the cascade boost
converter prototype is used to estimate the volume and mass of a 60 kV, 300 kW
converter designed for near-term, 5-year, and 10-year projected technology trends. The
scaling trend of the cascade boost converter demonstrates the dramatic reduction possible
for such a system, and projects the potential for the compact power conditioning systems
based on the topology of the cascade boost converter.
9
REFERENCES FOR CHAPTER 1.0 [1] J.A. Gaudet, “Research issues in developing compact pulsed power for high peak
power applications on mobile platforms,” Proceeding of the IEEE, vol. 92, No. 7, pp. 1180-1196, July 2004.
[2] I.R. McNab, “Developments in battlefield power technology,” in Proc. of Pulsed Power Conf., 1999, pp. 359-363 vol. 1.
[3] W. G. Homeyer, “Advanced power converters for More Electric Aircraft applications,” in Proc. of Energy Conversion Engineering Conference, 1997, pp. 591-596 vol. 1.
[4] H. Ohashi, “Power electronics innovation with next generation advanced power devices,” in Proc. of INTELEC, 2003, pp. 9-13.
[5] R.G. Hoft, Semiconductor Power Electronics, New York: Van Nostrand Reihold Company, 1986.
[6] D.W. Hart, Introduction to Power Electronics, Upper Saddle River, NJ: Prentice Hall, 1997.
[7] N. Mohan, T.M. Undeland, W.P. Robbins, Power Electronics, 2nd Edition. New York: John Wiley & Sons, 1995.
[8] C.A. Canesin, “Comparison of experimental losses among six different topologies
for a 1.6 kW boost converter, using IGBTs,” in Proc. of PESC, 1995, pp. 1265-1271 vol. 2.
[9] L. Huber, “A design approach for server power supplies for networking
applications,” in Proc. of APEC, 2000, pp. 1163-1169 vol. 2.
[10] J. Yungtaek, “A new, soft-switched, high-power-factor boost converter with IGBTs,” IEEE trans. on Power Electronics, vol. 17, pp. 469-476, July 2002.
[11] E.G. Cook, “Design and testing of a fast, 50 kV solid-state kicker pulser,” in Proc. of Power Modulator Conf., July 2002, pp. 106-109.
[12] M.P.J. Gaudreau, “Solid-state pulsed power systems for the Next Linear Collider,” in Proc. of Particle Accelerator Conf., 2003, pp. 547-549 vol. 1.
10
[13] W. Jiang, “Compact solid-State switched pulsed power and its applications,” Proceeding of the IEEE, vol. 92, No. 7, pp. 1180-1196, July 2004.
[14] M.A. Kempkes, “Crowbar replacement through solid-state opening switches [VED applications],” in Proc. of IVEC, 2004, pp. 271-272
[15] R.J. Barker, High-Power Microwave Sources and Technologies, New York: Institute of Electrical and Electronics Engineers, Inc., 2001.
[16] CPI Gyrotron Primer and Specifications Sheets.
[17] CPI Private Communication with Mr. Parent and Dr. Felch.
[18] R.L. Ives, “Design of a multistage depressed collector system for 1 MW CW gyrotrons. II. System consideration,” IEEE Trans. Plasma Science, vol. ED-27, pp. 503-511, April 1999.
11
CHAPTER 2.0 THEORETICAL CASCADE BOOST DESIGN
2.1 Switch-Mode Converters
The subject of switch-mode converters is a significant portion of power
conditioning electronics. The general design concept of switch-mode converters is the
delivery of controlled and regulated power from an unregulated source [1]. These
circuits are used in power processing systems integrated into power supplies, motor
control systems, computers, consumer and military electronics, electric transportation
drives, heating and cooling, and other applications where controlled and regulated power
is necessary [2]. Switch-mode converters are designed to sustain a constant output and
compensate variation from an unregulated power source. The focus of the following will
be on DC-DC switch-mode converters, which are designed for DC input and conditioning
of the DC output voltage. A high-level diagram of a DC-DC switch-mode converter is
shown in Figure 2.1. Here, the input and output diagnostics feed data to the controller.
The switch-mode converter’s diagnostics and control loop are designed to give the
necessary switching parameter compensation to maintain the regulated DC output.
12
Switch-mode converters operate by repetitively transferring energy from the input
source to the output load by controlled switching devices, hence the name switch-mode
converter. At steady state, the converter control system will maintain an average energy
transfer to the output by adjusting switching characteristics to account for unregulated
input variation. A controllable switching parameter is the switching duty ratio, which is
the ratio of on-time of the switching device(s) to the total time duration of the switching
period as seen in equation [2.1] below:
on onon
t tD = = tSwitching period Ts
f≡ , [2.1]
where f is the frequency in Hertz, and ton is the time the switch is conducting. The output
of switch-mode converters can be adjusted by altering the duty ratio of the switch, or
switches, which in turn adjusts the average energy transfer through the converter. This
control is called pulse width modulation (PWM).
Certain DC-DC switch-mode converter topologies are specifically designed to
step-up or step-down DC voltage. For instance, the buck converter topology creates a
Figure 2.1 General diagram of a generic DC-DC switch-mode converter.
Switching Converter
Unregulated DC
Regulated DC
Diagnostics
Controller
Load
13
less-than-unity voltage gain—it is designed to step-down a DC voltage to a lesser DC
voltage. The boost converter has a greater-than-unity voltage gain—it is designed to
step-up DC voltage. Also, some topologies, such as the buck-boost and the Ćuk
converter, are designed to do both—increase or decrease the DC output voltage
depending on the switching duty ratio. Thus stepping-up or stepping-down the voltage is
analogous to a transformer’s winding ratio in AC signal applications. However, the
controllability of the PWM allows switch-mode converters to have real-time adjustable
voltage ratios. The PWM controlled output compensates from variation in the input
source, or load, while delivering a steady DC voltage. Also, DC output filtering is
implemented in most converters for mitigation of the voltage ripple transferred to the
output from the active switching. For this reason, switch-mode converters are
implemented in applications where constant, regulated output is necessary.
2.2 The Boost Converter
The basic boost converter is comprised of an inductor, a switch, a diode, and a
capacitor for output DC filtering of the load. A schematic of the boost converter is
shown in Figure 2.2. The converter stores magnetic energy in the inductor and then
switches it to the output load, through the diode, with every switching period. The output
capacitor provides low-pass filtering, where the average diode current is delivered to the
load.
14
The average diode current through the load provides the output DC voltage, but
there is a certain amount of AC voltage ripple coupled to the output. The amplitude of
the AC voltage ripple is affected by the output capacitor, the impedance of the load, and
the switching frequency of the converter. If the output maximum voltage ripple is
specified to be ± 0.5%, the filter capacitance can be designed to meet this specification.
Figure 2.2 Single Stage Boost Converter
Deriving the gain equation for the boost converter is conditional on the
converter’s operational mode. A boost converter can be operated in two modes:
continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The
current waveform of the inductor indicates which conduction mode the converter is
operating. If the current in the inductor does not reach zero during the time when the
switch is open, the circuit is in CCM. If the boost circuit inductor current does go to
zero, it is in DCM. The inductor current for DCM and CCM is shown in Figure 2.3 and
Figure 2.4, respectively. The voltage gain in DCM and CCM is derived from the
principle of balanced inductor volt-second product, where the average voltage across the
inductor is zero during the steady state operation of the circuit.
15
Figure 2.3 Discontinuous Inductor Current. D is the switch duty ratio and ∆1 is the diode duty ratio or the fall
time of the inductor current.
Figure 2.4 Continuous Inductor Current. During the fall time of the inductor current, the current remains greater than zero.
For CCM, the derivation of the voltage gain is as follows. When the switch is
closed, the voltage across the inductor is equal to the supply voltage, Vs, where current
increases linearly through the inductor and switch. When the switch opens, the voltage
across the inductor is equal to the supply voltage minus the clamped voltage across the
capacitor, or output voltage, Vo. The inductor voltage is negative during this interval
(toff) and the inductor current will be transferred to the load, through the diode. The
average voltage, LV , across the inductor is equal to zero, as described in equation [2.2]
below:
[ ]L s s o1V = V DT (V - V )(1 - D)T 0T
+ = , [2.2]
DT toff
iL
IL
T
DT ∆1T
iL
Imax
T
16
where D is the duty ratio, T is the period, DT equals the time the switch on-time, and (1-
D)T equals the time the switch off-time. Solving for the ratio of output to input voltage,
using equation [2.2], will result in the following step-up voltage gain equation for CCM
is shown below:
o
s
V 1V (1-D)
=. [2.3]
A similar equation for DCM operation will also be derived. The inductor current
is shown in Figure 2.3, where ∆1T is the duration during which the inductor current falls
from Imax to zero. The time, ∆1T, is also the diode forward conduction time, where ∆1 is
the diode duty ratio. To determine the voltage gain in DCM, the same procedure is
followed as in CCM. The average voltage across the inductor, LV , during each period is
zero as shown in the following:
( )L s s o 11V = V DT+ V -V ∆ T =0T
⎡ ⎤⎣ ⎦ . [2.4]
The voltage gain from equation [2.4] yields the following relationship in equation [2.5]:
o 1
s 1
V (D+∆ )V ∆
= . [2.5]
17
The value of the interval ∆1, however, is dependent on the boost converter’s inductor,
switching frequency, switch duty ratio, and the output load as seen in equation [2.6]:
o1
s
V 2LV RDT
⎛ ⎞⎛ ⎞∆ = ⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠
. [2.6]
Inserting equation [2.6] into equation [2.5] yields equation [2.7] for the gain of a boost
converter in DCM:
2
o
s
V 1 2D RT= 1+ 1+V 2 L
⎛ ⎞⎜ ⎟⎜ ⎟⎝ ⎠
. [2.7]
2.3 Discontinuous Mode
The cascade boost converter has been designed using DCM due to the necessary
high voltage boost ratio and operation into a high impedance load. An important
advantage of DCM is that the boost converter can operate with a high step-up gain and
allow for reduced inductor size. Figure 2.5 displays a voltage step-up gain comparison of
a boost converter in DCM and in CCM. This shows a favorable linear relationship of the
gain with the switch duty ratio. Table 2.1 shows the CCM and DCM voltage gain ratios,
in relation to the minimum inductor value for operation in the CCM. The gain value for
both modes is independent of converter voltage input, output, or power specifications.
This shows that the inductor for CCM must be several times larger than the inductor used
18
in DCM for an equivalent step-up voltage gain. The inductor can consume a large
portion of the converter volume and mass, where power density of the converter can be
increased if the inductor size is minimized.
Unlike CCM, voltage gain for the discontinuous mode does not exclusively
depend on the switch duty ratio, D. Operating in DCM may have advantages over CCM
under the condition of a high impedance load, where the average output current is small.
For instance, in CCM, the duty ratio must be 90% of the switching period to achieve a
voltage gain of ten. In DCM, this gain can be accomplished with a duty ratio of 60%,
where ∆1 is 6.67% of the switching period. Operating at high duty ratios has
disadvantages, such as limited range for the control system to increase the duty ratio
further in order to maintain a regulated output. Thus, the converter’s ability to maintain a
constant output voltage is relatively limited in the CCM.
19
0
2
4
6
8
10
12
14
16
18
20
0 0.2 0.4 0.6 0.8 1Duty Ratio
Vol
tage
Rat
io
DCM
CCM
Figure 2.5 Comparison of DCM to CCM (R=25 kΩ, f=10 kHz, L=3.3 mH)
Table 2.1 Comparison of voltage gain and inductor values over a range of duty ratios and voltage gain ratios.
DCM inductor held at 3.3 mH; CCM Lmin adjusted to keep boost converter in CCM.
Duty Ratio CCM Gain CCM Lmin (mH) DCM Gain0.1 1.11 1098 2.430.2 1.25 976 4.270.3 1.43 854 6.120.4 1.67 732 7.980.5 2.00 610 9.850.6 2.50 488 11.710.7 3.33 366 13.580.8 5.00 244 15.440.9 10.00 122 17.31
0.95 20.00 61 18.240.98 50.00 24.4 18.80
Another important aspect of the DCM is a reduction of the reverse recovery loss
associated with typical power diodes in the boost circuits. The reverse recovery loss
occurs during the transient when the diode switches from conducting current in the
20
forward biased state to the reverse bias or off state. The reverse recovery current is
formed as residual junction charge is transferred out of the diode. The amount of reverse
recovery loss depends on the design of the diode, where power diodes and high voltage
diodes tend to recover more slowly than lower voltage rated high-speed diodes. Also, the
rate at which the current falls from conducting to blocking influences the peak reverse
recovery current, where higher dIf/dt generally results in higher peak reverse recovery
current. Manufacturers typically list reverse recovery characteristics from a given current
level and rate of current fall. The reverse recovery current, multiplied by the rising
reverse voltage, will result in power loss. Figure 2.6 shows the diode current in the
CCM. The high diode dif/dt in the CCM occurs as the diode turns to the off state, and the
reverse recovery can become significant. Additionally, the reverse recovery current
increases switch loss at turn-on, since the reverse recovery current will contribute to the
switch turn-on current level in the CCM.
The DCM reduces the peak reverse recovery current since the dIf/dt of the diode
is equal to the dIL/dt of the inductor, which can be orders of magnitude lower. The
diagram in Figure 2.7 of DCM diode and inductor currents shows the inductor-limited
dIf/dt diode current. Reduction of the reverse recovery loss can be lessened further by
use of new diode technology. Recent manufacturers such as Cree Inc. have developed
Silicon Carbide (SiC) Schottky diodes with 1200 V and 10 A ratings, that reduce reverse
recovery loss dramatically. Schottky diodes have no minority carrier stored charge, as it
is a majority carrier device, and with SiC, these diodes can have voltage ratings nearly
ten times that of Si Schottky diodes.
21
Figure 2.6 The CCM diode and inductor currents. High dif/dt occurring at diode turn-off.
Figure 2.7 The DCM diode and inductor currents
2.4 Cascade Boost Converter Design
The following section details the principles and the derivation of the system
equations used to determine component values under specified switching parameters,
voltage ripple, and load. Figure 2.8 below is an idealized schematic of the two stage
cascade boost converter. The analysis will determine L1, L2, C1, and C2 in an algebraic
form.
dID/dt = IL/dt
Diode current Inductor current
i(t)
High dif/dt
Diode current Inductor current
i(t)
0
IL(t) ID(t)
22
R L
D 2 L 2 L 1 D 1
C 2 S 2 C 1 S 1 V s
Figure 2.8 Simplified Cascade boost converter schematic.
2.4.1 Voltage Gain and Inductor Derivation
The cascade boost converter transfers energy through two series boost converter
stages where the output voltage of the second stage is maintained across the load, RL.
The resultant converter voltage gain is the product of the first stage voltage gain and
second stage voltage gain. This voltage multiplication is achieved without use of a
transformer. Each stage operates just as any boost converter, except the first stage does
not operate into a resistive load; rather the stages are coupled together by a controlled
average current flow through the stages. The first stage average output current is equal to
the average input current of the second stage. The effective load impedance for the first
stage will change if the average current through L2 increases or decreases from the PWM
controlled second stage. Thus, the first stage switching duty ratio must be controlled to
compensate for any changes in the average current drawn from the second stage.
The energy transfer process during steady state operation is as follows. During
time, DT or ton, of the switches, a linear-rate rise in current is drawn through L1 from the
DC input source, and L2 similarly draws current out of C1. An example of the inductor
current waveforms is illustrated in Figure 2.9. When both switches are open (time
23
duration T-DT), current through diode D1 flows through C1, and simultaneously, current
flows through diode D2 to the output load, filtered by C2. Also shown in Figure 2.9 is the
current through C1, where the charge flowing out of C1, during DT, must equal the charge
flowing into C1 during ∆2T, to maintain a constant capacitor voltage. This shows that
changes in the average second stage inductor current will affect accumulative charge
storage in C1 and thus first stage DC output voltage.
Figure 2.9 Example of the current waveforms of L1 (red), L2 (blue), and C1 (black). D is the switch duty
ratio, and ∆1 and ∆2 are the duty ratios of the diodes and fall time of the inductor current.
The calculation of the inductance values for inductors L1 and L2 is found by
assuming the circuit is in the steady state mode. As mentioned above, the average current
of the capacitors is zero, and the voltage across them equalizes to a constant DC voltage;
the average rate of charge input equals the average rate of discharge. Therefore the
integral of current over one period is zero:DT T
c c
0 DT
i dt= i dt∫ ∫ , charge flows into the capacitors
∆2T
iC1
iL1 iL2
T
DT
∆1T
i(t)
L1 Current L2 Current C1 Current
24
from 0 to DT and out of the capacitors from DT to T. If the net current per period is zero,
the net change in voltage per period is also zero: -∆vc = +∆vc. The governing equation of
the capacitors’ voltage is shown below in equation [2.8]:
c dt
c iQv = =
C C∆
∆ ∫ . [2.8]
The following analysis will find the relationship of L1 and L2 using steady state
voltage equalization of C1, where -∆vc1 = +∆vc1 per period. For simplicity, the analysis
also assumes switches S1 and S2 are switching synchronously, where the duty ratio and
period in the following derivation applies to both switches. However, asynchronous
switching may be desirable and will be discussed in section 2.5.
The illustration of the inductor currents that will be discussed is shown in Figure
2.9. The linear increase of the current through L2, while the switches are closed, has a
slope of VC1/L2 for time duration of DT. Therefore, the integral of current flowing out of
capacitor C1 and through inductor L2 is shown below in equation [2.9]:
1 11
DT 2C C
c 2 20
1 V -V (DT)i dt (DT) - DT2 L 2L
⎛ ⎞ = =⎜ ⎟⎝ ⎠∫ . [2.9]
The negative change in the C1 voltage while the switches are closed, then, is given by:
25
11 1
DT 2C
C C 1 2 10
1 V (DT)-∆v = i dt= C 2L C∫ . [2.10]
Using the same process when the switches are open results in a slightly more
complicated solution for +∆iC1 and +∆vC1. This is more complicated because while
charge is being added to C1 by iL1, charge is also being removed from C1 by iL2 during the
time ∆2T. Integrating the current through C1, when the switches are open, yields the
positive change in voltage:
11 1
Td C
C C 1 21 1 1 2DT
1 1 1 V 1 V+∆v = i dt= ∆ T DT- ∆ DTC C 2 L 2 L
⎛ ⎞⎜ ⎟⎝ ⎠∫ . [2.11]
Setting –∆vC1 = +∆vC1 and solving for the average capacitor voltage, VC1, results in the
equation [2.12] below:
12 1
C s1 2
L ∆V = VL D+∆
⎛ ⎞⎜ ⎟⎝ ⎠
. [2.12]
Since the design of the cascaded boost converter’s voltage gain or “boost” in the
first and second stages is calculated in DCM, the voltage gain of both stages is in the
form of equation [2.5]. The first stage voltage gain and second voltage gain are shown
below in equations [2.13] and [2.14]:
( )1 1C
s 1
D+∆V =V ∆
, [2.13]
26
2
1 1
C o 2
C C 2
V V (D + ∆ )= =V V ∆
, [2.14]
where the second stage output voltage, VC2 is the cascade boost output voltage, Vo.
The values of ∆1 and ∆2 can be solved from [2.13] and [2.14] respectively, given
the duty ratio value, D, and the voltage gain for both stages. Once ∆1 and ∆2 are known,
the value of L2 is found by using equation [2.6] and ∆2 as in equation [2.15]:
12 2
2 2C
C
V RDTLV
⎛ ⎞⎛ ⎞= ∆⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠
. [2.15]
After solving for L2, L1 is found using equation [2.12], as shown in the following
equation [2.16]:
11 2
2 1
VL LD V
s
C
∆⎛ ⎞= ⎜ ⎟+ ∆⎝ ⎠. [2.16]
This concludes the derivation of L1 and L2 given the output load resistance,
voltage gain per stage, duty ratio, and switching period with synchronous switching. The
derivation assumes ideal circuit parameters, where realistic circuit losses absorb energy
which lowers the gain and the output voltage. Such losses are analyzed in the cascade
boost converter prototype and are explained in the chapters to follow.
27
2.4.2 Filter Capacitors
As a design parameter, the capacitor C1 and C2 values must also be derived. The
values of these capacitors must fulfill the system requirements for voltage ripple
regulation. The voltage ripple is the ratio of the varying AC component to the average
DC value, and is commonly expressed in percentage. For system volume and mass
minimization, the capacitance values should not greatly exceed the value necessary for
the specified voltage ripple, where extraneous capacitance will consume extra volume
and mass of the system.
For the capacitor C1, the ratio of peak-to-peak AC voltage to DC voltage is
calculated with equation [2.17]:
C1
1 1
v ( Q/CV VC C
∆ ∆ )= , [2.17]
where VC1 represents the DC voltage value and ∆vC1 is the peak-to-peak magnitude of the
voltage ripple. The charge transfer ratio ∆Q, or the current flowing out of the capacitor
when the switches are closed, is used in the calculation, to simplify the integration. The
charge transfer ∆Q is:
C1C1
2
1 V∆Q ∆i dt (DT) DT2 L
⎛ ⎞= = −⎜ ⎟⎝ ⎠∫ . [2.18]
28
The results from equation [2.18] can be used to calculate the ripple in capacitor C1, as
given in equation [2.19]:
2
C1
C1 1 2
∆v (DT)V 2C L
= . [2.19]
The voltage ripple for the output capacitor, C2, is more complicated, but the
procedure is similar. The change in the capacitor charge is found by integrating the
amplitude of current above the average current, Io, flowing through the diode, where the
average diode current is equal to the DC output current, Vo/RL. Equation [2.20] below is
the voltage ripple across C2 and RL:
( )C2 2 o C112 C2 2 o
C2 o C1 2
∆v L I V2C V ∆ T DT IV V V L
− ⎡ ⎤⎛ ⎞⎛ ⎞= − −⎜ ⎟⎜ ⎟⎢ ⎥−⎝ ⎠⎝ ⎠⎣ ⎦, [2.20]
where VC2 is the DC output voltage and ∆vC2 is the peak-to-peak AC voltage.
Therefore, with the voltage ripple solved in terms of design parameters, the
capacitance values can be found. The equations [2.21] and [2.22] below derive the
values of capacitors C1 and C2 in terms of the voltage ripple across C1 and C2,
respectively:
2
1C1
2C1
(DT)C ∆v2 LV
= ; [2.21]
29
( )C22 o C11
2 2 oo C1 2
L I VC 2∆v ∆ T DT IV V L
− ⎡ ⎤⎛ ⎞⎛ ⎞= − −⎜ ⎟⎜ ⎟⎢ ⎥−⎝ ⎠⎝ ⎠⎣ ⎦. [2.22]
2.5 Asymmetrical Switching
Switching loss is a crucial parameter for consideration in the design of the cascade
boost converter. The average power loss in the switches is proportional to the switching
frequency from the energy lost per transition. Maximizing the switching frequency per
stage, while operating within the specified power loss, can optimize the inductor and
capacitor values for improved system power density. For instance, asymmetrical
switching allows the first stage to be operated at a higher switching frequency
independently of the second stage to take advantage of typically faster, lower voltage
rated switches of the first stage.
Asymmetrical switching of the first and second stages is not difficult to achieve,
given that the capacitance of C1 will satisfy the specified voltage ripple regulation
requirement. Capacitor C1 will then couple both stages with a steady DC voltage, and
both stages can have independent switching frequencies. The primary concern is to
control the steady state current and the subsequent DC voltage across C1 and C2.
One method for independent switching design is to first approach the circuit as a
symmetrically switching circuit. The inductance values are solved as they are solved in
equations [2.15] and [2.16]. Because the inductor values are inversely proportional to the
30
switching frequency, the inductors are scaled proportionally with a change in the
switching frequency in each stage. For instance, if the first stage is to be operated with a
ten times higher switching frequency than the second stage, the inductance values can
initially be solved using a symmetrical switching design with the first stage inductor L1
scaled to one tenth of the initial value. The reduced inductor value creates a
proportionally steeper inductor current slope, and the average current flowing into C1
from the first stage will remain as in the symmetrical switching case since the time
interval, D1T1, when the switch is closed would change in proportion to the change in
frequency. Therefore, the average current flowing into C1, C1I , in equation [2.23] shows
that if D1T1 is reduced by one tenth, L1 must be reduced by the same factor as seen in
equation [2.23] below:
s sC1 1 1 1 1 1 1 1
1 1 1
1 1 V 1 VI = ∆ T D T = ∆ D TT 2 L 2 L
⎛ ⎞⎛ ⎞⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠
. [2.23]
The preceding discussion and relation of the inductance to the switching frequency
per stage allows for the asymmetrical switching between stages. With the ability to
operate the stages independently, maximum switching frequency for each stage can be
accomplished. Maximized switching frequency results in minimized inductor values and
reduced inductor volume and mass.
31
2.6 Initial Design Values and Simulation Results of an Idealized Model
The inductor and capacitor values in the cascade boost converter are determined
from the equations in Chapter 2. These values were used to simulate an idealized circuit
model of the cascade boost converter with an output of 5 kV and 1 kW. Also the output
regulation has been simulated for a ±0.5% voltage ripple. The circuit simulation results
verify the circuit equations which were used to derive the circuit component values. The
circuit model was created and simulated using Orcad Pspice. The circuit model and the
associated circuit element values are shown in Figure 2.10.
In order to use the equations in Chapter 2, certain values must be specified. These
values are given below and were applied to equations [2.13] through [2.16]. A judgment
was made for the step-up ratios and switching frequencies of the first and second stage,
based on the load impedances per stage and the limiting peak inductor currents to limit
power loss and magnetic field radiation. Also, the second stage switching frequency is
limited to half of the first stage switching frequency due to higher anticipated switch loss.
The cascade boost efficiency must operate at 70% or higher; it has been assumed that a
converter operating at less than 70% efficiency will be unacceptable for the end user,
since heat removal can become a significant issue for high power converters. The
asymmetrical switching frequencies of the first and second stages were accounted for, as
discussed in section 2.5. Also, the values of L1, L2, C 1, and C2 were determined on the
basis of constant input voltage, constant gain, and constant output voltage. Due to
asymmetrical switching, the capacitance value of C1 was determined empirically by
sweeping the capacitance to attain the specified voltage ripple in the first stage output.
32
The following values were used as an initial parameter space to begin circuit modeling of
the converter. In the actual prototype cascade boost converter, the parameters were
modified, which will be discussed in Chapter 5.
1st stage gain = 5
2nd stage gain = 10
1st stage switching frequency = 20 kHz
2nd stage switching frequency = 10 kHz (limited due to switch loss)
Duty ratio of both stages = 0.5
Load resistance = 25 kΩ
± 0.5% or less Voltage ripple on C1 and C2
Efficiency = 70% or higher (specification for experimental circuit only)
The circuit values derived from equations [2.13] through [2.16]:
∆1 = 0.125; ∆2 = .055
L2 = 3.4375 mH (rounded down to 3.4 mH)
L1 = 76.6 µH
C1 = 28 µF
C2 = 0.383 µF(rounded up to 0.4 µF)
33
R1
.0001
D1
Vg2
TD = 0
TF = 1nPW = 50usPER = 100us
V1 = 0
TR = 1n
V2 = 1
D2R2
.0001
+-
+
-
S2
S
VON = 1.0VVOFF = 0.0V
R3.001
L1
76.6uH
L2
3.4mH
Vs100v
C20.4u
0
C128u
RL
25000
+-
+
-
S1
S
VON = 1.0VVOFF = 0.0V
Vg1
TD =
TF = 1nPW = 25usPER = 50us
V1 = 0
TR = 1n
V2 = 1
Figure 2.10 Idealized Pspice circuit model using derived component values. Resistors R1, R2, R3 were inserted into the model to avoid convergence problems.
The non-idealities existing in the model are negligibly small and do not affect the
converter output. The switches in the model are ideal, but incorporate 1 mΩ impedances
during the on-state. The resistance values of R1 and R2 were added as resistance for
simulation convergence, and the diodes have an internal forward voltage of 0.7-1.0 V.
The total power loss from the non-idealities is approximately 2 W, leading to a model
efficiency of 99.8%. These low losses can be neglected in the model with the efficiency
nearly ideal. The output voltage waveform generated by Pspice, in Figure 2.11, shows an
average DC voltage of about 5.07 kV with a voltage ripple of less than ± 0.5%. The
output is greater than 5 kV since L2 was rounded down to 3.4 mH from 3.4375 mH,
which slightly increases the peak inductor current and average charge transfer into C1.
The observed peak-to-peak magnitude of the ripple is 47.7 V, which correlates to a
0.94% peak-to-peak voltage ripple result. The ± 0.5% voltage ripple, specified above, is
34
fulfilled with a 0.4 µF capacitance for C2, which was rounded up from the calculated
value of 0.38 µF.
Figure 2.12 shows the voltage across capacitor C1 and the current through L1.
The peak-to-peak voltage ripple across C1 is calculated to be about 0.94% with a
capacitance of 28 µF. The voltage ripple meets the specification of ± 0.5% or less.
Figure 2.13 shows the voltage across capacitor C2 and the current through L2. The
current waveforms through L1 and L2 show the ∆1 and ∆2 duty ratio values of
approximately 0.125 and .055 respectively, which are in agreement with the calculated
values found with equations [2.13] and [2.14]. The current waveforms also indicate the
current peak as 33 A in L1 and 7.5 A in L2. Since the peak inductor current corresponds
to the current level which the switches must turn off, these current waveforms can be
used to select the solid state switches, estimate the switch loss and heat sink size, and
design the inductors for the experimental circuit.
Figure 2.11 Simulated output voltage of the second stage/converter. ∆V = 47.7 V, which correlates to a voltage ripple of less than ± 0.5%.
Output Voltage
5
5.02
5.04
5.06
5.08
5.1
5.12
5.14
0 100 200 300 400 500Time ( µs )
Out
put V
olta
ge (
kV )
∆V = 47.7 V
35
Figure 2.12 Simulated voltage across C1 and current through L1.
Figure 2.13 Simulated current through L2 with the second stage output voltage across C2.
The simulation of the idealized circuit model verifies the derived equations of
Chapter 2. Losses in a practical circuit model will affect the cascade boost converter
C1Voltage and L1Current
490
495
500
505
510
0 25 50 75 100 125Time ( µs )
C1
Vot
lage
( V
)
-505
10152025
3035
L1 C
urre
nt (
A )
C2 Voltage and L2 Current
5.04
5.05
5.06
5.07
5.08
5.09
5.1
0 25 50 75 100 125
Time ( µs )
C2
Vol
tage
( kV
)
-1012345678
L2 C
urre
nt (
A )
36
voltage gain, where increasing the duty ratio of both stages is necessary to overcome such
losses. Increasing the duty ratio, however, incurs higher peak inductor current, and thus,
higher current switch current and resistance loss. The losses to consider in the cascade
boost converter appear to be a result of the switching loss and the inductor loss. Other
losses include diode loss, and series resistive loss in the capacitors and inductors.
However, the idealized circuit model results demonstrate the circuit equations in Chapter
2, and show the interaction of the circuit component values.
37
REFERENCES FOR CHAPTER 2.0 [1] N. Mohan, T.M. Undeland, W.P. Robbins, Power Electronics, 2nd Edition. New
York: John Wiley & Sons, 1995.
[2] D.W. Hart, Introduction to Power Electronics, Upper Saddle River, NJ: Prentice Hall, 1997.
38
CHAPTER 3.0 CASCADE BOOST CONVERTER PROTOTYPE DESIGN
The cascade boost converter prototype has been designed and built to satisfy a DC
output of 5 kV, into a 25 kΩ load, from a 100 V DC source using cascaded boost circuits,
and maintain a +/- 0.5% output voltage ripple regulation. The design goals are
summarized in Table 3.1. This system has been designed with commercial off-the-shelf
(COTS) components, and is a bench top system for the analysis of circuit parameters
such as switch, diode, and inductor loss. A photograph of the bench top prototype
converter is shown in Figure 3.1. Switch theory and design involved in the cascade boost
converter is discussed in this chapter, where the voltage requirements for the second stage
switch, diode, output capacitance, and inductor must be designed to the converter’s
output voltage of 5 kV. This requires COTS switches, diodes, and capacitors to be
arranged in series, and requires adequate high voltage insulation within the second stage
inductor. The implementation of leading inductor core technology, and stacked series
device designs for the second stage, also facilitates scaling to higher power levels for
future designs. Fortunately, the first stage output of 500 V allows for conventional use of
widely available commercial components in this voltage range. This chapter describes
the cascade boost converter circuit design and experimental setup, and highlights the
switching theory used in the design of the second stage switch.
39
Table 3.1 Cascade boost converter prototype design goals.
Voltage Input 100 V Voltage Output 5 kV Power Output 1 kW
Output Voltage Regulation
+/- 0.5%
Figure 3.1 Bench top cascade boost converter prototype.
3.1 IGBT Switching Design Theory
The Insulated Gate Bipolar Transistor is a hybrid of a bipolar-junction transistor
(BJT) and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and has
accrued success has a high power solid state switching device for its fast switching, low
conduction loss, and high impedance control requirement. These qualities are favorable
for the cascade boost converter and applications such as SMPS, power converters, and
40
motor control. The implementation of IGBTs in the cascade boost converter will be
discussed in sections 3.2-4, where the first and second stage components will be covered.
The equivalent circuit of an IGBT is shown in Figure 3.2. The terminology for
the IGBT terminals is the following: the collector is the anode, the emitter is the cathode,
and the gate is the control terminal. The IGBT can be modeled as a MOSFET controlled
BJT, where the MOSFET front end forms the high-impedance gate input. Similar to the
MOSFET, the applied voltage from gate to emitter above the threshold level turns the
device on, and a voltage below this threshold voltage turns the device off. The low on-
state collector to emitter resistance is inherent to the conducting properties of the BJT
portion of the IGBT. The IGBT, in effect, has favorable qualities of both the MOSFET
and BJT. However, IGBTs with ratings greater than 1 kV are commonly used in
applications of 100 kHz or less, since switching loss tends be too great at higher
frequencies. The MOSFET, with a faster switching speed but higher on-state resistance,
are ideal for low power switching at frequencies in the kilohertz to megahertz range. As
a compromise between the MOSFET and the BJT, the IGBT was selected as the switch
of choice.
The frequency limitation of the IGBT switches can be linked to input and output
mechanisms of switching losses due to the MOSFET and BJT, respectively. In the
cascade boost converter application, the turn-off operation is of primary concern as the
switches turn-on with zero current conduction and turn-off current at the peak inductor
current. Two significant factors that affect the turn-off switching time and turn-off
energy loss of IGBTs will be the focus in the following theoretical IGBT switching
41
discussion. These factors included the internal IGBT capacitance of the MOSFET
structure and the slowly decaying current “tail” during turn off due to the BJT portion.
3.1.1 IGBT Capacitance
The switch capacitances commonly noted on IGBT data sheets include the input
capacitance, Cies, the reverse transfer capacitance (Miller capacitance), Cres, and the
output capacitance, Coes. These capacitance values vary with Vce, and capacitance versus
Vce curves also are typically provided on data sheets. The input capacitance may affect
the gate drive requirement, which is made up of Cres plus the gate to emitter capacitance,
Cge (Cies= Cres+ Cge). The output capacitance may affect the output circuit and is equal to
the collector to emitter capacitance, Cce, plus the Miller capacitance, Cres (Coes= Cce+ Cres).
The capacitances of the equivalent circuit are shown in Figure 3.2, along with the drift
region resistance, Rdrift, which will be discussed in section 3.1.2. The charge stored in the
input capacitance is the only charge that is to be transferred during switching of the
MOSFET, and thus contributes to the loss in the IGBT [1]. The turn-off transition
waveforms are illustrated in Figure 3.3. The MOSFET portion governs the first three
time intervals of the turn off transient: the turn-off delay time, td(off), the voltage rise
time, tvr, and the first interval of current during turn-off, tf1 [1].
42
Figure 3.2 The IGBT equivalent circuit including, internal MOSFET and BJT, switch capacitance, and
drift region resistance, Rdrift.
Figure 3.3 The IGBT turn-off waveforms in a clamped inductive load. td(off): dealy time; tvr: voltage rise-
time; tf1: 1st current fall-time; tf2: 2nd current fall-time.
The gate drive circuit has a significant effect on the switching behavior of IGBTs
[2-4]. In general, increasing the rate at which charge is extracted from the gate, which is
stored in the Cies, will shorten the MOSFET switching time and lower switching energy
loss [5]. This is because the gate drive circuit is similar to a capacitor
charging/discharging circuit. For example, the gate driver voltage charges or discharges
the IGBT input capacitance with a time constant of RC G iesR Cτ = , where RG is the total
resistance of the drive circuit, and Cies is the IGBT input capacitance. The total input
MOSFET
BJT
tvr tf1
tf2
td(off)
vce(t)
ic(t)
vge(t)
0
0
t
tvth
Gate
Collector
Emitter
Cce
Cge
Ccg
pnpBJT
MOSFET
Rdrift
Cies= Cres+ Cge Coes= Cce+ Cres Cres=Ccg
43
capacitance is fixed internal to the IGBT, and the external gate resistor is used to control
the gate charging and discharge rate. Using small external gate resistance reduces the
time constant and increases the peaks of the gate current pulses. Consequently, as the rate
at which the capacitance is charged and discharged is increased, faster turn-on and turn-
off of the IGBT will result, due of the faster switching of the MOSFET portion.
However, a minimum gate impedance must be considered in relation to the IGBT
application. Switching stress on the device affects reliability and lifetime. The magnitude
of current and voltage, along with high dvce/dt and dic/dt rates, can cause damage to the
IGBT. For instance, the gate resistor must be made large enough to prevent IGBT latch-
up from high collector to emitter voltage time-rate of change (dvce/dt), and to provide
noise immunity in the gate circuit [1]. Latch-up occurs when the pnpn regenerative
action results from the parasitic thyristor within the IGBT doping structure, and the gate
can no longer control the device to turn-off. Furthermore, controlling the switch rate with
the gate impedance reduces the effects of stray circuit inductance in series with the IGBT
collector, which may result in overshoot of Vce during turn-off from high -dic/dt and lead
to increased power loss or even device failure. Also, the external resistor will dampen
the ringing from the inductance in the gate circuit that may cause the gate voltage to ring
above the threshold voltage, resulting in spontaneous turn-on. With paralleled devices
that have varying lengths of gate connection, the gate resistance lowers the effect of
asymmetrical gate lead inductances that may cause triggering delay and asymmetrical
current sharing among the devices [6]. The main consideration is that the minimum gate
resistance must be designed based on the trade-off of mitigating switching energy loss
44
and the factors of insidious transient effects that can reduce the IGBT reliability and
lifetime.
The input capacitance is an important parameter to consider for high current,
switching applications, where fast turn-off is important to limit turn-off loss. The IGBT
modules with current ratings of approximately 100A or greater use several IGBT chips in
parallel to share current. When chips are paralleled, the input capacitance increases
proportional to number of dies in parallel. This creates a large equivalent input
capacitance of the module to charge and discharge during switching. The input
capacitance along with the corresponding stray inductance from gate wire bonds limits
the IGBTs gate drive bandwidth [6]. Utilizing the device datasheet information for input
capacitance information, the gate driver must be designed for the IGBT input capacitance
to meet the design specifications for switching speed and power loss. Such a gate driver
must have low resistance output drivers and low stray inductance in order to compensate
for high capacitance. The gate drive requirements for a specific device’s input
capacitance must be met, and the charging/discharging rate of the capacitance must be
considered for mitigation of switching loss. However under certain applications, device
reliability and lifetime during switching may be trade-off factors to fast switching.
3.1.2 The Turn-off Transient of IGBTs
The portion of the turn-off switching transition following the charge extraction of
the input capacitance, or the fourth and final time interval in Figure 3.3, is the decay of
45
the collector current before the IGBT completely turns off. This time interval exhibits an
exponential-like current decay, and has been commonly termed the current “tail”. The
current tail is a result of the Bipolar Junction Transistor (BJT) portion of the IGBT’s turn-
off process. The BJT portion is a pnp type transistor made of the p-type collector, n-type
drift region, and the p-type body. Figure 3.4 shows the cross-section of a Non-Punch
Through (NPT) type IGBT, where the p+ body and p+ collector are highly concentrated p-
typed doped regions, and the drift region is a lower concentrated n-type doped region.
The depletion region of the NPT IGBT, developed by a reverse voltage in the off-state,
does not extend past or “punch through” the n- drift region. Conversely, the Punch
Through (PT) type IGBT implements a thin, highly concentrated, n-type buffer layer
adjacent to the p+ collector and allows the depletion region to extend through the n- drift
region and stop in the n-type buffer layer. The NPT is a common type of IGBT for high
voltage ratings due to excellent thermal properties such as negative temperature
coefficient of resistivity and high thermal reliability [6]. However, as will be shown in
this section, increasing the voltage ratings of NPT type IGBTs can increase the turn-off
transition time [7]. Therefore synchronously switching multiple low voltage rated IGBTs
in series can lead to faster switching compared to a single high voltage rated IGBT,
which is exemplified later in section 3.4, with the design of the second stage switch.
When the NPT IGBT is reversed biased, the p-n junction, J2, can be modeled as
an abrupt p+n- junction of a reverse biased NPT PiN diode [1]. A reverse biased junction
of J2 is shown in Figure 3.5. The peak electric field, Epeak, occurs at this junction, and the
46
field is zero at the depletion width edges. The electric field slope depends upon the
background semiconductor doping concentration as shown in equation [3.1]:
0
( ) B
s
dE x Nqdx ε ε
= , [3.1]
where NB is the background doping concentration of a semiconductor device, ε0 is the
electric permittivity of free space, and εs is the relative permittivity of the semiconductor.
In the IGBT, electric field expands over the drift region primarily, due to a relatively low
donor doping concentration, ND, compared to the p+ body acceptor doping concentration,
NA. The electric field slope is much steeper in the higher doping concentration region,
and will therefore not penetrate as far into the p+ body, based on equation [3.1]. Also, by
definition, the NPT type IGBT depletion region width never exceeds the drift region
without device breakdown. Therefore, the minimum drift region size, ldrift, is equal to the
depletion region width, Wd, at breakdown (depletion width is maximum).
47
Figure 3.4 Cross-section of the NPT IGBT.
Figure 3.5 PNP transistor layers in the IGBT: Epeak occurs at the junction J2, and the depletion region
width, Wd, extends primarily into the n- drift region due to high doping concentration of the p+ body region. The x axis is the distance along the pnp layers, where the zero occurs at junction J2.
Therefore, the drift region thickness ldrift and NB are designed to hold off a
specified reverse voltage. However, when the IGBT is fully on, the resistance of the drift
p+ body
p+ collector n- drift region
Wd J2 J1
E(0)=Epea
x
dE(x)/dx xn xp
E(x)
ldrift
n- drift region
p + body n+ n+
Collector Contact
Gate Contact
Emitter Contact
GateOxide
J2
J1
p + collector
48
region becomes a component of the total on-state power loss, where Rdrift, is shown in the
equivalent IGBT circuit in Figure 3.2. The resistance of the drift region is mitigated as
minority carriers are injected from the p+ collector due to the forward biased junction J1.
The diffusion current density of injected free electrons and holes significantly affect the
drift region conductivity, which allows for low forward on-state voltage at high current
density levels. This minority carrier conductivity modulation mechanism is used in
devices such as BJTs and thyristors. When excess charge carrier concentration exceeds
the background doping concentration of a region by several orders of magnitude, a
condition of high level injection exists. Due to the space-charge neutrality condition, the
presence of free electrons is equally high, creating a plasma-like region of free charge
effectively distributed evenly within the drift region.
When the MOSFET portion turns off, the base current into the pnp BJT is
stopped, and the minority carrier injection of holes into the drift region halts. After the
BJT base current is cutoff and J1 is no longer forward biased, the excess carriers that have
been injected from the p+ collector remain stored in the drift region, and must recombine
for the IGBT to fully turn off. The recombination of the carriers within the drift region
drives the current tail at turn-off, which decays at a rate that depends on the carrier
lifetime [6].
The effect of the drift region thickness, and the voltage rating of the IGBT, on the
current tail can be shown using general equations found in semiconductor device theory.
As discussed earlier, the drift region thickness and doping concentration must be
designed to handle the depletion region width at the device’s specified maximum voltage
49
application. Using the peak electric field, Epeak, at J2 the depletion region penetration into
the p-body and the drift region can be found. Using Guass’s law and integrating the
charge within the electric field, the peak electric field is given by
0 0
A p D npeak
s s
qN x qN xEε ε ε ε
= = − , [3.2]
where xp is the distance of the depletion region in the p-body, xn is the distance into the
drift region, and εs is the relative permittivity of silicon. The depletion region width, Wd,
is the sum of xp and xn, and again the electric field ramps linearly from the edge of the
depletion region to the peak field, Epeak, as shown in Figure 3.5. By space-charge
neutrality, the charge from both sides of a p-n junction must be equal where,
A p D nqN x qN x= − . [3.3]
Since the doping concentration of the acceptor doped p-body side is much greater than
the n-type drift region in the IGBT, the distribution of the depletion region can again be
simplified as only reaching into the drift region, by equations [3.1] and [3.3]. Therefore,
from equation [3.2], the depletion width Wd in the drift region can be expressed solely in
terms of the donor concentration, ND, as shown in equation [3.4] below:
0 s peakd n
D
EW xqN
ε ε≈ = . [3.4]
50
When the maximum voltage is applied across the reverse-biased junction, Epeak
will be equal to the breakdown electric field, Ebr, of the semiconductor material, and the
depletion region will be at the boundary of the drift region and the p+ collector. In
silicon, Ebr = 3x105 V/cm, and the breakdown process occurs when the field becomes
high enough to start impact ionization in the depletion region from high kinetic energy
carriers accelerated in the field, which establishes the process of avalanche breakdown
[8]. The current flowing through the device, after the avalanche process has been
initiated, results in high power dissipation and device failure. The voltage, Vbr, when the
breakdown will occur is found by integrating the electric field distribution over the
depletion region width:
201
2 2s br
br d brD
EV W EqN
ε ε= =
. [3.5]
Also, it has been assumed that the applied voltage at breakdown is much greater than the
contact potential, Φ0, as expressed in equation [3.6] below:
0 2ln A D
i
kT N Nq n
⎛ ⎞Φ = ⎜ ⎟⎝ ⎠
, [3.6]
where ni is the intrinsic carrier density of the semiconductor. When the applied voltage is
at the breakdown voltage, Vbr, the depletion width equal to the width, brdW . The
51
thickness of the drift region, ldrift, must be equal to or greater than the depletion region
width at breakdown ( brdW ):
0 s brdrift dbr
D
El WqN
ε ε≥ = . [3.7]
By equations [3.5] and [3.7], brdW is directly proportional to the reverse breakdown
voltage of the device. It is evident that high voltage rated, NPT IGBTs require thick drift
regions and/or increased n-type doping concentration.
During the fully on-state, and at high level injection, the drift region charge
carrier profile and junction J1 can be modeled as a forward biased PiN diode [9]. The
resistivity of the drift region, ρdrift, is inversely proportional to the quantity of free charge
carriers. This relation is shown in equation [3.8]:
1( )
driftn pq n p
ρµ µ
=+
, [3.8]
where µn and µp are the electron and hole mobilities, and where n and p are the free
charge carrier levels of electrons and holes, respectively. At the high level injection
condition, the resistivity is reduced greatly when a high level of excess hole charge
carriers are injected from the p+ collector into the drift region. The high level injection
case requires the concentration profile length of injected holes, called the hole diffusion
52
length, Lp, to be longer than the thickness of the drift region [1]. The diffusion length for
holes during high level injection, LHL, is given in equation [3.9] as
HL a HL driftL D lτ= > , [3.9]
where Da is the ambipolar diffusion coefficient and τHL is the hole lifetime during high
level injection. The value of LHL is the average length of time a hole will diffuse before
recombining with the Auger recombination effects, which shortens the lifetime compared
to the low level injection lifetime [1]. The ambipolar diffusion coefficient is defined in
equation [3.10]:
a HL TD Vµ= , [3.10]
where VT is the thermal voltage, and µHL is the hole mobility at high level injection,
accounting for carrier-carrier scattering, which lowers the mobility compared to the low
level injection mobility [1]. The hole diffusion length is stated as the average distance a
hole will diffuse from the junction before it is recombined [8].
However, the distribution of holes in the preceding discussion deviates from the
PiN diode model with the p-n- junction, J2, at the p+ body is involved. At this junction,
the excess carrier concentration must fall to zero since it is reversed biased, which
changes the boundary conditions and the distribution. The carrier profile is similar to the
PiN diode profile until about midway through the drift region, where it begins to fall
towards the junction [10]. In other words, the distribution in the IGBT drift region does
53
not have a high level charge injection across the entire width as the PiN diode does. A
simplified distribution of holes without recombination effects appears linear from the
excess concentration at junction J1, down to the excess concentration at junction of J2,
where the J1 and J2 are shown in Figure 3.4 [10]. However, the distribution of excess
hole concentration can be solved by applying the continuity equation for holes with
recombination effects. The boundary conditions of the hole distribution, pn(x), are the
following: pn(x=0) = np∆ and pn(x=d) = 0, where x is zero at J1 and d is the distance to J1
from J2. At steady state, the continuity equation for holes is shown below in terms of the
hole diffusion length and hole concentration is the following:
2
2
2 0n n
HL
p px L
∂− =
∂ [6]. [3.11]
Applying the aforementioned boundary conditions to equation [3.11] and solving the
second-order differential equation, the derived final solution for pn(x), is expressed in
equation [3.12]:
sinh( ) / ( )sinh( / )
n drift HLn
drift HL
p l x Lp xl L
∆ −= , [3.12]
where np∆ is found by applying boundary conditions for the current densities for electrons
and holes: Jn(x=0) = 0, and Jp(x=0) = J [6]. The solution of np∆ , derived with these
boundary conditions, is shown in equation [3.13]:
54
tanh2
HLn
p HL
JL dpqD L
⎛ ⎞∆ = ⎜ ⎟⎝ ⎠
[6]. [3.13]
The principle result reveals that the distribution of the injected holes into the drift region
is related to the diffusion length, the current density, and also the thickness of the drift
region. It is clear that if the drift region is made to be larger, the injection of holes must
be made deeper, resulting in more stored charge existing in the drift region to maintain a
low resistance drift region.
When the IGBT begins to turn off, the excess carriers near J1 will only be
removed by the process of recombination. The effect of sweep out does not exist from J1,
where the growing depletion region removes charge carriers in the electric field—the
depletion region spreads from J2. The spreading depletion region from J2 will extend into
the drift region and sweep out some carriers, but the remaining charge carriers that are
not swept out, recombine at the rate depending on the carrier lifetime during high level
injection. If the beginning of the current tail initiates at t = 0, the collector decay
current, ( )tailCi t , is exponential as shown in the following:
( )(0)( ) HL
tail
tBC
HL
Qi t e βτ
τ
−
= , [3.14]
where QB (0) is the stored charge in the drift region, or pnp transistor base, at the
beginning of the tail, β is the pnp transistor current gain, and τHL is the high level
55
injection lifetime [6]. The carrier lifetime is sensitive to temperature where increased
thermal energy in the IGBT can cause current tail elongation [10]. Reducing the lifetime
can expedite the collector current during the tail time according to equation [3.14].
Lifetime reduction techniques such as gold doping, electron irradiation, and localized
proton implantation are used to speed up the recombination process [10]. However,
reducing the carrier lifetime has trade-offs such as lower charge carrier injection levels
and possibly increased resistivity in the drift region, which increases on-state loss.
The latest generation of high voltage IGBTs, such as the Fast Stop or Soft/Light
Punch Through technologies, and have shown reduced losses compared to similar rated
NPT designs [11]. These designs use advanced doping profiles, which add a thin n-type
doped buffer layer adjacent to the heavily doped p+ collector terminal (next to J1). This
buffer layer provides a desired low forward on-state voltage during conduction and
allows for a thinner drift region and faster recombination of carriers to mitigate switching
loss, especially concerning the current tail loss [12]. Also, new trench-gate IGBT designs
have been shown to lower on-state voltage compared to planar DMOS gate structures by
reducing the on-state resistance in the MOSFET portion [13]. These technologies are
employed in recent 6.5 kV rated and high speed COTS, IGBT modules, designed for
rugged industrial and commercial applications.
56
3.1.3 IGBT Switching Theory Conclusion
The IGBT switching frequency is partially limited by input capacitance, where the
gate drive impedance can limit the response of the MOSFET turn-off. The gate drive
circuit must be designed for fast discharge of the IGBT’s input capacitance for mitigated
switching time. Furthermore, the external gate drive resistor can be adjusted to
customize the IGBT switching rate if necessary, by adjustment of the gate drive circuit’s
capacitive time constant. Additionally, the turn-off transition of high voltage IGBTs is
relatively slow due to prolonged carrier recombination in the drift region. The drift
region, also the base of the pnp transistor, is typically designed with a certain thickness
and doping concentration for the IGBT’s off-state voltage rating. Since the total turn-off
time will generally increase as the voltage rating increases, IGBTs with high voltage
ratings can affect system performance such as efficiency and switching frequency in
switch-mode converters. Consideration of the device voltage rating must be taken into
account concerning turn-off loss. As an alternative to high voltage IGBTs, high voltage
switching can be accomplished with a stack of multiple lower voltage rated IGBTs in
series [14]. Isolated gate drivers for each IGBT are required in such an assembly, and
synchronized switching and equal voltage sharing must be ensured for reliable IGBT
stack operation, especially in harsh environments [14]. The maximum number of
switches in series, and parallel, is determined by the break-even point where reliability,
complexity, and cost meet the benefit of lowering switching loss relative to using single-
device IGBTs.
57
3.2 First Stage Detail
The first stage of the cascade boost converter experimental setup consists of two
Insulated Gate Bipolar Transistors (IGBTs) switched in parallel, four inductors in series,
two diodes in parallel, and two series capacitors for the DC filtering capacitors between
stages.
Figure 3.6 Schematic of first stage components
The IGBTs used for the first stage are International Rectifier IRGP30B120KD-E
1200 V, 60 A rated, Non-Punch Through (NPT), IGBTs, each in a TO-247AD package.
These IGBTs, switched in parallel, are driven by a single Powerex M57962L gate driver
which is powered by a single Powerex M57145L-01 DC-DC converter designed
specifically for the M57962L. The gate drive delivers a bipolar signal of +15.8 V and -
8.2 V. The DC-DC converter draws power from a 12-18 V input, which is provided by
0.24 Ω
400V TVS
Inductors
Rg ~21 Ω
Cree
Nippon Chemi-con
85.4 µH
Power Ten P83C-30033 Power Supply
237 µF
237 µF
(2 series capacitors)
Caddell-Burns SiC diodes
HP 8012B Pulse Generator
400V TVS
12.5 VPower Supply
gate driver& DC-DC converter
18V TVS
(4 series inductors)
0.24 Ω
Powerex International Rectifier IGBTs
58
an 18 W, 12.5 V power supply plugged into the 120V AC laboratory power. The gate
resistance for both IGBTs is controlled by a single potentiometer set nominally at 21Ω.
The gate drive input signal source is controlled by a Hewlett Packard, 8012B pulse
generator. The power supply delivering the input power is a Power Ten, P83C-30033
power supply that is rated at 10 kW with a 300 V maximum output voltage.
The development of the first stage involved determination of switching loss for
the IGBT cooling requirements. The first stage switching loss was determined based
upon initial IGBT testing using the circuit shown in Figure 3.6, but operating as a single
stage converter into a 249 Ω resistive load. The resistive load was used to simulate the
average current draw of the second stage. The test converter produced 550 VDC and the
turn-off current level of each IGBT was 25 A. The IGBT loss was determined to be
approximately 40-50 W when implemented in the final cascade boost converter
prototype.
In order to limit the operating temperature below the rated 125º C junction
temperature, each IGBT was clamped to a forced air cooled aluminum heat sink. The
heat sinks are E3045 profiles by Thermaflo, Inc. shown in Figure 3.7, where each heat
sink was cut to 5 in. in length to give a total surface area of 113 in2 per heat sink. The
heat sink air flow is provided by a 24 V fan that provides about 200 CFM. The thermal
resistance for each heat sink is estimated to be less than 0.5 ºC/W. The combined volume
is 40 in3 for the heat sinks. The total volume consumed by both heat sinks in the
prototype setup, including separation between heat sinks and brackets for mounting, is
given in Table 3.3.
59
Figure 3.7 Thermaflo E3045 heat sink profile.
The diodes shown in the schematic in Figure 3.6 are two Cree Inc., CSD10120
silicon carbide (SiC) Schottky diodes with a 1200 V, 10A rating each in a TO-247-3
package. These diodes represent an emerging power semiconductor technology using
SiC, which includes a number of advantages over silicon. Such advantages are the
following: approximately 10 times higher voltage blocking ability, higher operating
temperatures, and higher thermal conductivity. The SiC higher electric field strength
enables the production of Schottky type diodes with a 1200 V rating, where Si Schottky
diodes are rarely rated above 200 V. Schottky diodes are advantageous due to their
inherent fast switching speed and low reverse recovery loss compared to Si, 1200 V, p-n
junction diodes. The power loss of Schottky diodes is almost exclusively due to the on-
state conduction loss. The low power loss and low device temperature rise allows the use
of a small heatsink, where both diodes are mounted on a single heatsink (Wakefield 637-
20ABP) that has a rated temperature rise of 55º C with 6 W dissipated from both devices.
The first stage inductor, L1, is a series arrangement of four inductors by Caddell-
Burns. Two of these inductors are rated at 15 µH and two are rated at 22 µH. The
measured inductance showed that the actual inductance of the four inductors in series is
60
85.4 µH at 1 kHz, and was measured with a Sencore LC102, Auto-Z impedance meter.
The manufacturer’s product data of the inductors is given in Table 3.2. The “incremental
current” in Table 3.2, was used to define the peak current rating of the inductors, which
represents the current level at which the inductance decreases by 5% from the initial
(zero-DC) value at steady state conditions. The actual inductance of 85.4 µH changes
the duty ratio from 0.5 to 0.523 as specified in section 2.6 with a value of 76.6 µH for L1.
The inductors were selected with an expected peak current of 50A or less; actual
prototype inductor currents are analyze in Chapter 5.
Table 3.2 Caddell-Burns inductor specifications. Incremental current is the minimum current at which the inductance will be decreased by 5% from the initial (zero-DC) value.
Inductance Model # Max. DC
resistance, Ohms
Rated IDC, Amps
Incremental Current, Amps
15 µH 7000-03 .005 24 52 22 µH 7000-05 .007 21 41
The capacitors used for C1 are two Nippon Chemi-con 220 µF, 450 V rated
capacitors in series. The tested capacitance of each capacitor is 237 µF with 0.24 Ω
series resistance, which was measured with a Sencore LC102, Auto-Z impedance meter.
The capacitors are placed in parallel with two, P6KE400A, transient-voltage suppressor
(TVS) diodes in series, which prevents the first stage output from exceeding
approximately 800 V. The gate-to-emitter voltage of the IGBT is also limited to
approximately 18 V with a P6KE18CA, TVS diode, to prevent damage to the IGBT gate
61
from spurious voltage spikes; the gate to emitter voltage must not exceed ± 20 V
according to the manufacturer’s recommendations.
The volume and mass of individual components of the second stage are shown in
Table 3.3. This experimental system has the potential for further volume and mass
optimization with redesign of the first stage IGBT cooling. The heat sinks in the first
stage were utilized primarily due to availability and cost, but the volume and mass of the
cooling system may be reduced by a factor of two with a more efficient COTS heat sink
extrusion profile. Also, technology such as the recent developments in micro-channel
heat sinks with flowing, two-phase liquids for server CPUs, VLSI circuits, and power
electronics, may be efficient enough to extract over 500 W/cm2 in the near-term [15-16].
Such technology has the potential to reduce the cooling system volume and mass to a
fraction of the volume and mass shown in Table 3.3. Notwithstanding, the volume and
mass of the prototype cascade boost converter’s first stage provides adequate cooling for
operation of the experimental circuit, which gives a baseline understanding and allows
for projection of the system volume scaled to higher power levels, as is discussed in
Chapter 6.
Table 3.3 Volume and mass of first stage components using COTS components.
Volume: in3(cc) Mass: lbs(g) IGBTs + heat sinks 90 (1,475) 2.13 (966) Gate drive 6.25 (102.4) 0.046 (21) Diodes +heat sink 1.375 (22.5) 0.077 (34.68) Inductors 13.5 (221.2) 1.085 (492) Capacitors 10.125 (16.4) 0.82 (372) Total 121.25(1,987) 4.158 (1,886)
62
3.3 Second Stage Detail
The second stage of the cascade boost converter prototype consists of a stack of
six IGBTs in series, a single inductor, six diodes in series, and two output filter capacitors
in series. This section presents the second stage components and includes the design of
the output load. Figure 3.8 shows the schematic of the second stage with the components
utilized for the prototype converter.
Figure 3.8 Schematic of second stage components
The IGBT stack was built with six IGBTs in series, and is designed for
optimization of switching efficiency using COTS IGBTs in a customized stack assembly.
The stack is shown in Figure 3.9. This IGBT stack assembly, which includes isolated
gate drive circuitry and switch over-voltage protection, was custom built by Loree
Diodes: Inductor (Stangenes nanocrystalline core)
12.5 V power supply
25 kΩ load (10 series Ohmite 2K5L225J)
(6 series 10ETF12FP)
DC filter capacitors (2 series 3.5 kV, 5 µF CSI Capacitors)
3.5 mH
IGBT stack: (6 series IRGP30B120KD-E)
Gate Driver
Gate Driver5 µF
Optically isolated gate signals & isolation transformer
5 µF
First stage DC output voltage
+
-
63
Engineering to UMC specification for the cascade boost converter. The design of the
stack uses International Rectifier, IRGP30B120KD-E 1200 V, 60 A rated Non-Punch
Through (NPT) IGBT devices. These IGBTs are the same devices as the first stage
IGBTs. The circuit schematics with details of the stack’s isolated trigger board, isolated
power oscillator, and gate drive boards are given in Appendix A. Each IGBT gate signal
is transmitted through fiber-optics to the individual isolated gate driver boards on which
the IGBT is connected. The gate driver boards provide +15 V for turn-on, and 0 V for
turn-off through a 4.7 Ω gate resistor in series with the gate. The heat sink for each IGBT
is a flat milled aluminum plate (measuring 5.15” x 3” x 0.1875”), with 0.5” radius
rounded corners and 3/32” rounded edges. The stack requires a 12 V DC power input,
the trigger signal, and was forced-air cooled at full power operation.
64
Figure 3.9 The IGBT stack with six IGBTs in series, operating as the second stage switch.
Six diodes in series form the second stage 5 kV boost diode. The diode stack
consists of International Rectifier 10ETF12FP diodes, each rated at 1200 V and 10 A
average. These diodes come in a TO-220 “FullPack” package, where the collector
terminal is not exposed on the backside of the diode, as is common on TO-220 packages.
No heat sinks are utilized for the diodes since the expected power dissipation is nearly
negligible.
The second stage inductor, L2, was built by Stangenes Industries to the given
inductor specifications of the cascade boost converter of 3.4 mH. The tested inductance
was 3.5 mH at 1 kHz with a Sencore LC102, Auto-Z impedance meter, and is built with
65
four nanocrystalline “C” cores with a 3 mm gap spacing. The design expertise of
Stangenes provided a high quality nanocrystalline-core inductor for the design, which is
used as a basis to scale the cascade boost converter to higher power levels in Chapter 6.
The nanocrystalline core material provides the low core loss of ferrite cores, and
combines the high maximum flux density of iron-based cores. Analogous to SiC in the
semiconductor industry, the nanocrystalline core material represents modern technology
for inductor and transformer magnetic cores in power electronics [17-18]. The
inductance of 3.5 mH for L2 results in the duty ratio, D2, to increase from the ideal value
of 0.5 calculated using the equations in Chapter 2 to the actual value of 0.502.
66
The load for the cascade boost converter has an impedance of 25 kΩ. To achieve
operation at a full output voltage of 5 kV and 1 kW, ten 2.5 kΩ, 225 W rated resistors
were arranged in series. The load is shown in Figure 3.10. The resistors are Ohmite,
wire wound, vitreous enamel power resistors (2k5L225J). These resistors are rated for 3
kV dielectric voltage hold off, where each resistor was de-rated to handle 500 V and
dissipate only 100 W. A fan provided a constant air flow across all ten resistors, and the
laboratory temperature was also maintained below 25ºC. The load was measured and
found to be 25 kΩ, both before and immediately after a dissipation power level of 1 kW
output. The volume and mass of the individual second stage components is shown in
Table 3.4. As with the first stage, these volume and mass values for the cascade boost
converter prototype will be used for scaling to higher power levels. The load is not
included in the volume and mass measurements.
67
Figure 3.10 The output Load with 10 series Ohmite, wire wound resistors for dissipation of the 1 kW output of the prototype.
Table 3.4 Volume and mass of the second stage components.
Volume in3(cc) Mass lbs(g) IGBT stack 177(2,900) 3.35(1,518) Diodes 0.656(10.75) 0.027(12) Inductor 83.125(1,362) 4.76(2,158) Capacitors 77.3(1267) 2.9(1,330) Total 338.1 (5,540.5) 11.04(5,008)
The total bench top cascade boost converter volume and mass is shown in Table
3.5. The total mass of the system is 15.2 lbs, which represents about 15 lbs/kW. This
figure is not lightweight, but reduction in weight is possible with research specifically
aimed at engineering an advanced cooling system and utilizing next generation light-
68
weight, high density capacitors, inductors, and switches. The weight and volume of the
prototype is dominated by commercial off the shelf components, and can be substantially
reduced in an aerospace rated system. The total volume of the system is 459.35 in3 or
0.008 m3, which does not include a packaging factor.
Table 3.5 Total cascade boost converter prototype volume and mass.
Volume in3(cc) Mass lbs(g) First Stage 121.25 (1,987) 4.158 (1,886) Second Stage 338.1 (5,540.5) 11.04 (5,008) Total 459.35 (7,527.4) 15.2 (6,894)
3.4 Second Stage Switch Design Optimization
The original design of the second stage switch utilized two high current, 3.3 kV
IGBT modules in series, which resulted in high average switching loss of over 1.1 kW.
This high switching loss limited the total cascade boost circuit efficiency to
approximately 37%. Using the IGBT theory discussed in section 3.3, the six-series stack
of 1200 V IGBTs was designed to replace the two 3.3 kV IGBTs and provide lower
switching loss. Circuit measurement waveforms and improvement of the switching
efficiency performance of the six-series IGBT stack in contrast to the two 3.3 kV IGBT
modules is presented in the following. This experimental evidence validates the
preceding IGBT switching theory in section 3.1.
The 3.3 kV IGBTs are 200 A rated, NPT (Non-Punch Through) IGBTs from
Dynex Semiconductor. Two of these IGBTs are packaged in a single module unit
69
designed for half-bridge circuits for application in motor control or the traction industry.
The IGBTs devices in the module package were connected in series, and synchronized by
simultaneous gate signals. Both gate signals operated with 4.4 Ω external gate resistors.
The module has a 6 kV isolated base plate for mounting to a grounded heat sink. The
heat sink used for thermal management is a liquid cooled heat sink from Aavid
Thermalloy (part number: 416101U00000) and was applied with approximately 0.7 gpm
water flow rate. At this flow rate, the heat sink thermal resistance is rated as 0.013 ºC/W.
The total thermal resistance for each IGBT becomes 0.077 ºC/W, and the combined
IGBT maximum power dissipation handling results in approximately 2.6 kW, with the
maximum IGBT junction temperature at 125 ºC.
The performance of the two 3.3 kV and the six 1200 V IGBTs in series
demonstrates a significant difference in switching loss. Figure 3.11 shows the turn-off
voltage and current waveforms of the two 3.3 kV IGBTs in series as the second stage
switch in the cascade boost converter operating with an output of 5 kV and 1 kW. The
second stage schematic is similar to the circuit shown in Figure 3.8, except that two 3.3
kV IGBTs in series replaced the six 1200 V IGBTs. Figure 3.12 displays the power loss
during turn-off, and the integration of this power loss results in a total of 126.5 mJ of
energy loss per pulse. At a switching frequency of 9 kHz, this turn-off energy loss per
pulse equals an average power loss of 1139 W for the two 3.3 kV IGBTs in series.
70
2 Series 3.3 kV Dynex IGBT Turn-0ff Waveform
0
1000
2000
3000
4000
5000
6000
8 9 10 11 12 13 14 15 16 17 18
Time ( µs )
Col
lect
or-E
mitt
er V
olta
ge (
V )
0
2
4
6
8
10
12
Sw
itch
Cur
rent
( A
)Second stage switch voltage
Second stage switch current
Current tail
Figure 3.11 Voltage and current waveforms of two 3.3 kV IGBTs in series as the second stage switch of
the cascade boost converter with and output of 5 kV and 1 kW.
2 Series 3.3 kV Dynex IGBT Turn-0ff Loss
0
10
20
30
40
50
60
8 9 10 11 12 13 14 15 16 17 18Tim e ( µs )
Pow
er (
kW )
0
0.04
0.08
0.12
0.16
0.2
0.24
Ene
rgy
(J)
Second s tage switchturn-off lossEnergy Loss
Eof f = 126.5 mJ
Figure 3.12 Power loss waveform of the two 3.3 kV IGBTs in series. The integrated energy loss is 126.5
mJ per pulse, which results in an average power loss of 1139 W.
A comparison of the two IGBT turn-off loss figures is shown in Table 3.6. Table
3.7 shows the necessary switching duty ratio increase to compensate the switching loss in
71
the 5 kV output converter. The increased duty ratio increased the peak inductor charging
current and the average input current to the converter from the source power supply. The
duty ratio for the second stage was limited to 0.66 as the current limit and near-saturation
effects of L2 were reached at marginally higher duty ratios. The first stage IGBT loss
also increases with the 3.3 kV IGBTs implemented in the second stage since the first
stage peak switch current must increase proportionally to regulate the voltage across C1.
Due to the maximum first stage IGBT power loss limitations and the second stage
inductor current limit, the switching duty ratios of both stages were maximized in order
to optimize the converter’s step-up ratio. The optimized cascade boost converter’s
maximum voltage gain was only 46.7 with two series 3.3 kV IGBTs for S2. The 5 kV
and 1 kW output was achieved, using an input voltage of 107 V as shown below in Table
3.7. Again, the loss of the 3.3 kV devices resulted in a cascade boost converter efficiency
of approximately 37%.
Table 3.6 Turn-off loss comparison of the two IGBT designs.
Turn-off energy loss
Average turn-off power loss
2 series 3.3 kV, 200 A IGBTs 130 mJ 1139 W 6 series 1200 V, 60 A IGBTs 11.6 mJ 93.55 W
72
Table 3.7 Cascade boost converter parameter comparison of 3.3 kV and 1200 V IGBTs.
2 series 3.3 kV, 200 A IGBTs
6 series 1200 V, 60 A IGBTs
Efficiency 37 % 76.6 % Input voltage 107 V 100 V Average input current 24.8 A 13.1 A First stage output 589 V 503 V D1 0.8 .614 D2 .66 0.513 iL1 max 50 A 34.5 A iL2 max 11.3 A 8.1 A
The low system efficiency using 3.3 kV rated IGBTs motivated the redesign of S2
to achieve a lower switching loss. The waveforms of Figure 3.11 and Figure 3.12
demonstrate the theoretical relation between voltage ratings and current tail magnitudes
in IGBTs, where the high voltage rated IGBTs exhibit a long and substantial current tail.
The redesign of S2 with six series 1200 V rated IGBTs experimentally demonstrates a
lower current tail loss and faster switching speed, which results in nearly 92% lower loss
in S2 and increases the efficiency to 76.6% from 37%. Analysis of the IGBT stack turn-
off switching loss and further experimental results of the prototype cascade boost
converter are detailed in Chapter 5.
73
REFERENCE FOR CHAPTER 3.0 [1] N. Mohan, Power Electronics, 2nd Edition. New York: John Wiley & Sons, 1995.
[2] A. Raciti, “Control of the switching transients of IGBT series strings by high-performance drive units,” IEEE Trans. on Industrial Electronics, vol. 48, pp. 482-490, June 2001.
[3] Y.C , Gerstenmaier, “Switching behaviour of high voltage IGBTs and its dependence on gate-drive,” in 1997 Proc. ISPSD, pp. 105-108.
[4] R, Chokhawala, “Gate drive considerations for IGBT modules,” 1992 Conf. record on Industry Applications Society Annual Meeting, vol. 1, pp. 1186-1195.
[5] Dynex Semiconductor application note; AN4504 (http://www.dynexsemi.com)
[6] V. K. Khanna, IGBT Theory and Design, Piscataway, NJ: IEEE Press, 2003.
[7] A. Petterteig, J. Lode, and T.M. Undeland, “IGBT turn-off losses for hard switching and with capacitive snubbers,” Conf. Record of Industry Applications Society Annual Meeting, 1991, pp.1042-1049.
[8] B. G. Streetman, Solid State Electronic Devices, 2nd ed., N. Holonyak, Jr., Ed. Englewood Cliffs, NJ: Prentice-Hall Inc., 1980.
[9] S. Lefebvre and F. Miserey, “Analysis of CIC NPT IGBT's turn-off operations for high switching current level,” IEEE Trans. on Electronic Devices, vol. 46, pp. 1042-1049, May 1999.
[10] H.-W. Kim, “Excess carrier density and forward voltage drop in trench insulated gate bipolar transistor (TIGBT),” in 2002 Proc. MIEL Conf., vol. 1, pp. 12-15.
[11] H, Husken, “FieldStop IGBT with MOS-like (tailless) turn-off,” in 2003 Proc. ISPSD, pp. 338-340.
[12] X, Kang, “Characterization and modeling of high-voltage field-stop IGBTs,” 2002 Conf. record on Industry Applications Society Annual Meeting, vol. 3, pp. 2175-2181.
[13] J. Yamada, “Low Turn-off Switching Energy 1200V IGBT Module,” in 2002 Proc. Industry Applications Conf., pp. 2165-2169.
74
[14] P.R. Palmer, “A comparison of IGBT technologies for use in the series connection,” in 1996 Proc. Power Electronics and Variable Speed Drives Int. Conf., pp. 236-241.
[15] D. Faulkner, “Practical design of a 1000 W/cm2 cooling system,” in Proc. 19th Annu. IEEE Semiconductor Thermal Measurement and Management Symposium, 2003, pp. 223 – 230.
[16] G. Upadhya, “Closed-loop cooling technologies for microprocessors,” in Tech Digest IEEE Int. Electron Devices Meeting, 2003, pp. 32.4.1 - 32.4.4
[17] M. Ferch, “Light transformers for kilowatt SMPS based on nanocrystalline soft magnetic cores,” in Proc. of Seventh Int. Conf. on Power Electronics and Variable Speed Drives, 1998, pp. 411-415.
[18] W.A. Rease, “Design technology of high-voltage multi-megawatt polyphase resonant converter modulators” in Proc. of 29th Annu. Conf. IEEE Industrial Electronics Society, 2003, pp. 96-101.
75
CHAPTER 4.0 DIAGNOSTICS OF THE CASCADE BOOST CONVERTER PROTOTYPE
Evaluation of the cascade boost converter operation requires utilization of the
current and voltage waveforms in the system. The waveform diagnostics are paramount
for gauging component loss and verification of system performance. The voltage
measurements in the first and second stage require accurate voltage diagnostics for
measuring fast-changing switch voltage. Additionally, the second stage of the cascade
boost converter requires voltage diagnostics designed to measure the high voltage DC
and time-varying voltage transients. Also, the current measurements require diagnostics
capable of accurately measuring the current magnitudes in the system. This chapter
describes the diagnostic equipment used in the measurements of the experimental cascade
boost converter.
4.1 Voltage Diagnostics
The voltage diagnostics include DC voltage measurements and time varying
voltage measurements. The attenuation and frequency bandwidth response of the voltage
probes used for the cascade boost diagnostics are shown in Table 4.1. The output DC
voltage of the cascade boost converter was measured with a Fluke 80k-40, 1000X high
voltage probe. The Fluke 80k-40 probe has a maximum voltage rating of 40 kV DC, and
is designed to interface with digital multi-meters with 10 MΩ ( ± 1%) input impedance or
greater. The Fluke 80k-40 probe is connected to a Fluke 23 III, digital multi-meter. For
76
the first stage output DC voltage measurement, a Fluke 77 II, digital multi-meter was
connected directly across capacitor C1. The Fluke 23 III and 77 II DC voltage
measurement accuracy is ± 0.3%. The input DC voltage was monitored using the voltage
monitor on the front panel of the PowerTen P83C-30033, input power supply, and the
accuracy has been verified with a Fluke digital multi-meter. These DC voltage
diagnostics provide a convenient method to observe the cascade boost converter’s input,
first stage, and output DC voltages.
The cascade boost converter’s voltage waveforms of the first and second stage
IGBTs and the output voltage ripple were measured with a Tektronix P6015A, 1000X
high voltage probe. The P6015A has a 20 kV maximum DC voltage rating, 75 MHz
bandwidth, and includes a compensation box for probe frequency response
characteristics. A Tektronix P5100, 100X voltage probe, which has a 2.5 kV maximum
rating, was also used to measure the first stage output voltage for measurement of first
stage voltage ripple. The measurement of the IGBT gate drive circuitry was
accomplished with a Hewlett Packard 10071A, 10X voltage probe, which monitored the
switch duty ratio and the switching frequency for each stage of the cascade boost
converter. A summary of the voltage diagnostics is displayed in Table 4.2 below.
Table 4.1 Voltage probes for circuit diagnostics including attenuation factor and bandwidth.
Voltage Probe Attenuation Bandwidth Fluke 80k-40 1000X DC-60 Hz Tektronix P6015A 1000X 75 MHz Tektronix P5100 100X 250 MHz Hewlett Packard 10071A 10X 150 MHz
77
Table 4.2 Measurement and diagnostic equipment implemented.
Measurement Diagnostic Equipment Input Voltage Power supply (PowerTen P83C-30033) voltage monitor display First Stage Output DC Voltage Direct connection to a Fluke 23III DMM Second Stage Output DC Voltage Fluke 80k-40 1000X HV probe to a Fluke 77II DMM First Stage Output Waveform Tektronix P5100 100X probe Second Stage Output Waveform Tektronix P6015A 1000X HV probe First Stage IGBT Waveform Tektronix P6015A 1000X HV probe Second Stage IGBT Waveform Tektronix P6015A 1000X HV probe
4.2 Current Diagnostics
All of the current measurements were made using two current monitors. One of
the current monitors is a Pearson Electronics current monitor model 110A. This current
monitor gives an output of 0.1 V/A of current flowing through the conductor being
measured. It has a rating of 10 kA, 0.8% droop/ms, usable rise time of 20 ns, and
maximum RMS current of 65 A. The probe has a 4 inch outer diameter and a 2.1 inner
diameter. These specifications allow the 110A current monitor to accurately measure the
system current.
The second current monitor is made by Stangenes Industries, model SI 17385.
This probe is smaller in size, consuming 4.25 inch outer diameter and 1 inch inner
diameter. The Stangenes current monitor gives an output of 0.1 V/A, has a rating of 5
kA, 1.0 % droop/ms, a usable rise time of 20 ns, and maximum RMS current of 30 A.
These specifications will also satisfy the diagnostic requirements for accurate current
measurement. A summary of the current diagnostics are displayed in Table 4.3 below.
78
Table 4.3 Current monitors for circuit diagnostics
Current Monitor Output Peak Current Maximum Continuous Current
Usable rise time
Droop
Pearson 110A 0.1 V/A 10 kA 65 A RMS 20 ns 0.8 %/ms Stangenes SI 17385 0.1 V/A 5 kA 30 A RMS 20 ns 1.0%/ms
4.3 Oscilloscope
The voltage and current measurements utilized a Tektronix TDS3034, four
channel color digital phosphor oscilloscope. The TDS3034 oscilloscope bandwidth is
300 MHz and has a sample rate of up to 5 GS/s. The waveform data was collected and
saved on to a computer disk, where data analysis was completed using Microsoft Excel
and MATLAB. Specific measurement setups for the voltage and current diagnostics and
data analysis processes are discussed further in Chapter 5. The waveforms and
component loss analysis are also presented in Chapter 5.
79
CHAPTER 5.0 CASCADE BOOST CONVERTER PROTOTYPE RESULTS
The output, efficiency, and loss analysis of the cascade boost converter prototype,
are described in the following sections, where the prototype converter has satisfied the
goals given in Chapter 3, and are summarized in Table 5.1. The experimental converter
has demonstrated a step-up voltage gain of 50, an output of 5 kV DC at 1 kW, and a
regulation of better than +/- 0.5%. Thus a 100 V DC input was stepped up to 5 kV DC
into the 25 kΩ resistive load, which produces an output power of 1 kW. The gains for the
first and second stages were 5 and 10, respectively. With the switching frequencies
operating at 20 kHz for the first stage and 9 kHz for the second stage, the converter
efficiency resulted in 76.6%.
It is believed that the efficiency improvement is possible with additional
optimization of the circuit, such as lowering the inductor losses and the IGBT switching
loss with faster switches and possibly parallel stages. The detailed analysis of the
component loss is used for extrapolation of the loss per stage, and also enables a realistic
loss estimation of the cascade boost converter scaled to higher output power and voltage
levels.
Table 5.1 Cascade boost converter prototype design goals.
Voltage Input 100 V Voltage Output 5 kV Power Output 1 kW
Output Voltage Regulation
+/- 0.5%
80
5.1 Cascade Boost Converter Output and Efficiency
The circuit performance of the converter is evaluated in this section while
operating with a DC output voltage of 5 kV from a 100 V DC input. As discussed in
Chapter 4, the input voltage to the cascade boost converter was measured using the
voltage monitor on the front panel of the input power supply (PowerTen P83C-30033),
the first stage DC output voltage was measured with the Fluke 77 II digital multi-meter.
The second stage output was measured with the Fluke 80k-40, 1000X high voltage DC
probe and Fluke 23 III, digital multi-meter. The switch duty ratios were adjusted
manually to tune the step-up voltage gain to 5 for the first stage and 10 for the second
stage, which resulted in .614 and .513 for the first and second stage duty ratios,
respectively. The output voltage of the first and second stage was also measured with the
Tektronix P6015A, high voltage probe, and the Tektronix TDS3034, oscilloscope. The
first stage output voltage waveform, with an average of 503 V, is shown in Figure 5.1,
and the converter output voltage, with an average output of 5 kV, is displayed in Figure
5.2.
The converter output ripple is measured to be 49.3 V, which corresponds to a
regulation of +/-0.49% and meets the +/-0.5% regulation goal. According to these
results, the 2.5 µF filter capacitance used for the converter appears to be the minimum
capacitance to achieve a +/-0.5% regulation when stray switch inductance of the actual
circuit is present. The stray switch inductance in both stages resulted in a voltage
overshoot across the switches during turn-off, which coupled to the first and second stage
outputs, as can be seen in Figure 5.1 and Figure 5.2, respectively. In order to provide
81
regulation within the specified value, the switch overshoot was attenuated by the output
capacitors. In a future design, mitigation of stray inductance from a low-inductance
circuit design can lead to an optimal output regulation with reduced filter capacitance.
Thus the capacitor volume and mass will be reduced and result in a more compact
converter design.
Firs t Stage Output Voltage
400
450
500
550
600
Tim e ( µs )
1st S
tage
Out
put (
V )
Averge voltage = 503 V
Stray switch inductance voltage spike.
∆1T
Figure 5.1 First stage DC output voltage; the average output voltage is displayed at 503 V, for a voltage
gain of 5 from the 100 V input.
82
Second Stage Output Voltage
4800
4900
5000
5100
5200
Time ( µs )
2nd S
tage
Out
put (
V ) Averge voltage = 5010 V
∆2T
Figure 5.2 Cascade boost DC converter output voltage; the average output voltage is displayed at 5010 V,
for a voltage gain of approximately 10 from the 503 V first stage output.
The efficiency values were calculated by using the input voltage, the first stage
output voltage, and the converter output voltage. These values were then multiplied by
the average current flow at each stage. The average current values were determined
using the current waveforms measured from the first and second stage inductor currents.
The Pearson 110A and the Stangenes current monitors were utilized to measure these
inductors currents. The first stage inductor current waveform is shown in Figure 5.5, and
the second stage inductor current waveform is shown in Figure 5.6. The time-average
value of each current waveform equals the average input current per stage. Thus, the
time-average power delivered to each stage was calculated as the following: [5.1], [5.2],
[5.3]
83
( )( )0 0 0DCP V I= ; [5.1]
( )( )1 1 1DCP V I= ; [5.2]
( )( )2 2 2DCP V I= , [5.3]
where P0 is the average input power, VDC0 is the input voltage, P1 is the average first
stage output power, VDC1 is the first stage output voltage, P2 is the average second stage
output (converter output) power, VDC2 is the converter output voltage, and 0 2I I− are the
average current values from the respective stage.
Table 5.2 summarizes the average values measured in the cascaded boost
converter, where the average current values listed are the time average values of the stage
input currents as discussed above. Table 5.3 summarizes the calculated efficiency and
loss of the system per stage. Also, the input voltage to the cascade boost converter was
gradually increased from 0 V to 100 V, with constant switch duty ratios of .614 and .513
for S1 and S2, respectively. The converter’s first stage output voltage, rising from an
increasing input voltage, are shown in Table 5.4, and the voltages per stage, shown in
Figure 5.3, show a highly linear relationship with the input. The total system efficiency,
first stage efficiency, and second stage efficiency with respect to the output voltage is
shown in Figure 5.4.
84
Table 5.2 Average value data of the system operated at 5 kV output.
DC Voltage
Average Current
Average Power
Converter Input 100 V 13.1 A 1,310 W First Stage Output 503 V 2.3 A 1,157 W Converter Output 5,010 V 200.4 mA 1,004 W
Table 5.3 Efficiency and loss for the first and second stages operated at 5 kV output.
Efficiency Power Loss First stage 88.33% 152.9 W Second stage 86.77% 153.08 W Total system 76.64% 305.98 W
Table 5.4 First stage and second stage voltage data of the cascade boost converter prototype as input voltage is varied from 0 V to 100 V.
Input Voltage (V) First Stage Output (V) Second Stage Output (V)
0 0 0 10 48.1 428 20 93.2 931 40 200.3 1,964 50 252.7 2,485 60 300.9 2,984 70 351 3,470 80 401 3,990 90 454 4,530
100 503 5,010
85
First & Second Stage Output Voltage
0
1000
2000
3000
4000
5000
6000
0 20 40 60 80 100 120
Input Voltage
Out
put V
olta
ge
Firs t Stage Output
Second Stage Output
Figure 5.3 First stage and second stage output voltages as input voltage is varied from 0 to 100 V, with constant switching duty ratios of .614 and .513 for the first and second stages respectively.
Cascade Boost Efficiency
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 1000 2000 3000 4000 5000 6000
Output ( V )
Effi
cien
cy
Total Efficiency
2nd Stage Efficiency
1st Stage Efficiency
Figure 5.4 Efficiency of the individual stages and the overall converter.
86
The inductor charging currents of the cascade boost converter prototype shown
below in Figure 5.5 and Figure 5.6 display subtle differences with the inductor currents
produced by the ideal converter simulated and discussed in section 2.6. These
differences are to be expected due to the non-ideal properties and losses of the prototype
converter. One of the obvious differences is the larger duty ratio of the prototype
converter, as compared to the simulation. As the converter losses accrue, the duty ratio
must be increased to store more energy in the inductor that provides compensation for the
losses. The rising current slope of the first stage inductor, indicating a closed position of
the first stage switch, accounts for about 30.1 µs of the total 49 µs switching period. This
corresponds to a 0.614 duty ratio, where the ideal converter operated at a duty ratio 0.5.
In addition to the losses, the larger duty ratios of the prototype converter are a result of
larger inductor values. The actual inductance utilized in the first stage is 85.4 µH as
described in section 3.1, which is larger than the 76.6 µH ideal inductance value. The
larger inductance is evident by the lower time-rate of change, or di/dt, of the rising first
stage inductor current. The same effect is seen in the second stage, where the actual
inductor is 3.5 mH and the ideal converter inductor is 3.3 mH. The duty ratio of the
second stage is 0.513 in the prototype converter, and 0.5 in the ideal converter simulation.
87
Firs t Stage Input Current
-505
10152025303540
0 5 10 15 20 25 30 35 40 45 50 55 60Tim e ( µs )
Inpu
t Cur
rent
( A
)Experimental CurrentSimulated Current
Figure 5.5 First stage experimental and simulated input currents when the converter is operated with a 100
V input and 5 kVoutput.
Second Stage Input Current
-2
0
2
4
6
8
10
0 20 40 60 80 100 120
Tim e ( µs )
Inpu
t Cur
rent
( A
)
Experimental Current Simulated Current
Figure 5.6 Second stage experimental and simulated input currents when the converter is operated with a
100 V input and 5 kV output.
88
5.2 Component Loss Analysis
The loss analysis of the cascade boost converter prototype operating at 5 kV
output indicates that the IGBT switching loss and inductor loss are the two most
significant components of the total power loss. The following discussion estimates the
switching, diode, and capacitor loss of both stages from analysis, and from these, the loss
in the inductor was derived. The loss analysis also provides a baseline for the loss of a
cascade boost converter scaled to higher power levels. For all of the following
component loss analysis, the cascade boost converter operating conditions are shown
below in Table 5.5.
Table 5.5 Cascade boost converter operating conditions for the component loss analysis
Circuit Conditions Input Voltage 100 V First Stage Output 503 V First Stage IGBT Frequency 20 kHz First Stage Duty Ratio 0.614 Second Stage Output 5010 V Second Stage IGBT Frequency 9 kHz Second Stage Duty Ratio 0.513
5.2.1 Measurement of the First Stage IGBT Loss
The loss of the first stage IGBTs is determined from the measured voltage and
current waveforms during operation of the cascade boost converter at the full 5 kV
output. The Stangenes CT was utilized to measure the combined current of the parallel
diodes comprising diode D1, and the Pearson CT was setup to measure the inductor
89
current of L1. The combined current of the parallel IGBTs is found by subtracting the
diode current from the inductor current. This method allows for the measurement of L1,
D1, and S1 current with two current monitors. The voltage probe setup includes the
P5100 probe measuring the voltage across C1, and the P6015A probe across the collector
and emitter of one IGBT. The data recorded by the Tektronix TDS3035 oscilloscope,
was saved and analyzed as a spreadsheet in Microsoft Excel. Utilizing functions in
Excel, the voltage and current waveforms were multiplied together to produce the
waveforms for power loss. The power loss waveforms were integrated, using a custom
routine in MATLAB, for calculation of energy loss per period. Average power loss is
calculated by multiplying the energy loss per period by the switching frequency as in
equation [5.4] below:
/0
( ) ( )T
loss s sloss periodP f E f v t i t dt∗ ∗= = ∫ , [5.4]
where v(t) and i(t) are the instantaneous voltage and current values. The MATLAB
routine that was used for integration is given in Appendix B.
The turn-off loss and conduction loss, during the on-state, were processed
separately and the respective average powers were added together to derive the total
switch loss. The derivation for the average conduction loss of the IGBTs is discussed in
Appendix C. The IGBT turn-on loss was neglected due to the zero turn-on current
inherent in discontinuous conduction mode of the cascade boost converter. Also, the
90
slow time-rate of change of switch current, after turn-on, is limited by the inductance of
L1.
Figure 5.7 shows the turn-off voltage and current waveforms of the two first stage
IGBTs in parallel, where the current is sum of both collector currents. The first stage
IGBT turn-off demonstrates decaying current after the initial fast drop in current,
commonly termed the “current tail”. The current tail increases the turn-off loss
significantly and is an inherent characteristic which results from the minority carrier
recombination and the bipolar junction transistor component of the IGBT. According to
IGBT theory, the current tail does not scale linearly with the IGBT current at turn-off; the
current tail loss significance reduces as the turn-off current is increased [1]. This
explains the increasing system efficiency as the input voltage is increased, as seen in
Figure 5.4.
Figure 5.8 shows the IGBT turn-off power loss waveform for the two first stage
IGBTs, where the cascade boost is operating at the conditions shown in Table 5.5.
Average power loss calculated from these waveforms is 49.3 W per IGBT or 98.57 W
total. Table 5.6 displays a summary of the IGBT waveforms and average power loss.
91
First Stage Switch Turn-0ff Waveform
0
100
200
300
400
500
600
700
0.5 1 1.5 2 2.5 3
Time ( µs )
Col
lect
or-E
mitt
er V
olta
ge (
V )
0
5
10
15
20
25
30
35
40
Sw
itch
Cur
rent
( A
)
First stage switch voltage
First stage switch current
Current tail
Figure 5.7 Turn-off voltage and collector current waveforms of the first stage IGBTs in parallel.
First Stage Turn-0ff Loss
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
0.5 1 1.5 2 2.5 3Time ( µs )
Pow
er (
kW )
Eof f = 4.83 mJ
Figure 5.8 First stage turn-off power loss. The integrated turn-off loss = 4.83 mJ at 20 kHz for 98.57 W
average loss.
92
Table 5.6 Summary of the first stage IGBT data.
Switching period (frequency) 49 µs (20.4 kHz) Duty ratio 0.614 Ic 34.5 A Vce 503 V Voltage rise time (10-90%) 94 ns Current fall time (90-10%) 240 ns Conduction loss per IGBT 12.55 W Turn-off loss per IGBT 36.75 W Total IGBT loss 98.57 W
5.2.2 Measurement of the Second Stage IGBT Loss
The second stage IGBT loss was determined by the same process as the first stage
IGBT loss. The diagnostic equipment used to monitor the voltage and current includes
the Pearson and the Stangenes current transformers, and two Tektronix P6015A 1000X
probes. The Pearson probe measured the total emitter current of the IGBT stack. One of
the P6015A probes measured the collector voltage, and the other was used to measure the
converter output voltage. The turn-off voltage and current waveforms and turn-off loss
are shown in Figure 5.9 and Figure 5.10 below.
93
Second Stage Turn-0ff Waveform
0
1000
2000
3000
4000
5000
6000
0 1 2 3 4 5Time ( µs )
Col
lect
or-E
mitt
er V
olta
ge (
V )
0
1
2
3
4
5
6
7
8
9
Em
itter
Cur
rent
( A
)
Second stage switch voltage
Second stage switch current
Figure 5.9 Turn-off voltage and current waveforms of the second stage IGBT stack.
Second Stage Turn-0ff Loss
0
5
10
15
20
25
30
35
40
1 1.5 2 2.5 3 3.5 4Time ( µs )
Pow
er (
kW )
Eof f = 11.6 mJ
Figure 5.10 Second stage IGBT stack turn-off power loss. The integrated turn-off energy loss = 11.6 mJ at
9 kHz for 104.7 W average loss.
94
Table 5.7 Summary of second stage IGBT data.
Switching period (frequency) 110.6 µs (9.04 kHz) Duty ratio 0.513 Voltage rise time (10-90%) 586 ns Current fall time (90-10%) 438 ns Current at turn-off 8.1 A Off-state voltage 5010 V Conduction loss per IGBT 2 W Turn-off loss per IGBT 15.22 W Total IGBT stack loss 104.7 W
5.2.3 Measurement of Diode Losses
The diode loss in the first stage was measured, where the diagnostic setup for
measuring the diode current and voltage waveforms is identical to the measurements of
the first stage IGBT waveforms. However, a differential voltage measurement was taken
by subtracting the output voltage from the IGBT collector voltage to obtain the voltage
across the diode. The analysis of determining average power loss is also the same as the
IGBT average power loss. High frequency oscillations and noise occurring in the
following waveforms are significant, but considered to be a result of stray capacitance
and inductance in the diagnostic equipment and circuit. Such oscillations produce zero
net energy loss after integration as they are purely reactive. Figure 5.11 and Figure 5.12
display the diode current and voltage waveforms.
The parallel SiC Schottky diodes exhibit very low reverse recovery current loss.
The small negative current aberration following the 8 µs mark may be due to junction and
stray capacitance as a result of the time rate of change in the diode voltage [1-3]. The
first stage diode average power loss has been determined to be 1.67 W from an integrated
95
energy loss of 0.87 mJ per pulse. As a comparison, the diode loss represents only 1.7%
of the IGBT loss. This loss generally agrees with the very small temperature rise of the
heat sink on which the diodes are mounted.
First Stage Diode Waveforms
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 1 2 3 4 5 6 7 8 9Time ( µs )
Dio
de V
olta
ge (
V )
-5
0
5
10
15
20
25
30
35
Dio
de C
urre
nt (
V )
First stage diode voltage
First stage diode current
Figure 5.11 First stage diode voltage and current waveforms.
96
Firs t Stage Diode Power Waveform
-500
0
500
1000
1500
2000
0 1 2 3 4 5 6 7 8 9Tim e ( µs )
Pow
er (
W )
Eloss=0.82 mJ
Figure 5.12 First stage diode power loss waveform. Integrated energy loss is 0.82 mJ per pulse and
average power loss is 1.67 W.
The second stage diode was also measured with the same diagnostic setup as the
first stage diode loss measurements, and the loss was determined using the same
procedure as the first stage diode loss above. Figure 5.13 and Figure 5.14 displays the
voltage and current waveforms, along with the power loss waveform for the second stage
diode. The average power loss of 4.13 W was determined from 0.457 mJ integrated
energy loss per pulse. Since six diodes are connected in series, 690 mW per diode is
dissipated as heat. The temperature rise of these diodes is practically imperceptible.
97
Second Stage Diode Waveforms
-200
-150
-100
-50
0
50
100
150
200
10 11 12 13 14 15 16 17 18Time ( µs )
Dio
de V
olta
ge (
V )
-1
0
1
2
3
4
5
6
7
Dio
de C
urre
nt (
V )
Second stage diode voltage
Second stage diode current
Figure 5.13 Second stage diode voltage and current waveforms.
Second Stage Diode Power Waveform
-600
-400
-200
0
200
400
600
800
10 11 12 13 14 15 16 17Time ( µs )
Pow
er (
W )
Eloss=0.457 mJ
Figure 5.14 Second stage diode power loss waveform. Integrated energy loss is 0.457 mJ per pulse and
average power loss is 4.13 W.
98
5.2.4 Total Component Loss Calculation
In order to complete the total component loss calculation, the capacitor and
inductor loss must be determined. The capacitor loss is estimated by using the equivalent
series resistance, capacitor RMS current, and calculation of the I2R loss. The RMS value
of the first stage filter capacitor, C1, can be found by addition of the RMS current flowing
into C1 through D1, and current flowing out of C1 through L2. The RMS values are
calculated in a simple MATLAB routine from the measured current waveforms. The
current values calculated are
ID1 = 7.064 A rms and
IL2 = 3.55 A rms,
where ID1 is the RMS current into C1 and IL2 is the current out of C1. The MATLAB
routine for the RMS calculation is shown in Appendix D. The resultant C1 current equals
3.514 A rms. The current through C2 is 1.204 A rms using a similar procedure as with
the C1 current. Both capacitors have approximately 0.5 Ω series resistance.
The total capacitor power loss is given in Table 5.8, along with a summary of the
component losses presented in the previous sections. The inductor loss was determined
by neglecting stray system resistance loss, and assuming the inductors consume the
remaining loss. The following accounts for the total power loss of the inductor of each
stage, which includes core and I2R winding loss:
inductor total switch diode capacitorP P P P P= − − − , [5.5]
99
where Ptotal is the total power loss per stage, Pswitch is the IGBT loss, Pdiode is the diode
loss, and Pcapacitor is the capacitor loss as shown in Table 5.8 below.
Table 5.8 Average component power loss.
Total Loss per Stage
Switch Loss
Diode Loss
Capacitor Loss
Inductor Loss
First Stage 152.9 W 98.6 W 1.7 W 6.2 W 46.5 W
Second Stage 153.1 W 104.7 W 4.1 W 0.5 W 43.8 W
Total Average power ( W ) 306.0 W 203.3 W 5.8 W 6.7 W 90.3 W
5.3 Optimization of the Prototype Converter
The component loss analysis provides the insight as to where further design can
achieve a higher efficiency of the converter. According to Table 5.8, the switches and
inductors are the leading component losses of the prototype converter. As such, it is
believed that a loss mitigating design of the switches and inductors can significantly
improve the efficiency. In particular, the first stage inductor, made up of four inductors
in series in the prototype, can be re-designed as a single more efficient inductor, which
can utilize nanocrystalline core material similar to the second stage inductor design and
likely have reduced winding loss [4-5]. For the switches, minimizing the stray
inductance in the first and second stage IGBT connections will reduce voltage overshoot
during turn-off and the subsequent power loss. However, a significant improvement to
the switching loss can be made through dedicated research towards optimizing the turn-
off time. For instance, a thorough semiconductor trade study can reveal alternative
100
IGBTs with faster turn-off times for the first stage and second stage switch. For example,
the latest generation of fast-stop and light punch through IGBTs show evidence of faster
turn-off time than the non-punch through IGBTs in the prototype [6-7]. Also, faster
switching speed may be possible with experimentation with device configurations, such
as increasing the number of parallel IGBTs in the first stage or possibly even utilizing a
series and parallel matrix of high speed MOSFET devices. Additionally, development of
the gate drive circuitry, such as ultra-low impedance gate circuit can expedite gate charge
removal during the turn-off process. These efforts of lowering the switching loss and
optimizing the inductors have the potential for a future prototype converter design with
an efficiency as high as 90%. For this efficiency, the total loss of a 1 kW output
converter must be reduced to 111 W. The switching loss must be reduced by
approximately 75% and the inductor loss must be reduced by approximately 50% of the
presented prototype converter’s switching and inductor loss, respectively.
101
REFERENCES FOR CHAPTER 5.0 [1] V. K. Khanna, IGBT Theory and Design, Piscataway, NJ: IEEE Press, 2003.
[2] Cree Inc. application note; CPWR-AN03 (www.cree.com)
[3] G. Spiazzi, “Performance evaluation of a Schottky SiC power diode in a boost PFC application,” IEEE Trans. Power Electronics, vol. 18, issue 6, pp. 1249-1253, Nov. 2003.
[4] M. Ferch, “Light transformers for kilowatt SMPS based on nanocrystalline soft magnetic cores,” in Proc. of Seventh Int. Conf. on Power Electronics and Variable Speed Drives, 1998, pp. 411-415.
[5] W.A. Rease, “Design technology of high-voltage multi-megawatt polyphase resonant converter modulators” in Proc. of 29th Annu. Conf. IEEE Industrial Electronics Society, 2003, pp. 96-101.
[6] H, Husken, “FieldStop IGBT with MOS-like (tailless) turn-off,” in 2003 Proc. ISPSD, pp. 338-340.IGBT with MOS-like (tailless) turn-off,” in 2003 Proc. ISPSD, pp. 338-340.
[7] J. Yamada, “Low Turn-off Switching Energy 1200V IGBT Module,” in 2002 Proc. Industry Applications Conf., pp. 2165-2169.
102
CHAPTER 6.0 CASCADE BOOST CONVERTER SCALING TO HIGHER POWER LEVELS
The prototype cascade boost converter has provided a basis for a cascade boost
converter scaled to the higher voltage and power output levels of 60 kV and 300 kW, as
listed in Table 6.1, for power conditioning applications such as gyrotron microwave
tubes. As discussed in Chapter 1, gyrotron tubes require a high voltage source for
support of the high current electron gun in the depressed collector configuration. To
achieve this power conditioning output, the cascade boost circuit equations of Chapter 2,
and performance of the prototype converter have been integrated, and are used to derive
the higher power design. The DC input has also been selected as 1 kV for the converter
design, which requires a total converter step-up gain of 60 instead of 50, as in the
prototype converter. Multiple converters must be paralleled to achieve the constant
current, megawatt gyrotron tube power requirements of 2.4 MW provided by CPI in
Chapter 1. Thus, eight 300 kW converters modules must be paralleled to deliver 40 A, at
60 kV, to produce 2.4 MW of power. The following sections provide a near-term, 5-year,
and a 10-year volume and mass estimate of the cascade boost converter module, which
indicate a potential for a very compact and lightweight converter design.
Table 6.1 Cascade boost converter specifications for a 60 kV, 300 kW module.
Voltage Input 1000 V Voltage Output 60 kV Power Output 300 kW
103
6.1 Near-Term Technology Based Scaling
The design equations of Chapter 2 have been integrated into the design of the 60
kV, 300 kW cascade boost converter. The parameters calculated for an ideal 300 kW
cascade boost converter are shown in Table 6.2. The parameters of this system differ
from the 5 kV prototype system in correlation to the higher voltage step-up ratio of 60
and lower impedance load to deliver a 5A output. The load has been simplified as a
constant resistive load for a constant current electron beam, although in practice the load
can be modeled as a complex and time-varying impedance. These parameters are also
ideal parameters for a lossless converter, and have been calculated using synchronous
switching waveforms for both stages.
From the ideal converter design, the switching parameters must be modified for
the losses in an actual system. If the estimated efficiency of a 300 kW converter is
established to be 90%, which is believed to be a realistically achievable value based
primarily on mitigated switching losses as discussed in section 5.3, the total power loss
will be 33.3 kW. The parameters corresponding to a system with a 90% efficiency are
shown in Table 6.3. Thus, the parameters have been calculated to provide an average
input current of 333.3 A for an average input power of 333.3 kW. It has been assumed
that each stage contributes half of the power loss, similar to the results of the 5 kV
prototype cascade boost converter. For total system efficiency of 90%, each stage of the
300 kW converter must have an efficiency of approximately 95%. Therefore, the second
stage average input current has been adjusted to be 63.3 A for an average second stage
104
input power of 316.5 kW. The current waveforms through L1 and L2 indicate the peak
switch turn-off current of each stage, which is utilized for scaling the parallel diode and
switch assemblies and inductor core sizes. Also, due to the increasing duty ratio, the
capacitances C1 and C2 increase slightly; the adjusted capacitance values have been
determined to reflect the realistic capacitance values of a non-ideal converter.
Table 6.2 Ideal parameters calculated for a 60 kV, 300 kW cascade boost converter.
Switching frequency 10 kHz (both stages) Ideal duty ratio 0.6 (both stages) Load impedance 12 kΩ Average output current 5 A L1 74.9 µH L2 1.64 mH C1 110 µF C2 788 nF
Table 6.3 Switching parameters adjusted, corresponding to 90% efficiency.
Efficiency 90 % Average input power 333.3 kW Duty ratio D1 0.632 Duty ratio D2 0.617 L1 peak current 844 A L2 peak current 188 A C1 125 µF C2 1 µF
The following presents the methodology for the converter volume and mass
estimation using the values found in Table 6.3. The active switching components of the
first and second stages were designed as assemblies of series and parallel IGBTs similar
to the assemblies implemented in the 5 kV cascade boost converter prototype. The
primary switching device is based on the Powerex CM300DY-24NF IGBT module,
105
which has a rating of 1200 V and 300 A with two IGBTs integrated into a single IGBT
module package. This IGBT module is the latest generation of IGBT devices and
represents modern, high performance switching devices produced with silicon. This
IGBT uses trench-gate technology for reduced on-state voltage and the Light Punch
Through doping structure (discussed at the end of section 3.1.2) for fast charge carrier
recombination at turn-off, and is optimized for high switching frequency and low turn-off
loss. The device was selected based on published low turn-off energy loss figures and
high switching frequency ability [1]. The reported turn-off energy per pulse is 8.4 mJ
(0.028 mJ/A turn-off loss) with a bus voltage 600 V and switching 300 A [2]. Series and
parallel arrangement of these modules for S1 and S2 have low loss, where the turn-off
energy loss is considered the primary loss. The necessary number of devices in series
and parallel for S1 and S2 is shown in Table 6.4. The voltage and current per device
during turn-off and the average expected assembly turn-off loss, based on reported turn-
off energy loss per device, is shown in Table 6.5. Utilizing the reported energy loss
relation of 0.028 mJ/A and switching 281.3 A (shown in Table 6.5), the energy loss is
approximately 7.9 mJ per pulse. However, scaling the loss in relation to the higher
voltage of 833.3 V (instead of 600 V), scales it up by 38% to 11 mJ per pulse. The
switching frequency for the calculation of the turn-off loss is 10 kHz, which gives
approximately 110 W per IGBT.
106
Table 6.4 Number of IGBT modules in series and parallel for assembly of S1 and S2.
No. of series IGBTs
No. of parallel IGBTs
Total modules (2 IGBTs per module)
S1 6 3 9 S2 73 1 37
Table 6.5 Expected voltage and current per IGBT, and total average turn-off loss.
Voltage per IGBT
Current per IGBT
Average turn-off loss
S1 833.3 V 281.3 A 1980 W S2 810.8 V 188 A 5402 W
The cooling of the assemblies for the near-term is estimated based on COTS
liquid cooled heat sinks. On-board cooling systems of mobile platforms, such as aircraft
oil cooling, integrated with these liquid heat sinks will minimize the size and eliminate a
dedicated heat exchanger. The heat sink design is based on a flowed water component
from Aavid Thermalloy with 0.002 ºC/W thermal resistance rating for a 0.6”x7”x24”
model (part #: 416301U). The thermal resistance ratings of IGBT module cases and heat
sinks were used to maintain IGBT junction temperature below 125 ºC with the expected
power loss and liquid coolant temperature of 25 ºC. The junction temperature is found as
[6.1]
( )j d th lT P R T= + , [6.1]
where Pd is the average power loss, Rth is the total thermal resistance from IGBT chip
junction to the liquid coolant, and Tl is the liquid coolant temperature [3]. The volume
and mass of switches S1 and S2 (including heat sinks and IGBT assemblies) is included in
107
the component data for the first and second stage, which is shown in Table 6.6 and Table
6.7, respectively.
The inductor scaling method uses the second stage inductor dimensions of the 5
kV converter prototype and scales them up for the first and second stage inductors in the
60 kV, 300 kW converter design. This method provides an approximate estimate for the
projected inductor volume and mass. First, the peak flux density, Bm, of the inductor
cores is assumed to be conserved from the prototype as the inductor currents are scaled
up to 844 A and 188 A from the lesser prototype current levels for L1 and L2,
respectively. The peak flux density must be conserved since the inductor core must
operate below the magnetic saturation level of the nanocrystalline core material. Since
Bm is inversely proportional to the core area and directly proportional to the magnetic
flux, the relation becomes [6.2]:
mm
cB
AΦ
= . [6.2]
where, Ac is the core cross section area and Φm is the maximum flux that occurs at peak
inductor current. If the inductor parameters are constant, then Bm is proportional to the
projected increased inductor current, by the following equation [6.3]:
4
g
0.4 102
l
DCm
c
IN IBm
A
π −∆⎛ ⎞+ ×⎜ ⎟Φ ⎝ ⎠= = [6.3]
108
where lg is the air gap length, N is the number of inductor winding turns, IDC is the DC
current level, and ∆I is the peak current level [4]. However, Bm can remain constant,
despite increases in the current level, by manipulating N and lg from equation [6.3] and
the core area Ac from equation [6.2]. If the inductor core area, Ac, is scaled by a factor
limited to approximately one-half of the scaling factor for peak inductor current value,
which requires a new winding density and longer air gap distance for increased core
reluctance, then the approximated scaling relation can be shown in equation [6.4]:
2
IA
SS = , [6.4]
where SA is the inductor core area scaling factor, and SI is the scaling factor for the peak
inductor currents from the prototype converter. The total volume and weight of the
inductor can then be scaled as the cube of the change in the length of one side of the
core’s cross-section area, based upon general inductor and transformer scaling trends [4].
If the core cross section area has an area scaling factor of SA as shown above, then the
length of one side of the core’s cross section is approximately proportional to the square-
root of SA. Thus, the inductor volume and mass scaling factor, SL, is equal to the
following equation [6.5]:
( )3L AS S= , [6.5]
109
where AS is the scaling factor of one of the sides of the core’s cross-section. The
dimension scaling factor SL allows for the inductor volume and mass scaling based on the
increase of inductor current in the 300 kW converter scaled up from the inductor current
of the 5 kV prototype converter. This method creates a scaling factor by conserving the
magnetic flux density, Bm in the first and second stage inductor cores, and by using the
second stage inductor in the 5 kV prototype as the baseline. The scaled inductor volume
and mass of L1 and L2 is shown in Table 6.6 and Table 6.7, respectively.
The diodes of the 60 kV converter have been scaled based on the diodes of the 5
kV converter prototype. The two parallel diodes of D1 in the prototype effectively form a
single diode module that is used as a model for a 500 V, 50 A rated diode module, and
the six series diodes of D2 in the prototype likewise form a 5000 V, 10 A diode module.
These diode modules, arranged in parallel and series, create the diodes for the 60 kV
converter. The volume and mass of D1 and D2 in the 60 kV converter are displayed in
Table 6.6 and Table 6.7, respectively.
Finally, the capacitors for near-term cascade boost converter were estimated
based upon the existing energy densities (J/cc) for high voltage capacitors. The
capacitors used in the 5 kV converter prototype did not provide the baseline for modern
technology, instead the energy density value of 0.47 J/cc and mass density value of 1.2
g/cc, of modern COTS capacitors were utilized for determining the mass and volume of
the capacitors in the converter. The capacitor data was taken from General Atomics
capacitor datasheets. The overall volume and mass was estimated based on these
110
volumes along with the amount of energy stored in C1 and C2. The energy stored in the
capacitors is found by [6.6]
212
storedE CV= (Joules), [6.6]
where V is the voltage across the capacitors. Using the capacitance value shown in Table
6.3, the energy stored in C1 (125 µF) is 1,562.5 J and the energy stored in C2 (1 µF) is
1,800 J. The volume and mass of C1 and C2 is shown in Table 6.6 and Table 6.7,
respectively.
Table 6.6 First stage components volume and mass for the near-term 60 kV, 300 kW converter.
in3 lbs S1 421.0 41.0 L1 565.2 46.0 D1 233.8 13.1 C1 202.9 8.8 Total 1,422.8 108.9
Table 6.7 Second stage components volume and mass for the near-term 60 kV, 300 kW converter.
in3 lbs S2 1,538.0 150.0 L2 3,348.0 96.0 D2 149.6 6.2 C2 233.7 10.1 Total 5,277.2 262.3
The component volume and mass data are displayed by the component category
in Table 6.8. The estimated mass of the near-term cascade boost converter shows that the
111
switches in the system consume about 50% of the mass, and the inductors consumes
about 38% of the converter mass.
Table 6.8 Estimated volume and mass of components of the near-term 60 kV, 300 kW converter.
in3 lbs Switches 1,959.0 191.0 Inductors 3,913.2 142.0 Diodes 383.3 19.3 Capacitors 436.6 18.9 Total 6,692.1 371.2
The total component volume and mass values in Table 6.9 do not describe a
completely packaged and operational 300 kW cascade boost converter. The total
component volume and mass values have been adjusted by a factor of 20% to estimate a
complete converter, accounting for the additional volume and mass of the converter
enclosure, shielding, support structure, control system electronics, insulation, and
possibly shock and vibration damping. Table 6.9 shows the estimated power density of
the near-term 60 kV, 300 kW converter using existing technology is approximately 1.5
lbs/kW.
Table 6.9 Total near-term projected component volume and mass and complete system volume and mass of a 300 kW converter. The 20% scaling factor estimates additional volume and mass for a completely
packaged and operational converter.
in3 lbs lbs/kW Total Component 6,692.1 371.2 Complete System
(20% factor) 8,030.5 445.4 1.5
112
6.2 Five & Ten-year Future Technology Scaling
Future technologies such as Silicon Carbide (SiC) semiconductor devices offer
the potential for great power density improvement of power conditioning systems.
Increased switching frequency and higher voltage handing per device are the leading
factors for the following projected reduction in volume and mass of the 300 kW cascade
boost converter module. The 1200 V SiC Schottky diode, implemented in the 5 kV
cascade boost converter prototype, already has shown advantages such as fast switching
speed and zero reverse recovery current [5-6]. Research has demonstrated SiC devices
will have a substantial impact on switch-mode converters and high voltage power
conditioning applications [7-9]. A switch-mode converter using 200 V SiC devices
(JFETs and diodes) has demonstrated reduced passive component size and higher power
density, which is largely due to approximately 6.7 times higher switching frequency than
a comparable converter with Si devices [10].
Properties of SiC that make the material so attractive for high voltage
semiconductor devices, compared to Si, include higher electric field breakdown, higher
thermal conductivity, larger saturation velocity, and higher operating temperature. The
SiC devices are known as wide band gap semiconductor devices—the band gap energy of
SiC is more than twice as large as Si. Table 6.10 lists the specific qualities of SiC in
comparison to Si. The band gap energy level affects the semiconductor material
operating temperature range and electric field breakdown strength. Two polytypes of SiC
that are used as semiconductor material: hexagonal 4H-SiC and 6H-SiC. The 4H-SiC
113
however is more commonly employed than 6H-SiC, which includes a higher band gap
and higher electron mobility.
Table 6.10 Properties of SiC that will enhance power semiconductor devices.
Si 4H-SiC Band Gap Energy 1.12 ev 2.2-2.9 ev Electric Field Breakdown 300 kV/cm 4000 kV/cm Thermal Conductivity ~ 1.5 W/cm-˚C ~ 5 W/cm-˚C Saturation Velocity ~ 1x107 cm/s ~ 2x107 cm/s Max Junction Temp. 150˚C 300˚C
The first generation of high voltage SiC devices used may not be IGBTs or
MOSFETs, instead SiC BJT power switching devices may enter the market first [11-14].
Apparently, gate oxide issues and low channel mobility coupled with material science
issues are the major challenges for high power SiC MOS controlled devices. These
challenges result in SiC gate structures which have reliability issues and high on-state
resistance in the inversion layer. Devices that do not use MOS control, such as the BJT,
eliminate such problems. High voltage, SiC BJT devices have recently been
demonstrated [15]. Also, BJTs and other minority carrier devices can theoretically
exhibit approximately 100 times faster switching speed than equivalent Si devices [16].
This is due to SiC’s 10 times higher electric field strength, which allows voltage blocking
layers to be made 0.1 times as thick. The ten-fold reduction in thickness of the voltage
blocking layers allows for a proportional reduction in the diffusion length of injected
minority carriers, and the shorter diffusion length reduces the carrier lifetime to 100 times
less. As discussed in Chapter 3, such reduction in carrier lifetime impacts the effect of
the current tail at turn-off, to be nearly eliminated. The SiC devices also offers thinner
114
base regions than Si, which allows SiC BJTs to operate with higher current gain (beta) for
reduced base drive current to control the device. The future SiC BJT, with fast switching,
high beta, and avoidance of problematic MOS control issues, becomes a strong candidate
for the first generation of commercial high voltage and high power SiC switching.
However, the SiC BJT may also share the same trend as the Si BJT ancestor. Ultimately,
with technical solutions of the aforementioned SiC material science challenges with SiC,
voltage controlled MOS SiC devices will be the next standard for solid state power
devices.
Reevaluation of the cascade boost converter using future SiC technology,
projected for the time range of 5 and 10 years, provides a technological basis for an
estimated size and weight reduction of the 300 kW cascade boost converter. The voltage
ratings and switching frequencies for these devices in 5 and 10 years have been
estimated. However, estimating the trend of SiC devices is highly unpredictable, as SiC
represents a new paradigm in semiconductors that is currently very young, and can only
represent a hypothesized technology projection. Therefore these estimates are based on
demonstrations, simulations, and projections found in published literature of SiC research
and development efforts [7] [10] [17-19]. A summary of the projected key parameter
estimates are shown in Table 6.11. The following 5-year trend estimate is that SiC
devices, implemented in the cascade boost converter, will achieve voltage blocking
ratings of 5 kV, and the switching speed will be increased to 70 kHz. The 10-year trend
estimate is that 8 kV ratings will exist per SiC device, and the switching frequency will
be increased to 100 kHz.
115
The faster switching ability of the SiC devices allows the converter to be operated
at the higher switching frequencies. However, the switching frequencies for the two time
frames are assumed to be limited by average switching power loss, which has been
assumed to be equal to the near-term average switching loss displayed in Table 6.5.
Thus, the average power loss in the semiconductor devices for all three time frames will
be assumed constant. This increase in switching frequency will reduce the volume and
mass of the inductors, which scale inversely proportional to the switching frequency. For
instance, the first stage inductor volume and mass has been scaled for the 5-year trend to
be one-seventh, or 14.3%, of the first stage inductor in the near-term because of the seven
times switching frequency increase. The ideal inductor derivation in Chapter 2 indicates
the linear relationship with the switching frequency.
Likewise, the capacitance value required for the first and second stage filter
capacitors will reduce linearly with the increase in frequency according the derivations in
Chapter 2. Subsequently, the energy storage requirement reduces linearly with the
capacitance in the 5 and 10-year time frames according to equation [6.6]. Also, energy
densities of 1 J/cc and 5 J/cc are anticipated to be available in the 5 and 10-year terms,
respectively, based upon reports in published literature [20-21]. The reduced energy
storage requirement, compounded with future high energy density dielectric technology,
result in dramatic size reduction of the capacitors. The first and second stage output
capacitors of the cascaded boost converter reduce to the resultant volume and mass of
approximately 6.7% of the near term, for the 5-year trend, and 1% of the near term, for
the 10-year trend. This advance in capacitor technology and the increase in switching
116
frequency reduce the first and second capacitors down to the size of circuit board
mountable components.
The higher voltage capability of SiC devices will reduce the necessary number of
devices in series for each switch stack assembly. The first and second stage switch
volume and mass are linearly scaled based on the number of devices, in the 5 and 10-year
assemblies, relative to the number of devices in the near-term switch assemblies. The
number of devices to be used in series and parallel for the first and second stage switch
assemblies, for the two time frames, is shown in Table 6.12.
Table 6.11 Summary of the key parameter estimates for SiC devices in 5 and 10 years.
5-year 10-year Voltage rating per device 5 kV 8 kV Converter switching freq. 70 kHz 100 kHz
Table 6.12 Number of devices to be placed in series and parallel for the 5 and 10-year time frames for the 300 kW converter’s first and second stage switches.
5-year (5 kV rated devices) 10-year (8 kV rated devices) Series Parallel Series Parallel
S1 2 3 1 3 S2 20 1 10 1 26 devices 13 devices
As discussed above, the average switching loss in the 5 and 10-year estimates will
remain equal to the near-term switching loss although fewer devices will be
implemented. Thus, the average power loss, on an individual device basis, will increase.
However, an estimation of future advanced cooling technology will allow for a favorable
scaling of the thermal management hardware, based on the literature available on
advanced cooling methods. The near-term switching assemblies have been designed with
117
conventional water cooled, bulk-aluminum heat sinks, with lower heat flux than
advanced technologies, which have been primarily motivated by the thermal management
needs of high performance server CPUs, VLSI devices, and high-density power
electronics. High heat flux removal from micro-channel systems for local heat extraction
has shown the ability to remove to up to 500 W/cm2 in local hotspots [22]. Future heat
flux may reach 1000 W/cm2 with the optimization of multi-phase fluid flow within
micro-channels for a number of future systems [23]. Furthermore, the near-term estimate
uses IGBT modules with standardized industrial packaging. Integrated, on-chip cooling
has been pursued for densely packed, high performance IC’s for highly efficient heat
extraction [22]. Customized packaging with integration of the cooling system within the
device package can eliminate the contact resistance between the IGBT base plate and the
heat sink. Finally, the typical maximum junction temperature of SiC is approximately
double the maximum junction temperature of Si, which reduces the required thermal
resistance of the cooling system by a factor of 2.
The approximated scaling, of the 300 kW converter’s cooling system volume and
mass, is assumed to be linear in relation to the number of switches in the 5 and 10-year
time frames. Therefore, the total switch assembly volume and mass will be directly
related to the reduction of the number of switches and diodes. For instance, the first stage
switch design in the 5-year trend will have a total mass of 13.7 lbs, or one-third of the
mass of the same assembly in the near-term, since there will be one-third the number of
devices in the assembly as in the near-term.
118
Table 6.13 and Table 6.14 show the first and second stage component volume and
mass for the 5-year and 10-year technology trend estimates. Table 6.15 shows a
breakdown per component of the cascade boost converter in the 5 and 10-year trends.
Table 6.16 and Table 6.17 give the estimates for the final system for the 5 and 10-year
trends including a 20% factor for additional volume and mass for a fully packaged and
operational converter. As with the near-term converter estimate, the 20 % accounts for
the additional hardware that may include the converter enclosure, shielding, support
structure, control system electronics, insulation, and possibly shock and vibration
damping.
119
Table 6.13 First stage component projected volume and mass for the 5 & 10-year trend in a 60 kV, 300 kW converter module.
5-year 10-year in3 lbs in3 lbs
S1 140.3 13.7 70.2 6.8 L1 80.7 6.6 56.5 4.6 D1 46.8 2.6 23.4 1.3 C1 13.6 0.6 1.9 0.1
Total 281.4 23.4 152.0 12.8
Table 6.14 Second stage component projected volume and mass for the 5 & 10-year trend in a 60 kV, 300
kW converter module.
5-year 10-year in3 lbs in3 lbs S2 421.4 41.1 209.7 20.4 L2 478.3 13.7 334.8 9.6 D2 52.5 2.2 26.2 1.1 C2 15.7 0.7 2.2 0.1
Total 967.8 57.7 573.9 31.1
Table 6.15 Estimated total volume and mass of each component category in a 60 kV, 300 kW converter
module.
5-year 10-year in3 lbs in3 lbs
Switches 561.7 54.8 280.9 27.4 Inductors 559.0 20.3 391.3 14.2 Diodes 99.2 4.8 49.6 2.4 Capacitors 29.3 1.3 43.7 1.9
Total 1,249.3 81.1 725.9 44.1
Table 6.16 5-year total projected component and complete system volume and mass for a 60 kV, 300 kW
converter module. The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter.
120
5-year scaled in3 lbs Lbs/kW
Total Component 1,249.3 81.1 Packaged System
(20% factor) 1,499.1 97.3 0.32
Table 6.17 10-year total projected component and total system volume and mass for a 60 kV, 300 kW
converter module. The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter.
10-year scaled in3 lbs Lbs/kW Total Component 725.9 44.1 Packaged System
(20% factor) 871.1 53.0 0.18
The volume and mass trends for a 300 kW converter in the near-term and for the 5
and 10-year projections are displayed in Figure 6.1 and Figure 6.2 respectively. Figure
6.3 and Figure 6.4 display the significant mass reduction trend for a 1.2 MW and 2.4 MW
system, where four 300 kW converters are paralleled for the 1.2 MW output and eight are
paralleled for the 2.4 MW power output. The mega-watt class power converter shows an
attractive scaling profile, where the projected technology advancements in high voltage
semiconductor devices can greatly increase the power density of high power conditioning
systems. The scaling indicates the potential of multi-megawatt class conversion under
500 lbs. The compact and lightweight potential of the cascade boost converter design
enables mega-watt class power support for applications such as gyrotrons aboard mobile
platforms.
121
Volume Scaling of a 300 kW Converter
871
1,499
8,031
0
1,000
2,000
3,000
4,000
5,000
6,000
7,000
8,000
9,000
Near-term 5-year 10-year
Vol
ume
( In
3 )
Figure 6.1 300 kW converter volume scaling from estimated technology trends.
Mass Scaling of a 300 kW Converter
97
445
53
0
100
200
300
400
500
Near-term 5-year 10-year
Mas
s ( L
bs )
Figure 6.2 300 kW converter mass scaling from estimated technology trends.
122
Volume Scaling of a 1.2 & 2.4 MW Converter
64,244
6,9693,4845,997
32,122 11,993
0
20,000
40,000
60,000
80,000
100,000
120,000
Near-term 5-year 10-year
Vol
ume
( In
3 )
2.4 MW Vol1.2 MW Vol
Figure 6.3 1.2 and 2.4 MW converter volume scaling using parallel 300 kW converter modules.
Mass Scaling of a 1.2 & 2.4 MW Converter
389
1,781
212
3,563
424
779
0
400
800
1,200
1,600
2,000
2,400
2,800
3,200
3,600
4,000
Near-term 5-year 10-year
Mas
s ( L
bs )
1.2 MW Mass2.4 MW Mass
Figure 6.4 1.2 and 2.4 MW converter mass scaling using parallel 300 kW converter modules.
123
REFERENCE FOR CHAPTER 6.0 [1] E.R. Motto and J.F. Donlon, “The latest advances in industrial IGBT module
technology,” in Proc. Applied Power Electronics Conference and Exposition, 2004, pp. 235-240.
[2] J. Yamada, “Low Turn-off Switching Energy 1200V IGBT Module,” in Proc. Industry Applications Conf., 2002, pp. 2165-2169.
[3] N. Mohan, Power Electronics, 2nd Edition. New York: John Wiley & Sons, 1995.
[4] Wm. T. McLyman, Magnetic Core Selection for Transformers and Inductors, New York and Basel: Marcel Dekker, Inc., 1964.
[5] A. Elasser, “A comparative evaluation of new silicon carbide diodes and state-of-the-art silicon diodes for power electronic applications,” IEEE Trans. on Industry Applications, vol. ED-39, pp. 915-921, July-Aug. 2003.
[6] G. Spiazzi, “Performance evaluation of a Schottky SiC power diode in a boost PFC application,” IEEE Trans. on Power Electronics, vol. ED-18, pp. 1249-1253, Nov. 2003.
[7] J. A. Cooper “SiC Power-Switching Devices—the Second Electronics Revolution?,” Proceedings of the IEEE, vol. ED-90, pp. 956–968, June 2002.
[8] A. Elasser and T.P. Chow, “Silicon carbide benefits and advantages for power electronics circuits and systems,” Proceedings of the IEEE, vol. ED-90, pp. 969-986, June 2002.
[9] J. Wang and B.W. Williams, “Evaluation of high-voltage 4H-SiC switching devices,” IEEE Trans. on Electronic Devices, vol. ED-46, pp. 589-597, March 1999.
[10] Abou-Alfotouch, “1 MHz hard-switched silicon carbide DC/DC converter.” in Proc. Applied Power Electronics Conference and Exposition, 2003, pp. 132-138.
[11] A.K. Agarwa, ”Recent progress in SiC bipolar junction transistors,” in Proc. Power Semiconductor Devices and ICs, 2004, pp. 361-364.
[12] Yanbin Lou, “High voltage (>1kV) and high current gain (32) 4H-SiC power BJTs using Al-free ohmic contact to the base,” IEEE Electronic Device Letters, vol. ED-
124
24, pp. 695-697, Nov. 2003.
[13] Y. Lou, “Fabrication and characterization of high current gain (Beta =430) and high power (23a-500V) 4H-SiC Darlington bipolar transistors,” IEEE Trans. on Electronic Devices, vol. ED-51, pp. 2211-2216, Dec. 2004.
[14] R. Sei-Hyung, “1800 V NPN bipolar junction transistors in 4H-SiC,” IEEE
Electronic Device Letter, vol. ED-22, pp. 124-126, March 2001.
[15] J. Zhang, “Demonstration of first 9.2 kV 4H-SiC bipolar junction transistor,” IEEE Electronic Device Letters, vol ED-40, pp. 1381-1382, Oct. 2004.
[16] T.R. McNutt, ”Silicon carbide PiN and merged PiN Schottky power diode models implemented in the Saber circuit simulator,” IEEE Trans. on Power Electronics, vol ED-19, pp. 573-581, May 2004.
[17] A.Q. Huang, “The future of bipolar power transistors,” IEEE Trans. on Electronic Devices, vol ED-48, pp. 2535-2543, Nov. 2001.
[18] C.M. Johnson, “Comparison of silicon and silicon carbide semiconductors for a 10 kV switching application,” in Proc. Power Electronics Specialists Conf., 2004, pp. 572-578.
[19] P.G. Neudeck, “High-temperature electronics - a role for wide bandgap semiconductors?,” Proceedings of the IEEE, vol. ED-90, pp. 1065-1076, June 2002.
[20] F.W. McDougal, “High energy density pulsed power capacitors,” in Digest of Technical Papers of Pulsed Power Conf., 2003, vol. 1, pp. 513-517, June 2003.
[21] M.V. Fazio, “Ultracompact Pulsed Power,” Proceedings of the IEEE, vol. 92, pp. 1197-1204, July 2004.
[22] G. Upadhya, “Closed-loop cooling technologies for microprocessors,” in Tech Digest IEEE Int. Electron Devices Meeting, 2003, pp. 32.4.1 - 32.4.4.
[23] D. Faulkner, “Practical design of a 1000 W/cm2 cooling system,” in Proc. 19th Annu. IEEE Semiconductor Thermal Measurement and Management Symposium, 2003, pp. 223-230.
125
CHAPTER 7.0 CONCLUSION
This work has provided the design of the cascade boost converter topology, which
has been experimentally demonstrated as a viable converter for high step up ratio, high
voltage, DC-DC conversion through a prototype cascade boost converter. The equations
derived, successfully enabled the design, fabrication, and testing of the prototype cascade
boost converter by producing a 5 kV DC, 1 kW output from a constant 100 V input at an
efficiency of 76.6%. Furthermore, with the fruition of anticipated high voltage silicon
carbide power devices and high energy density capacitor dielectrics, the power density of
high voltage power conditioning systems will drastically increase. The cascade boost
converter topology has been shown to have very attractive scaling trends in response to
these technological advances for the 5 and 10-year projections.
The cascade boost converter prototype was designed based on the theoretical
converter work as described in Chapter 2. After the circuit analysis of the prototype, the
switches and inductors appear to be the leading sources of power loss in the converter.
Chapter 3 presented a discussion on IGBT switching considerations, where the
application of IGBTs must take into consideration switching loss, with respect to the
voltage rating of the IGBTs. Six series, 1200 V rated IGBTs implemented for the second
stage switch, enabled a 76.6% total prototype efficiency, and was compared to two series
3.3 kV rated IGBTs, as the second stage switch, which resulted in a lower prototype
efficiency of 37%. As discussed in Chapter 5, further research on semiconductor devices,
with optimization of series and parallel arrangement, will likely extend high voltage
126
capability and mitigate switching losses in future designs of the cascade boost converter.
Also, dedicated inductor optimization may reduce copper winding and magnetic core
hysteresis loss of the first and second stage inductors. An efficiency reaching 90% may
likely be realized with dedicated component optimization and circuit fabrication, which
has been based on testing of the cascade boost prototype converter.
Using the assumption that 90% efficiency is possible, system scaling in Chapter 6
for a 60 kV and 300 kW converter for the near-term, 5-year, and 10-year time frames
have been estimated. The scaling uses the basic series and parallel switching concepts
implemented by the prototype cascade boost converter. The COTS IGBT module used
for the first and second stage switch assemblies, in the 60 kV converter design, is a 1200
V, 300 A device that exhibits low turn-off loss, and has been optimized to mitigate the
current tail by using Light Punch Through technology. The diodes have been estimated
by scaling the necessary number of diodes in series and parallel to accomplish the diode
parameters for the higher voltage and power level. The inductors were scaled based on
the core cross sectional area required to prevent magnetic flux saturation in the cores due
to the peak inductor current, scaled up from the prototype converter. Chapter 6 discusses
estimated volume and mass of a converter scaled to 60 kV and 300 kW in the near-term,
5-year, and 10-year time frames. The 10-year converter estimation shows a potential for
a 300 kW system volume under 1,000 in3 and approximately 53 lbs. Parallel 300 kW
modules can be utilized to fabricate multi-megawatt class converters. For instance, four
converter modules assembled in parallel for a 1.2 MW system, scales to approximately
127
3,500 in3 and 212 lbs, and a 2.4 MW system will proportionally have a volume of 7,000
in3 and a mass of 424 lbs, remarkable by any system standards.
The cascade boost converter shows that reduction by 88% in weight may be
achievable in a 10-year time frame, which allows for high power conditioning systems to
be integrated onto platforms that are impractical today, such as mobile platforms. High
energy lasers, weapon systems, and pulsed power systems for the military can be
operated on land vehicles, aircrafts, and possibly man-portable systems given this
technology trend. Such power density advances will allow power conditioning systems
to satisfy volume and mass requirements for such military applications.
128
APPENDIX A
Drive Circuit Schematics of the Second Stage IGBT Stack
Below, Figure A.1 through Figure A.3, respectively show circuit schematics of
the trigger module, power oscillator, and gate drive circuit in the IGBT stack of six
individual, 1200V rated, IGBTs that is used in the second stage of the cascade boost
converter prototype. The IGBT trigger module, in Figure A.1, displays the six fiber optic
transmitters (HFBR1521), synchronized with the 50 Ω trigger TTL input signal, that send
optical signals to each IGBT gate driver board. The gate driver boards are powered by
the power oscillator shown in Figure A.2, where the secondary winding of T1 couples to
a magnetic core (CST206-1A) on each IGBT driver board, shown in Figure A.3, using a
single loop of high voltage insulated wire that is strung through each driver board. On
each gate driver board, the fiber optic receiver (HFBR2521) is coupled to the main gate
driver IC (MIC4451) that provides +15 V for turn-on and 0 V for turn-off with the
capability of 12 A peak drive current. Also, a 4.7 Ω external gate resistor is in series with
the IGBT (IRGP30B120KD-E) gate input, and each IGBT is overvoltage protected by a
series of six transient voltage suppressor diodes (D10-D15) that provide a clamping
voltage of 1200 V for the IGBT collector to the emitter voltage.
129
Figure A.1 IGBT trigger module.
Figure A.2 Power oscillator.
130
Figure A.3 IGBT gate driver circuit.
131
APPENDIX B
MATLAB function integratcsv.m. This routine integrates waveform data saved as an array in a comma separated
variable (.csv) file. The routine is specifically designed to open a file with two columns
of data. Column “B” is numerically integrated with respect to column “A”, where
column A may represent time values and column B represent waveform data. When
implemented in MATLAB, the result will be the integral of the data. Integratecsv.m is
shown below:
function Intgrl = integratecsv(csvfile) %integratecsv('directory path\filename.csv') %integratecsv numerically integrates a csv file (comma sep var) where %column B is integrated with respect to column A. M = csvread(csvfile); t = M(:,1); x = M(:,2); Y = trapz(t,x); Intgrl = Y(end);
132
APPENDIX C
Derivation of the IGBT conduction power loss
The conduction power loss of the IGBTs is found by multiplication of the on-state
current and voltage for a single period during stead state operation. The solution for the
power is integrated to give the energy loss during the on-state per period and multiplied
by the switching frequency, which provides the average conduction power loss. The
conduction current is given by [C.1]
( ) Linitial
VIcond t t IL
= + , [C.1]
where VL is the voltage across the inductor, L is the inductance, and Iinitial is zero if the
boost converter is in discontinuous mode conduction. The on-state voltage, vf, of the
IGBT is approximated as [C.2]
0.7 0.068 Lf
Vv tL
= + , [C.2]
which was determined from on-state forward conduction test shown in
Figure C.1. Multiplication of [C.1] and [C.2] results in the power equation: [C.3]
2
( ) 0.7 0.068L Lcond
V VP t t tL L
⎛ ⎞= + ⎜ ⎟⎝ ⎠
. [C.3]
Integration of Pcond, results in the conduction energy loss per period: [C.4]
( ) ( )2
2 3
0
1 1( ) 0.7 0.0682 3
DTL L
on condV VE P t DT DTL L
⎛ ⎞ ⎛ ⎞ ⎛ ⎞= = +⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠ ⎝ ⎠∫ , [C.4]
133
where the integration limits are from the beginning of the period to end of the switch on-
time, DT. The average of Pcond(t) equals the Eon multiplied be the switching frequency:
[C.5]
1cond sw on onP f E E
T= = . [C.5]
On-State Forw ard Voltage Data & Trendline
0
10
20
30
40
50
60
0 1 2 3 4 5 6Vf
Am
ps
Vf data
Poly. (Vfdata)
Vg = 12.5 V
Figure C.1 Experimental on-state forward conduction voltage and trend line of the International Rectifier
IRGP30B120KD-E 1200 V, 60 A rated, Non-Punch Through (NPT), IGBT; Vg = 12.5 V.
134
APPENDIX D
MATLAB function RMSCalc.m. This routine calculates the RMS value of data saved as an array in a comma
separated variable (.csv) file. The routine is specifically designed to open a file with two
columns of data, where column A may represent time values and column B represent
waveform data. The time duration of the data must be equal to one period of a periodic
waveform. The result of the routine is the calculated RMS value of the data.
RMSCalc.m is shown below:
function Irms = rmscalc(csvfile) %rmscalc('directory path\filename.csv') %rmscalc calculates the RMS value of a waveform in a CSV file, particularly from a Tektronics oscilloscope. %First and last data point in the CSV file define the period of a repetitive waveform. M = csvread(csvfile); t = M(:,1); x = M(:,2); Y = cumtrapz(t,x.^2); T = max(t)-t(1); Irms = sqrt(Y(end)/T);