Report Suhas Cadence (1)

PROJECT REPORT

(Project Semester January-June 2014)

Front End Design and Constraint Capture using System

Connectivity Manager (SCM)

Submitted by

SUHAS BUDHIRAJA

SID: 11105055

Under the Guidance of

Ms. Jasbir Kaur Mr. Deepak Gupta

Assistant Professor PV Manager

ECE Department Allegro Ops Noida

PEC University of Technology Cadence Design Systems

Department Of Electronics and Communication Engineering

PEC University of Technology, Chandigarh

January to June, 2014

DECLARATION

I hereby declare that the project work entitled “Front End Design and Constraint Capture

using System Connectivity Manager (SCM)” is an authentic record of my own work

carried out at Cadence Design Systems as requirements of 22 weeks project semester for

the award of degree of B.E. Electronics and Communication Engineering, PEC University

of Technology, Chandigarh, under the guidance of Mr. Deepak Gupta and Ms. Jasbir Kaur

during 13 Jan 2014 to 13 June 2014.

Suhas Budhiraja

11105055

Date: 13th June 2014

Certified that the above statement made by the student is correct to the best of our

knowledge and belief.

Ms. Jasbir Kaur Mr. Deepak Gupta

Assistant Professor PV Manager

ECE Department Allegro Ops Noida

PEC University of Technology Cadence Design Systems

Cadence Design Systems, Inc. 2

ACKNOWLEDGEMENT

It gives me a great pleasure to take this opportunity to thank Cadence Design Systems for

giving me an opportunity to work in their esteemed organization.

I would like to express my sincere gratitude and indebtedness to my Manager Mr. Deepak

Gupta for his invaluable guidance and enormous help and encouragement, which helped

me to complete my project successfully. His way of working was a constant motivation

throughout the project term.

I would like to acknowledge my mentors Ms. Ankita Mathur and Mr. Boopathy J who

helped me in one way or the other with their constant involvement during my project tenure

here.

I would also like to take this opportunity to express my sincere gratitude to my faculty co-

coordinator, Ms. Jasbir Kaur for her constant guidance, valuable suggestions and moral

support.

I acknowledge gratefully the help and suggestions of all members of Allegro-Ops Noida

who were always eager to help me with their warm attitude and technical knowledge, in

spite of their busy schedule and huge workload.

Suhas Budhiraja


PREFACE

Today the world is moving rapidly with changing technological advancements and in

modern era technology is also changing very fast and sometimes it looks difficult to pace

up the technological advancements. Electronic and Computer engineering and its associate

engineering modules are playing a vital role. The most important role is played by new

hardware’s and software’s being modified and introduced for more applications to help the

industry and mankind at large.

We can say that we are living in the computer age and passing through the information

technology revolution which has turned the universe into a global village, so computer

have become an essential and integral part of our daily lives. This process is advancing day

by day and it is putting lot of challenges in front of us.

To look and understand these challenges which we have to face in future, our college

provides an opportunity for all its students to gain professional training and actual work

environment for the students. This knowledge will help us in our future prospects and skill

development.

I have prepared this project report with great enthusiasm in the most practical way.

During this period, we get the first real world experience on working in an actual

environment with different technical skills which normally cannot be experienced by us in

college studies. Apart from this, we get an opportunity to learn the latest technologies, and

gain insights into the working of the system.

And most of all I observed how team effort is organized and integrated for the finished

product to take shape.


CONTENTS

1. Summary 7

2. Introduction to EDA Technology 8

2.1 EDA Technology 8

3. About Cadence 10

3.1 Market 11

3.2 An overview of Cadence 13

3.3 Cadence Design Solutions 13

3.4 Cadence: Layperson’s language 14

4. System Connectivity Manager 16

4.1 What is SCM? 16

4.2 Designing systems using SCM 16

4.3 Complete Design Flow 16

4.4 SCM Features 17

4.5 Designing PCB in SCM 20

4.6 SCM User Interface 27

4.7 Types of designs that can be created in SCM 36

4.8 Working with components 38

4.9 Capturing connectivity 41

4.10 Generating document schematics for a design 41

4.11 Exporting schematics for a design 46

4.12 Other features of SCM 47

4.13 Transforming the Logical design to board & Design Sync 51

4.14 Running Design Rule Check 54

4.15 Team Designing 54

5. Design Entry HDL (DEHDL) 59

5.1 What is DEHDL? 59

5.2 Why DEHDL? 59

5.3 What does it do? 59

5.4 Features 61


6. Tasks Assigned 63

6.1 Preface 63

6.2 Validation: A process 63

6.3 Automation as a process 68

6.4 List of automated testcases 73

6.5 Bug search & crash retracing 73

6.6 Design capture 76

6.7 Test Plan 77

7. Tools and Softwares used 80

7.1 Clearcase 80

7.2 Tcl/tk 85

7.3 UNIX 87

7.4 Extensible Markup Language (XML) 88

8. Conclusion 90

9. References 91


CHAPTER-1

SUMMARY

Electronic design automation (EDA) is the category of tools for designing and producing

electronic systems. This is known as ECAD (electronic computer-aided design) or just

CAD. The objective of the project is to learn the design flow of System and Packaging

level EDA tools, and to validate the tools for proper functioning. The Cadence tool SCM

(System Connectivity Manager) is used as an industry standard for System Level

designing, Design Entry HDL organizes schematic information into and Cadence PCB

Designer provides a scalable, full-featured PCB design solution. The validation is achieved

using generation of test cases ,based on either the company’s own combination of design

steps or based on the CCRs (Cadence Change Requests) filed by the leading customers

which are confidential ,since the end product based on the design issues is still to be

launched in the market. The verification based on these issues not only enhances the

validation skills ,but also provides an insight into the level of complexity at which the

System Level Design companies like QUALCOMM, ERICSSON, IBM ,CISCO, HP etc

work. Validating the tool not only hones the testing/debugging skills but also greatly

improves the design concepts both in the hardware and the software domains. The

tools are designed and validated for different platforms viz. Linux, Solaris, Windows XP

etc. The scripting language Tcl are used for making the test case generation and automation

tasks more efficient with respect to time consumption. In this report significant weightage

has been given to understand the design flows of the Cadence SCM, Cadence Design Entry

HDL and Cadence PCB Designer based on the company’s confidential user guides and

design workshops.


CHAPTER 2

INTRODUCTION TO EDA TECHNOLOGY

2.1 EDA TECHNOLOGY

Electronic design automation (EDA) is the category of tools for designing and producing

electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. This is

sometimes referred to as ECAD (electronic computer-aided design) or just CAD.(Printed

circuit boards and wire wrap both contain specialized discussions of the EDA used for

those.). The tools work together in a design flow that chip designers use to design and

analyze entire semiconductor chips.

The objective of the project is to learn the design flow of System and Packaging level

EDA tools, and to validate the tools for proper functioning. Allegro Design Workbench

(ADW) represents a suite of products that help implement collaborative design

environment involving your design teams, methodologies, corporate design databases, and

tools. In addition, you can use design lifecycle, library development and management, and

data management features to control the design and library management processes.

The validation is achieved using generation of test cases ,based on either the company’s

own combination of design steps or based on the CCRs (Cadence Change Requests) filed

by the leading customers which are confidential ,since the end product based on the design

issues is still to be launched in the market. The verification based on these issues not only

enhances the validation skills ,but also provides an insight into the level of complexity at

which the System Level Design companies like QUALCOMM,ERICSSON,IBM

,CISCO,HP etc work. Validating the tool not only hones the testing/debugging skills but

also greatly improves the design concepts both in the hardware and the software domains.

The tools are designed and validated for different platforms viz. Linux, Solaris, Windows

XP etc. The scripting language Tcl are used for making the test case generation and

automation tasks more efficient with respect to time consumption. In this report significant

weight age has been given to understand the design flows of the Cadence Part Developer,

Cadence Design Entry HDL and Cadence Database Editor, Cadence Library Distribution,


Cadence Flow Manager based on the company’s confidential user guides and design

workshops..

EDA is specifically for electronics, and used for designing integrated circuits. The

segments of the industry that must use EDA are chip designers at semiconductor

companies. Large chips are too complex to design by hand. Growth of EDA for electronics

has rapidly increased in importance with the continuous scaling of semiconductor

technology. Some users are foundry operators, who operate the semiconductor fabrication

facilities, or "fabs", and design-service companies who use EDA software to evaluate an

incoming design for manufacturing readiness.

The term EDA is also used as an umbrella term for computer-aided engineering, computer-

aided design and computer-aided manufacturing of electronics in the discipline of electrical

engineering. This usage probably originates in the IEEE Design Automation Technical

Committee.

Electronic Design Automation is using the computer to design lay out, verify and

simulate the performance of electronic circuits on a chip or printed circuit board .

While the public mostly focuses on the end products and is only moderately aware of

the chips and circuits inside. EDA for electronics has rapidly increased in importance

with the continuous scaling of semiconductor technology. EDA tools are also used for

programming design functionality into FPGAs.

The tools in EDA are divided into two categories:

1. FE tools (Front End) - This includes tools for system development activities and logic

design activities that encompass logic synthesis, formal checking, and design for test. For

example, Cadence PDV (Part Developer), Cadence Design Entry HDL, Cadence Database

Editor, Cadence Library Distribution, Cadence Flow Manager etc..

2. BE tools (Back End)-This includes tools for the physical implementation of the logical

designs

For example, Cadence Allegro PCB editor.


CHAPTER 3

ABOUT CADENCE

Cadence Design Systems is the world's largest supplier of EDA technologies and

engineering services. Cadence helps its customers break through their challenges by

providing a new generation of electronic design solutions that speed advanced IC and

system designs to volume.The primary corporate product is software used to design chips

and printed circuit boards.

Founded: 1988

Corporate Headquarters: 2655 Seely Ave, San Jose CA 95134 USA

Website: www.cadence.com

Company Type: Public

CEO/President: Mr. Lip Bu Tan.

Cadence Design Systems is the global leader in software, hardware, methodologies, and

services that play essential roles in accelerating innovation in today’s highly complex

integrated circuits, printed circuit boards, and electronics systems.

Companies use Cadence electronic design automation (EDA) tool design services to

design, verify, and prepare semiconductors and systems for manufacturing. Today,

complex chips go into millions of Set-top boxes, PDAs, cellular phones, and other

consumer items, all designed and brought out under intense cost and time-to-market

pressures. Today, Electronics touches almost every part of our lives, and is ubiquitous, and,

is literally changing everything in and around our lives, for the better. This is truly, the

Golden Age of Electronics. It would have been nearly impossible to design Today's

semiconductors and electronic without electronic design automation (EDA). Electronic

Design Automation (EDA) is a complex and highly leveraged technology that enables the

Electronics Industry by handling design complexity; enabling faster time-to market; higher

productivity, accuracy and efficiency.


http://www.cadence.com/

Company Profile

To keep pace with market demand for more performance and functionality in today’s

mobile phones, digital cameras, computers, automotive systems and other electronics

products, manufacturers pack billions of transistors onto a single chip. This massive

integration parallels the shift to ever-smaller process geometries, where the chip’s

transistors and other physical features can be smaller than the wavelength of light used to

print them.

Designing and manufacturing semiconductor devices with such phenomenal scale,

complexity and technological challenges would not be possible without electronic design

automation (EDA). It is essential for everything from verifying that the myriad transistors

do what the designer intended to dealing with physical effects on electrons traveling miles

of wires with widths sometimes measuring less than 100 nanometers.

Cadence Design Systems is a leading global EDA company. Cadence customers use our

software, hardware, and services to overcome a range of technical and economic hurdles.

Our technologies help customers create mobile devices with longer battery life. Designers

of ICs for game consoles and other consumer electronics speed their products to market

using our hardware simulators to run software on a ‘virtual’ chip—long before the actual

chip exists. We bridge the traditional gap between chip designers and fabrication facilities,

so that manufacturing challenges can be addressed early in the design stage. And our

custom IC design platform enables designers to harmonize the divergent worlds of analog

and digital design to create some of the most advanced mixed-signal system on chip (SoC)

designs. These are just a few of the many essential Cadence solutions that drive the success

of leading IC and electronic systems companies.

3.1Market:

Cadence® serves the more than $1 trillion worldwide electronics market, which is

increasingly being driven by consumer-oriented products.


The major vertical market segments include computers, wired and wireless

communications, and consumer electronics, such as multimedia and personal entertainment

devices. Globally, these account for 75 percent of electronics equipment revenue and more

than 90 percent of semiconductor revenue.

3.1.1The major horizontal segments are:

1. Systems companies,

2. Semiconductor companies, and

3. Silicon providers (ASIC vendors, foundries, and FPGA companies).

Cadence® is a leading provider of EDA solutions in each of these segments, giving the

company unparalleled visibility into the electronics design industry.

3.1.2Two major trends drive electronics design:

1. Increasing silicon capacity and

2. Converging market demands.

Silicon capacity has been doubling every 18-24 months for more than 30 years. Although

what is known as Moore’s Law continues, constraints such as power are now stretching the

limits of productivity, and there seems to be an end in sight. Nonetheless, to meet market

demands to converge computer, communications, and consumer capabilities into a wide

variety of products including cell phones, PCs, PDAs, flat panel HDTVs, set-top boxes,

wireless networks, and automobiles electronics companies need to invest continually to

make the best use of this growing silicon capacity. This means breaking down barriers

between today’s separate domains of embedded software, digital logic, analog circuits, and

PCB design to meet time-to-market pressures and demands for continued evolution of

device functionality.

Cadence® is the only company with the combination of product line breadth, domain

expertise, and vertical design methodology experience to best address these challenges.


3.2 AN OVERVIEW OF CADENCE INDIA

Cadence Design Systems (I) Pvt. Ltd., Noida is the largest R&D Center of Cadence Design

Systems Inc. outside the US. Cadence is responsible for developing various critical and

mainstream technology products across the entire spectrum of electronic products and

system design automation. Cadence set up in India plays a very important role in promoting

the development of electronics industry. Cadence is also promoting collaboration programs

with premier engineering institutes in India including .Cadence India has evolved to be a

leader in technology at the international level, through representations through forums like

the VITAL TAG, the IEEE Timing subcommittee, which is responsible for defining the

VITAL standard (VHDL Initiative towards ASIC Libraries) and in the synthesis Inter-

operability Working Group (SIWG) set up under the auspices of VHDL International.

Cadence India plays a critical part in promoting the annual VLSI Design Conference and

VLSI Design and Test (VDAT) conference.

3.3 CADENCE DESIGN SOLUTIONS

3.3.1 DIGITAL DESIGN: The Cadence Encounter digital design platform accurately

converts the high-level logical specification of a digital integrated circuit (IC) into a

detailed physical blueprint and then detailed design information showing how the IC will

be physically implemented. This data is used for the creation of the photo masks used in

chip manufacture.

3.3.2 CUSTOM DESIGN: The Cadence Virtuoso custom design platform develops

differentiated silicon for ICs that must be designed at the transistor level, including analog,

radio frequency (RF), memories, high-performance digital blocks, and standard cell

libraries. Detailed design information showing how the IC will be physically implemented

is used for the creation of the photo masks used in chip manufacture. The Virtuoso

platform offers the industry’s fastest, most silicon-accurate way to design custom analog,

RF, and mixed-signal ICs.

3.3.3 SYSTEM INTERCONNECTS: This product group consists of printed circuit board

(PCB) and IC package design products, including the Cadence Allegro system


interconnect design platform, which enables co-design of advanced ICs, IC packages,

and PCBs.

3.3.4 FUNCTIONAL VERIFICATION: The Cadence Incisive® functional verification

platform reduces risk and increases quality by verifying that the high-level logical

specification of an IC design is correct. Employing the industry’s first single-kernel

architecture, the Incisive platform delivers the fastest, most efficient way to verify large,

complex chips. Cadence verification process automation enables customers to manage their

entire verification effort, which boosts productivity, increases predictability, and ensures

system-level quality.

3.3.5 DESIGN FOR MANUFACTURING: Cadence design-for-manufacturing (DFM)

solutions ensure that advanced ICs will be manufacturable with high yields while also

meeting aggressive performance, power, and schedule requirements.

3.3.6 CADENCE KITS: Cadence Kits help companies in the wired networking, wireless,

and multimedia sectors achieve shorter, more predictable design cycles and greater

productivity by simplifying the application and integration of EDA technologies and

verification intellectual property (IP). Each Cadence Kit addresses application-specific

design issues.

3.4 Cadence : Layperson’s language

There are people in the electronics industry who design Integrated Circuits (IC's or chips)

and Printed Circuit Boards (PCB's). These engineers are commonly referred to as

electronic designers. They decide how the IC's and PCB's can most efficiently and

effectively are designed to perform their intended functions. Today IC's and PCB's have

become so increasingly complex that is virtually impossible to design them manually.

Cadence provides software programs for electronic designers allowing them to design their

products with greater efficiency and more precision. The term EDA software stands for

Electronic Design Automation software. We provide EDA software to electronic design

engineers and we are number one in the EDA industry.


Fig 3.1 Electronic Design Automation

Although Cadence is number one in the Electronic Design Automation industry, consumers

rarely hear of us. Instead, companies like Sony, Mitsubishi, Palm, and Intel usually come to

mind as major technology players with internationally recognized brands. So where does

Cadence fit in?

Cadence does most of its business with other electronic companies: our EDA software tools

allow them to design the products that they pass on to individual consumers around the

globe. EDA technology is used to design chips and such EDA tools used to design chips

are created by Cadence. In today’s world chips are manufactured using EDA technologies.

Electronic products such as small cell phones, PDA’s and laptop computers would simply

not be possible without EDA.


CHAPTER 4

SYSTEM CONNECTIVITY MANAGER

4.1 What is System Connectivity Manager?

System Connectivity Manager is a new design capture environment that provides logic

designers the flexibility of capturing their designs in multiple ways. While Allegro Design

Entry HDL offered schematic based design capture environment, System Connectivity

Manager allows you to capture your design using spreadsheets, schematic and Verilog

HDL.

The spreadsheet-based design capture environment in System Connectivity Manager allows

you to quickly capture connectivity information in the design. Spreadsheet-based design is

very effective for capturing designs with large pin count components and backplanes.

4.2 Designing Systems Using System Connectivity Manager

While working with SCM, a system is defined as a set of functions, which when put

together perform a particular task. These functions communicate with each-other through a

set of interfaces that are implemented as wires carrying signals from one function to

another.

The ability of SCM to manage communication interfaces between these functions makes it

a useful tool to implement partitioning of system design. Defining system partitions is one

of the primary tasks in the system design cycle. Partitioning consists of dividing a system

into different functional groups and then targeting an implementation for each group. This

is important design task because partitioning of the system hardware or software directly

impacts the cost of the system. After the system is partitioned into groups, sub-systems or

components, the physical implementation of the system is each partition is finalized.

4.3 The Complete Design flow

In today's board-level digital designs historical schematic capture techniques are not as

efficient as they once were. The designs today are increasing in complexity, but decreasing

in the number of components on the board. To reduce the number of components on a


board, large pin-count devices are being used extensively. As these large pin-count devices

cannot be placed on a single schematic page, designers spend great amounts of time to split

these devices into multiple symbols based on functionality and place each symbol on

separate schematic pages. A natural effect of this is the increased complexity of the logical

interconnects on the PCB.

Most of the schematics today that represent these complex designs do not have room to

draw connecting wire segments between logical pins so the design is entirely connect-by-

name. This coupled with the fact that very few of the symbol's graphics indicate any logical

meaning makes today's designs very ineffective in documenting the design intent. It is clear

that designs dominated by large pin-count devices require a more efficient way of capturing

the inter connect.

System Connectivity Manager is the next generation PCB design capture tool that helps

you tackle your PCB design capture challenges.

4.4 System Connectivity Manager Features

Besides providing support for the co-design objects and spreadsheet editor, there are

various other features in SCM that can be used to capture the connectivity of a complex

and huge system in a fast and simple manner. Using SCM, logic designers have the

flexibility of capturing their designs in multiple ways. Unlike schematic-based design

capture environment, SCM allows you to capture your design using spreadsheets,

schematic and Verilog HDL.

The spreadsheet-based design capture environment in System Connectivity Manager

allows you to quickly capture connectivity information in the design. Spreadsheet-based

design is very effective for capturing designs with large pin count components and

backplanes.

System Connectivity Manager also provides a Verilog design environment that

integrates the power of spreadsheets with a language sensitive Verilog editor to enable you

to quickly capture your design in Verilog HDL.


We can also import existing Verilog files into our design. When we import a Verilog

file, SCM parses the file for errors and creates blocks for the modules in the Verilog file.

We can then add the blocks in our design edit them using the Verilog Design Editor.

Besides the capability to capture designs using spreadsheets, schematics and Verilog HDL,

System Connectivity Manager has the following features:

Intuitive User Interface: System Connectivity Manager provides a highly

customizable and intuitive user interface with features like multi-select connectivity, drag-

drop, copy/paste, multiple undo-redo, error highlighting, find/replace, global find/replace

and design comments.

Capturing Connectivity: The spreadsheet-based design capture environment in

System Connectivity Manager allows you to quickly capture connectivity information in

the design.

Easy Property and Electrical Constraint Management: System Connectivity

Manager lets you use the Constraint Manager tool to capture and manage property and

electrical constraint information across your design. Constraint Manager provides a

spreadsheet interface that helps you to quickly work with properties and electrical

constraints across your design. You can also use the Properties window in System

Connectivity Manager to work with properties on individual components, nets and pins in

your design.

Online Packaging : Unlike Allegro Design Entry HDL where you have to package a

saved design to assign reference designators, physical net names and packages, System

Connectivity Manager performs online packaging to automatically assign reference

designators, physical net names and packages.

Easy Management of Associated Components: Today's designs have a large

number of discrete components such as terminations, bypass capacitors and pull-up/pull

downs connected to components in the design. System Connectivity Manager allows you to

quickly add these discrete components in the design. System Connectivity Manager

preserves the association between these discrete components and the component to which

they are connected. If you move or delete the component to which these discrete


components are connected, the associated discrete components are also moved or deleted.

This makes it easy to manage associated components in the design.

Support for Assigning Signal Integrity Models: System Connectivity Manager lets

you assign signal integrity (SI) models to components and pins in your design during the

design capture phase. You can then use SigXplorer to perform topology exploration and

analyze the nets in your design for signal integrity issues. This helps you correct signal

integrity issues early in the design cycle.

Easier Management of Hierarchical Designs: System Connectivity Manager lets

you quickly create and manage hierarchical designs using top-down and bottom-up design

methodologies. You can have a combination of spreadsheet, Verilog and schematic blocks

in your hierarchical design.

Support for Functional Verification of the Design: System Connectivity Manager

provides support for generating verilog netlist of your design. You can perform the

functional verification of your design by simulating the generated netlist in any verilog

simulator.

Support for Generating Reports: System Connectivity Manager provides powerful

report design and generation features. You can design report templates and then use the

templates to generate reports for any design.

Support for Generating Schematics for Documentation Purposes: If you captured

your design using spreadsheets or Verilog HDL, you might want to generate a schematic of

the design for documentation purposes. System Connectivity Manager allows you to

generate a document schematic of your design.

Design Debugging with Design Rule Checks (DRCs) and the Physical View:

System Connectivity Manager lets you run design rule checks (DRCs) to identify

connectivity and other errors in the design. System Connectivity Manager provides a

standard set of DRCs. System Connectivity Manager also lets you write your own custom

DRCs in Tcl language and run the custom DRCs from System Connectivity Manager.

The Physical View in System Connectivity Manager provides a physical netlist view of

the design as it appears in your board layout. You can use the physical view to debug the


design with respect to the board layout and verify whether you have assigned the correct

signal integrity (SI) models on components and pins, and assign SI models, if required.

4.5 Designing a PCB in SCM

The first task we perform in designing a PCB is to create a design project. A design project

is the encapsulation of paths to libraries, part tables, tool settings, project-level settings,

global settings and other related settings for designing a PCB to required specifications.

A design project consists of the following:

Reference libraries

Project libraries

cds.lib file

Project file (.cpm file)

4.5.1 What are Libraries?

We begin the design process by creating a logic design using System Connectivity

Manager or Allegro Design Entry HDL and then a board-level design that translates the

logic design into a manufacturable entity. To accomplish this process, tools need a software

representation of the various parts to be used in the design. The representations of these

parts are organized into libraries.

The different tools used in the various stages of the design flow, need different views or

information about the same part. Some of these views are schematic, footprint, and

simulation. These views are organized into several libraries. For example, footprints of

various parts are consolidated into a single layout library.

Part libraries

These libraries contain views for design entry or schematic creation. The information

contained in these views includes logical symbols (graphical representations of the part),

pin outs, and packaging information.


Figure 4.1 Library organization for Cadence PCB design tools

Footprint libraries

These libraries contain the footprints that correspond to the physical parts specified in part

libraries. These libraries are required at the layout stage of the design flow.

Simulation Libraries

These libraries model the behavior of the part in the Verilog or VHDL Hardware

Description Languages. These libraries are required during the design verification phase.

Reference Libraries

Cadence supplies a set of reference libraries that contain views of parts belonging to

several logic families. Reference libraries are usually stored in an area to which you do not

have write permissions and are managed by a librarian. The following figure illustrates the

structure of a reference library.


Figure 4.2 Library Organization: Reference Libraries


The following table describes each view within a part in a reference library.

View Name Description

sym_1 Contains the schematic symbol. When you add a part to a design, a reference

to the symbol view is placed in the design only (not the actual part).

Chips Maps the logical part to the physical package (pin outs). You can also use this

view to assign other physical properties (for example, input and output

loading characteristics, and voltages).

part_table Lets you add custom part properties to fit your company needs. For example,

you can add a company part number, part description or any in-house or

vendor information you require.

Metadata Contains version information for the part.

Table 4.1 Component Views and their descriptions

4.5.2 Project Libraries

Project libraries (also known as local or design libraries) are used by designers at the

project level. Project libraries contain parts customized for your project and the logical

design you capture in System Connectivity Manager.

The libraries in which the designs you capture in System Connectivity Manager are stored

are known as working libraries. By default, the directory for the working library for a

project has the name <projectname>_lib. For example, if you create a project named

memory.cpm, the working library for the project will be named memory_lib.

Each design is stored in a subdirectory within a working library. This subdirectory is

known as a cell. A cell can represent the entire design or just a portion of the design (or


hierarchy). Each cell or design contains subdirectories that represent different design

phases (known as cell views).

Figure 4.3 illustrates the structure of a project library


The following table describes each view in a design library.

View Description

tbl_1 Contains the table based design.

sch_1 Contains the schematics.

vlog_structural Contains the Verilog description of the design.

packaged Contains the results of packaging.

physical Contains the PCB layout.

metadata Contains version information for the design.

Table 4.2 Design library view

4.5.3 What is a cds.lib File?

System Connectivity Manager is a by-reference design editor. This means that System

Connectivity Manager references all parts in the design from various libraries that reside at

the reference or project area.

The cds.lib file is the library definition file that defines all the libraries used in your design

and maps them to their physical locations. The contents of a typical cds.lib file are given

below:

DEFINE standard ./archive_libs/standard

DEFINE project_lib ./project_lib


4.5.4 What is a Project File?

When you create a new project, System Connectivity Manager creates a project file called

<projectname>.cpm in the project directory. The <projectname>.cpm file includes the

following setup information for your project:

The name of the top-level design and the library in which it is located.

The list of project libraries.

The location of the temporary directory where tools generate intermediate data

Setup directives for System Connectivity Manager, Design Entry HDL, PCB Editor, and

any other tool launched from the project.

Example of Project (.cpm) file

{Machine generated file created by SPI}{Last modified was 11:45:02 Tuesday, June 3, 2014}{NOTE: Do not modify the contents of this file. If this is regenerated by}{ SPI, your modifications will be overwritten.}

START_GLOBALdesign_name 'top'design_library 'project_lib'library 'project_lib' 'standard'temp_dir 'temp'ref_cdslib_path '/net/lx-boopathy1/export/home/boopathy/libraries/cds.lib'project_creator 'scm'cpm_version '16.6'SI_MODEL_PATH '.' '/lan/psd_install/16.6/latest/share/local/pcb/signal' '/lan/psd_install/16.6/latest/share/pcb/signal' '/lan/psd_install/16.6/latest/share/pcb/signal/optlib' 'Models'END_GLOBAL

START_CREFERHDLcref_data_file 'cref.dat'END_CREFERHDL

START_DSSCHGENdc_net_voltage_list ''END_DSSCHGEN


START_CONSTRAINT_MGREDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'END_CONSTRAINT_MG

4.6 SCM User Interface

Figure 4.3 the System Connectivity Manager Start Page


Figure 4.4 SCM workspace

When you open a project in System Connectivity Manager, the System Connectivity

Manager workspace appears.

At the center of the System Connectivity Manager workspace lies the Spreadsheet Editor.

You can use the Spreadsheet Editor to view or modify the information about components

and blocks and their connectivity information.

The Spreadsheet Editor is the heart of System Connectivity Manager. You can use the

spreadsheet editor to quickly manage components and blocks and the connectivity

information for the components and blocks in the design.


4.6.1 The Spreadsheet Editor has the following components:

Component List

You can use the Component List to work with the components and blocks in the design.

Each row in the Component List corresponds to a component or block in the current block

or design.

Fig 4.5 Component List

Signal List

We can use the Signal List to work with the signals in the design. The Signal List displays

the list of signals in the current block or design and the global signals from the blocks

added in the current block or design. Each row in the Signal List corresponds to a signal in

the current design or block.

Fig 4.6 Signal List Pane


The Signal List displays the following information:

Differential Pair: Displays whether the signal listed in the signal list pane is a

differential pair signal.

Type Icon: Displays the scope of the signal.

Component Connectivity Details Pane

The Component Connectivity Details pane displays the connectivity information for the

component or block you selected in the Component List.

You can use the Component Connectivity Details to capture the connectivity information

for the components and blocks in the design. The Component Connectivity Details pane

lets you quickly connect component pins to signals, apply terminations, add pullups and

pull downs, assign signal integrity models, and add comments on component pins.

Figure 4.7 Component Connectivity Details Pane


Signal Connectivity Details Pane

The Signal Connectivity Details pane displays the connectivity information for the signal

you selected in the Signal List.

You can use the Signal Connectivity Details pane to quickly connect a signal to component

pins, apply terminations to pins, and assign signal integrity models.

Figure 4.8 Signal Connectivity Details Pane

4.6.2 Toolbars and Windows

System Connectivity Manager has the following three toolbars:

File Toolbar

Fig 4.9 File Toolbar


Design Toolbar

Fig 4.10 Design Toolbar

Tools Toolbar

Fig 4.11 Tools Toolbar

Status Bar

The status bar located at the bottom of the System Connectivity Manager window displays

the status of operations you are performing in System Connectivity Manager. When you

place the mouse pointer on a menu or on a toolbar button, the status bar displays a brief

description of the menu or toolbar button.

Figure 4.12 Status Bar

Hierarchy Viewer

The Hierarchy Viewer provides you a tree view of the complete design hierarchy and lets

you quickly access all the blocks and components in your design.


Figure 4.13 Hierarchy Viewer

File Viewer The File Viewer displays the files related to your design and let you

open the files from System Connectivity Manager. For example, you can double-click on

the board file to open it in Allegro PCB Editor. You can also add any other file that you

want to refer to when working in the design. For example, you can add the design

specifications document for your design in the File Viewer so that you can easily access it

when you are working in the design.


Figure 4.14 File Viewer

Properties Window

You can use the Properties window to work with properties on individual components, net

and pins in your design.

Figure 4.15 Properties Window


Signal Navigate

The Signal Navigate window lets you quickly view the aliases for a signal at all levels of a

hierarchical design and navigate the signal to view its connective.

Figure 4.16 Signal Navigate Window

Session Log Window

The Session Log window displays the details of the current session. These details include

the information about opened design files and packaged designs.

Figure 4.17 Session Log Window


Violations Window

The Violations window displays the error, warning, and informational messages that occur

while working in System Connectivity Manager. To highlight the object causing the error,

warning or informational message, double-click on the row for the message.

Figure 4.18 Violations Window

4.7 Types of Designs that can be created in SCM:

Hierarchical design

Flat design

4.7.1 Creating a flat design

The flat design method is typically followed for small and simple designs. These Designs

are not divided into individual blocks but taken all together.

4.7.2 Creating a Hierarchical Design

The hierarchical design method is typically followed for large and complex designs. These

designs are divided into individual blocks where each block represents a logical function.

To create a hierarchical design in System Connectivity Manager, you can use either of the

following methods:

Top Down method

Bottom Up method


Let us take the example of the hierarchical design shown in Figure 4.19 to understand the

methods for creating a hierarchical design.

Figure 4.19 Example of a Hierarchical Design [2]

4.7.2.1 Top down Method

In the Top Down method, you first create the top-level design (PC in this case). In the top-

level design you can add blocks that represent individual modules. In the case of the PC

design, the top-level design will have three blocks:

CPU

Ethernet

Memory Controller

After creating the top-level design with the necessary blocks, you create the lower-level

blocks. For example, for the block CPU, create the three sub-blocks named:

ALU

Control Unit Cadence Design Systems, Inc. 37

On-chip Cache

4.7.2.2 Bottom up Method

In the Bottom Up method, you create a lower-level block first. For the design Ethernet, you

can first create the blocks for Transceiver, Line Drivers, and Receivers. You then create the

higher level block Ethernet and add the blocks Transceiver, Line Drivers, and Receivers

under it. Finally you add the Ethernet block in the PC design.

4.7.3 Advantages of Hierarchical Designs

Hierarchical designs have the following advantages:

The top-level data flow in the design is easy to understand. The design stays compact.

Part properties that control packaging or part placement, and electrical constraints

defining the electrical design rules can be assigned at the block level.

You can replicate blocks easily. Changes within a block are replicated to all instances of

the block in your design.

You can debug each block separately.

You can use hierarchy to facilitate a team design approach, when separate engineering

teams are working within their respective blocks. For information on working on

hierarchical designs in a team design environment.

Blocks can be associated with PCB layout blocks for design reuse. For information on

creating and using reusable blocks in your design.

4.8 Working with Components

The various procedures for working with components in the design are:

4.8.1 Adding Components: The Component Browser is used to add components in a

design. While adding the component the following things have to be kept in mind:

You can only add components from the libraries that are listed in the Project Libraries

list in the Libraries tab of the Setup dialog box. Do not add components with mixed or


uppercase names, or components whose names have special characters except the

underscore character.

Do not add components whose symbol or physical part table (.ptf) file have properties

with null (empty) values. Such components will not be packaged in System Connectivity

Manager. If you add such components in the design, packaging errors are reported in the

Violations window for the components.

It is recommended to add split parts as a package.

4.8.2 Modifying Components: We can modify a component to modify its physical

properties.

4.8.3 Replacing Components: You can replace components in your design with other

components. System Connectivity Manager lets you:

Replace a component in your design with another component.

Replace all the instances of a component in your design with another

component using Global Replace.

Figure 4.20 Replace Component Dialog Box


4.8.4 Copying and Pasting Components: You can quickly add components in the

design by copying a component in the Component List and pasting it. You can also copy

components from another block or design and paste it in the current block or design.

When you copy and paste a component, its connectivity and property information, and the

comments and bypass capacitors added on the component are also copied. This lets you add

connectivity and property information on one instance of a component and copy and paste

it to quickly add another instance of the component with the same connectivity and

property information, thus avoiding the need to add connectivity and property information

for each instance of the component in the design.

4.8.5 Modifying Component Instance Names: The components you add in System

Connectivity Manager are automatically assigned instance names like i1, i2, and so on. The

instance names are displayed in the Name column in the Component List.

4.8.6 Modifying Component Reference Designators: The components you add in System

Connectivity Manager are automatically assigned reference designators. The reference

designators of components are displayed in the Ref Des column in the Component List.

You can modify the reference designators of components. If you have modified the

reference designator of a component, you can reset the reference designator value to a tool

assigned reference designator value.

4.8.7 Working with Power Pins and NC Pins of Components: You can specify the

power pins of a component using the POWER_PINS and POWER_GROUP properties and

specify NC (not connected) pins using the NC_PINS property. The power and NC pins are

unconnected pins that exist on the physical part but are not shown on the symbol.

4.8.8 Swapping Pins across Functions of a Component: You can exchange the location

of two pins across two functions in a multi-function component by swapping the two pins.

Swapping pins across functions lets you minimize the average net length when you route

the board in Allegro PCB Editor.

4.8.9 Deleting Components: We can delete the added components.


4.9 Capturing Connectivity

4.9.1 Capturing Pin-Net Connectivity for a Component: The Component Connectivity

Details Pane allows you to quickly connect signals to pins of components.

4.9.2 Capturing Pin-Net Connectivity for Multiple Components: You can use the

Component Connectivity Details pane to edit the pin-signal connectivity information of

multiple components in different panes within the Component Connectivity Details pane at

the same time. This allows you to quickly capture connectivity information on components

that require similar connectivity. This can also be done for Component Connectivity

Details Pane: Different Panes for Multiple Instances of Different Components.

4.9.3 Modifying Connectivity Simultaneously in Same Pane: You can use the

Component Connectivity Details pane to edit the connectivity information of multiple

components in the same pane in the Component Connectivity Details pane at the same

time. This allows you to quickly edit the connectivity information for a group of

components at the same time.

4.10 Generating Document Schematic for a Design

System Connectivity Manager allows you to generate a schematic for your logical design.

You can use the generated schematic for documentation purposes, or for communicating

various aspects of the design to your team members or customers. Though the generated

schematic is mainly for documentation purposes, if required, you can modify component

placements and these can be preserved while regenerating the documentation schematic.

The contents on the documentation schematic can be controlled using various setup

options. Using System Connectivity Manager, you can generate a flat schematic for your

spreadsheet-based design.


Figure 4.21 Document schematic generation

Termination in SCM Corresponding Schematics in HDL

Fig 4.22 Differential Pair Terminations in Document Schematic


4.10.1 Features of the Document Schematic:

The document schematic has the following features:

The document schematic is only meant for documentation purposes. In the preserve

mode, you can do placement modifications in the document schematic.

The document schematic will always be a flat design.

If the source design in System Connectivity Manager is a hierarchical design, the

design is flattened .The schematic blocks in your design in System Connectivity Manager

will be copied without any changes into the document schematic.

In the documentation schematic, connectivity is specified using net names. Physical

net names, displayed near the component pins, are used for specifying net connections.

Comments added to a design in System Connectivity Manager are displayed as notes

in the document schematic, provided you had selected appropriate options in the Comments

tab of the Document Schematic Generation Setup dialog box.

Cross references are placed only on the project-level schematic.

If document schematic has offpage connectors added to it, cross references are placed

on the symbols for the offpage connectors.

If you have selected the option to add offpage connectors, offpage connectors will

only be added for signals that run across pages. For signals terminating on the left- or right-

side of the schematic page, the symbols specified in the setup dialog box for the right-side

or the left-side are used.

In the generated document schematic, offpage connectors are not added to global and

template nets, and to nets with power bodies.

Ports and IO pins are not placed in the documentation schematic. However, if ports

and IO pins are present in the schematic blocks, they are not modified.

If required you can modify the schematic design to change component placement.


You can plot the document schematic in Design Entry HDL. However, as the

document schematic is a flat schematic, do not use the hierarchical plotting option in

Design Entry HDL.

You can also run PDF Publisher on the document schematic. However, before you

need to reset module order from Design Entry HDL.

The document schematic is always a flat design. Therefore, properties added to a

schematic block, in the Occurrence Edit mode in Design Entry HDL, are not displayed in

the document schematic.

If a property has a placeholder on the symbol for the component, the location,

visibility, justification, rotation and color of the placeholder for the property will be

retained in the document schematic, irrespective of the property color and display settings

in the Document Schematic Generation Setup dialog box.

To prevent unnecessary clutter in the document schematic, any pin property, except

the PN property, that does not have a placeholder on the symbol for the component will not

be displayed on the document schematic.

If a symbol is larger than the page border size, an attempt is made to instantiate the

symbol by rotating the symbol such that it fits within the page border size. In such

cases, success is not always guaranteed.

4.10.2 Specifying Component Grouping

By default, the component placement in the document schematic is based on connectivity.

System Connectivity Manager provides you with the ability to specify components that are

to be grouped together in the generated document schematic.


Fig 4.23 Using SCHEMATIC_GROUP property

4.10.3 Generating Document Schematic in Preserve Mode

Preserve option is useful if you are regenerating your document schematic and want to

preserve the modification done to the document schematic generated initially. In this mode,

Modifications made to the original document schematic are preserved.

Features of Generating a Document Schematic with Preserve Option

Component placement is always preserved.

Routing changes are preserved only if there are no connectivity changes. In case of

Connectivity changes, the nets on the page for which connections have been modified, are

rerouted.


Only the comments originally added in System Connectivity Manager are preserved.

Any New comments added to the design, or modifications made to the comments in the

Generated schematic are not preserved.

Setup options related to number of associated components in a rail are valid for new

Components and schematics only. These do not hold true while regenerating a

Documentation schematic with preserve options. For example, consider that the setup

Option for document schematic generation is set to allow a maximum of 5 resistors in a

rail. Any new rail that gets created will honor this directive. But an existing rail with 7

resistors will not be modified while recreating a documentation schematic with preserve

options.

Modifying page borders with preserve option on is not supported. This means that if

the user changes the page border and also regenerates the schematic with preserve option

selected, the schematic will not be preserved. In such scenarios, an error is thrown and the

schematic generation process stops.

New components added to the design are placed on the last page of the document

schematic.

New components added to an existing schematic group are placed in a new page

added immediately after the page on which other components of the same group exist.

4.11 Exporting Schematics for a Design

The Generate Schematic process, discussed above Topic 5.10, “Generating Document

Schematic for a Design,” is used, mainly to generate a schematic used for documentation

purposes. If you are looking at System Connectivity manager to quickly capture design

logic, especially for high pin-count devices, but would rather continue with the traditional

design process using schematics, then it is recommended that you use the export schematic

process.

System Connectivity Manager allows you to export your spreadsheet-based design as a

schematic. You can then open the exported schematic using Design Entry HDL and

continue the design process. On exporting the design as a schematic, a new Design Entry

HDL project is created with schematic pages, associated libraries, and other required files.

You also need to understand that the export schematic is a one way process.


Important

You cannot back-annotate any changes that you have made in the exported schematic

to the spreadsheet-based design.

The export schematic process leverages the block-level schematics created by the

Generate Document Schematic process. If you have already generated block-level

schematics those can be reused; else new block-level schematics are generated.

Figure 4.24 SCM design after doing Export Schematic

4.12 Other features of SCM

4.12.1 Creating Parts from .CSV Files and Adding them in the Design

System Connectivity Manager can import part information stored in a comma separated

value (.csv) file and create packages and symbols from it. You can then add the part in the

Design.

4.12.2 Creating Parts from Text Files

While creating a design in System Connectivity Manager, you can import part information

stored in a delimiter-separated text file and create packages and symbols from it. You can

then add the part in the design

4.12.3 .Archiving Projects

Any design project that you create can use two types of libraries—local and reference.

Local


Libraries are stored in the project directory. Reference libraries are referenced from a

central location. The project directory contains the cds.lib file that includes links to the

local and reference libraries used in the design. If you need to send a design to another

person residing in a different geographical location, you will have to send the design along

with all the libraries that it references. Each reference library contains hundreds of parts but

your design may be using only a few parts. Archiving the project allows you to create a

standalone project that includes only the parts used in the project from the reference

libraries. For example, if your project uses only the ls00 part in the lsttl reference library,

the Archiver utility will copy only ls00 to the project archive and not the entire lsttl

reference library.

Another need for archiving arises because the reference libraries are updated from time to

time. This may cause situations where your project references parts that have changed and,

thereby, impact the functionality of the design. Archiving the project ensures that the

design always uses the correct set of reference libraries.

The Archiver utility allows you to archive a project and all the parts that it uses without

archiving entire reference libraries. Archiver identifies every physical part used in the

project and then creates a local library containing only those parts. Archiving only the parts

used in the project significantly reduces the amount of data that is to be archived, and

considerably simplifies the archiving and restoration processes. An archived project can be

used independent of reference libraries and other reference data. You can use this feature to

store the project on a tape and use it later.

4.12.4 Importing a Block

System Connectivity Manager allows you to import a block from another project (.cpm)

file or from the cds.lib file of another project into your current design. You can import a

block as a read-only block or as a read-write block into your design.

When you import a block, the cell for the block is copied into the working library for the

current project. You can then add the block in your design.


4.12.5 Working with Associated Components

Today's designs contain components, called associated components that do not contribute

to the logic of the design, but are a must for the correct functioning of the design. For

example, bypass capacitors are needed for controlling power and ground bounce in the

design. By definition, associated components are mostly passive devices. System

Connectivity Manager classifies associated components into three categories—

terminations, bypass capacitors and pull up/pull downs. Traditional design entry tools do

not capture the association between the parent object and the associated components. This

makes design entry time consuming and error prone. For example, if you move or delete

the parent object to which these passive devices are attached in your schematic, you must

ensure that the passive devices are also moved or deleted. System Connectivity Manager

automates the tedious task of working with associated components in your design.

Terminations

Bypass Capacitors

Pullups and Pulldowns

Terminations

Terminations are a group of components, typically resistors or diodes, added to pins or

buses to prevent the reflection of electrical signals occurring at the end of buses. System

Connectivity Manager provides you a convenient way to apply terminations. You can

quickly apply a termination at the bus-level and System Connectivity Manager

automatically applies it to all bits, thereby saving time and effort. You can also apply

terminations to specific bits of a bus or scalar pins using multi-select or copy-paste

features.

For example, Series Termination

Series termination is power efficient. It effectively dampens ringing and overshoots


Fig 4.25 Series termination

Bypass Capacitors

In high-speed environments, the instantaneous current generated with the rising and falling

edges of the outputs causes the power plane to generate noise. Hence one of the key tasks

in minimizing the variation of effective power plane and ground bounce, is to provide

enough bypass capacitors near power pins to maintain power supply voltage. Bypass

capacitors act as local power storage for the device to which they are associated.

System Connectivity Manager lets you quickly add the bypass capacitors you want to

associate with the power pins of a component.

Pullups and Pulldowns

Pullups and pull downs are used to reduce noise in the circuit.

Pull down For Each Connection

Fig 4.26 Pullups and pulldowns

4.12.6 Netlisting the Design for Simulation

System Connectivity Manager allows you to generate the structural Verilog netlist for all

the blocks in the design. You can then use the Verilog netlist to simulate the design using

the

Cadence Verilog XL and NC Verilog simulators or third-party Verilog simulators.


4.13 Transferring the Logical Design to a Board and Design Synchronization

The development of any design involves an iterative process of synchronizing the

differences between the logical design and the board. Changes especially caused by

Engineering

Change Orders (ECOs) in the logical design need to be updated in the board. Similarly,

changes in the board such as reference designator changes, constraint changes, and section

and pin swaps require corresponding updates in the logical design.

Based on how you create a design, you can synchronize the logical design and the board in

one of the following two ways:

1. The conventional or linear flow

In the conventional flow, you first create the logical design in System Connectivity

Manager, make changes to it, get the logical design reviewed and approved. Next, you

prepare the board and send it for manufacturing. When you prepare the board, last minute

changes, such as adding terminations or removing components, can cause property and

connectivity differences between the logical design and the board. These changes need to

be back annotated to the logical design.

2. The concurrent or parallel flow

In the parallel flow, the logic and board designers work in parallel. First, the logic designer

starts work on the logical design. At some point in time, the board designer imports the

logical design and uses it to create the board. Meanwhile, the logic designer starts work on

the next module. Later, the logic designer might make changes to the logical design and the

board designer might make changes to the board. Therefore, it is important to synchronize

the logical design and the board.

Whether you follow the linear flow or the parallel flow, it is important that the logical

design and the board are always synchronized. System Connectivity Manager lets you

compare the logical design and the board. You can update changes from the logical design


to the board or from the board to the logical design. However, you cannot update changes

from one logical design to another or from one board to another.

All the predefined properties you add in System Connectivity Manager that are set up as

transferrable between System Connectivity Manager and the board are automatically

passed to the board when you run Export Physical to update the board with the changes in

System Connectivity Manager. Similarly, when you run Import Physical to update the

design in System Connectivity Manager with the changes in the board, all the predefined

properties that are set up as transferable between System Connectivity Manager and the

board are automatically passed from the board to the logical design in System Connectivity

Manager.

We can export the logical design to translate it into a physical design ready for board layout

in Allegro PCB Editor or in SiP Layout.

SCM provides following options during export physical:

Generate package files (pstdedb.cdsz): Select this check box if you want to package

the System Connectivity Manager design before exporting it to the physical layout tool.

System Connectivity Manager creates the pstdedb.cdsz file that contains the four

packaging files (pstchip.dat, pstxprt.dat, pstxnet.dat and pstcmdb.dat) in the packaged view

of the root design.

Update Board (Netrev): Transfers the design in System Connectivity Manager

Design and updates the board in the board layout tool. While designing a PCB, the board

layout tool used in Allegro PCB Editor. For designing a SiP, SiP Layout is used as the

board design tool.

Input Board File: Specifies the name of the board file that you want to update.

Output Board File: Specifies the name of the resulting updated board file.


4.13.1 Design Synchronization Tasks

1. Exporting the logical design to translate it into a physical design ready for layout in

Allegro PCB Editor or SiP Layout.

1. Back annotating the changes made in the board to the logical design

2. Updating the changes made in the logical design, after initial packaging, to the board.

Figure 4.27 System Connectivity Manager to Allegro PCB Editor Flow

4.13.2 PCB Design Flow

Figure 4.28 PCB Design Flow in SCM


Project Creation & Setup

SCM

Packaging your Design

PCB Layout

Archiving your Design

Sync

hron

izin

g ta

ble

desi

gn

& b

oard

Library

Managem

ent

4.14 Running Design Rule Checks

System Connectivity Manager lets you run design rule checks (DRCs) to identify

connectivity and other errors in the design. System Connectivity Manager provides a

standard set of DRCs. System Connectivity Manager also lets you write your own custom

DRCs in Tcl language and run the custom DRCs from System Connectivity Manager.

You can enable or disable individual DRCs. When you run DRCs, the DRC errors are

reported in the Violations window. You can also set the error severity level—Error,

Warning or Information—to be reported in the Violations window if an enabled DRC fails.

For example, if you set the error severity level for the Unconnected Nets DRC as Warning,

System Connectivity Manager displays warning messages for each unconnected net in the

Violations window.

Fig 4.29 Violations Window

4.15 Team Designing

With an increase in the complexity of designs and the need to reduce design cycle time,

hierarchical design is becoming the preferred design approach. In the hierarchical design

approach, a design is divided into sub designs or blocks, where each block represents a

logical function.


We can use System Connectivity Manager to create hierarchical designs in a team design

environment, in which a team of designers work on a design. Each designer may be

working on one or more blocks of the hierarchical design.

Fig 4.30 Hierarchical Design Using a Team Design Approach

In the above example of a hierarchical design COMM_DEVICE, teams of designers work

on different blocks of the design. The Librarian creates the components for the design. The

Integrator (a team leader or a designated person) integrates all the blocks into the top-level

design (COMM_DEVICE) for testing the design during the design cycle, and for signing

off on the design after all the designers working on the blocks have completed their work

During the design cycle, the components used in the design might be modified by the

Librarian. The designers need to be notified when a component is modified and be able to

update all the instances of the component used in the design with the modified version, on a

need basis.


A designer may want to copy over a block being developed by another designer and modify

it to suit his requirements. For example, in the hierarchical design COMM_DEVICE shown

above, Designer E may want to copy the RFAMP block being developed by Designer D

and modify it to create the RFAMP_1 block.

The Integrator may want to take a snapshot of the blocks at various points of time and

integrate them into the top-level design during the testing or signoff phases of the design

cycle. To achieve this, the Integrator needs to be notified when a block integrated into the

top level design is modified so that he can use the latest snapshot of the block during the

testing or signoff phases.

System Connectivity Manager provides the following features to enable teams of designers

to create hierarchical designs.

Creating sub projects

Importing blocks

Base lining blocks that are modified

Notifying designers when a block used in a design is base lined and allowing to

update the block used in the design with the base lined block

Re importing a Read-Only Block

Updating the Source Location of a Read-Only Block

Viewing the Version History of Blocks and Components.

Notifying designers when a component used in the design is modified by the

Librarian and allowing them to update all the instances of the component used in the design

with the modified version.

4.15.1 Team Design Methodology

Developing a hierarchical design in a team design environment involves the following

steps:


1. Integrator creates a project for the top-level design and specifies the project settings that

he wants to be used for the hierarchical design.

2. Integrator creates sub-projects for each block in the hierarchical design. This ensures that

the project for the hierarchical design and the project for each block used in the hierarchical

design have the same settings.

3. Designers use the sub-projects to work on the blocks assigned to them.

4. Integrator imports the blocks being developed by the designers as read-only blocks into

the project for the top-level design for the hierarchical design.

Note: Other designers may also import a block as a read-only block in to the design they

are working on.

Note: The integrator or other designers may also import a block as a read-write block if

they want to copy a block from another design and modify it to suit the requirements of

their current design.

5. Designers baseline the blocks they are working on, when they want to notify the

integrator or other designers who have imported the blocks into their design as read-only

blocks that changes have been made in the source block for the read-only block.

The integrator or other designers who have imported the blocks into their design as read

only blocks re import the blocks when System Connectivity Manager reports that the

version of the source block for a read-only block has changed

6. When the Librarian modifies the components used in the hierarchical design, he Base

lines the components in Part Developer. System Connectivity Manager reports the list of

components used in the design that have changed and allows designers to update all

instances of the components used in their design with the latest version of the components.


4.15.1.1 Creating Sub-Projects

When you are creating a hierarchical design in a team design environment, each designer in

the design team has to create a project for the blocks assigned to him.

This requires that the projects created by every designer must have the same settings. For

example, all the projects must have the same packaging options, use the same list of

component libraries, signal integrity model libraries, physical part table files, and so on.

System Connectivity Manager lets you specify the project settings in the project containing

the top-level or root design for the hierarchical design and then create sub-projects for each

block in the hierarchical design. The sub-projects will have the same project settings as that

of the project containing the top-level design. The settings in the sub-projects can further be

modified as required.

4.15.1.2 Base lining a Design

In a team design environment, the designer or integrator who has imported a block being

developed by another designer as a read-only block needs to be notified when changes are

made to the source block so that he can re import the latest version of the block into his

design.

To achieve this, the designer who is working on the source block needs to baseline the

block when he wants to notify other designers that the source block has changed. When the

source block is base lined, System Connectivity Manager notifies the designers who have

imported the block as a read-only block into their designs so that they can re import the

latest version of the block into design.

4.15.1.3 Notifying the Design Team When a Block is Base lined

System Connectivity Manager supports notifying the designer who has imported a block as

a read-only block of changes in the source block, when the source block is base lined. You

can specify that the designer who has imported a block as a read-only block is notified in

one of the following ways:

When we open the design containing the read-only block in SCM

At specific time intervals

When we run the Project – Validate Revisions command.


CHAPTER 5

Design Entry HDL (DEHDL)

5.1 What is DEHDL?

Design Entry HDL is a design environment that supports behavioral and structural design

descriptions captured in text and graphics. It incorporates block editing functions for quick

architectural design.

5.2 Why DEHDL?

Design Entry HDL is the tool used for Design Entry (also known as Design Capture) in the

Printed Circuit Board design flow. With Design Entry HD, you can create a project, place

components (parts), connect parts, name signals, add ports, and save designs. When you

save a design, Design Entry HDL checks for errors and helps you locate the spots on the

schematic where connectivity errors have occurred.

Design Entry HDL organizes schematic information into pages. It captures and displays

only one page of schematic information at a time. Design Entry HDL is a by-reference

editor because it references all parts in the schematic from various libraries that reside at

the reference or local area.

5.3 What does it do?

Design Entry HDL is the tool used for Design Entry (also known as Design Capture) in the

Printed Circuit Board design flow. With Design Entry HD, you can create a project, place

components (parts), connect parts, name signals, add ports, and save designs. When you

save a design, Design Entry HDL checks for errors and helps you locate the spots on the

schematic where connectivity errors have occurred.

Design Entry HDL organizes schematic information into pages. It captures and displays

only one page of schematic information at a time. Design Entry HDL is a by-reference

editor because it references all parts in the schematic from various libraries that reside at

the reference or local area. A standalone, self-contained database of the libraries and the

design can be created using the Archiver utility. After you open the desired design project


in Project Manager, the flow area of Project Manager displays the Cadence Board Design

flow. In the Board Design flow, click the Design Entry icon.

Figure 5.1 Allegro Design Entry HDL schematic


Fig 5.2 Allegro Design Entry HDL workspace

5.4 Features

A top-down (hierarchical) design that lets you quickly draws blocks and connects

wires between blocks. A cross-view generator (Gen view) to create blocks from HDL

descriptions or automatically generate HDL text from high-level diagrams.

A customizable user interface that lets you customize menus and toolbars, map keys

to functions, and create new commands.

A hierarchy editor lets you view the structure of your design.

An attribute editor that lets you annotate properties on a design to drive the physical

layout.

Integration with the Design Synchronization toolset. This toolset lets you view

differences between your schematic and the board layout and then synchronize them.


Cross-probing between Design Entry HDL and other Cadence tools.

Support for design reuse. You can associate logical components with a layout section

to create reusable components. This component can be reused in other areas in your design

and also in the designs you create later.

Integration with Check Plus, an advanced rule checking and rule development

system.

Integration with Constraint Manager Tool that allows you to capture and manage

electrical constraints as you implements logic.


CHAPTER 6

TASKS ASSIGNED

As a trainee, here at Cadence Design Systems, I was entitled to do the following, as a

part of my project completion and understanding the way in which the company

works:

6.1 Preface

Before starting on with any work, it was indispensable to have a brief knowledge about the

various Front-End and Back End tools like:

Allegro System Architect-System Connectivity Manager

Allegro Design Entry HDL

6.2 Validation: A process

Once I started getting familiar with the SCM tool, which included creating logical designs

and playing with the tool, I shifted on to the validating part; which was the main concern.

6.2.1 Validation

When we talk about validating, this is an idea what it really is:

Validation is getting the right system. Figure below depicts one way in which validation is

integrated with the lifecycle of software design:

Fig 6.1 Validation Lifecycle


The raw material for validation of software in lifecycles like the one in Figure is obtained

from the following sources:

Requirements : Informal (normally) description of users' needs.

Specfications : Formal/informal description of properties of the system.

Designs : Describe how the specification will be satisfied.

Implementations : Source code (normally) of the system.

Changes : Modifications to correct errors or add functionality.

Using this raw material we then attempt to satisfy a number of objectives:

Correctness : Is the system fault free?

Consistency : Does everything work in harmony?

Necessity : Are there things in it which aren't essential?

Sufficiency : Is everything essential there?

Performance : Does it do the job well enough?

These objectives are general and it probably will not be possible to prove we have attained

them (for example it is very difficult to be sure that traditional software is fault free).

Nevertheless, they are the aspirations of validation and verification. Why is attainment so

difficult? Here are some reasons:

Usually it is impractical to test a program on all possible inputs.

Even if we can enumerate the inputs, it may be impractical to test all execution

paths.

Proofs of equivalence between programs may be easier, but that's not the same as

proving absolute correctness.

In mission-critical software systems, where flawless performance is absolutely

necessary, formal methods may be used to ensure the correct operation of a system.

However, often for non-mission-critical software systems, formal methods prove to be very


http://en.wikipedia.org/wiki/Formal_methods

http://en.wikipedia.org/wiki/Mission-critical

costly and an alternative method of software validation must be sought out. In such

cases, syntactic methods are often used:

Test cases

A test case is a tool used in the process. They may be prepared for software verification - to

determine if the process that was followed to develop the final product is right -, and also

for software validation - if the product is built according to the requirements of the user.

6.2.2 Automation

The automatic operation or control of equipment, a process, or a system. The techniques

and equipment used to achieve automatic operation or control. Automation is the

replacement of manual operations by computerized methods. Office automation refers to

integrating clerical tasks such as typing, filing and appointment scheduling. Factory

automation refers to computer-driven assembly lines.

Figure 6.2 Elements of an automated system

6.2.2.1 Types of Automation:

Although automation can play a major role in increasing productivity and reducing costs in

service industries—as in the example of a retail store that installs bar code scanners in its

checkout lanes—automation is most prevalent in manufacturing industries. In recent years,

the manufacturing field has witnessed the development of major automation alternatives.


http://en.wikipedia.org/wiki/Syntactic_methods

Other types of automation include:

1. Information technology (IT): Information technology (IT) encompasses a broad

spectrum of computer technologies used to create, store, retrieve, and disseminate

information.

2. Computer-aided manufacturing (CAM): Computer-aided manufacturing (CAM)

refers to the use of computers in the different functions of production planning and control.

CAM includes the use of numerically controlled machines, robots, and other automated

systems for the manufacture of products.

3. Numerically controlled (NC) equipment: - Numerically controlled (NC) machines are

programmed versions of machine tools that execute operations in sequence on parts or

products. Individual machines may have their own computers for that purpose; such tools

are commonly referred to as computerized numerical controlled (CNC) machines.

4. Robots: - Robots are a type of automated equipment that may execute different tasks

that are normally handled by a human operator.

5. Computer Integrated Manufacturing: A computer-integrated manufacturing (CIM)

system is one in which many manufacturing functions are linked through an integrated

computer network. These manufacturing or manufacturing-related functions include

production planning and control, shop floor control, quality control, computer-aided

manufacturing, computer-aided design, purchasing, marketing, and other functions.

The Advantage of Automation: -

Reduce production time, increase manufacturing flexibility, reduce costs,

eliminate human error, or make up for a labor shortage:

The power of computers is that they perform repetitive tasks quickly, efficiently and

without complaints. This extends to transferring data. Whether you have one field sales

office or 100, you should automate your communications whenever possible. More than

likely, the cost savings of automation will outweigh the cost of the commercial software

needed.


Manual testing can be replaced by test automation. It is possible to record and

playback manual steps and writes automated test script(s) using Test automation

tools: Many commercial communication packages support automation through a scripting

language. A scripting language is a means of programming your software to perform the

repetitive tasks which meet your needs. However, all scripting languages are not created

equal. Some languages consist of a few commands to automate a basic file transfer. Others

contain hundreds of commands and functions allowing you to develop applications capable

of handling all your communication needs. Some packages require the user to understand

programming in order to write the simplest of scripts. Others provide interfaces to assist

users in developing scripts. Some will even write scripts based on your use of the software.

Quality software packages include pre-built scripts for common communication tasks

which can be used as templates for your own needs.

Whether it is a small or a large design in which changes have to be made,

automation makes it easier to perform such tasks without any complexity: Higher

output and increased productivity have been two of the biggest reasons in justifying the use

of automation.

It uses the power of computers to perform repetitive tasks quickly, efficiently

and without complaints: One of the most common automation features of

communications software is known as "server polling." Polling involves a single computer

system calling (or polling) a number of remote computers for the purpose of downloading

or uploading data. The restaurant chain described previously uses polling to gather its sales

and inventory data.

If you have multiple platforms, this greatly reduces your development time:

When selecting a communications package based on the power of its scripting language,

understand your needs and know your capabilities. If you have multiple platforms, look for

compatibility between the scripts from one platform to another. This greatly reduces your

development time.


6.2.3 Sanity and Performance Testing

The following testing criteria are required by a tool in order to manage its performance and

provision of features according to the license. These testing’s play a very important role in

helping to judge what needs to be added or modified in a tool so as to make it more

compatible to work in different environments and in perform better in relation to other

tools or products.

Sanity testing :

This testing includes performing operations on various features of a tool and testing for any

kind of issue while performing for the same. The sanity testing can vary according to the

hierarchy set.

Performance testing

This type of testing relates to measure of the performance of a tool. It also depends and

varies with the hierarchy set.

The task on performance checks can involve comparison of one tool with other or

comparison among hierarchies as well (in this case among daily updates in 16.6). And, also

the categorization of performance testing can be on the bases of design parameters such as

small ,medium, large or mid-large etc designs.

6.3 Automation as a process

1. The test case can either be created manually for the particular scenario or can be

downloaded from CCMS (Cadence change management system) testcase directory. In

CCMS zipped case is present along with the description and details (notes) explaining the

particular step in the tool where the bug/problem had been encountered. The other details

are also provided such as the name of the requester, severity of the case, product, release

number, OS, etc.


2. After downloading testcase from CCMS testcase directory or making it

manually, it is saved as a tar format (like zip) named as test.tar. After untar the major files

which are present at this level are/should be :

Cpm file:the main design of the testcase.

Cds.lib of the design: The cds.lib file is the library definition file that defines

all the libraries used in your design and maps them to their physical locations.

lib folder of the design: supports all the components of the design

3. The files that have to be created manually at the testcase level(also called initial

state) are/should be:

Golds folder: Contains the files to be diffed.

test.tar: The design to be used while automation.

4. Verification of the data includes following the steps mentioned for a particular

testcase in description/notes while performing the operations on the tool. This verification

is performed on the .cpm file which is already present in test.tar. The prerequisite of

verification is to have the knowledge of the tool it is being performed on.

5. The Verification status can then decide the accuracy of the test case in form of :

Incorrect: irreproducible, not fixed, unavailability of testcases and cpm design,

etc.

Correct: Reproducible, fixed.

The accuracy then decides what is to be done of a particular testcase. If correct, Tcl script

is recorded and restored for further use.

6. After verification the files that have to be created at testcase level (also called final

level) are :

Makefile: This script includes the steps to be performed while automation and the

files to be diffed.


env.sh: file describing the test, worklib and cell name of a particular testcase in which

changes have to be made manually.

nc.tcl: The tcl script recorded while performing the commands in a tool required for a

testcase.

Comp_graphics.xml: It is the Extended Markup language file, which is defines

characteristics to be dumped or extracted while the testcase is srunning.

Readme.txt: This includes the brief description of a testcase.

7. The env.sh, Makefile, tcl script have to be edited for assigning identity to the testcase,

diffing files that need to be moved in golds and for running the tcl script at the location

mentioned respectively.

8. The tcl script is made to run on different ports i.e. Windows and UNIX port to verify

the automated results.

9. The status of the testcase is checked after running them on ports by obtaining the status

of pass/fail.

6.3.1 Terms used in Testing

6.3.1.1 Test Case

A TEST CASE as already described is legal action whose outcome is likely to set a

precedent or test the constitutionality of a statute. In software engineering, the most

common definition of a test case is a set of conditions or variables under which a tester will

determine if a requirement or use case upon an application is partially or fully satisfied. It

may take many test cases to determine that a requirement is fully satisfied. In order to fully

test that all the requirements of an application are met, there must be at least one test case

for each requirement unless a requirement has sub requirements. In that situation, each sub

requirement must have at least one test case. Written test cases should include a description

of the functionality to be tested, and the preparation required to ensure that the test can be

conducted.


http://www.answers.com/topic/application-software

http://www.answers.com/topic/use-case

http://www.answers.com/topic/requirement

6.3.1.2 Tcl

TCL stands for “Tool Command Language” and invented in 1987. The idea was to spend

extra effort to create a good interpreted language, and furthermore to build it as a library

package that could be reused in many different applications. The language interpreter

would provide a set of relatively generic facilities, such as variables, control structures, and

procedures.

6.3.1.3 Makefile

A makefile is used with the UNIX make utility to determine which portions of a program to

compile. A makefile is basically a script that guides the make utility to choose the

appropriate program files that are to be compiled and linked together.

The make utility keeps track of the last time files were updated so that it only updates the

files containing changes. However, all of the files that are dependent on the updated files

must be compiled as well, which can be very time-consuming. With the help of makefile,

the make utility automates this compilation to ensure that all files that have been updated -

and only those - are compiled and that the most recent versions of files are the ones linked

to the main program, without requiring the user to perform the tasks separately.

6.3.1.4 Env.sh

It contains the list of environmental variables which are required while running the

testcase. It mainly contains the worklib name, cell name, & cpm file name as a variable.

The variables are passed by this file while automation and is mentioned in Makefile.

6.3.1.5 nc.tcl

nc.tcl is a tcl script in which commands are written according to the actions to be

performed. You can either manually write the nc.tcl script or use it from the temp folder

formed at the .cpm level. SCM dumps all the actions in file ProjectTcl.tcl in the temp

folder.


http://searchEnterpriseLinux.techtarget.com/sDefinition/0,,sid39_gci212948,00.html

http://searchCIO-Midmarket.techtarget.com/sDefinition/0,,sid183_gci213265,00.html

http://WhatIs.techtarget.com/definition/0,,sid9_gci873189,00.html

6.3.2 Data Flow Diagram for Automation

Fig 6.3 Flow diagram showing automationCadence Design Systems, Inc. 72

6.4 List of automated testcases

Since the automation process was carried on upon an ongoing live project, hence the

detailed documentation cannot be listed because of its confidentiality. A brief list of the

generated testcases are as follows:

1. For the validation of component support in SCM, Fed-ex testcases were made and

automated. These involved as many as 20 cases, which were regressively run with the

daily updates in the hierarchical build.

2. For the improvements in the Graphic User Interface and the innovative advancements in

the Schematic Editor, a series of around 60 testcases were made and then automated to be

regressively run alongside the daily hierarchical updates.

3. Manual testing of as many as around 40 components of a customer. Manual testing

involves the characterization of the various components in the tools based upon how they

appear and function.

6.5 Bug-search and crash retracing

Another task in the Validation process is to find the glitches and shortcomings in the tool

and report for any crash occurred during the working of the tool.

While new features are added in a tool, there is obviously a code associated with that

particular feature. If something goes wrong in the code, the outcome is reflected in the

functionality.

Hence, my job was to look for the scenarios which lead to some issue in the functionality

of a particular operation or a command.

Sometimes, a series of operations caused the tool crash or lead to hang. The target was to

recreate the steps in a script so as to replay the corresponding crash.

After observing the bugs and crashes and successfully recording respective scripts for that,

the bugs and crashes were to be filed on a system pool for bugs named Bugzilla.

6.5.1 Bugzilla

Bugzilla is a Web-based general-purpose bugtracker and testing tool originally developed

and used by the Mozilla project, and licensed under the Mozilla Public License. Released

as open source software by Netscape Communications in 1998, it has been adopted by a


http://en.wikipedia.org/wiki/Netscape_Communications

http://en.wikipedia.org/wiki/Open_source_software

http://en.wikipedia.org/wiki/Mozilla_Public_License

http://en.wikipedia.org/wiki/Software_license

http://en.wikipedia.org/wiki/Mozilla

http://en.wikipedia.org/wiki/Test_automation

http://en.wikipedia.org/wiki/Bugtracker

http://en.wikipedia.org/wiki/World_Wide_Web

variety of organizations for use as a bug tracking system for both free and open source

software and proprietary projects and products.

Fig 6.4 Bugzilla main window

The bugs and crashes observed by all the people working on a common project file the

bugs at one common platform, where it gets accessible to everyone related to that project,

from development team to the Validation Department.

The filed bug contains the following details to be appended with:

Component: Firstly, we select the component with which the bug or the crash is

associated.

Fig 6.5 Component Window


http://en.wikipedia.org/wiki/Proprietary_software

http://en.wikipedia.org/wiki/Free_and_open_source_software

http://en.wikipedia.org/wiki/Free_and_open_source_software

http://en.wikipedia.org/wiki/Bug_tracking_system

Summary: A brief one line summary or the title to the bug is then given.

Fig 6.5 Summary Window

Description: This box contains the detailed steps to be followed to recreate the bug

or the crash.

Fig 6.7 Description Window

Attachment: The scripts or designs that might be required to be added.

Fig 6.8 Attachment button


The bug is assigned to the particular Developer who is responsible for creation of the

particular feature. The window where bug is filed looks like:

Fig 6.9 Sample bug window

6.6 Design Capture

Another step in the process of Validation is Capturing certain diagrams, analog designs and

electrical circuits on the tool, to validate the overall user friendly functionality of the tool.

To validate the functionality of certain components and their connectivity properties,

several designs were captured repeatedly with the timely build updates. The alongside

crashes and bugs were also taken care of. The reproduction of the crash was dealt with.

The key concept is to make the tool conceptually right, make it perform the logic correctly

and most of all, make it user-friendly.

Hence steps were devised to test the usability of the tool by capturing the designs such as:


Fig 6.10 Captured design

Many of the other designs were also captured, but they cannot be listed due to

confidentiality issues.

6.7 Test Plan

A test plan documents the strategy that will be used to verify and ensure that a product or

system meets its design specifications and other requirements. A test plan is usually

prepared by or with significant input from Test Engineers.

Depending on the product and the responsibility of the organization to which the test plan

applies, a test plan may include one or more of the following:

Design Verification or Compliance test: To be performed during the development

or approval stages of the product, typically on a small sample of units.

Manufacturing or Production test: To be performed during preparation or assembly

of the product in an ongoing manner for purposes of performance verification and quality

control.

Acceptance or Commissioning test: To be performed at the time of delivery or

installation of the product.


Service and Repair test: To be performed as required over the service life of the

product.

Regression test: To be performed on an existing operational product, to verify that

existing functionality didn't get broken when other aspects of the environment are changed

(e.g., upgrading the platform on which an existing application runs).

A complex system may have a high level test plan to address the overall requirements and

supporting test plans to address the design details of subsystems and components.

Test plan document formats can be as varied as the products and organizations to which

they apply, but there are three major elements of a test strategy that should be described in

the test plan: Test Coverage, Test Methods, and Test responsibilities.

Test coverage in the test plan states what requirements will be verified during what stages

of the product life. Test Coverage is derived from design specifications and other

requirements, such as safety standards or regulatory codes, where each requirement or

specification of the design ideally will have one or more corresponding means of

verification. Test coverage for different product life stages may overlap, but will not

necessarily be exactly the same for all stages. For example, some requirements may be

verified during Design Verification test, but not repeated during Acceptance test. Test

coverage also feeds back into the design process, since the product may have to be

designed to allow test access.

Test methods in the test plan state how test coverage will be implemented. Test methods

may be determined by standards, regulatory agencies, or contractual agreement, or may

have to be created new. Test methods also specify test equipment to be used in the

performance of the tests and establish pass/fail criteria. Test methods used to verify

hardware design requirements can range from very simple steps, such as visual inspection,

to elaborate test procedures that are documented separately.

Test responsibilities include what organizations will perform the test methods and at each

stage of the product life. This allows test organizations to plan, acquire or develop test

equipment and other resources necessary to implement the test methods for which they are

responsible. Test responsibilities also includes, what data will be collected, and how that

data will be stored and reported (often referred to as "deliverables"). One outcome of a


successful test plan should be a record or report of the verification of all design

specifications and requirements as agreed upon by all parties.

The test plan was well adhered to, and a whole series of actions was based upon the test-

plan.

All the possible operational behavior was covered in the test plan and then validated.

I also made several test plans for the new features added in scm, details of which cannot be

documented because of the confidential agreement.


CHAPTER-7

TOOLS AND SOFTWARES USED

7.1 ClearCase

ClearCase is termed as a software configuration management system.

We use clearcase as it manages multiple variants of evolving software systems, keep

updating about which versions were used in software builds, performs builds of individual

programs or entire releases according to user-defined version specifications, and enforces

site-specific development policies.

ClearCase is a comprehensive software configuration management system. It manages

multiple variants of evolving software systems, tracks which versions were used in

software builds, performs builds of individual programs or entire releases according to

user-defined version specifications, and enforces site-specific development policies.

These capabilities enable ClearCase to address the critical requirements of organizations

that produce and release software.

Effective development — ClearCase enables users to work efficiently, allowing

them to fine-tune the balance between sharing each other's work and isolating themselves

from destabilizing changes. ClearCase automatically manages the sharing of both source

files and the file produced by software builds.

Effective management — ClearCase tracks the software build process, so that users

can determine what was built, and how it was built. Further, ClearCase can instantly

recreate the source base from which a software system was built, allowing it to be rebuilt,

debugged, and updated — all without interfering with other programming work.

Enforcement of development policies — ClearCase enables project administrators

to define development policies and procedures, and to automate their enforcement.

7.1.1 ClearCase Data Structures

Figure 7.1 shows a development environment managed by ClearCase. At its heart is a

permanent, secure data repository. It contains data that is shared by all users: this includes


current and historical versions of source files, along with derived objects built from the

sources by compilers, linkers, and so on. In addition, the repository stores detailed

“accounting” data on the development process itself: who created a particular version (and

when and why), what versions of sources went into a particular build, and other relevant

information.

Only ClearCase commands can modify the permanent data repository. This ensures orderly

evolution of the repository and minimizes the likelihood of accidental damage or malicious

destruction.

Conceptually, the data repository is a globally accessible, central resource. The

implementation, however, is modular: each source (sub) tree can be a separate versioned

object base (VOB). VOBs can be distributed throughout a local area network, accessed

independently or linked into a single logical tree. To system administrators, modularity

means flexibility; it facilitates load-balancing in the short term, and enables easy expansion

of the data repository over the long term.

Figure 7.1 ClearCase Development Environments

7.1.2 Version Control

The most basic requirement for a software configuration management system is version

control — maintaining multiple versions of software development objects. Traditional


version-control systems handle text files only; ClearCase manages all software

development objects: any kind of file, and directories and links, as well.

Versions of non-text files are also stored efficiently, using data compression. Version

control of directories enables the tracking of changes to the organization of the source code

base, which are just as important as changes to the contents of individual files. Such

changes include creation of new files, renaming of files, and even major source tree

“cleanups”.

7.1.3 Versioned Object Bases (VOBs)

A versioned object base, or VOB, is the permanent data repository for a development tree or sub tree. A VOB stores file system objects: directories, files, symbolic links, and hard links.

ClearCase development data is organized into any number of versioned object bases (VOBs). Each VOB provides permanent storage for all the historical versions of all the source objects in a particular directory tree. As seen through a ClearCase view, a VOB seems to be a standard directory tree — the “right” versions of the development objects appear, and all other versions are hidden (Figure 7.2).

Figure 7.2 VOB

A version-controlled object in a VOB is called an element; its versions are organized into a version tree structure, with branches and sub branches (Figure 9.2). As this figure shows, branches have user-defined names, typically chosen to indicate their role in the development process. All versions have integer ID numbers; important versions can be


assigned version labels, to indicate development milestones — for example, a product release.

7.1.4 Views and Transparent Access

As described in “ClearCase Data Structures”, a view directly accesses the version-controlled elements in the permanent, shared data repository. There is no need to copy the versions required for a particular project to a view; instead, the correct versions are accessed dynamically. A particular version of each element is selected according to user-specified rules in the view's config spec (“configuration specification”): a file element appears to be an ordinary file; a directory element appears to be an ordinary directory.

Figure 7.3 Version Selections by a View

Views are dynamic — config spec rules are continually reevaluated. This means that a view is open-ended; as new data is added to the central repository, it is immediately accessible to all views. It also means that a view's configuration can be instantly modified — for example, to “shut out” a recent destabilizing change to the repository.

7.1.5 Example: Editing Source Files in a View


A user, working in a view, enters a checkout command to make a source file editable. This seems to change a file element in the data repository from read-only to read-write. In reality, ClearCase copies the read-only repository version to a writable file in the view's private storage area. This writable file, the checked-out version, appears in the view at the same pathname as the file element; the view accesses this editable, checked-out version until the user enters a check in command, which updates the repository and deletes the view-private file.

Figure 7.4 Check out/Check in and View-Private Storage

7.1.6 Version Control - ClearCase VOBs

ClearCase supports a well-organized, controlled development environment by maintaining two kinds of data storage:

Permanent data repository — a globally-accessible, shared data resource that can be modified only by ClearCase commands. The repository contains both historical and current development data.

Working data storage — any number of distinct areas which provide “scratchpad storage” for day-to-day development activities. A typical area belongs to an individual user, or to a small group working on the same task.

7.2 Tcl/Tk


As explained earlier TCL stands for “Tool Command Language” and invented in 1987. The idea was to spend extra effort to create a good interpreted language, and furthermore to build it as a library package that could be reused in many different applications. The language interpreter would provide a set of relatively generic facilities, such as variables, control structures, and procedures.

7.2.1 Advantages of Tcl/Tk

One of the primary advantages of Tcl/Tk is that the source code is freely available on the Internet from Sun Microsystems.

By making the source code freely available, two other advantages arise:

1. First, that fact that Tcl/Tk is free has undoubtedly contributed to its widespread use. The Tcl/Tk community is estimated to number in the tens of thousands, therefore providing the new user with a well established user-base to fall back on for assistance and guidance.

2. Second, freely distributing the source code leads to open development of the package. End users are free to fix bugs and make suggestions and enhancements to the existing Tcl core. The existence of a clean, well-documented functional interface to the internal mechanisms of Tcl makes it relatively easy to extend Tcl to include features which are either too slow or not directly supported in Tcl.

Programming a GUI can be a very arduous and demanding chore. Tcl/Tk helps make the task easier by raising the level of abstraction for the programmer, thereby making the implementation of user interfaces easier and quicker. Graphical interfaces written using Tcl/Tk typically require significantly less code than an equivalent interface written in C. Tcl is relatively easy to learn and provides most of the features one would expect from a general purpose programming language. Since Tcl is an interpreted scripting language, there is no need for the developer to compile the code. This makes rapid prototyping more feasible with Tcl/Tk.

7.2.2 Tcl Language Syntax

set <variable_name> <variable_value> : Sets value to the variable

expr < any arthmatic function> : Perform arthematic operation

eval < argument > : To execute the script

lindex < list of elements > : To extract element from list

string length < string > : To get length of string


button.b –text < string > -fg < color > : To display the string in desired

format.

incr < variable_name > < variable_value> : Increments the value

set matrix( I,j) < value > : To represent a array

concat { string1 } { string2 } : To Combine strings

llength {{string 1}{string2}} : tells no of elements in a list

linsert $< variable_name > <position> <value> : To insert value at given

position in the list.

lrange $ <variable_name > < range > : To extract range of elements from a

list.

lsearch $ < variable_name > < variable to be searched > : To search element

from the list.

lsort { string1, string2…. } : Arrange in increasing lexicographic order

split $ < variable_name >/ : Breaks up a string into component pieces

proc < function_name > {arguments} { tcl script} : Creates a new

commands.

cd?dirName?: Changes the working directory to dirName

close ?fileId?: Closes the file given by fileId. Returns an empty string.

Eof fileId: Returns 1 if an end-of-file condition has occurred,0 otherwise.

gets fileId?varname?: Reads the next line from fileId and discards its

terminating value.

open name ?access?: Opens file name in the mode given by access.

pwd: Returns the full path name of the current working directory.

tell fileId: Returns the current access position for fileId.


file executable name: Returns 1 if name is executable by the current user

file exists name: Returns 1 if name exists ,0 otherwise

file isfile name: Returns 1 if name is an ordinary file,0 otherwise

file readable name: Returns 1 if name is readable by the current user,

otherwise.

file readlink name: Returns the value of the symbolic link given by name

file size name: Returns a decimal string giving the size of file name in bytes

file writable name: Returns 1 if name is writable by the user, 0 otherwise.

7.2.3 Command evaluation

Tcl evaluates a command in two steps: parsing and execution.

In the parsing step the Tcl interpreter applies the rules to divide the command up in to words and perform substitutions. Parsing is done in exactly the same way for every command .During the parsing step the Tcl interpreter does not apply any meaning to the values of the words. Tcl just performs a set of simple string operations such as replacing the characters “$a” with the string stored in variable a; Tcl does not know or care whether a or the resulting word is a number or the name of a widget or anything else.

In the execution step meaning is applied to the words of the command . Tcl treats the first word as a command name , checking to see if the command is defined an locating a command procedure to carry out its function . If the command is defined then the Tcl interpreter invokes its command procedure , passing all the words of the command to the command procedure. The command procedure is free to interpret the words in any way that it pleases, and different commands apply very different meanings to their arguments.

7.3 UNIX

UNIX is an operating system which was first developed in the 1960s, and has been under constant development ever since. By operating system, we mean the suite of programs which make the computer work. It is a stable, multi-user, multi-tasking system for servers, desktops and laptops.

UNIX systems also have a graphical user interface (GUI) similar to Microsoft Windows which provides an easy to use environment. However, knowledge of UNIX is required for


operations which aren't covered by a graphical program, or for when there is no windows interface available, for example, in a telnet session.

7.3.1 Types of UNIX

There are many different versions of UNIX, although they share common similarities. The most popular varieties of UNIX are Sun Solaris, GNU/Linux, and Mac OS X.

7.3.2 UNIX Operating System

The UNIX operating system is made up of three parts; the kernel, the shell and the programs.

The kernel

The kernel of UNIX is the hub of the operating system: it allocates time and memory to programs and handles the file store and communications in response to system calls.

As an illustration of the way that the shell and the kernel work together, suppose a user types rm myfile (which has the effect of removing the file myfile). The shell searches the filestore for the file containing the program rm, and then requests the kernel, through system calls, to execute the program rm on myfile. When the process rm myfile has finished running, the shell then returns the UNIX prompt % to the user, indicating that it is waiting for further commands.

The shell

The shell acts as an interface between the user and the kernel. When a user logs in, the login program checks the username and password, and then starts another program called the shell. The shell is a command line interpreter (CLI). It interprets the commands the user types in and arranges for them to be carried out. The commands are themselves programs: when they terminate, the shell gives the user another prompt (% on our systems).

The adept user can customize his/her own shell, and users can use different shells on the same machine.

7.4 Extensible Markup Language (XML)

Extensible Markup Language (XML) is a markup language that defines a set of rules for encoding documents in a format that is both human-readable and machine-readable

The design goals of XML emphasize simplicity, generality, and usability over the Internet. It is a textual data format with strong support via Unicode for different human


http://en.wikipedia.org/wiki/Language

http://en.wikipedia.org/wiki/Unicode

http://en.wikipedia.org/wiki/Internet

http://en.wikipedia.org/wiki/Machine-readable_data

http://en.wikipedia.org/wiki/Human-readable_medium

http://en.wikipedia.org/wiki/File_format

http://en.wikipedia.org/wiki/Markup_language

languages. Although the design of XML focuses on documents, it is widely used for the representation of arbitrary data structures, for example in web services.

To dump data in a well ordered fashion containing all the required attributes, in a test case, an XML is used.

The template of XML is as follows:

<fedb>

<version>1.0</version>

<schematic unit=”grid”>

<pages>

<pagename=”page(1)”>

<drawingobjects>

</drawingobjects>

</page>

</pages>

</schematic>

</fedb>

CHAPTER 8

CONCLUSION


http://en.wikipedia.org/wiki/Web_service

http://en.wikipedia.org/wiki/Data_structures

http://en.wikipedia.org/wiki/Language

Automated around 150 Test Cases for SCM.

Generated TCL scripts for automation cases.

Learned the design flow and had hands on experience on the below mentioned tools.

a. SCM (System Connectivity Manager).

b. DEHDL (Design Entry HDL)

Hands on experience on various platforms like UNIX and Windows 7 and 8.

Experience in capturing designs on SCM in a user-directive manner.

Experience in Bug-handling and crash recreation.

Hands on experience on Clearcase.

Learned and understood the fundamentals of the EDA industry.

During my six months industrial training period in Cadence, I have gained a lot of practical

knowledge and a good experience of working in an industry. I have learned how to handle the

given tasks in a given period of time more efficiently and in an organized way, I have gained a

lot of practical knowledge while working in the industry. This is the purpose of this training

and not only have I learned a lot about the industry, I have even learned new languages and

tools.

In Cadence, I worked on a design authoring tool, System Connectivity Manager. With the help

of this tool; we can capture the design at the board level. I worked on different utilities of these

tools. I learnt about the flat designs and hierarchical designs. I also learnt the importance of the

hierarchical designs and how it helps in reducing time while designing large designs. While

designing these circuits, I got much more details of the circuit at the schematic level and got

familiarized with many technical terms such as diff- pairs, nets, rats, break, etc.

CHAPTER 9

REFERENCES


Allegro SCM User Guide v16.6

UNIX Tutorials by tutorialspoint

CSHELLIII by Norman Matloff

DEHDL User Guide v166

www.cadence.com

http://softwaretestingfundamentals.com/verification-vs-validation/

www.tcl.tk



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