Laboratory KEEE 1174Experiment 2: Flip-Flop (Digital Lab)TAN JIA HUEI (KET 120044)Name of demonstrators: Mr. Shameem Ahmad

1. Abstract1. To ensure students understand and further be able to explain the operation of the flip-flop circuit.2. To verify the truth table for flip-flop circuits.

2. Introduction1. In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

2. Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.

3. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered).

4. Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"), T ("toggle"), and JK types are the common ones. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, in terms of the input signal(s) and/or the current output, .

5. SR and JK flip-flops are considered simple Set-Reset latches.

6. The D ip-op is widely used. It is also known as a data or delay flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line. Below is a diagram of a clocked D flip-flop.

7. The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse.

The outputs from Q and Q from the slave flip-flop are fed back to the inputs of the master flip-flop with the outputs of the master flip-flop being connected to the two inputs of the slave flip-flop. During the positive clock pulse, the master flip-flop is active and the slave flip-flop remains inoperative. During the negative clock pulse, the master flip-flop is inactive and slave flip-flop copies the operation of the master flip-flop.

3. Results:1. RS Flip-Flop:a. The truth table for the circuit:E1 (S)E2 (R)

00UndefinedUndefined

011 (set)0 (reset)

100 (reset)1 (set)

11No changeNo change

Table 1: Truth table for RS Flip-Flop

b. The sketched circuit using NAND logic gates:

Diagram 1: Circuit diagram for RS Flip-Flop

c. Conclusion from the results obtained above based on practical use of the RS Flip-Flop as a memory circuit:

The circuit can be considered to be a one bit memory circuit since Q can be set to one or zero, depending on the S-R inputs. When either S or R has 1 (HIGH) as input, the output Q will be either 1 or 0. When both S and R are 1, then the circuit remembers the previous value. Thus the circuit functions as a basic memory circuit.

2. Extended RS Flip-Flopa. The truth table for the circuit:E1 (S)E2 (R)

00No changeNo change

010 (reset)1 (set)

101 (set)0 (reset)

11UndefinedUndefined

Table 2: Truth table for Extended RS Flip-Flop

b. The sketched circuit using NOT and NAND logic gates:

Diagram 2: Circuit diagram for Extended RS Flip-Flop

c. Explanation of the circuit output signal:The circuit above is a representation of a S-R Flip-Flop constructed using NOR logic gates. The output of the circuit (table 2) will be directly inverse of that of the first circuit (refer to table 1). This is due to the NOT logic gates producing inversed S-R inputs to the flip-flop.When either S or R is HIGH, then the output will be either HIGH (set) or LOW (reset). When both inputs are LOW, the output will be unchanged. When both inputs are HIGH, the output state will be undefined and is invalid.

3. RS Flip-Flop with Dominant Reseta. The truth table for the circuit:E1 (S)E2 (R)

00No changeNo change

010 (reset)1 (set)

101 (set)0 (reset)

110 (reset)1 (set)

Table 3: Truth table for RS Flip-Flop with Dominant Reset

b. The sketched circuit using NOT and NAND logic gates:

Diagram 3: Circuit diagram for RS Flip-Flop with Dominant Reset

c. Advantage of this circuit compared to the previous circuits:This circuit design eliminates the Undefined output state in previous circuit designs, and outputs zero (reset) instead. This means that this circuit can produce more output states then previous circuit designs. The extra output state can enable more flexible complex circuits to be built upon this circuit, compared to the previous circuit which have less output states. The flexibility when designing further more complex circuits upon using this circuit is larger. Besides that, this design also prevents the circuit from being in the Undefined or Invalid output state. This prevents potential machine failure due to the Undefined output state.4. Clock State Triggered D Type Flip-Flopa. The timing diagram:

Diagram 4: Timing diagram for Clock State Triggered D Type Flip-Flop

b. The sketched circuit using NOT and NAND logic gates:

Diagram 5: Circuit diagram for Clock State Triggered D Type Flip-Flop

c. Comment on output switching for the Clock State Triggered D Type Flip-Flop :The output of the D flip-flop tries to follow the input D but cannot make the required transitions unless it is enabled by the clock. If the clock is low when a transition in D occurs, the tracking transiton in Q occurs at the next upward transition of the clock. If the clock is high when a transition in D occurs, the tracking transiton in Q occurs immediately.

5. JK Master Slave Flip-Flop

a. The truth table for the circuit:E1E2 ( ) ( )

00001

00111

01001

01110

10001

10111

11001

11110

Table 4: Truth table for JK Master Slave Flip-Flop

b. The timing diagram:

Diagram 6: Timing diagram for JK Master Slave flip-flop

c. Comment on output switching for the JK Master Slave flip-flop :

The input signals J and K are connected to the gated "master" SR flip-flop which "locks" the input condition while the clock (Clk) input is "HIGH" at logic level "1". As the clock input of the "slave" flip-flop is the inverse (complement) of the "master" clock input, the "slave" SR flip-flop does not toggle. The outputs from the "master" flip-flop are only "seen" by the gated "slave" flip-flop when the clock input goes "LOW" to logic level "0". When the clock is "LOW", the outputs from the "master" flip-flop are latched and any additional changes to its inputs are ignored. The gated "slave" flip-flop now responds to the state of its inputs passed over by the "master" section. Then on the "Low-to-High" transition of the clock pulse the inputs of the "master" flip-flop are fed through to the gated inputs of the "slave" flip-flop and on the "High-to-Low" transition the same inputs are reflected on the output of the "slave" making this type of flip-flop edge or pulse-triggered.Then, the circuit accepts input data when the clock signal is "HIGH", and passs the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a "synchronous" device as it only passes data with the timing of the clock signal.

d. Advantages of using JK Master Slave flip-flop:i. It eliminates the toggle / race around condition of the JK flip-flop.ii. It is more efficient while being used in microprocessors.

4. Conclusion :From the experiment, 1. we learned and understood the operation of the flip-flop circuit. 2. we are able to further explain its operation.3. we have verified the truth table for different types of Flip Flop.4. we have discussed about the advantages of each Flip Flop.5. we have compared some pairs of Flip Flop.

5. References :1. Wayne Storr. (2013, April). Electronics Tutorial about JK Flip-flops [online] Available: http://www.electronics-tutorials.ws/sequential/seq_2.html 2. (2013, March 30). Flip-flop (electronics) [online] Available: http://en.wikipedia.org/wiki/Flip-flop_(electronics)3. V Sanjith. (2012, June 7). Master-Slave JK Flip-Flop | Working | Advantages | Uses [online] Available: http://electronicsnow.in/master-slave-jk-flip-flop-workingadvantagesuses/4. Prof. Bernd-Peter Paris. (1998, December 14) [online] Available: http://thalia.spec.gmu.edu/~pparis/classes/notes_101/node115.html