Reouven Elbaz – February 10 t h , 2009reouven@uwater loo.caOff ice room: DC3576

ECE223

Outline

MultiplexersDecoders3-state GatesRead Only Memories (ROM)

Multiplexers

A 2n-to-1 multiplexer selects one of its 2n

input values and outputs it – data selector.

How? Using control signals that encode the position of the targeted input…

How many control signals? For 2n

inputs, n control signals

MUX8-to-1

I0

I1

I2

I3

I4

I5

I6

I7

Output

a b c

I3I6I7

2-to-1 Multiplexer

Output = aI0 + a’I1

MUX

I0

I1

Output

a

2-to-1

a Output

0

1

I1

I0

4-to-1 Multiplexer

Output = a’b’I0 + a’bI1 + ab’I2 + abI3

MUX4-to-1

I0

I1

I2

I3

Output

a b

a b Output

0 0 I0

0 1 I1

1 0 I2

1 1 I3

a’b’I0

a’bI1

ab’I2

abI3

a' b'

General Case: 2n-to-1 multiplexer

kk

k ImOutputn

12

0

I0

I1

I2

I

Output

2n

MUX2n-to-1

S0 S1 Sn

Minterm k of the n control signals

Input designated by the minterm k

4-to-1 Multiplexer with Enable

e a b Output

1 0 0 I0

1 0 1 I1

1 1 0 I2

1 1 1 I3

MUX4-to-1

I0

I1

I2

I3

Output

a b

e

0 X X 0

How to construct a 8-to-1 Mux from 4-to-1 Muxes ?

MUX

4-to-1

I0

I1

I2

I3

O1

a

b

MUX

4-to-1

I4

I5

I6

I7

O2

e

e a b O1 O2 Y

1 0 0 I0 0 I0

1 0 1 I1 0 I1

1 1 0 I2 0 I2

1 1 1 I3 0 I3

0 0 0 0 I4 I4

0 0 1 0 I5 I5

0 1 0 0 I6 I6

0 1 1 0 I7 I7

Or Y

I4

I5

I6

I7

I0

I1

I2

I3

a b

a b

What we wantWhat we have

Done!

VHDL Example

entity Mux4-to-1 is port(

I0, I1, I2, I3: in std_logic; CTRL: in std_logic_vector(1 downto 0); Output: out std_logic );

end Mux4-to-1;

architecture behav of Mux4-to-1 is begin case CTRL is when "00" => Output <= I0; when "01" => Output <= I1; when "10" => Output <= I2; when "11" => Output <= I3; when others => Output <= I1; end case; end;

MUX4-to-1

I0

I1

I2

I3

Output

CTRL

2

Decoders

An n-to-m (m ≤2n) decoder converts binary information from n input lines (n-bit coded information) to a maximum of 2n unique output lines.

How?It generates all the minterms of the n input

variables (to have exactly one of the outputs at 1 for each combination of inputs)

Example: n=3 and m=8

3-to-8 Decoder

I0

I1

I2

O0

O1

O2

O3

O4

O5

O6

O7

Example: 3-to-8 Decoder

a b c O0 O1 O2 O3 O4 O5 O6 O7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

3-to-8 Decoder

a

b

c

O0

O1

O2

O3

O4

O5

O6

O7

c

b

a

O0= a’b’c’

O1= a’b’c

O2= a’bc’

O3= a’bc

O4= ab’c’

O5= ab’c

O6= abc’

O7= abc

c’

b’

a’

From Decoder to Multiplexer

a b O0 O1 O2 O3

0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

2-to-4 Decoder

a

b

O0

O1

O2

O3

b

a

O0= a’b’

O1= a’b

O2= ab’

O3= ab

b’

a’

a b Output

0 0 I0

0 1 I1

1 0 I2

1 1 I3MUX

4-to-1

I0

I1

I2

I3

Output

ab

b

a

b’

a’

Output = a’b’I0 + a’bI1 + ab’I2 + abI3

OrOutput

I0

I1

I2

I3

Decoder with Enable Input

e a b O0 O1 O2 O3

0 0 0 1 0 0 00 0 1 0 1 0 00 1 0 0 0 1 00 1 1 0 0 0 11 X X 0 0 0 0

2-to-4 Decoder

a

b

e

O0

O1

O2

O3

b

a

O0= a’b’e’

O1= a’be’

O2= ab’e’

O3= abe’

b’

a’

e

How to construct a 3-to-8 Decoder from 2-to-4 Decoders ?

e

a b O0 O1 O2 O3 O4 O5 O6 O7

1 0 0 1 0 0 0 0 0 0 01 0 1 0 1 0 0 0 0 0 01 1 0 0 0 1 0 0 0 0 01 1 1 0 0 0 1 0 0 0 00 0 0 0 0 0 0 1 0 0 00 0 1 0 0 0 0 0 1 0 00 1 0 0 0 0 0 0 0 1 00 1 1 0 0 0 0 0 0 0 1

2-to-4 Decoder

a

b

e

O0

O1

O2

O3

O4

O5

O6

O7

2-to-4 Decoder

VHDL Example

entity DECODER2-to-4 is port(

I: in std_logic_vector(1 downto 0);O: out std_logic_vector(3 downto 0));

end DECODER2-to-4;

architecture behav of DECODER2-to-4 is begin case I is when "00" => O <= "0001"; when "01" => O <= "0010"; when "10" => O <= "0100"; when "11" => O <= "1000"; when others => O <= “0000"; end case; end;

2-to-4 Decoder

a

b

O0

O1

O2

O3

2-to-4 Decoder

I(“ab”)

O(“O1O2O3O4”

)2

4

3-state Gates

Component exhibiting three states: Logic ‘1’ and logic ‘0’ states as in conventional gates High impedance ‘Z’ state.

What is high impedance? (1) The gate behaves like an open circuit – Output

disconnected (2) The circuit has no logic significance (3) The circuit connected to a 3-state gate in high

impedance is not affected by the inputs to the gate.3-state buffer:

s

a y = a if s = 1 Z if s = 0

a

b

c

d

yMUX4-to-1

Multiplexers constructed from 3-state buffers

1a y

2b

s

MUX

a

b

y

s

2-to-1

s y

0 a

1 b

2-to-1 Mux

4-to-1 Mux

s0 s1 y

0 0 a

0 1 b

1 0 c

1 1 d

s0s1 ay

b

c

d

s0

s1

s2

s3

2-to-4 Decode

r

s0

s1

VHDL Example

entity 3-state_buffer is port( a: in std_logic_vector(7 downto 0); s: in std_logic; y: out std_logic_vector(7 downto 0)); end 3-state_buffer;

architecture behav of 3-state_buffer is begin if s = '1' then y <= a; else y <= "ZZZZZZZZ"; end if; end;

s

ay = a if s = 1 Z if s = 0

8

8

Read Only Memory (ROM)

A ROM is a memory where data are permanently stored… A memory that retains data across power cycles.

Different types of ROM: Mask programmable (data defined during the manufacture

process) field-Programmable ROM (PROM): initialization done by user

using fusible Erasable Programmable ROM (EPROM): charge storage is used

to program – UV light to erase EEPROM: use electrical pulses instead of UV light

2n m-bit words ROM

a0a1

an

n Address

lines

d0d1

dn

m data lines