Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder

210 IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 25, NO. 3, JULY 2002

Reliability Investigations of Hard Core Solder BumpsUsing Mechanical Palladium Bumps and SnPb Solder

Hermann Oppermann, Member, IEEE, Robert Kalicki, Sabine Anhoeck, Christine Kallmayer, Matthias Klein,Rolf Aschenbrenner, and Herbert Reichl, Fellow, IEEE

Abstract—The choice of solder joint metallurgy is a key issue es-pecially for the reliability of flip-chip assemblies. Besides the met-allurgical systems already widely used and well understood, newmaterials are emerging as solderable under bump metallization(UBM). For single chip bumping Pd stud bumps form a solid coreunder the solder layer. These hard core solder bumps are an ade-quate solution if single dies are available only and the chosen as-sembly technology is flip chip soldering. The scope of this paper isto summarize the results from aging of lead/tin solder bumps onPalladium. The growth of intermetallic and its impact on the me-chanical reliability are investigated.

Index Terms—Flip chip, intermetallic compound, inter-metallics, mechanical stud bumping, palladium, reliability, singlechip bumping, solder reaction, under bump metallization.

I. INTRODUCTION

SOLDERING technique is a cost effective way for flip chipon board assemblies in manufacturing environment due to

simple pick and place and common reflow with surface mountdevices [1]. For flip chip in package, e.g., CSP and BGA, sol-dering is often used on rigid and flex interposers.

One of the key technologies for flip chip is bumping. The con-ventional C4 process of IBM uses sputtering, etching, vacuumevaporation and lift-off techniques for the formation of high leadbumps. This was the only accepted technology for long time.With the development of electrolytes and thick photosensitiveresist techniques electroplating of gold came up. Straight wallopenings in thick resists with an aspect ratio better than 8 areattainable today [2]. The gold bumping process was a key tech-nology for TAB and is widely used today for isotropic conduc-tive adhesive (ICA) bonding. By electroplating tin after gold asolderable bump is formed [3]. Electrolytes for plating eutecticor high lead containing Sn/Pb bumps are also used today [4].

Electroplating demands for comparable expensive sputteringand phototooling equipment. A low cost approach for bumpingwas introduced by electroless deposition of nickel [5], pal-ladium or copper [6]. The electroless deposition method isadapted to the aluminum pad metallization of CMOS wafers

Manuscript received April 23, 1999; revised June 6, 2002. This work wassupported in part by the Federal Ministry of Education and Research (Germany)under Project VIMP.

H. Oppermann is with the University of Tokyo, Tokyo 153, Japan (e-mail:[email protected]).

R. Kalicki, R. Aschenbrenner, and H. Reichl are with Fraunhofer IZM, Berlin,Germany.

S. Anhoeck, C. Kallmayer, and M. Klein are with the Technical University ofBerlin, Berlin D-13355, Germany.

Digital Object Identifier 10.1109/TEPM.2002.806787

and does not require for sputtering or phototooling steps. Allprocedures are maskless and performed in chemical baths.In extensive reliability tests nickel/gold bumps revealed highadhesion strength. Additionally they seal the aluminum padsand corrosion is heavily delayed even in harsh chemicalenvironments.

The Ni/Au metallization offers a perfect layer for the appli-cation of solder paste by stencil printing [7]. In this case theNi/Au layer acts as an under bump metallization (UBM) forthe solder. Due to their high corrosion resistance and excellentbump height uniformity Ni/Au bumps are suitable for the appli-cation of isotropic (ICA) or anisotropic conductive adhesives asfilm (ACF) or paste (ACP) [8], [9].

Single chip bumping processes were developed for proto-typing and due to the fact that many IC’s are often not availablein wafer format. A modified wire bonder is used for single studbumping. Gold and palladium bumps can be formed directly onthe aluminum metallization of the IC pads [10], [11].

For the application of solder wires a wettable surface isrequired, like electroless nickel, gold or palladium stud bumps.Solder bumps can be formed on nickel or palladium pads usingeutectic SnPb or high lead solder wires [12]. Another approachto achieve a high melting solder bump is the stud bumping ofgold on aluminum pads followed by wedge bumping usingSnAg3 alloy wire [13]. During reflow a solderable AuSn cap isformed with an eutectic melting temperature of 280C.

For SnPb solder bumps Ni or Pd is acting as an adhesionlayer and diffusion barrier between solder and Al pad. In thisinvestigations the authors will focus on the barrier function ofpalladium and compare the results with the barrier behavior ofelectroless deposited nickel.

II. BUMPING PROCESS

A. Pd Stud Bumping as UBM

Silicon test chips of 5 5 mm size, 84 peripheral I/Os and200 m pitch were used for palladium stud bumping. Octagonalpad openings of 80m in the chip passivation are exposing alu-minum bond pad of 800 nm thickness.

In a first step palladium stud bumps were formed mechani-cally with a modified wire bonder using optimized parametersfor ultrasonic power and time, chip temperature and bond force.The palladium wire used here had a thickness of 25m. A spe-cial capillary tool suitable also for gold stud bumping was usedto form the stud bumps. With another tool the palladium studswere coined on a flip chip bonder to achieve a flattened Pd bumpwith equal height.

1523-334X/02$17.00 © 2002 IEEE

OPPERMANNet al.: RELIABILITY INVESTIGATIONS OF HARD CORE SOLDER BUMPS 211

TABLE IRELIABILITY TEST PROGRAM FORPd+ SnPb

B. Electroless Ni/Au

Test chips of 10 10 mm size, 184 I/Os, 200 m pitchand 100 100 m pad size were used for electroless nickelbumping. For deposition of electroless Ni/Au the standardprocess of IZM/TUB was used. The procedure starts with twocleaning steps (passivation cleaning and Al pad cleaning) anda short zincate treatment to form a seeding layer. The nickeldeposition takes 15 minutes to form a 5m thick mushroombump. Finally immersions gold is deposited to serve as abondable and solderable layer which prevents the nickel fromoxidation.

C. Solder Bumping on Pd

Eutectic SnPb solder balls with 125m in diameter wereplaced on top of the flattened palladium studs. The samples werereflowed in liquid bath at two temperatures (220C and 230 C)to study their influence. The liquid bath provides a unique tem-perature and protects the solder from oxidation. In the reflowstep the solder is wetting the whole Pd stud bump forming aball which incorporates the palladium stud as a hard core.

D. Solder Bumping on Electroless Ni/Au

Eutectic SnPb solder paste was applied on test wafers withelectroless Ni/Au using stencil printing and a reflow at 230C.Finally the wafer was wet cleaned to remove the flux residues,rinsed, dried and singulated.

E. Bump Reliability Test

The test procedures should exhibit the metallurgical reactionsof Pd stud bumps with SnPb solder on top and their impact onthe reliability. 48 test chips were divided in 3 lots for different re-liability tests as shown in Table I. The bumps were investigatedby shear testing, SEM and EDX analyzes after cross-sectioning.

High temperature storage at 150C up to 4000 hours was per-formed to investigate the phase formation and phase growth atthe interface between Nickel and solder. Shear tests were carriedout to characterize the mechanical properties and the reliabilityof Ni/solder joints.

III. PHASE FORMATION

A. Initial State

The reflowed condition of the hard core solder bumps is de-fined as the initial state. Cross-section in Fig. 1 indicates thatPd–Sn intermetallic phases have already formed. PdSnwasfound closed to the Pd bump in a distance of about 15m. In-termetallic phases grow into the solder by transforming Sn. Re-maining Pb is enclosed in between.

Fig. 1. Initial state after reflow at 220C.

Fig. 2. Remelting of eutectic SnPb reacted with Pd.

Fig. 3. Pd with SnPb after 25 hours at 150C.

DSC measurements (Fig. 2) of Pd with SnPb solder showedthat the reaction changed from eutectic melting at 184C to amelting interval between 184C and 190 C after the metallur-gical reaction of solder with Pd.

B. High Temperature Storage

The cross-sectioning in Fig. 3 and EDX analysis show thatafter 25 hours aging at 150C a closed layer of PdSnwith a


Fig. 4. Pd with SnPb after 125 h aging at 150C.

Fig. 5. Pd with SnPb, aged for 1000 hours at 150C.

thickness of less than 1m forms on Pd. Several small grainsof PdSn grow up to 8 m in height on top of the PdSnlayer.Starting from PdSnprecipitates and directly from the PdSnlayer PdSn columns of 50 m length grow vertically into thesolder and Pb remains in between. The columns near to the Pdstud consist of stacked thin plates. With larger distance to the Pdstud single grains with selected orientations grow into the soldervolume. Above the columns a zone of dendrites consisting ofPdSn is embedded in Pb. Only on top of the bump SnPb solderis left.

After 50 hours no Sn grains were found in the solder. Thebump is transformed from ball to post shape, which indicates alarge amount of material transport (Fig. 4).

After 500 hours at 150C very thin PdSn plates are formedperpendicular to the PdSncolumns. The bump consists of Pdstud, a PdSnlayer, some PdSn3 precipitates, columns of PdSnwith perpendicular thin plates of PdSn, a zone of PdSnden-drites and pure Pb on top (Fig. 5). The growth ratewas cal-culated using layer thicknessafter aging time according to:

Fig. 6. Growth rate of intermetallic compounds during high temperaturestorage.

Fig. 7. Pd with SnPb, 250 cycles (�55 C to 125 C).

Fig. 8. Growth rate during temperature cycling.

. The growth for PdSncolumns and PdSnlayerare given in Fig. 6.

C. Temperature Cycling

The solder forms a cap on top of the columnar PdSngrains.At the outer rim the solder is already transformed completely(see Fig. 7). Kirkendall voids appear between PdSnand solderand agglomerate to large pores. The maximum temperature was125 C for 20 minutes each cycle. The time in the upper tem-perature period was accumulated to calculate the growth timeof intermetallic compounds. Due to the lower temperature theirgrowth rate is reduced compared with accelerated aging test(Fig. 8).


Fig. 9. After temperature/humidity testing 50 h.

Fig. 10. Pd with SnPb, temperature/humidity test 250 h.

D. Temperature/Humidity Testing

The lowest temperature of 85C was applied during hu-midity testing. In a sequence one can see how the bumpsshape transforms by the growth of intermetallic compounds.Columnar grains of PdSnstart to grow at the interface next tothe Pd into the solder and reach the outer site of the solder capat the bottom of the hard core bump (Fig. 9). In a later stage thegrowth direction is only upward because the solder at the sideis already consumed (Fig. 10). In some samples PdSnwasfound between Pd stud and the columnar PdSn. Pores nearto the Pd interface (Fig. 11) were found. The growth rate ofPdSn was calculated from Fig. 12.

E. Bump Shear Strength

After solder ball placement two different methods of reflowwere compared a) using the laser of the solder ball placer, fol-lowed by a reflow in liquid bath and b) using a liquid bath only.

With high temperature storage at 150C ball lift and siliconcratering were observed by shear testing. Three independentprocess steps could cause silicon cratering: Pd stud bumping,

Fig. 11. Pd with SnPb, temperature/humidity test 750 h.

Fig. 12. Growth rate of PdSnfound during temperature/humidity testing.

TABLE IISHEAR FORCE AND CRATERING APPEARANCEAFTER EACH PROCESSSTEPS

(B = Pd STUD BUMPING, C= COINING, L = LASER REFLOW, M =

MANUAL PLACEMENT, R= REFLOW IN LIQUID BATH, T = AGING

AT 150 C FOR 25, 50OR 125 HOURS)

coining or laser reflow. Therefore an extended evaluation wasperformed by shear force testing and infrared microscopy aftereach process step. Instead of the solder ball placement andlaser reflow manual placement was chosen for comparison (seeTable II).

Cratering of silicon was observed only after laser reflowand thermal aging by shear mode evaluation and infrared mi-croscopy. With manual placement the shear mode was changed


TABLE IIISHEAR FORCE OFSOLDERED Ni BUMPS

Fig. 13. Soldered Ni bumps after reflow and annealing at 150C for 2000 h.

to ball lift. But anyway, shear forces drop always with increasedaging time. This indicates that the laser reflow is damaging thesilicon, but thermal aging results always in adhesion loss of Pdstud on aluminum pad.

F. Results on Electroless Ni/Au SnPb Solder

For high temperature storage of soldered Ni bumps at 150Cup to 4000 hours no significant decrease in the shear force wasobserved. Solder shear was the only shear mode, cratering couldnot be observed. Table III shows the results of high temperaturestorage.

The reaction between solder and Ni takes place especiallyduring solder bump reflow and at elevated temperature. Afterreflow at 230 C the intermetallic compound formed at the in-terface between Ni bump and solder shows an initial thicknessof 0.5 m. The composition is close to the formula of NiSn .

A cross section of soldered Ni bumps after reflow and an-nealing at 150C for 2000 h is shown in Fig. 13. In the interfacebetween Ni and eutectic solder a thin intermetallic layer of NiSn can be observed.

The chemically deposited nickel consists of nickel and phos-phorus due to the composition of the electrolyte. For standardnickel bumping process developed at IZM/TUB a phosphoruscontent of 10 wt.-% P is used.

A layer structure of the Ni/P bump can be observed afteretching shown in Fig. 14. Small variation of phosphorus con-tent of about 1 weight-% across a distance of 100 nm are causingthe lines of equal growth revealed by this etching method. Thevertical lines are also caused by higher phosphorus content andthey separate different growth columns of metallic Ni–P startingfrom the tiny seeding layer at the Al interface.

During annealing of Ni UBM the phosphorus distributes ho-mogeneously in the Ni. For soldered Ni bumps the phosphorus

Fig. 14. Etched Ni bump to reveal the microstructure.

was not found in the solder itself. A very thin layer of phos-phorus rich Ni–P at the interface between Ni and NiSn phaseis formed. The phosphorus rich Ni–P layer inhibits the Ni dif-fusion into the solder.

IV. DISCUSSION

A. Pd Stud Bumps

The reliability test program showed that the main failure isdue to the formation and growth of intermetallic Pd–Sn phases.This results in

a) fast consumption of Sn, only Pb remains between thePd–Sn phases.

b) columnar growth of PdSnneedles into the solder re-ducing the volume of the solderable cap.

c) void formation between Pd and PdSnas well as betweenPdSn and solder cap.

d) bump transformation from ball to post shape.e) adhesion loss between the Pd and the Al pad.Each of the changes described above could cause a failing in-

terconnect. The large changes in solder composition and Pd–Snphase formed a) can result in excessive molar volume that re-sults in inner stresses. With the columnar growth b) across thewhole bump the ductility is reduced. Other bump compositions,e.g., Ni or Cu with solder, show a slow planar growth with minorchanges in solder composition.

The arrangements of voids or pores along an interface c) caninitiate cracks and they are preferred paths for crack propaga-tion, especially for brittle interfacing materials.

In temperature/humidity testing at 85C pores were formedat the interface between Pd and PdSn. Therefore it is concludedthat Pd is diffusing much faster through PdSnto the soldercap than the Sn through PdSnto the Pd stud. This unbalanceddiffusion transport lead to the precipitation of Kirkendall voidsand finally to the formation of large pores. After long time smallpores have been found additionally between the PdSncolumnsin the residual Pb.

Whereas during temperature cycling with 125C maximumtemperature pores are only located at the interface betweenPdSn and solder cap.

With high temperature storage no large pores could be found.One possible reason could be that the excess vacancies created


Fig. 15. Arrhenius plot of growth rates for different Pd–Sn compounds.

Fig. 16. Ni Sn growth of eutectic SnPb on electroless deposited Ni bumps.

by the unbalanced diffusion could precipitate at the surface ofthe bump due to their high mobility at increased temperatures.The appearance of a PdSnlayer and the formation of PdSnmight give another reason. These compounds could limit thediffusion flow of Pd. On the other hand they could also absorbexcess vacancies at their interface to accommodate the excessvolume caused by differences in molar volume of formed com-pounds.

Shape transformation d) are caused by a large anisotropic ma-terial transport and can result in bump distortions and stresses.

The adhesion loss between Pd and aluminum pads e) wasstudied intensively to reveal the impact of laser reflow. It wasfound that tempering of Pd studs alone would not reduce theadhesion strength (see Table II). Only after solder applicationand reflow a decrease in shear strength was found. Phase forma-tion and changes in molar volume, which result in inner stresses,might cause this.

Similar results were already observed in an earlier investiga-tion [2]. Silicon chips with AuSn bumps in the as plated con-dition with a Sn cap on top of Au initiated cracks into a glasssubstrate during flip chip soldering. Whereas reflowed bumpswith eutectic AuSn cap did not show any cracking in the glasssubstrate. The large volumes in phase transformation in the caseof soldering AuSn directly on glass and in this case of solder re-flow on Pd core produce similar stresses, which result in glasscracking respectively in adhesion losses.

The growth rates of the different Pd–Sn compounds are sum-marized in an Arrhenius plot. Although the growth rates usedhere are derived from different reliability test methods, theyshow credible temperature dependence in Fig. 15. The activa-

tion energy was estimated with 0.2 eV and indicates that thetemperature dependence for PdSnand PdSn is very low.

B. Electroless Ni

The Ni Sn layer formed between solder and Ni grows in aclosed planar layer. No voiding could be observed. The growthrate at 150 C was calculated with 1.2*10 cm/s (Fig. 16).

Results on temperature/humidity tests and temperature cy-cling of bumps as well as of assemblies on FR-4 have been al-ready published elsewhere [1], [5], [7] and did not show anyfailure caused by the reaction of electroless Ni and the solder.

V. CONCLUSION

The eutectic SnPb solder on Pd studs were intensively studiedin bump reliability tests. The formation and rapid growth of in-termetallic compounds revealed several critical points regardingthe long time reliability. Adhesion loss of Pd on aluminum, largeconsumption of Sn in the solder, void formation and excessivebump deformation were observed. This bumping method shouldtherefore only be used for rapid prototyping, but the reliabilityis week.

Electroless Ni shows only minor growth of planar in-termetallic compound layers. The adhesion strength is notchanging significantly in reliability tests. Electroless Ni de-position according to the process developed by FraunhoferIZM and TU Berlin is suitable as a reliable UBM for flip chipinterconnects.

REFERENCES

[1] A. Ostmann, J. Kloeser, and H. Reichl, “Implementation of a chem-ical wafer bumping process,” inProc. 1996 Int. Electron. Packag. Symp.(IEPS’96), San Diego, CA, 1996, pp. 354–366.

[2] H. H. Oppermann, E. Zakel, G. Engelmann, and H. Reichl, “Investiga-tion of self-alignment during flip-chip assembly using eutectic gold–tinmetallurgy,” inProc. 4th Int. Conf. Exhibition Microelectro, Opto, Mech.Syst. Comp. (Microsyst. Technol.’94), 1994.

[3] E. Zakel, J. Simon, G. Azdasht, and H. Reichl, “Gold–tin bumps forTAB inner lead bonding with reduced bonding pressure,”Solder SurfaceMount Technol., p. 27, Oct. 1992.

[4] L. Dietrich, E. Zakel, E. Jung, and H. Reichl, “Optimization of bumpingmetallurgy for Pb–Sn solder bumps,” inProc. Area Array Packag.Technol.—Workshop Flip Chip Ball Grid Arrays, Berlin, Germany,Nov. 13–15, 1995.

[5] A. Ostmann, G. Motulla, J. Kloeser, E. Zakel, and H. Reichl, “Low costtechniques for flip chip soldering,” inProc. SMI Conf., San Jose, CA,Sept. 10–12, 1996, pp. 318–326.

[6] R. Aschenbrenner, A. Ostmann, U. Beutler, J. Simon, and H. Reichl,“Electroless nickel/copper plating as a new bump metallization,”IEEETrans. Comp., Packag., Manufact. Technol. B, vol. 18, p. 334, May 1995.

[7] J. Kloeseret al., “Low cost flip chip technologies using chemicalNi-bumping and solder printing,” inProc. ISHM’96 Conf., Min-neapolis, MN, Oct. 6–10, 1996, p. 93.

[8] R. Aschenbrenner, E. Zakel, G. Azdasht, A. Kloeser, and H. Reichl,“Fluxless flip-chip bonding on flexible substrates: A comparison be-tween adhesive bonding and soldering,”Solder. Surface Mount Technol.,pp. 5–11, June 1996.

[9] R. Aschenbrenner, A. Ostmann, G. Motulla, K. F. Becker, E. Zakel,and H. Reichl, “Flip chip interconnection to glass substrates usinganisotropic adhesives and electroless nickel bumping,” inAdhesives inElectron.’96, Stockholm, Sweden, June 3–5, 1996, p. 258ff.

[10] J. Eldring, E. Zakel, and H. Reichl, “Flip chip attach of silicon and GaAsfine pitch devices as well as inner lead TAB attach using ball bump tech-nology,” in Proc. IEPS Conf., San Diego, CA, Sept. 1993.

[11] M. Klein, H. Oppermann, R. Aschenbrenner, and H. Reichl, “Singlechip bumping,” inProc. IMAPS’98 Conf., San Diego, CA, 1998, pp.633–638.


[12] E. Jung, J. Eldring, J. Kloeser, A. Ostmann, E. Zakel, and H. Reichl,“Flip chip soldering on printed wiring boards using vapor phase reflow,”in Proc. ITAP’95 Conf., San Jose, CA, 1995, pp. 22–31.

[13] J. Nave, E. Jung, C. Kallmayer, D. Lin, P. Kasulke, E. Zakel, and H.Reichl, “A new bumping technique using ball and wedge bumpingfor manufacturing of hard core solder bumps,” inProc. Micro SystemTechnol.’96, Potsdam, Germany, Sept. 1996.

Hermann Oppermann (M’94) received thediploma in materials science and technology fromthe Technical University of Clausthal, Germany, in1985 and the Dr.Ing. degree in materials sciencefrom the Metals Research Institute, TechnicalUniversity Berlin, Berlin, Germany, in 1992.

Since 1993, he has been with the MicroperiphericCenter, Technical University Berlin, and wasworking in flip chip technologies and CSP pack-aging. His most important contributions have beenin the development of the gold/tin flip chip soldering

technology. Since October 1998, he has been working with the Fraunhofer IZMwhere he leads the Assembly of Optoelectronics, RF, and Sensor ComponentsGroup. Between November 1998 and May 1999, he joined the Institute ofMicrosystem and Advanced Packaging Laboratory, University of Tokyo,Tokyo, Japan, as an Associate Professor.

Robert Kalicki , photograph and biography not available at the time ofpublication.

Sabine Nieland née Anhoeckreceived the M.S. andPh.D. degrees in material science from the TechnicalUniversity of Berlin (TU Berlin), Berlin, Germany, in1997 and 2002, respectively.

She joined the Microperipherical Center of TUBerlin in 1997 as a Research Fellow. Her researchinterests are on fundamental investigations of softsolders and their reactions as well as solder jointreliability. She has authored or co-authored severaltechnical publications on ternary Au–Sn–X systems,reliability of electroless Ni/P bumps, as well as high

temperature solder joint reliability.

Christine Kallmayer received the M.S. degreein experimental physics from the University ofKaiserslautern, Germany, in 1994.

Afterwards, she was a Research Scientist withTechnologien der Mikroperipherik Research Center,Technical University of Berlin, Berlin, Germany.Her main field of activity was the development andinvestigation of packaging technologies with theAu–Sn metallurgy for different applications, e.g.optoelectronics, chip on flex, chip scale packages,and the reliability of the metallurgical system.

Since 1998, she has been responsible for the Flex Circuit Application Group,Fraunhofer IZM, Germany. During her time at the institute she has presented13 technical papers as main author at different international conferences.Additionally she co-authored over 20 technical papers. She is also involved inseven submitted patents.

Ms. Kallmayer received the Outstanding Young Engineer Award from IEEECPMT, in 2002.

Matthias Klein received the M.S. degree in physicsfrom the University of Kiel, Germany, in 1997.

He joined the Center of Microperipheric Tech-nologies, Technical University of Berlin, Berlin,Germany, in 1997, where he worked as a Re-search Scientist. Since 2002, he has been with theFraunhofer IZM, Berlin. His main research is thedevelopment of chip interconnection and packagingtechniques. He is especially engaged in single chipbumping and thermo-compression bonding for flipchip applications.

Rolf Aschenbrenner received the B.S. degree inmechanical engineering from the University forApplied Science, Gießen, Germany, in 1986 andthe M.S. degree in physics from the University ofGießen, Germany, in 1991.

In 1993, he joined the Technologien der Mikrope-ripherik“ Research Center, Technical University ofBerlin, Berlin, Germany, working in the area ofelectroless metal deposition. Since March 1994, hehas been employed at the Fraunhofer Institute Re-liability and Microintegration Berlin (IZM), where

he is presently head of the Chip Interconnection Technologies Department. In2000, he became the Deputy Director of the Fraunhofer Institute IZM.

Mr. Aschenbrenner was a member of the Board of Governors, IEEE CPMTSociety. He is General Chair of the first International IEEE Conference on Poly-mers and Adhesives in Microelectronics and Photonics.

Herbert Reichl (M’89–SM’97–F’01) is the Directorof the Fraunhofer IZM, Berlin, Germany, anda Professor for packaging and interconnectiontechnologies at the Technical University of Berlin,Germany, where he also heads the Research Centerof Microperipheric Technologies. For the pastdecade he has been at the forefront of the develop-ment and application of innovative assembly andpackaging solutions world-wide. He has publishedmore than 500 papers and authored or co-authoredsix books. He is a member of program committees

and advisory boards of a number of national and international conferences,and among others he chairs the SMT/ES&S/Hybrid and the Micro SystemTechnologies Conference.

Dr. Reichl received the Order of Merit of the Federal Republic of Germanyin 2000.

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Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder