RELIABILITY EVALUATION QUALIFICATION OF SOIC8L …1.0 05-May-2016 F.VENTURA I&PC QA&R / B/E A.PLATINI I&PC QA&R MNG. Final report Note: This report is a summary of the reliability

AMG

Analog & Mems -Group

Industrial & Power Conversion

Div.

Quality & Reliability B-END RR000116CT6004

1/10

RELIABILITY EVALUATION QUALIFICATION

OF SOIC8L Narrow & SOIC8L E-PAD XDLF-IDF

(EXTREAM DENSITY LEAD FRAME) ATP1 (AMKOR PHILIPPINES SUBCON)

DOCUMENT INFORMATION

Version Date Pages Prepared by Approved by Comment 1.0 05-May-2016 F.VENTURA

I&PC QA&R / B/E A.PLATINI I&PC QA&R

MNG.

Final report

Note: This report is a summary of the reliability trials performed in good faith by STMicroelectronics in order to evaluate the potential reliability risks during the product life using a set of defined test methods. This report does not imply for STMicroelectronics expressly or implicitly any contractual obligations other than as set forth in STMicroelectronics general terms and conditions of Sale. This report and its contents shall not be disclosed to a third party without previous written agreement of STMicroelectronics.

AMG



Div.


2/10

General Information

Product Line CRO7*U093ADZ

P/N L6561D-1HLF/ L6561D13TR-1HLF/

Product Group AMG Product division Industrial & Power Discrete Package SOIC 8L .150 NARROW Silicon Process technology A3 - BCD1 Maturity level step 29

Locations

Wafer fab AMK6 (ANG MO KIO S’PORE)

Assembly plant ATP1-SUBCON PHILIPPINES

Final Reliability Assessment

PASSED

Reliability Lab ST-MOROCCO

Document reference Short description AEC-Q100 Stress test qualification for automotive grade integrated circuits JESD47 Stress-Test-Driven Qualification of Integrated Circuits ADCS:8161393 General specification for product development

1 GLOSSARY DUT Device Under Test SS Sample Size

AMG



Div.


3/10

2 RELIABILITY EVALUATION OVERVIEW

2.1 Objectives TO QUALIFY NEW XDLF (EXTREAM DENSITY L/FRAME) VERS. ON SOIC8L .15O/E-PAD NARROW PKG. ATP1 SUBCON

2.2 Conclusion

Qualification Plan requirements (WORKABILITY/ TESTING / CONSTRUCTION ANALISYS) have been fulfilled without exception. It’s stressed that reliability tests have shown that the devices behave correctly against environmental tests (no failure). Moreover, the stability of electrical parameters during the accelerated tests demonstrates the ruggedness of the products and safe operation, which is consequently expected during their lifetime. NOTE: The present RR (RR000116CT6004) CAN BE EXTENDED to all involved AMG/I&PC tech/products assembled on SOIC8L XDLF ATP1 line

DENSITY LEAD FRAME SCENARIO:

NEW FRAME OLD FRAME

AMG



Div.


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2.3 Construction note

*U093_ P/N: L6561D-1HLF/ L6561D13TR-1HLF/

Wafer/Die fab. information AMK6 Wafer fab manufacturing location ANG MO KIO S’PORE Technology BCD 1 Process family A3 BCD1 Die finishing back side CHROMIUM/NICKEL/GOLD Die size 2590,2060 UM Bond pad metallization layers Al/Si Passivation type SIN (NITRIDE) Wafer Testing (EWS) information Electrical testing manufacturing location AMK6 Assembly information Assembly site ATP1/ AMKOR PHILIPPINES Package description SOIC8L NARROW .150 Molding compound SUMITOMO EME G600 ECOPAK 2 COMPLIANCE Frame material OLIN C194 COPPER Die attach process EPOXY GLUE Die attach material HENKEL ABLEBOND 8290 Die pad size 90 X 130 mil XD IDF PN 101379012 Wire bonding process THERMOSONIC Wires bonding materials/diameters 1.3 mils Au Lead finishing process Pre- plated Package code O7 Final testing information Testing location ST-BSK MOROCCO

AMG



Div.


5/10

3 TESTS RESULTS SUMMARY

3.1 Test vehicle *U093

Lot #

Diffusion Lot Assy Lot Trace Code Process/

Package Product Line Comments

1 V6517VN3

CZ6040C601 n/a SOIC 8L NARROW CRO7*U093ADZ

Detailed results in below chapter will refer to P/N and Lot #.

3.2 Test plan and results summary P/N L6561D-1HLF/ L6561D13TR-1HLF/

Test PC Std ref. Conditions Steps Note

PC Y JESD22 A020-D

MSL_1 HTS 24H @125°C+TH

168H(85°C@85%RH)+3IR@260° 0/100

NO DELAMINATION TOP/BOTTOM

BEFORE & AFTER PRECOND.

TC Y JESD22 A-104

Ta = -65°C to 150°C

500CY 0/77

1000CY 0/77

In case of Automotive customer insert here the family data. In case of rejects include a short description of the failure analysis and corrective actions.

AMG



Div.


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3.4.1 ANNEXES: MOUNT BOND DIAGRAM (MBD)

AMG



Div.


7/10

3.2.1 Package outline/Mechanical data

AMG



Div.


8/10

AMG



Div.


9/10

AMG



Div.


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Tests Description

Test name Description Purpose

Package Oriented

PC Preconditioning

The device is submitted to a typical temperature profile used for surface mounting devices, after a controlled moisture absorption.

As stand-alone test: to investigate the moisture sensitivity level. As preconditioning before other reliability tests: to verify that the surface mounting stress does not impact on the subsequent reliability performance. The typical failure modes are "pop corn" effect and delamination.

TC Temperature

Cycling

The device is submitted to cycled temperature excursions, between a hot and a cold chamber in air atmosphere.

To investigate failure modes related to the thermo-mechanical stress induced by the different thermal expansion of the materials interacting in the die-package system. Typical failure modes are linked to metal displacement, dielectric cracking, molding compound delamination, wire-bonds failure, die-attach layer degradation.

Reliability Report RR000716CS6080

AMG Group – RELIABILITY - CASTELLETTO

Version 1.0 Page 1/13

Preliminary Reliability Report

General Information

Locations

Product Line UK17 Wafer fab location ANG MO KIO

Product Description Step Down Switching Regulator

Assembly plant location

AMKOR ATP1 PHILIPPINES Product division I&PC

Package HSOP 8L

Silicon process technology BCD5-40NP Reliability assessment Pass

DOCUMENT HISTORY

Version Date Pages Author Comment

1.0 26-Feb-2016 13 S.O.Cannizzaro Preliminary release

Approved by Giuseppe Capodici




Table of Contents

1 APPLICABLE AND REFERENCE DOCUMENTS ....................................................................... 3

2 RELIABILITY EVALUATION overview ........................................................................................ 4

2.1 Objectives ........................................................................................................................................ 4

2.2 Conclusion ....................................................................................................................................... 4

3 Device Characteristics ............................................................................................................... 5

3.1 Device description ............................................................................................................................ 5

3.1.1 Pin connection ................................................................................................................................................... 5

3.1.2 Bonding diagram ............................................................................................................................................... 5

3.1.3 Package outline/Mechanical data ..................................................................................................................... 6

3.2 Traceability ...................................................................................................................................... 7

4 Tests results summary ............................................................................................................... 8

4.1 Test plan and results summary of UK17 with XD lead frame strip ....................................................... 8

4.2 Test plan and results summary of UK17 with HD lead frame strip ....................................................... 9

5 Tests Description & detailed results ........................................................................................... 10

5.1 Die oriented tests ........................................................................................................................... 10

5.1.1 High Temperature Operating Life .................................................................................................................... 10

5.1.2 Early Life Failure Rate ..................................................................................................................................... 10

5.2 Package oriented tests ................................................................................................................... 11

5.2.1 Pre-Conditioning .............................................................................................................................................. 11

5.2.2 High Temperature Storage .............................................................................................................................. 11

5.2.3 Thermal Cycles ............................................................................................................................................... 11

5.2.4 Autoclave ......................................................................................................................................................... 11

5.2.5 Temperature Humidity Bias ............................................................................................................................. 12

5.2.6 Power Temperature Cycling ............................................................................................................................ 12

5.3 Electrical Characterization Tests ..................................................................................................... 13

5.3.1 Latch-up........................................................................................................................................................... 13

5.3.2 E.S.D. .............................................................................................................................................................. 13




1 APPLICABLE AND REFERENCE DOCUMENTS

Document reference Short description AEC-Q100 : Stress test qualification for integrated circuits 0061692 : Reliability tests and criteria for qualifications





2.1 Objectives

This report contains the reliability evaluation of UK17 device diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES in the overall plan of the S08ExpPad lead frame strip change in Amkor.

According to Reliability Qualification Plan, below is the list of the trials performed: Package Oriented Tests

Preconditioning

Temperature Cycling

Power Temperature Cycling

Autoclave

2.2 Conclusion

Taking in account the preliminary results of the trials performed on the UK17 diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES a positive judgment can be given out. To complete the evaluation the PTC trial need to be performed.




3 DEVICE CHARACTERISTICS

3.1 Device description

3.1.1 Pin connection

3.1.2 Bonding diagram








3.2 Traceability

Wafer fab information

Wafer fab manufacturing location ANG MO KIO

Wafer diameter 6 inches

Wafer thickness 375 µm

Silicon process technology BCD5-40NP

Die finishing back side Cr/Ni

Die size 2770x1980 µm

Bond pad metallization layers AlSiCu

Passivation PSG+SiON+Polyimide

Metal levels 3

Assembly Information

Assembly plant location AMKOR ATP1 PHILIPPINES

Package description HSOP 8L

Die pad size 2.413x3.099 mm

Molding compound Ablebond 8290

Wires bonding materials/diameters Au/1.3 mils

Die attach material Sumitomo G600

Lead solder material Sn





4.1 Test plan and results summary of UK17 with XD lead frame strip

Package Oriented Tests

Test Method Conditions Failure/SS

Duration

Note Lot 1 Lot 2 Lot 3

PC Pre-Conditioning: Moisture sensitivity level 3

192h 30°C/60% - 3 reflow PBT 260°C 0/154 0/154 0/154

PTC Power Temperature Cycling

On Chip Boards Tj=-40°C÷150°C Vcc=36V, Iout=0.7A

To be performed - - 1000h

AC Autoclave

PC before 121°C 2atm 0/77 0/77 0/77 96h

TC Temperature Cycling

PC before Temp. range: -50/+150°C 0/77 0/77 0/77 1000cy




4.2 Test plan and results summary of UK17 with HD lead frame strip

Die Oriented Tests


Duration


HTOL High Temperature Operating Life

PC before Tj=150°C Vcc=36V, Iout=3A

0/77 0/77 0/77 1000h

ELFR Early Life Failure Rate

Tj=150°C Vcc=32V, Iout=0.4A

800 800 800 24h



Duration



192h 30°C/60% - 3 reflow PBT 260°C 0/308 0/308 0/308

THB Temperature Humidity Bias

PC before Ta=85°C/85%RH Pdut~0W, Vcc=20V

0/77 0/77 0/77 1000h



0/45 - - 1000h

AC Autoclave

PC before 121°C 2atm 0/77 0/77 0/77 96h



HTSL High Temperature Storage

No bias Tamb=150°C 0/77 - - 1000h

Electrical Characterization Tests


Duration


ESD Electro Static Discharge

Human Body Model +/- 2kV 0/3 - -

Machine Model +/- 100V 0/3 - -

Charge Device Model

+/- 1.5kV 0/3 - -

LU Latch-Up

Over-voltage and Current Injection

Tamb=125°C Jedec78

0/6 - -

All above trials performed on ABA rev.




5 TESTS DESCRIPTION & DETAILED RESULTS

5.1 Die oriented tests

5.1.1 High Temperature Operating Life

This test is performed like application conditions in order to check electromigration phenomena, gate oxide weakness and other design/manufacturing defects put in evidence by internal power dissipation. The read-outs flow chart is the following:

Initial testing @ Ta=-40°C/25°C/125°C

Check at 168 and 500hrs @ Ta=25°C

Final Testing (1000hrs) @ Ta=-40°C/25°C/125°C

5.1.2 Early Life Failure Rate

This test is to evaluate the defects inducing failure in early life. The device is stressed in biased conditions at the max junction temperature. The read-outs flow chart is the following:

Initial testing @ Ta=25°C/125°C

Final Testing (24 hrs) @ Ta=25°C/125°C




5.2 Package oriented tests

5.2.1 Pre-Conditioning

The device is submitted to a typical temperature profile used for surface mounting, after a controlled moisture absorption. The scope is to verify that the surface mounting stress does not impact on the subsequent reliability performance. The typical failure modes are "pop corn" effect and delamination. The read-outs flow chart is the following:

Initial testing @ Ta=25°C/125°C.

Final Testing @ Ta=25°C/125°C

5.2.2 High Temperature Storage

The device is stored in unbiased condition at the max. temperature allowed by the package materials, sometimes higher than the max. operative temperature. The scope is to investigate the failure mechanisms activated by high temperature, typically wire-bonds solder joint ageing, data retention faults, metal stress-voiding The read-outs flow chart is the following:




5.2.3 Thermal Cycles

The purpose of this test is to evaluate the thermo mechanical behavior under moderate thermal gradient stress. The read-outs flow chart is the following:

Initial testing @ Ta=125°C.

Check at 500 cycles @ Ta=25°C

Final Testing (1000 cycles) @ Ta=125°C TEST CONDITIONS:

Ta= -50°C to +150°C(air)

5.2.4 Autoclave

The purpose of this test is to point out critical water entry path with consequent corrosion phenomena related to chemical contamination and package hermeticity. The read-outs flow chart is the following:


Final Testing (96hrs) @ Ta=25°C. TEST CONDITIONS:

P=2.08 atm

Ta=121°C

test time= 96 hrs




5.2.5 Temperature Humidity Bias

The test is addressed to put in evidence problems of the die-package compatibility related to phenomena activated in wet conditions such as electro-chemical corrosion. The device is stressed in static configuration approaching some field status like power down. Temperature, Humidity and Bias are applied to the device in the following environmental conditions => Ta=85°C / RH=85%. Input pins to Low / High Voltage (alternate) to maximize voltage contrast. Test Duration 2000 h. The read-outs flow chart is the following:




5.2.6 Power Temperature Cycling

This test simulates typical power automotive application. The test is addressed mainly to focus die-attach and wire bonding problems in all the temperature stress changes. Combined stress performing an HTOL stress while the ambient temperature is cycling between –40 to +110°C (Tj=150°C) with the DUT switched alternatively ON/OFF (5min. each) in asynchronous mode with respect the ambient temperature change, (1 cycle: 10’ @ stress Temp. / 20’ to change Temperature). The read-outs flow chart is the following:


Check at 168, 500hrs @ Ta=25°C





5.3 Electrical Characterization Tests

5.3.1 Latch-up

This test is intended to verify the presence of bulk parasitic effects inducing latch-up. The device is submitted to a direct current forced/sinked into the input/output pins. Removing the direct current no change in the supply current must be observed. The read-outs flow chart is the following:


Latch-UP trial @ Ta=125°C

Final Testing @ Ta=25°C/125°C Stress applied:

condition NEG. INJECTION POS. INJECTION OVERVOLTAGE

IN low -100mA Inom+250mA

1.5 x VDD or MSV or AMR, whichever is less

IN high -100mA Inom+250mA


5.3.2 E.S.D.

This test is performed to verify adequate pin protection to electrostatic discharges. The read-outs flow chart is the following:


ESD discharging @ Ta=25°C

Final Testing @ Ta=25°C/125°C TEST CONDITIONS:

o Human Body Model ANSI/ESDA/JEDEC STANDARD JES001 CDF-AEC-Q100-002

o Machine Model JEDEC STANDARD EIA/JESD-A115 CDF-AEC-Q100-003

o Charge Device Model ANSI/ESD STM 5.3.1 ESDA – JEDEC JESD22-C101

CDF-AEC-Q100-011


IPC – RELIABILITY - CASTELLETTO


Preliminary Reliability Report

General Information

Locations

Product Line UK18 Wafer fab location ANG MO KIO




Package HSOP 8L


DOCUMENT HISTORY


1.0 27-May-2016 13 A. Spiezia Original document





Table of Contents



2.1 Objectives ........................................................................................................................................ 4

2.2 Conclusion ....................................................................................................................................... 4



3.1.1 Pin connection ................................................................................................................................................... 5

3.1.2 Bonding diagram ............................................................................................................................................... 5


3.2 Traceability ...................................................................................................................................... 7


4.1 Test plan and results summary of UK18 with XD lead frame strip ....................................................... 8

4.2 Generica Data from UK17 ................................................................................................................ 9








5.2.3 Thermal Cycles ............................................................................................................................................... 11

5.2.4 Autoclave ......................................................................................................................................................... 11




5.3.1 Latch-up........................................................................................................................................................... 13

5.3.2 E.S.D. .............................................................................................................................................................. 13










2.1 Objectives

This report contains the reliability evaluation of UK18 device diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES, according to the AEC-Q100 (Grade1) specifications, in the overall plan of the S08ExpPad with XD lead frame strip qualification.

According to Reliability Qualification Plan, considering UK18 as circuit rerouting of UK17, below is the list of the trials performed:


Preconditioning

Temperature Cycling


Electrical Characterization

ESD resistance test

LATCH-UP resistance test

2.2 Conclusion

Taking in account the preliminary results of the trials performed on the UK18 diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES a positive judgment can be given out.

To complete the evaluation the PTC need to be performed.















3.2 Traceability










Metal levels 3













4.1 Test plan and results summary of UK18 with XD lead frame strip



Duration

Note Lot 1


192h 30°C/60% - 3 reflow PBT 260°C 0/77


On Chip Boards Tj=-40°C÷150°C To be performed 1000h


PC before Temp. range: -50/+150°C 0/77 1000cy



Duration

Note Lot 1


Human Body Model +/- 2kV 0/3

Charge Device Model

+/- 1.5kV 0/3

LU Latch-Up


Tamb=125°C Jedec78

0/6

All above trials performed on ABA rev.




4.2 Generica Data from UK17

Die Oriented Tests


Duration



PC before Tj=150°C 0/77 0/77 0/77 1000h


Tj=150°C 800 800 800 24h



Duration



192h 30°C/60% - 3 reflow PBT 260°C 0/308 0/308 0/308


PC before Ta=85°C/85%RH 0/77 0/77 0/77 1000h


On Chip Boards Tj=-40°C÷150°C 0/45 - - 1000h

AC Autoclave

PC before 121°C 2atm 0/77 0/77 0/77 96h




No bias Tamb=150°C 0/77 - - 1000h

































Ta= -50°C to +150°C(air)

5.2.4 Autoclave




P=2.08 atm

Ta=121°C

test time= 96 hrs


















5.3.1 Latch-up






IN low -100mA +60mA 1.5 x VDD or MSV or AMR, whichever is less

IN high -100mA +100mA 1.5 x VDD or MSV or AMR, whichever is less

5.3.2 E.S.D.







CDF-AEC-Q100-011




Reliability Report

General Information

Locations

Product Line UT20 Wafer fab location ANG MO KIO



AMKOR ATP1 PHILIPPINES Product division IPC

Package HSOP 8L


DOCUMENT HISTORY


1.0 14-Jan-2016 13 S.O.Cannizzaro Preliminary release

1.1 6-May-2016 13 A. Spiezia Final results updated





Table of Contents



2.1 Objectives ........................................................................................................................................ 4

2.2 Conclusion ....................................................................................................................................... 4



3.1.1 Pin connection ................................................................................................................................................... 5

3.1.2 Bonding diagram ............................................................................................................................................... 5


3.2 Traceability ...................................................................................................................................... 7


4.1 Generic data from UK17 ................................................................................................................... 9








5.2.3 Thermal Cycles ............................................................................................................................................... 11

5.2.4 Autoclave ......................................................................................................................................................... 11




5.3.1 Latch-up........................................................................................................................................................... 13

5.3.2 E.S.D. .............................................................................................................................................................. 13










2.1 Objectives

This report contains the reliability evaluation of UT20 device diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES, according to the AEC-Q100 (Grade1) specifications, in the overall plan of the S08ExpPad with XD lead frame strip qualification.

According to Reliability Qualification Plan, considering UT20 as circuit rerouting of UK17, below is the list of the trials performed: Package Oriented Tests

Preconditioning

Temperature Cycling

Power Temperature Cycling Electrical Characterization

ESD resistance test


2.2 Conclusion

Taking in account the preliminary results of the trials performed on the UT20 diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES can be qualified from a reliability viewpoint.















3.2 Traceability









Passivation USG-PSG-SiON-PIX

Metal levels 3





Molding compound Sumitomo G600


Die attach material Ablebond 8290






Test plan and results summary of UT20 with XD lead frame strip



Duration



192h 30°C/60% - 3 reflow PBT 260°C 0/77


On Chip Boards Tj=-40°C÷150°C 0/45 1000h


PC before Temp. range: -50/+150°C 0/77 1000cy



Duration



Human Body Model +/- 2kV 0/3

Charge Device Model

+/- 750V 0/3

LU Latch-Up


Tamb=125°C Jedec78

0/6




4.1 Generic data from UK17

Die Oriented Tests


Duration



PC before Tj=150°C 0/77 0/77 0/77 1000h


Tj=150°C 800 800 800 24h



Duration



192h 30°C/60% - 3 reflow PBT 260°C 0/308 0/308 0/308


PC before Ta=85°C/85%RH 0/77 0/77 0/77 1000h


On Chip Boards Tj=-40°C÷150°C 0/45 - - 1000h

AC Autoclave

PC before 121°C 2atm 0/77 0/77 0/77 96h




No bias Tamb=150°C 0/77 - - 1000h

































Ta= -50°C to +150°C(air)

5.2.4 Autoclave




P=2.08 atm

Ta=121°C

test time= 96 hrs


















5.3.1 Latch-up






IN low -100mA Inom+100mA 1.5 x VDD or MSV or AMR, whichever is less

IN high -100mA Inom+100mA 1.5 x VDD or MSV or AMR, whichever is less

5.3.2 E.S.D.







CDF-AEC-Q100-011




Reliability Report

General Information

Locations

Product Line UD73 Wafer fab location ANG MO KIO




Package HSOP 8L


DOCUMENT HISTORY


1.0 14-Jan-2016 13 S.O.Cannizzaro Original document

1.1 27-May-2016 13 A. Spiezia Typo corrections





Table of Contents



2.1 Objectives ........................................................................................................................................ 4

2.2 Conclusion ....................................................................................................................................... 4



3.1.1 Pin connection ................................................................................................................................................... 5

3.1.2 Bonding diagram ............................................................................................................................................... 5


3.2 Traceability ...................................................................................................................................... 7


4.1 Test plan and results summary of UD73 with XD lead frame strip ....................................................... 8

4.2 Generic data from UK17 ................................................................................................................... 9








5.2.3 Thermal Cycles ............................................................................................................................................... 11

5.2.4 Autoclave ......................................................................................................................................................... 11




5.3.1 Latch-up........................................................................................................................................................... 13

5.3.2 E.S.D. .............................................................................................................................................................. 13










2.1 Objectives

This report contains the reliability evaluation of UD73 device diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES, according to the AEC-Q100 (Grade1) specifications, in the overall plan of the S08ExpPad with XD lead frame strip qualification.

According to Reliability Qualification Plan, considering UD73 as circuit rerouting of UK17, below is the list of the trials performed: Package Oriented Tests

Preconditioning

Temperature Cycling


Electrical Characterization

ESD resistance test


2.2 Conclusion

Taking in account the results of the trials performed the UD73 diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES can be qualified from reliability viewpoint.















3.2 Traceability










Metal levels 3













4.1 Test plan and results summary of UD73 with XD lead frame strip



Duration



192h 30°C/60% - 3 reflow PBT 260°C 0/77 - -



0/45 - - 1000h


PC before Temp. range: -50/+150°C 0/77 - - 1000cy



Duration



Human Body Model +/- 2kV 0/3 - -

Charge Device Model

+/- 1kV 0/3 - -

LU Latch-Up


Tamb=125°C Jedec78

0/6 - -

All above trials performed on EEA rev.




4.2 Generic data from UK17

Die Oriented Tests


Duration



PC before Tj=150°C Vcc=36V

0/77 0/77 0/77 1000h


Tj=150°C Vcc=32V

800 800 800 24h



Duration



192h 30°C/60% - 3 reflow PBT 260°C 0/308 0/308 0/308


PC before Ta=85°C/85%RH Pdut~0W, Vcc=20V

0/77 0/77 0/77 1000h



0/45 - - 1000h

AC Autoclave

PC before 121°C 2atm 0/77 0/77 0/77 96h




No bias Tamb=150°C 0/77 - - 1000h

































Ta= -50°C to +150°C(air)

5.2.4 Autoclave




P=2.08 atm

Ta=121°C

test time= 96 hrs


















5.3.1 Latch-up






IN low -100mA 100mA


IN high -70mA 100mA


5.3.2 E.S.D.







CDF-AEC-Q100-011




Reliability Report

General Information

Locations

Product Line UA50 Wafer fab location CATANIA M5



AMKOR ATP1 PHILIPPINES Product division IPC

Package HSOP 8L

Silicon process technology BCD6S Reliability assessment Pass

DOCUMENT HISTORY


1.0 26-Feb-2016 13 S.O.Cannizzaro Original document

1.1 27-May-2016 13 A. Spiezia Typo corrections





Table of Contents



2.1 Objectives ........................................................................................................................................ 4

2.2 Conclusion ....................................................................................................................................... 4



3.1.1 Pin connection ................................................................................................................................................... 5

3.1.2 Bonding diagram ............................................................................................................................................... 5


3.2 Traceability ...................................................................................................................................... 7


4.1 Test plan and results summary of UA50 with XD lead frame strip ....................................................... 8

4.2 Test plan and results summary of UA50 with HD lead frame strip ....................................................... 9








5.2.3 Thermal Cycles ............................................................................................................................................... 11

5.2.4 Autoclave ......................................................................................................................................................... 11




5.3.1 Latch-up........................................................................................................................................................... 13

5.3.2 E.S.D. .............................................................................................................................................................. 13










2.1 Objectives

This report contains the reliability evaluation of UA50 device diffused in CATANIA M5 and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES, according to the AEC-Q100 (Grade1) specifications, in the overall plan of the S08ExpPad with XD lead frame strip qualification. According to Reliability Qualification Plan, below is the list of the trials performed: Package Oriented Tests

Preconditioning

Temperature Cycling


Autoclave

2.2 Conclusion

Taking in account the results of the trials performed the UA50 diffused in CATANIA M5 and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES can be qualified from a reliability viewpoint.















3.2 Traceability


Wafer fab manufacturing location CATANIA M5



Silicon process technology BCD6S

Die finishing back side Cr/Ni/Au


Bond pad metallization layers AlCu

Passivation TEOS+SiON+Polyimide

Metal levels 4





Molding compound Sumitomo G600


Die attach material Ablebond 8290






4.1 Test plan and results summary of UA50 with XD lead frame strip



Duration



192h 30°C/60% - 3 reflow PBT 260°C 0/154 0/154 0/154


On Chip Boards Tj=-40°C÷150°C, Vcc=25V, Iout=0.7A 0/45 - - 1000h

AC Autoclave

PC before 121°C 2atm 0/77 0/77 0/77 96h






4.2 Test plan and results summary of UA50 with HD lead frame strip

Die Oriented Tests

Test Method Conditions Sample/Lots

Number of lots

Duration Results


On Chip Boards Tj=150°C, Vcc=20V, Iout=3,5A (Max) 77 3 1000h PASSED


On Chip Boards Ta=85°C 85% RH, Vcc=38V 77 3 1000h PASSED


On Chip Boards Tj=-40°C÷150°C, Vcc=25V, Iout=0.7A 45 1 1000h PASSED


Tj=150°C Vcc=25V, Iout=0,35A

800 3 1000h PASSED

Package Oriented Tests Test Method Conditions Sample/

Lots Number of lots

Duration Results


192h 30°C/60% - 3 reflow PBT 260°C 180 3 PASSED

AC Autoclave

PC before 121°C 2atm 77 3 96h PASSED


PC before Temp. range: -50/+150°C 77 3 1000cy PASSED

HTSL High Temperature Storage Life

No bias Tamb=150°C 77 1 1000h PASSED

Electrical Characterization Tests Test Method Conditions Sample/

Lots Number of lots

Duration Results


Human Body Model +/- 2kV 3 1 PASSED

Charge Device Model

+/- 500V +/- 750V on corner pins

3 1 PASSED

LU Latch-Up


Tamb=125°C Jedec78 – Level B

6 1 PASSED

































Ta= -50°C to +150°C(air)

5.2.4 Autoclave




P=2.08 atm

Ta=121°C

test time= 96 hrs


















5.3.1 Latch-up






IN low -10mA +100mA


IN high -10mA +100mA


5.3.2 E.S.D.






o Charge Device Model ANSI/ESD STM 5.3.1 ESDA – JEDEC JESD22-C101 CDF-AEC-Q100-011

Documents

RELIABILITY EVALUATION QUALIFICATION OF SOIC8L …1.0 05-May-2016 F.VENTURA I&PC QA&R / B/E A.PLATINI I&PC QA&R MNG. Final report Note: This report is a summary of the reliability