Regular Expression Manipulation FSM Model

Regular Expression ManipulationFSM Model

Sequential Machine Theory

Prof. K. J. HintzDepartment of Electrical and Computer

Engineering

Lecture 6

Modifications by Marek Perkowski

Null Machine

3 Methods for Proving That a Machine Accepts No Words– By inspection

• Any path from the start state to a final state means that at least one word is accepted by the machine

– By state diagram manipulation• If a final state is relabeled as a start state, then the

machine must accept at least one word

Null Machine

– By converting the regular expression into a deterministic FA

• If possible, FA must accept at least one word• Conversion to FA may not be possible

– Machine may have no final states.– There is no path from the initial state to any final state.

State Diagram Manipulation

A procedure to determine if a machine accepts no strings

1. Remove all edges (arrows) to the start state.2. From the start state, identify all single-step “next

states.”3. Relabel these “next states” as start states and

eliminate the edges used to get there.4. go to (b)5. If a final state is relabeled as a start state, then the

machine must accept at least one word.




Does Not Accept AnyWord Since There Is No Path From - To +.

The Complement Machine

• A Complement Machine Accepts All Expressions Other Than Those Accepted by the Original Machine

• Method– Change all non-final states into final states– Change all final states into non-final states– Leave start state unchanged

Language Decidability

Methods for Determining If Two Regular Expressions Define the Same Language– Language Enumeration with 1:1

correspondence between the 2 languages.– The regular languages can be accepted by

identical FAs.– Generate

L L L L Loverlap 1 2 2 1?

Language Overlap

• If the Overlap Language Is NOT the Null Set, Then There Is Some Word in L1 Which Is Not Accepted by L2 and Vice Versa.

• If the Overlap Language Accepts the Null String, Then the Languages Are Not Equal.

L 1L 2L 1

L 2

DeMorgan’s Theorem

Applies Equally Well to Sets As Well As Boolean Algebra

BABA

andBABA

Regular Expression Equivalence

Methodology– Construct the complement machines– Apply DeMorgan’s theorem since it is difficult

to form the intersect machine

L L L L LL L L L

overlap

1 2 2 1

1 2 2 1

Regular Expression Equivalence

Take the Unions of the Complemented and Non-complemented Several Times to Determine Whether Loverlap Is the Null Set or Not

RE Equivalence Example*

Two REs are represented by their equivalent FAs (FA1 does = FA2)

*Cohen, Prob. 2, page 233.

RE Equivalence Example

Form the Complement Machines


Make the Product Machine of FA2 and the Complement of FA1.


• States of Product Machine, FA1-bar & FA2• Only One Start State / Multiple Final States

Start/Final -/+

New State State Vector

-/+ 1 ( p1, y1 )

+ 2 ( p1, y2 )

+ 3 ( p1, y3 )


Start/Final

-/+ New State State

Vector 4 ( p2, y1 )

+ 5 ( p2, y2 )

6 ( p2, y3 )

Product Machine State Table

Start/Final -/+

Present State a b

-/+ 1 5 3 + 2 5 3 + 3 5 3 4 5 3

+ 5 5 3 6 5 3

State Diagram of Product

FA1-Bar, FA2

Reduced State Diagram

Non-Reachable States Removed


• Take the Complement Of the Union by changing final states to non-final and vice-versa

• No Final States, So Complement FA Accepts No Words

21 LL


Do the Same for the Right Term of Loverlap


• Application of Same Procedure to Preceding Machine Also Results in No Recognizable Words.

• Since Both Terms of Loverlap are Null, Then REs Are Equivalent Since Their Union Is Null.

Moore & Mealy Machines

• The Behavior of Sequential Machines Depends on Previous Inputs.– Moore Machine

• Output only depends on present state– Mealy Machine

• Output depends on both the present state and the present input

Moore & Mealy Machines

Equivalent Descriptive Methods– Transition (state) table– Transition (state) diagram– Operational descriptions using set theory– (Language recognized by the machine)

Moore Machine

Present State

InputComb

Ckt

Memory

Comb Ckt

Output Is Only a Function of Present State

Output

Primitive State Diagram, Moore

Legend

state/output

input

A/0

C/0 D/0

B/1

etc.

off

on

off

Moore Machine State Diagram

Legend

s1s0/z

x1x0

00/1

10/1 11/1

01/0

etc.

00

10

01

Mealy Machine

Output Is Function of Present State AND Present Input

Present State

InputComb

Ckt

Memory

Comb Ckt

Output

Primitive State Diagram, Mealy

Legend

state

input/output

A

C D

B

etc.

off/1

on/0

off /0

Mealy Machine State Diagram

Legend

s1s0

x1x0 /z

00

10 11

01

etc.

00 /1

10 /0

01 /1

Transition Table

Present State

Variables

Input Variables

Next State

Variables

Output Variables

si xj sk zm

FSM Design Approaches

• “One-Hot”– One flip-flop is used to represent each state– Costly in terms of discrete hardware, but trivial to

design– Efficient in FPGAs because FF part of each CLB

• Binary Coded State– n flip-flops used to store 2n states– Most efficient– Need to account for unused states

FSM and Clocks

• Synchronous FSMs may change state only when a unique input, the clock, occurs

• Asynchronous FSMs may change state when input changes

• Next state depends on present input and present state for both Moore and Mealy

Synchronous versus Asynchronous Machines in Design

• Synchronous FSMs– Easier to design, turn the crank– Slower operation

• Asynchronous– Harder to design because of potential for races,

iterative solutions– Faster operation

Mealy “0101” Detector

M = ( S, I, O, )S: { A, B, C, D }I: { ‘0’, ‘1’ }O: { 0, 1 } = { not detected, detected}next slidenext slide

Mealy Transition/Output Table

Present InputPresentState ‘0’ ‘1’

A B/0 A/0B B/0 C/0C D/0 A/0D B/0 C/1

Next State/Output

“0101“ State Diagram

A

DC

B

‘1’/0 ‘0’/0

‘0’/0

‘1’/0‘1’/0

‘0’/0

‘1’/1

‘0’/0

Moore “0101” Detector

M = ( S, I, O, )S: { A, B, C, D, E }I: { ‘0’, ‘1’ }O: { 0, 1 } = { not detected, detected} next slidenext slide

Moore Transition/Output Table

Present InputPresentState ‘0’ ‘1’

Output()

A B A 0B B C 0C D A 0D B E 0E D A 1

Next State

Moore “0101“ State Diagram

A/0

D/0C/0

B/0‘1’

‘0’‘0’

‘1’‘1’

‘0’

‘0’

‘0’ detected

“01” det“010” det

E/1

“0101” det‘1’

‘0’‘1’

Asynchronous FSM

Fundamental Mode Assumption– Only one input can change at a time

• Analysis too complicated if multiple inputs are allowed to change simultaneously

– Circuit must be allowed to settle to its final value before an input is allowed to change

• Behavior is unpredictable (nondeterministic) if circuit not allowed to settle

Asynch. Design Difficulties

Delay in Feedback Path– Not reproducible from implementation to

implementation– Variable

• may be temperature or electrical parameter dependent within the same device

– Analog• not known exactly

Stable State

• PS = present state• NS = next state• PS = NS = Stability

– Machine may pass through none or more intermediate states on the way to a stable state

– Desired behavior since only time delay separates PS from NS

• Oscillation– Machine never stabilizes in a single state

Races

• A Race Occurs in a Transition From One State to the Next When More Than One Next State Variables Changes in Response to a Change in an Input

• Slight Environment Differences Can Cause Different State Transitions to Occur– Supply voltage– Temperature, etc.

Races

01

10

11 00

PS

desired NS

if Y1 changes first

if Y2 changes first

Types of Races

• Non-Critical– Machine stabilizes in desired state, but may

transition through other states on the way• Critical

– Machine does not stabilize in the desired state

Races

01

10

11 00

PS

desired NS

non- critical race

if Y1 changes first

if Y2 changes first

critical race

00

Asynchronous FSM Benefits

• Fastest FSM• Economical

– No need for clock generator• Output Changes When Signals Change, Not When

Clock Occurs• Data Can Be Passed Between Two Circuits Which

Are Not Synchronized• In some technologies, like quantum, clock is just

not possible to exist

Asynchronous FSM Example

next

statepresent

statey1

y2

input

Next State Variables

12

2212

2211

2211211

,,

,,

yxy

yxyyyxY

yxyyxyx

yxyyxyxyyxY

Sequential Machines Problems

Three Problems of Sequential Machines– State minimization problem

• Determine all equivalent states of a sequential machine, and,

• Eliminate redundant states– Machine Decomposition

• Separate large machines into an interconnected set of smaller machines

• Easier to design and analyze small machines

Sequential Machine Problems

– State assignment problem• There is no guidance on which binary number to

assign to which state in a primitive state table• Complexity of implementation is dependent on

mapping of states to binary numbers• Unsolved problem

– Design all machines and compare– Benefit of decomposition of large machine into smaller

machines.

Set Theoretic Description

Moore Machine is an ordered quintuple

Moore= S I O

SIO

S I SS O

, , , ,

, , ,, , ,

, , ,

whereFinite set of states , s s sFinite set of inputs , i i iFinite set of outputs , o o o

Next state function which maps Output function which maps

1 2 n

1 2 m

1 2 l

Set Theoretic Description

Mealy Machine is an ordered quintuple

OISSIS

OIS

OIS

maps whichfunctionOutput maps whichfunction stateNext

o,,o,o, outputs ofset Finitei,,i,i, inputs ofset Finites,,s,s, states ofset Finite

where,,,,

l21

m21

n21

=Mealy

Recursive Definitions of Delta

State Transition for Moore & Mealy– Single-valued, else not deterministic.– At least a partial function– Not necessarily injective or surjective– Shield’s nomenclature

:

: , , ,

S I S

S I S

s i sk k k1

Recursive Definitions of Delta

*

*

is none or more occurrances of the definitionof a particular mapping from Let

. ., a stringthen define

* , , . ., the response to a null string is no state change

S I S

SII

sax i e

s e s i e

Recursive Definitions of Beta

• Causal, No Output for No Input.• For a Given Input Sequence, There Will Be

a Deterministic Output Sequence of the Same Length As the Input.

OISOIS

,,,::

1 kkk ois

Recursive Definitions of Lambda

Same Caveats As Beta

xxsasxas

sos

kkk

k

kk

,,*.,.,*,*

,,::

21

1

OSOS

sk sk-1

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Regular Expression Manipulation FSM Model